davinci: Add watchdog base address flexibility
The watchdog code currently hardcodes the base address
of the timer its using. To support new SoCs, make it
support timers at any address. Use the soc_info structure
to do this.
Signed-off-by: Mark A. Greer <mgreer@mvista.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 36c528f..7ebf671 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -216,8 +216,6 @@
static struct resource wdt_resources[] = {
{
- .start = 0x01c21c00,
- .end = 0x01c21fff,
.flags = IORESOURCE_MEM,
},
};
@@ -231,6 +229,11 @@
static void davinci_init_wdt(void)
{
+ struct davinci_soc_info *soc_info = &davinci_soc_info;
+
+ wdt_resources[0].start = (resource_size_t)soc_info->wdt_base;
+ wdt_resources[0].end = (resource_size_t)soc_info->wdt_base + SZ_1K - 1;
+
platform_device_register(&davinci_wdt_device);
}
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 293a419..1b7c16c 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -646,6 +646,7 @@
.intc_irq_prios = dm355_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm355_timer_info,
+ .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
};
void __init dm355_init(void)
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 8e9385c..c662692 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -589,6 +589,7 @@
.intc_irq_prios = dm644x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm644x_timer_info,
+ .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
};
void __init dm644x_init(void)
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 219063f..83d67cf 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -568,6 +568,7 @@
.intc_irq_prios = dm646x_default_priorities,
.intc_irq_num = DAVINCI_N_AINTC_IRQ,
.timer_info = &dm646x_timer_info,
+ .wdt_base = IO_ADDRESS(DAVINCI_WDOG_BASE),
};
void __init dm646x_init(void)
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 90b43be..d637038 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -57,6 +57,7 @@
u8 *intc_irq_prios;
unsigned long intc_irq_num;
struct davinci_timer_info *timer_info;
+ void __iomem *wdt_base;
};
extern struct davinci_soc_info davinci_soc_info;
diff --git a/arch/arm/mach-davinci/include/mach/time.h b/arch/arm/mach-davinci/include/mach/time.h
index 1428d77..1c971d8 100644
--- a/arch/arm/mach-davinci/include/mach/time.h
+++ b/arch/arm/mach-davinci/include/mach/time.h
@@ -13,6 +13,7 @@
#define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400)
#define DAVINCI_TIMER1_BASE (IO_PHYS + 0x21800)
+#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
enum {
T0_BOT,
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index faafb89..f80ae25 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -35,8 +35,6 @@
static struct clock_event_device clockevent_davinci;
static unsigned int davinci_clock_tick_rate;
-#define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00)
-
/*
* This driver configures the 2 64-bit count-up timers as 4 independent
* 32-bit count-up timers used as follows:
@@ -343,7 +341,8 @@
void davinci_watchdog_reset(void)
{
u32 tgcr, wdtcr;
- void __iomem *base = IO_ADDRESS(DAVINCI_WDOG_BASE);
+ struct davinci_soc_info *soc_info = &davinci_soc_info;
+ void __iomem *base = soc_info->wdt_base;
struct clk *wd_clk;
wd_clk = clk_get(&davinci_wdt_device.dev, NULL);