[PATCH] ppc32: Fix MPC83xx IPIC external interrupt pending register offset
The pending registers for IRQ1-IRQ7 were pointing to the interrupt pending
register instead of the external one.
Signed-off-by: Tony Li <Tony.Li@freescale.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c
index 580ed65..8f01e0f 100644
--- a/arch/ppc/syslib/ipic.c
+++ b/arch/ppc/syslib/ipic.c
@@ -79,7 +79,7 @@
.prio_mask = 7,
},
[17] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_A,
.force = IPIC_SEFCR,
@@ -87,7 +87,7 @@
.prio_mask = 5,
},
[18] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_A,
.force = IPIC_SEFCR,
@@ -95,7 +95,7 @@
.prio_mask = 6,
},
[19] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_A,
.force = IPIC_SEFCR,
@@ -103,7 +103,7 @@
.prio_mask = 7,
},
[20] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
.force = IPIC_SEFCR,
@@ -111,7 +111,7 @@
.prio_mask = 4,
},
[21] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
.force = IPIC_SEFCR,
@@ -119,7 +119,7 @@
.prio_mask = 5,
},
[22] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
.force = IPIC_SEFCR,
@@ -127,7 +127,7 @@
.prio_mask = 6,
},
[23] = {
- .pend = IPIC_SIPNR_H,
+ .pend = IPIC_SEPNR,
.mask = IPIC_SEMSR,
.prio = IPIC_SMPRR_B,
.force = IPIC_SEFCR,