diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4b797e7..395c4d3 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -157,7 +157,7 @@
 	ring->set_tail(dev, ring, 0);
 
 	/* Initialize the ring. */
-	I915_WRITE(ring->regs.start, obj_priv->gtt_offset);
+	I915_WRITE_START(ring, obj_priv->gtt_offset);
 	head = ring->get_head(dev, ring);
 
 	/* G45 ring initialization fails to reset head to zero */
@@ -168,7 +168,7 @@
 				I915_READ(ring->regs.ctl),
 				I915_READ(ring->regs.head),
 				I915_READ_TAIL(ring),
-				I915_READ(ring->regs.start));
+				I915_READ_START(ring));
 
 		I915_WRITE(ring->regs.head, 0);
 
@@ -178,7 +178,7 @@
 				I915_READ(ring->regs.ctl),
 				I915_READ(ring->regs.head),
 				I915_READ_TAIL(ring),
-				I915_READ(ring->regs.start));
+				I915_READ_START(ring));
 	}
 
 	I915_WRITE(ring->regs.ctl,
@@ -194,7 +194,7 @@
 				I915_READ(ring->regs.ctl),
 				I915_READ(ring->regs.head),
 				I915_READ_TAIL(ring),
-				I915_READ(ring->regs.start));
+				I915_READ_START(ring));
 		return -EIO;
 	}
 
@@ -781,7 +781,6 @@
 	.regs                   = {
 		.ctl = PRB0_CTL,
 		.head = PRB0_HEAD,
-		.start = PRB0_START
 	},
 	.mmio_base		= RENDER_RING_BASE,
 	.size			= 32 * PAGE_SIZE,
@@ -818,7 +817,6 @@
 	.regs			= {
 		.ctl = BSD_RING_CTL,
 		.head = BSD_RING_HEAD,
-		.start = BSD_RING_START
 	},
 	.mmio_base		= BSD_RING_BASE,
 	.size			= 32 * PAGE_SIZE,
@@ -929,7 +927,6 @@
        .regs			= {
                .ctl    = GEN6_BSD_RING_CTL,
                .head   = GEN6_BSD_RING_HEAD,
-               .start  = GEN6_BSD_RING_START
        },
        .mmio_base		= GEN6_BSD_RING_BASE,
        .size			= 32 * PAGE_SIZE,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 2dfcd9b..9d0ae5a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -9,6 +9,8 @@
 
 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL(ring->mmio_base))
 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL(ring->mmio_base), val)
+#define I915_READ_START(ring) I915_READ(RING_START(ring->mmio_base))
+#define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val)
 
 struct drm_i915_gem_execbuffer2;
 struct  intel_ring_buffer {
@@ -20,7 +22,6 @@
 	struct		ring_regs {
 			u32 ctl;
 			u32 head;
-			u32 start;
 	} regs;
 	u32		mmio_base;
 	unsigned long	size;