commit 52378445da0253d5031590e5e9186ee448dc0b4a
author Peter Horton <pdh@colonel-panic.org> Sun Jan 29 21:33:48 2006 +0000
committer Ralf Baechle <ralf@linux-mips.org> Tue Feb 07 13:30:24 2006 +0000
tree bb4028a9ff2543e29c5f31863a441f1f9d7608f5
parent c315a2b5fed42aea4dda98b5ced35d1d1a3a8349

[MIPS] Fix Cobalt PCI cache line sizes
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/pci/fixup-cobalt.c

diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index b664df1..75a01e7 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -52,7 +52,7 @@
 	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
 	if (lt < 64)
 		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
-	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
 }
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
@@ -69,7 +69,7 @@
 	 * host bridge.
 	 */
 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
-	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
+	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
 
 	/*
 	 * The code described by the comment below has been removed