| commit | 493c65aab4cfbdec1b065d409fd8b2c9b907d8ec | [log] [tgz] |
|---|---|---|
| author | Jon Medhurst <tixy@linaro.org> | Mon Dec 02 11:47:16 2013 +0000 |
| committer | Jon Medhurst <tixy@linaro.org> | Mon Dec 02 12:54:16 2013 +0000 |
| tree | 1f4dd1703e51c4beed66eac5fbceac00b37f9580 | |
| parent | 4bb2d496b52029fc12322af09f1a5dda95affdba [diff] |
ARM: vexpress/TC2: Match mainline cache disabling sequence in tc2_pm_down When the TC2 pm code was finally upstreamed [1] the cache disbling sequence had been modified to avoid some potential race conditions. So lets backport these changes. [1] Commit 11b277eabe70 ARM: vexpress/TC2: basic PM support Signed-off-by: Jon Medhurst <tixy@linaro.org>