overo: support 200Mhz memory on 37XX
Signed-off-by: Steve Sakoman <steve@sakoman.com>
diff --git a/board/overo/overo.c b/board/overo/overo.c
index 7b4064c..28c7344 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -169,16 +169,30 @@
*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
- *mcfg = MICRON_V_MCFG_165(256 << 20);
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ if (get_cpu_family() != CPU_OMAP36XX) {
+ *mcfg = MICRON_V_MCFG_165(256 << 20);
+ *ctrla = MICRON_V_ACTIMA_165;
+ *ctrlb = MICRON_V_ACTIMB_165;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ } else {
+ *mcfg = MICRON_V_MCFG_200(256 << 20);
+ *ctrla = MICRON_V_ACTIMA_200;
+ *ctrlb = MICRON_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ }
break;
case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
- *mcfg = HYNIX_V_MCFG_165(256 << 20);
- *ctrla = HYNIX_V_ACTIMA_165;
- *ctrlb = HYNIX_V_ACTIMB_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ if (get_cpu_family() != CPU_OMAP36XX) {
+ *mcfg = HYNIX_V_MCFG_165(256 << 20);
+ *ctrla = HYNIX_V_ACTIMA_165;
+ *ctrlb = HYNIX_V_ACTIMB_165;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ } else {
+ *mcfg = HYNIX_V_MCFG_200(256 << 20);
+ *ctrla = HYNIX_V_ACTIMA_200;
+ *ctrlb = HYNIX_V_ACTIMB_200;
+ *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ }
break;
default:
*mcfg = MICRON_V_MCFG_165(128 << 20);