driver: dwmmc: Add the clock divider code for exynos dwmmc
The exynos dwmmc Ip has 2 stage divider. The first divider
Register is in the vendor specific region of the dwmmc core
(CLK_SEL), and second is part of the dwmmc generic registers
(CLK_DIV).
The goal of this patch is to maintain a 100MHz clock output
before dividing it further by using the CLK_DIV.
Depending on the card enumeration, it can be further divided
by writing a correct divider in the dwmmc CLK_DIV register.
Signed-off-by: Girish K S <ks.giri@samsung.com>
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index 286a7df..fdb62b0 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -30,7 +30,7 @@
{
u32 val;
val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) |
- DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0);
+ DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(3);
dwmci_writel(host, DWMCI_CLKSEL, val);
}
@@ -44,6 +44,12 @@
return 1;
}
+ /* MPLL = 800MHz
+ * FSYS DIVS = 0, 2
+ * CLK_SEL = 4 800/2/4 = 100MHz
+ * Set the sclk_mmc such that it generates 100Mhz output
+ */
+ set_mmc_clk(index, 1);
host->name = EXYNOS_NAME;
host->ioaddr = (void *)regbase;
host->buswidth = bus_width;