mx6qsabrelite: enet: force master, maximize tx clock delay
Register 0x106 is tx data delay register.
With this patch, gigabit mode still does not work reliably.
Ping shows about a 10% packet loss on large packets.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 5c811de..b76146d 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -193,13 +193,17 @@
int fecmxc_mii_postcall(int phy)
{
- /* prefer master mode */
- miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00);
+ /* force master mode */
+ miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x1f00);
/* min rx data delay */
miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105);
miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
+ /* min tx data delay */
+ miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8106);
+ miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
+
/* max rx/tx clock delay, min rx/tx control delay */
miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104);
miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0);