| commit | ba5ee185ad76cb41f028e5816f7f1d0e4e5ef724 | [log] [tgz] |
|---|---|---|
| author | Troy Kisky <troy.kisky@boundarydevices.com> | Thu Dec 22 08:42:06 2011 +0100 |
| committer | John Rigby <john.rigby@linaro.org> | Thu Jan 19 17:08:51 2012 -0700 |
| tree | eea18644bc7ad14734149a4e8c5e46c4632fedfc | |
| parent | 85fe4bf4ae2e1eed20979445030354b3e491b907 [diff] |
mx6qsabrelite: enet: force master, maximize tx clock delay Register 0x106 is tx data delay register. With this patch, gigabit mode still does not work reliably. Ping shows about a 10% packet loss on large packets. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>