- 852d12c Fix clang build. by Peter Collingbourne · 4 years, 6 months ago dev/fix-clang
- 21d4684 Fix encoding for integer PAC instructions with zero context by Pierre Langlois · 4 years, 7 months ago master
- 7c107ea Skip top 64-bit write in movi if identical. by Pierre Langlois · 4 years, 8 months ago
- 2ed1d31 Fix ldapr test by Martyn Capewell · 4 years, 8 months ago
- bb4ed21 Add missing aliases for mov instruction with immediate by mateusz.kalinowski · 4 years, 8 months ago
- 78de951 [sve] Fix while simulation corner case by Martyn Capewell · 4 years, 9 months ago
- acdea50 Remove "dummy" from test and tools by Martyn Capewell · 4 years, 8 months ago
- d42989c Remove use of "dummy" by Martyn Capewell · 4 years, 8 months ago
- c4ef66e Make the stack size configurable. by Jacob Bramley · 4 years, 9 months ago
- f73036b Fix FPRoundInt's handling of INT64_MAX. by Jacob Bramley · 4 years, 8 months ago
- a26a26c Don't simulate invalid logical immediate instructions by Martyn Capewell · 4 years, 10 months ago
- 6f755e6 Fix undefined behaviour in Halve by Martyn Capewell · 4 years, 10 months ago
- d02f437 Simplify the command-line disassembly example UI. by Jacob Bramley · 4 years, 9 months ago
- e522c6e Add a command-line disassembly example. by Jacob Bramley · 4 years, 9 months ago
- 46ce31f Add email address for bug reporting by Martyn Capewell · 4 years, 10 months ago
- 63ceff5 Define values for unallocated prefetch modes by Martyn Capewell · 4 years, 10 months ago
- 4c55093 Fix lint.py error regex. by Jacob Bramley · 4 years, 10 months ago
- e66b090 Optimise single handler tables in the decoder. by Martyn Capewell · 5 years ago
- 8ed8352 [sve] Disallow dup with shift on byte-sized lanes by Martyn Capewell · 5 years ago
- 32a7cd9 Fix infinite loops in some native tests. by Jacob Bramley · 5 years ago
- b8da04d Remove undefined behaviour in add/sub immediate by Martyn Capewell · 5 years ago
- f84b464 Revert optimisation for add/sub immediates by Martyn Capewell · 5 years ago
- aaf02c5 Fix initialisation order for ID register fields. by Jacob Bramley · 5 years ago
- f3f5d24 Fix add/sub immediate for min-int case by Martyn Capewell · 5 years ago
- f48172b Add missing aliases for SVE 0.0 moves. by Jacob Bramley · 5 years ago
- b9616b3 Fix and enable CanTakeSVEMovprfx. by Jacob Bramley · 5 years ago
- 8c4ceb6 Support more than 64 CPU features. by Jacob Bramley · 5 years ago
- caa40ee Fix CPUFeature iterator behaviour. by Jacob Bramley · 5 years ago
- 28ff597 Add an example that dumps CPU feature information. by Jacob Bramley · 5 years ago
- 31d432b Add support for AT_HWCAP2. by Jacob Bramley · 5 years ago
- 3d8d394 Add CPUFeatures up to Armv8.6. by Jacob Bramley · 5 years ago
- 960606b Emit pairs of add/sub for larger immediates by Martyn Capewell · 5 years ago
- 4635261 Use segments in SVE indexed fmul simulation by Martyn Capewell · 5 years ago
- 3eb24e9 Fix numerous issues related to CAS* instructions. by Jacob Bramley · 5 years ago
- 102e7a5 Make assembler more strict about SVE prefetch arguments by Martyn Capewell · 5 years ago
- ebc3b8f Use PgLow8 rather than Pg<12, 10>. by Jacob Bramley · 5 years ago
- 7b5819c Always assert that 'pg' does not have a lane size. by Jacob Bramley · 5 years ago
- ecca4b1 Disallow x31/xzr for SVE prefetch scalar offset register by Martyn Capewell · 5 years ago
- 4606adc Fix simulation of FCMNE. by Jacob Bramley · 5 years ago
- 5a5e71f Require an immediate (0.0) for compare-with-zero instructions. by Jacob Bramley · 5 years ago
- a8461cf Prefer to use 'rd' as a scratch. by Jacob Bramley · 5 years ago
- 32f8fe1 Fix CPURegister::GetArchitecturalName(). by Jacob Bramley · 5 years ago
- dfb93b5 Fix simulation of FTSMUL. by Jacob Bramley · 5 years ago
- 8caa873 Fix the `sve_fmla_fmls` test. by Jacob Bramley · 5 years ago
- a3d6110 Fix simulation of BRKNS. by Jacob Bramley · 5 years ago
- 3980b74 Make the 'sve_punpk' test VL-agnostic. by Jacob Bramley · 5 years ago
- 7c8c1f0 Update FPCR test. by Jacob Bramley · 5 years ago
- df01bce Merge branch 'sve' by Jacob Bramley · 5 years ago
- 75892bd [sve] Restore LaneSize to predicate logical operations. by Martyn Capewell · 5 years ago sve
- 9927c4f [sve] Improve disasm substitution for sign-extending loads by Martyn Capewell · 5 years ago
- f67b1af [sve] Remove generated comments from the disassembler by Martyn Capewell · 5 years ago
- 5e2df59 [sve] Remove extra spaces from load/store register lists. by Jacob Bramley · 5 years ago
- 2993695 [sve] Remove redundant 'USE' macros. by Jacob Bramley · 5 years ago
- 8982025 [sve] Ternary substitution for disassembler by Martyn Capewell · 5 years ago
- 1f1ab9b Merge branch 'master' into sve by Jacob Bramley · 5 years ago
- 15d7843 [sve] Make modifiers lower case in disassembly by Martyn Capewell · 5 years ago
- 5f3928c [sve] Implement 32-bit scatter store (scalar plus vector mode). by TatWai Chong · 5 years ago
- fa098bc [sve] Implement 64-bit scatter store (scalar plus vector mode). by Martyn Capewell · 5 years ago
- a511234 [sve] Complete remaining gather loads. by Martyn Capewell · 5 years ago
- cd3f6c5 [sve] Fix the index specifier decoding error in the gather load helper. by TatWai Chong · 5 years ago
- cb0cfc3 Remove some unnecessary casts in `LoadStoreMemOperand`. by Jacob Bramley · 5 years ago
- 50ef171 [sve] Relax the lane size restriction of register in MacroAssembler. by TatWai Chong · 5 years ago
- 7b9a5f1 Use Register for macro assembler ldpsw by Martyn Capewell · 5 years ago
- 4fc4bec [sve] Add a strlen example using ldff1b. by Jacob Bramley · 6 years ago
- 6ebcc8a Ensure stable build directory name under Python 3 by Matthew Bentham · 5 years ago
- 5f9b380 [sve] Implement ContiguousNonFaultLoad by Martyn Capewell · 5 years ago
- d154a44 Don't template 'Rx' on the register type. by Jacob Bramley · 5 years ago
- 0d754e9 [sve] Trace writes to FFR. by Jacob Bramley · 5 years ago
- 7d3a329 [sve] Remove a bad assertion. by Jacob Bramley · 5 years ago
- 1c45cfe [sve] Rename IsScalar to IsPlainScalar. by Jacob Bramley · 5 years ago
- 7db8210 [sve] Implement fmov aliases. by Martyn Capewell · 5 years ago
- ae3902a [sve] Implement logical immediate aliases. by Martyn Capewell · 5 years ago
- 83ebf7c Remove redundant tests. by Jacob Bramley · 5 years ago
- e2de607 [sve] Implement aliases for mov immediate by Martyn Capewell · 5 years ago
- 9ccc4d2 [sve] Implement aliases for mov from register by Martyn Capewell · 5 years ago
- a24d95c [sve] Implement predicate logical instruction aliases by Martyn Capewell · 5 years ago
- b56cf22 [sve] Implement scatter str, vector plus immediate form by Martyn Capewell · 5 years ago
- a3c1146 Remove stray assembler method declarations by Martyn Capewell · 5 years ago
- fd0fc20 Merge branch 'master' into sve by Jacob Bramley · 5 years ago
- 2b66cd6 Fix the 'sh' field for ADD/SUB immediate. by Jacob Bramley · 5 years ago
- fe7cb10 Compatibility fixes for scons using Python 3 by Matthew Bentham · 5 years ago
- 1af34f1 [sve] Implement gather load first-fault data to 64-bit vector (vector index). by TatWai Chong · 5 years ago
- 6537a9a [sve] Implement gather load first-fault data to 32-bit vector (vector index). by TatWai Chong · 5 years ago
- 823509b Merge branch 'master' into sve by Jacob Bramley · 5 years ago
- 504d5e9 Fix clang-format errors. by Jacob Bramley · 5 years ago
- 3db2c49 [sve] Implement prefetch instructions. by TatWai Chong · 5 years ago
- 8667956 Remove undefined casts to PrefetchOperation. by Jacob Bramley · 5 years ago
- 113d919 [sve] Implement gather load data to 32-bit vector (vector index). by TatWai Chong · 5 years ago
- 1a5dcd2 Merge "Merge branch 'master' into sve" into sve by Jacob Bramley · 5 years ago
- d9859c0 Merge branch 'master' into sve by Jacob Bramley · 5 years ago
- 85e1510 [sve] Implement load and broadcast data to vector. by TatWai Chong · 5 years ago
- b944bff [sve] Assert destination register is X for count-like instructions by Martyn Capewell · 5 years ago
- 991ee19 [simulator] Remove instruction instrumentation support. by Pierre Langlois · 5 years ago
- 2fe55ec Update clang tools to 4.0. by Jacob Bramley · 5 years ago
- fa3f6bf [sve] Implement indexed sdot and udot. by TatWai Chong · 5 years ago
- 3e2fb50 [sve] Implement ContiguousNonTemporalStore by Martyn Capewell · 5 years ago
- 72765d1 [sve] Implement ContiguousNonTemporalLoad by Martyn Capewell · 5 years ago
- 452ad8b [sve] Implement LoadAndBroadcastQuadword by Martyn Capewell · 5 years ago
- b2a19fa Remove bitfields from the CPURegister API. by Jacob Bramley · 5 years ago
- 8d4bbd2 Merge branch 'master' into sve by Jacob Bramley · 5 years ago