Merge branch 'main' into mte
diff --git a/SConstruct b/SConstruct
index bb8638c..934a81e 100644
--- a/SConstruct
+++ b/SConstruct
@@ -187,7 +187,7 @@
'AArch64. Set `target` to include `aarch64` or `a64`.')
-# Default variables may depend on each other, therefore we need this dictionnary
+# Default variables may depend on each other, therefore we need this dictionary
# to be ordered.
vars_default_handlers = OrderedDict({
# variable_name : [ 'default val', 'handler', 'validator']
diff --git a/benchmarks/aarch64/bench-utils.cc b/benchmarks/aarch64/bench-utils.cc
index d3ad507..04f56eb 100644
--- a/benchmarks/aarch64/bench-utils.cc
+++ b/benchmarks/aarch64/bench-utils.cc
@@ -306,7 +306,7 @@
void BenchCodeGenerator::BindAllPendingLabels() {
while (!labels_.empty()) {
- // BindPendingLables generates a branch over each block of bound labels.
+ // BindPendingLabels generates a branch over each block of bound labels.
// This will be repeated for each call here, but the effect is minimal and
// (empirically) we rarely accumulate more than 64 pending labels anyway.
BindPendingLabels(UINT64_MAX);
diff --git a/examples/aarch64/custom-disassembler.cc b/examples/aarch64/custom-disassembler.cc
index 9ea6aac..73ca489 100644
--- a/examples/aarch64/custom-disassembler.cc
+++ b/examples/aarch64/custom-disassembler.cc
@@ -106,7 +106,7 @@
// We override this method to add a comment to some instructions. Helpers from
// the vixl::Instruction class can be used to analyse the instruction being
-// disasssembled.
+// disassembled.
void CustomDisassembler::Visit(Metadata* metadata, const Instruction* instr) {
vixl::aarch64::Disassembler::Visit(metadata, instr);
const std::string& form = (*metadata)["form"];
diff --git a/examples/aarch64/neon-matrix-multiply.cc b/examples/aarch64/neon-matrix-multiply.cc
index f56c410..17fe70a 100644
--- a/examples/aarch64/neon-matrix-multiply.cc
+++ b/examples/aarch64/neon-matrix-multiply.cc
@@ -75,7 +75,7 @@
__ Ld1(v16.V4S(), v17.V4S(), v18.V4S(), v19.V4S(), MemOperand(x2));
// Initialise vectors of the output matrix with zeros.
- // This is only for the purposes of showing how this can be achived
+ // This is only for the purposes of showing how this can be achieved
// but technically this is not required because we overwrite all lanes
// of the output vectors.
__ Movi(v0.V16B(), 0);
diff --git a/src/aarch32/location-aarch32.h b/src/aarch32/location-aarch32.h
index 512b9c7..ae803f6 100644
--- a/src/aarch32/location-aarch32.h
+++ b/src/aarch32/location-aarch32.h
@@ -217,7 +217,7 @@
protected:
// Types passed to LocationBase. Must be distinct for unbound Locations (not
- // relevant for bound locations, as they don't have a correspoding
+ // relevant for bound locations, as they don't have a corresponding
// PoolObject).
static const int kRawLocation = 0; // Will not be used by the pool manager.
static const int kVeneerType = 1;
diff --git a/src/aarch32/macro-assembler-aarch32.cc b/src/aarch32/macro-assembler-aarch32.cc
index 56c0ffb..fa93fb3 100644
--- a/src/aarch32/macro-assembler-aarch32.cc
+++ b/src/aarch32/macro-assembler-aarch32.cc
@@ -599,7 +599,7 @@
Vmsr(FPSCR, tmp);
Pop(tmp);
Msr(APSR_nzcvqg, tmp);
- // Restore the regsisters.
+ // Restore the registers.
if (Has32DRegs()) Vpop(Untyped64, DRegisterList(d16, 16));
Vpop(Untyped64, DRegisterList(d0, 8));
Pop(RegisterList(saved_registers_mask));
diff --git a/src/aarch32/operands-aarch32.h b/src/aarch32/operands-aarch32.h
index 9a143d4..1f01d81 100644
--- a/src/aarch32/operands-aarch32.h
+++ b/src/aarch32/operands-aarch32.h
@@ -190,7 +190,7 @@
}
private:
-// Forbid implicitely creating operands around types that cannot be encoded
+// Forbid implicitly creating operands around types that cannot be encoded
// into a uint32_t without loss.
#if __cplusplus >= 201103L
Operand(int64_t) = delete; // NOLINT(runtime/explicit)
@@ -615,7 +615,7 @@
// - a shifted index register <Rm>, <shift> #<amount>
//
// The index register may have an associated {+/-} sign,
-// which if ommitted, defaults to + .
+// which if omitted, defaults to + .
//
// We have two constructors for the offset:
//
diff --git a/src/aarch64/cpu-features-auditor-aarch64.cc b/src/aarch64/cpu-features-auditor-aarch64.cc
index 1e5bfe3..692ca97 100644
--- a/src/aarch64/cpu-features-auditor-aarch64.cc
+++ b/src/aarch64/cpu-features-auditor-aarch64.cc
@@ -40,31 +40,33 @@
static const FormToVisitorFnMap form_to_visitor = {
DEFAULT_FORM_TO_VISITOR_MAP(CPUFeaturesAuditor),
SIM_AUD_VISITOR_MAP(CPUFeaturesAuditor),
- {"fcmla_asimdelem_c_h", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fcmla_asimdelem_c_s", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmlal2_asimdelem_lh", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmlal_asimdelem_lh", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmla_asimdelem_rh_h", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmla_asimdelem_r_sd", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmlsl2_asimdelem_lh", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmlsl_asimdelem_lh", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmls_asimdelem_rh_h", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmls_asimdelem_r_sd", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmulx_asimdelem_rh_h", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmulx_asimdelem_r_sd", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmul_asimdelem_rh_h", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"fmul_asimdelem_r_sd", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"sdot_asimdelem_d", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"smlal_asimdelem_l", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"smlsl_asimdelem_l", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"smull_asimdelem_l", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"sqdmlal_asimdelem_l", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"sqdmlsl_asimdelem_l", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"sqdmull_asimdelem_l", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"udot_asimdelem_d", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"umlal_asimdelem_l", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"umlsl_asimdelem_l", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
- {"umull_asimdelem_l", &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fcmla_asimdelem_c_h"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fcmla_asimdelem_c_s"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmlal2_asimdelem_lh"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmlal_asimdelem_lh"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmla_asimdelem_rh_h"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmla_asimdelem_r_sd"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmlsl2_asimdelem_lh"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmlsl_asimdelem_lh"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmls_asimdelem_rh_h"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmls_asimdelem_r_sd"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmulx_asimdelem_rh_h"_h,
+ &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmulx_asimdelem_r_sd"_h,
+ &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmul_asimdelem_rh_h"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"fmul_asimdelem_r_sd"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"sdot_asimdelem_d"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"smlal_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"smlsl_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"smull_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"sqdmlal_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"sqdmlsl_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"sqdmull_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"udot_asimdelem_d"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"umlal_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"umlsl_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
+ {"umull_asimdelem_l"_h, &CPUFeaturesAuditor::VisitNEONByIndexedElement},
};
return &form_to_visitor;
}
@@ -1401,363 +1403,368 @@
void CPUFeaturesAuditor::Visit(Metadata* metadata, const Instruction* instr) {
VIXL_ASSERT(metadata->count("form") > 0);
const std::string& form = (*metadata)["form"];
+ uint32_t form_hash = Hash(form.c_str());
const FormToVisitorFnMap* fv = CPUFeaturesAuditor::GetFormToVisitorFnMap();
- if ((fv->count(form) > 0) && fv->at(form)) {
- fv->at(form)(this, instr);
- } else {
+ FormToVisitorFnMap::const_iterator it = fv->find(form_hash);
+ if (it == fv->end()) {
RecordInstructionFeaturesScope scope(this);
- std::map<const std::string, const CPUFeatures> features = {
- {"adclb_z_zzz", CPUFeatures::kSVE2},
- {"adclt_z_zzz", CPUFeatures::kSVE2},
- {"addhnb_z_zz", CPUFeatures::kSVE2},
- {"addhnt_z_zz", CPUFeatures::kSVE2},
- {"addp_z_p_zz", CPUFeatures::kSVE2},
- {"bcax_z_zzz", CPUFeatures::kSVE2},
- {"bdep_z_zz",
+ std::map<uint32_t, const CPUFeatures> features = {
+ {"adclb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"adclt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"addhnb_z_zz"_h, CPUFeatures::kSVE2},
+ {"addhnt_z_zz"_h, CPUFeatures::kSVE2},
+ {"addp_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"bcax_z_zzz"_h, CPUFeatures::kSVE2},
+ {"bdep_z_zz"_h,
CPUFeatures(CPUFeatures::kSVE2, CPUFeatures::kSVEBitPerm)},
- {"bext_z_zz",
+ {"bext_z_zz"_h,
CPUFeatures(CPUFeatures::kSVE2, CPUFeatures::kSVEBitPerm)},
- {"bgrp_z_zz",
+ {"bgrp_z_zz"_h,
CPUFeatures(CPUFeatures::kSVE2, CPUFeatures::kSVEBitPerm)},
- {"bsl1n_z_zzz", CPUFeatures::kSVE2},
- {"bsl2n_z_zzz", CPUFeatures::kSVE2},
- {"bsl_z_zzz", CPUFeatures::kSVE2},
- {"cadd_z_zz", CPUFeatures::kSVE2},
- {"cdot_z_zzz", CPUFeatures::kSVE2},
- {"cdot_z_zzzi_d", CPUFeatures::kSVE2},
- {"cdot_z_zzzi_s", CPUFeatures::kSVE2},
- {"cmla_z_zzz", CPUFeatures::kSVE2},
- {"cmla_z_zzzi_h", CPUFeatures::kSVE2},
- {"cmla_z_zzzi_s", CPUFeatures::kSVE2},
- {"eor3_z_zzz", CPUFeatures::kSVE2},
- {"eorbt_z_zz", CPUFeatures::kSVE2},
- {"eortb_z_zz", CPUFeatures::kSVE2},
- {"ext_z_zi_con", CPUFeatures::kSVE2},
- {"faddp_z_p_zz", CPUFeatures::kSVE2},
- {"fcvtlt_z_p_z_h2s", CPUFeatures::kSVE2},
- {"fcvtlt_z_p_z_s2d", CPUFeatures::kSVE2},
- {"fcvtnt_z_p_z_d2s", CPUFeatures::kSVE2},
- {"fcvtnt_z_p_z_s2h", CPUFeatures::kSVE2},
- {"fcvtx_z_p_z_d2s", CPUFeatures::kSVE2},
- {"fcvtxnt_z_p_z_d2s", CPUFeatures::kSVE2},
- {"flogb_z_p_z", CPUFeatures::kSVE2},
- {"fmaxnmp_z_p_zz", CPUFeatures::kSVE2},
- {"fmaxp_z_p_zz", CPUFeatures::kSVE2},
- {"fminnmp_z_p_zz", CPUFeatures::kSVE2},
- {"fminp_z_p_zz", CPUFeatures::kSVE2},
- {"fmlalb_z_zzz", CPUFeatures::kSVE2},
- {"fmlalb_z_zzzi_s", CPUFeatures::kSVE2},
- {"fmlalt_z_zzz", CPUFeatures::kSVE2},
- {"fmlalt_z_zzzi_s", CPUFeatures::kSVE2},
- {"fmlslb_z_zzz", CPUFeatures::kSVE2},
- {"fmlslb_z_zzzi_s", CPUFeatures::kSVE2},
- {"fmlslt_z_zzz", CPUFeatures::kSVE2},
- {"fmlslt_z_zzzi_s", CPUFeatures::kSVE2},
- {"histcnt_z_p_zz", CPUFeatures::kSVE2},
- {"histseg_z_zz", CPUFeatures::kSVE2},
- {"ldnt1b_z_p_ar_d_64_unscaled", CPUFeatures::kSVE2},
- {"ldnt1b_z_p_ar_s_x32_unscaled", CPUFeatures::kSVE2},
- {"ldnt1d_z_p_ar_d_64_unscaled", CPUFeatures::kSVE2},
- {"ldnt1h_z_p_ar_d_64_unscaled", CPUFeatures::kSVE2},
- {"ldnt1h_z_p_ar_s_x32_unscaled", CPUFeatures::kSVE2},
- {"ldnt1sb_z_p_ar_d_64_unscaled", CPUFeatures::kSVE2},
- {"ldnt1sb_z_p_ar_s_x32_unscaled", CPUFeatures::kSVE2},
- {"ldnt1sh_z_p_ar_d_64_unscaled", CPUFeatures::kSVE2},
- {"ldnt1sh_z_p_ar_s_x32_unscaled", CPUFeatures::kSVE2},
- {"ldnt1sw_z_p_ar_d_64_unscaled", CPUFeatures::kSVE2},
- {"ldnt1w_z_p_ar_d_64_unscaled", CPUFeatures::kSVE2},
- {"ldnt1w_z_p_ar_s_x32_unscaled", CPUFeatures::kSVE2},
- {"match_p_p_zz", CPUFeatures::kSVE2},
- {"mla_z_zzzi_d", CPUFeatures::kSVE2},
- {"mla_z_zzzi_h", CPUFeatures::kSVE2},
- {"mla_z_zzzi_s", CPUFeatures::kSVE2},
- {"mls_z_zzzi_d", CPUFeatures::kSVE2},
- {"mls_z_zzzi_h", CPUFeatures::kSVE2},
- {"mls_z_zzzi_s", CPUFeatures::kSVE2},
- {"mul_z_zz", CPUFeatures::kSVE2},
- {"mul_z_zzi_d", CPUFeatures::kSVE2},
- {"mul_z_zzi_h", CPUFeatures::kSVE2},
- {"mul_z_zzi_s", CPUFeatures::kSVE2},
- {"nbsl_z_zzz", CPUFeatures::kSVE2},
- {"nmatch_p_p_zz", CPUFeatures::kSVE2},
- {"pmul_z_zz", CPUFeatures::kSVE2},
- {"pmullb_z_zz", CPUFeatures::kSVE2},
- {"pmullt_z_zz", CPUFeatures::kSVE2},
- {"raddhnb_z_zz", CPUFeatures::kSVE2},
- {"raddhnt_z_zz", CPUFeatures::kSVE2},
- {"rshrnb_z_zi", CPUFeatures::kSVE2},
- {"rshrnt_z_zi", CPUFeatures::kSVE2},
- {"rsubhnb_z_zz", CPUFeatures::kSVE2},
- {"rsubhnt_z_zz", CPUFeatures::kSVE2},
- {"saba_z_zzz", CPUFeatures::kSVE2},
- {"sabalb_z_zzz", CPUFeatures::kSVE2},
- {"sabalt_z_zzz", CPUFeatures::kSVE2},
- {"sabdlb_z_zz", CPUFeatures::kSVE2},
- {"sabdlt_z_zz", CPUFeatures::kSVE2},
- {"sadalp_z_p_z", CPUFeatures::kSVE2},
- {"saddlb_z_zz", CPUFeatures::kSVE2},
- {"saddlbt_z_zz", CPUFeatures::kSVE2},
- {"saddlt_z_zz", CPUFeatures::kSVE2},
- {"saddwb_z_zz", CPUFeatures::kSVE2},
- {"saddwt_z_zz", CPUFeatures::kSVE2},
- {"sbclb_z_zzz", CPUFeatures::kSVE2},
- {"sbclt_z_zzz", CPUFeatures::kSVE2},
- {"shadd_z_p_zz", CPUFeatures::kSVE2},
- {"shrnb_z_zi", CPUFeatures::kSVE2},
- {"shrnt_z_zi", CPUFeatures::kSVE2},
- {"shsub_z_p_zz", CPUFeatures::kSVE2},
- {"shsubr_z_p_zz", CPUFeatures::kSVE2},
- {"sli_z_zzi", CPUFeatures::kSVE2},
- {"smaxp_z_p_zz", CPUFeatures::kSVE2},
- {"sminp_z_p_zz", CPUFeatures::kSVE2},
- {"smlalb_z_zzz", CPUFeatures::kSVE2},
- {"smlalb_z_zzzi_d", CPUFeatures::kSVE2},
- {"smlalb_z_zzzi_s", CPUFeatures::kSVE2},
- {"smlalt_z_zzz", CPUFeatures::kSVE2},
- {"smlalt_z_zzzi_d", CPUFeatures::kSVE2},
- {"smlalt_z_zzzi_s", CPUFeatures::kSVE2},
- {"smlslb_z_zzz", CPUFeatures::kSVE2},
- {"smlslb_z_zzzi_d", CPUFeatures::kSVE2},
- {"smlslb_z_zzzi_s", CPUFeatures::kSVE2},
- {"smlslt_z_zzz", CPUFeatures::kSVE2},
- {"smlslt_z_zzzi_d", CPUFeatures::kSVE2},
- {"smlslt_z_zzzi_s", CPUFeatures::kSVE2},
- {"smulh_z_zz", CPUFeatures::kSVE2},
- {"smullb_z_zz", CPUFeatures::kSVE2},
- {"smullb_z_zzi_d", CPUFeatures::kSVE2},
- {"smullb_z_zzi_s", CPUFeatures::kSVE2},
- {"smullt_z_zz", CPUFeatures::kSVE2},
- {"smullt_z_zzi_d", CPUFeatures::kSVE2},
- {"smullt_z_zzi_s", CPUFeatures::kSVE2},
- {"splice_z_p_zz_con", CPUFeatures::kSVE2},
- {"sqabs_z_p_z", CPUFeatures::kSVE2},
- {"sqadd_z_p_zz", CPUFeatures::kSVE2},
- {"sqcadd_z_zz", CPUFeatures::kSVE2},
- {"sqdmlalb_z_zzz", CPUFeatures::kSVE2},
- {"sqdmlalb_z_zzzi_d", CPUFeatures::kSVE2},
- {"sqdmlalb_z_zzzi_s", CPUFeatures::kSVE2},
- {"sqdmlalbt_z_zzz", CPUFeatures::kSVE2},
- {"sqdmlalt_z_zzz", CPUFeatures::kSVE2},
- {"sqdmlalt_z_zzzi_d", CPUFeatures::kSVE2},
- {"sqdmlalt_z_zzzi_s", CPUFeatures::kSVE2},
- {"sqdmlslb_z_zzz", CPUFeatures::kSVE2},
- {"sqdmlslb_z_zzzi_d", CPUFeatures::kSVE2},
- {"sqdmlslb_z_zzzi_s", CPUFeatures::kSVE2},
- {"sqdmlslbt_z_zzz", CPUFeatures::kSVE2},
- {"sqdmlslt_z_zzz", CPUFeatures::kSVE2},
- {"sqdmlslt_z_zzzi_d", CPUFeatures::kSVE2},
- {"sqdmlslt_z_zzzi_s", CPUFeatures::kSVE2},
- {"sqdmulh_z_zz", CPUFeatures::kSVE2},
- {"sqdmulh_z_zzi_d", CPUFeatures::kSVE2},
- {"sqdmulh_z_zzi_h", CPUFeatures::kSVE2},
- {"sqdmulh_z_zzi_s", CPUFeatures::kSVE2},
- {"sqdmullb_z_zz", CPUFeatures::kSVE2},
- {"sqdmullb_z_zzi_d", CPUFeatures::kSVE2},
- {"sqdmullb_z_zzi_s", CPUFeatures::kSVE2},
- {"sqdmullt_z_zz", CPUFeatures::kSVE2},
- {"sqdmullt_z_zzi_d", CPUFeatures::kSVE2},
- {"sqdmullt_z_zzi_s", CPUFeatures::kSVE2},
- {"sqneg_z_p_z", CPUFeatures::kSVE2},
- {"sqrdcmlah_z_zzz", CPUFeatures::kSVE2},
- {"sqrdcmlah_z_zzzi_h", CPUFeatures::kSVE2},
- {"sqrdcmlah_z_zzzi_s", CPUFeatures::kSVE2},
- {"sqrdmlah_z_zzz", CPUFeatures::kSVE2},
- {"sqrdmlah_z_zzzi_d", CPUFeatures::kSVE2},
- {"sqrdmlah_z_zzzi_h", CPUFeatures::kSVE2},
- {"sqrdmlah_z_zzzi_s", CPUFeatures::kSVE2},
- {"sqrdmlsh_z_zzz", CPUFeatures::kSVE2},
- {"sqrdmlsh_z_zzzi_d", CPUFeatures::kSVE2},
- {"sqrdmlsh_z_zzzi_h", CPUFeatures::kSVE2},
- {"sqrdmlsh_z_zzzi_s", CPUFeatures::kSVE2},
- {"sqrdmulh_z_zz", CPUFeatures::kSVE2},
- {"sqrdmulh_z_zzi_d", CPUFeatures::kSVE2},
- {"sqrdmulh_z_zzi_h", CPUFeatures::kSVE2},
- {"sqrdmulh_z_zzi_s", CPUFeatures::kSVE2},
- {"sqrshl_z_p_zz", CPUFeatures::kSVE2},
- {"sqrshlr_z_p_zz", CPUFeatures::kSVE2},
- {"sqrshrnb_z_zi", CPUFeatures::kSVE2},
- {"sqrshrnt_z_zi", CPUFeatures::kSVE2},
- {"sqrshrunb_z_zi", CPUFeatures::kSVE2},
- {"sqrshrunt_z_zi", CPUFeatures::kSVE2},
- {"sqshl_z_p_zi", CPUFeatures::kSVE2},
- {"sqshl_z_p_zz", CPUFeatures::kSVE2},
- {"sqshlr_z_p_zz", CPUFeatures::kSVE2},
- {"sqshlu_z_p_zi", CPUFeatures::kSVE2},
- {"sqshrnb_z_zi", CPUFeatures::kSVE2},
- {"sqshrnt_z_zi", CPUFeatures::kSVE2},
- {"sqshrunb_z_zi", CPUFeatures::kSVE2},
- {"sqshrunt_z_zi", CPUFeatures::kSVE2},
- {"sqsub_z_p_zz", CPUFeatures::kSVE2},
- {"sqsubr_z_p_zz", CPUFeatures::kSVE2},
- {"sqxtnb_z_zz", CPUFeatures::kSVE2},
- {"sqxtnt_z_zz", CPUFeatures::kSVE2},
- {"sqxtunb_z_zz", CPUFeatures::kSVE2},
- {"sqxtunt_z_zz", CPUFeatures::kSVE2},
- {"srhadd_z_p_zz", CPUFeatures::kSVE2},
- {"sri_z_zzi", CPUFeatures::kSVE2},
- {"srshl_z_p_zz", CPUFeatures::kSVE2},
- {"srshlr_z_p_zz", CPUFeatures::kSVE2},
- {"srshr_z_p_zi", CPUFeatures::kSVE2},
- {"srsra_z_zi", CPUFeatures::kSVE2},
- {"sshllb_z_zi", CPUFeatures::kSVE2},
- {"sshllt_z_zi", CPUFeatures::kSVE2},
- {"ssra_z_zi", CPUFeatures::kSVE2},
- {"ssublb_z_zz", CPUFeatures::kSVE2},
- {"ssublbt_z_zz", CPUFeatures::kSVE2},
- {"ssublt_z_zz", CPUFeatures::kSVE2},
- {"ssubltb_z_zz", CPUFeatures::kSVE2},
- {"ssubwb_z_zz", CPUFeatures::kSVE2},
- {"ssubwt_z_zz", CPUFeatures::kSVE2},
- {"stnt1b_z_p_ar_d_64_unscaled", CPUFeatures::kSVE2},
- {"stnt1b_z_p_ar_s_x32_unscaled", CPUFeatures::kSVE2},
- {"stnt1d_z_p_ar_d_64_unscaled", CPUFeatures::kSVE2},
- {"stnt1h_z_p_ar_d_64_unscaled", CPUFeatures::kSVE2},
- {"stnt1h_z_p_ar_s_x32_unscaled", CPUFeatures::kSVE2},
- {"stnt1w_z_p_ar_d_64_unscaled", CPUFeatures::kSVE2},
- {"stnt1w_z_p_ar_s_x32_unscaled", CPUFeatures::kSVE2},
- {"subhnb_z_zz", CPUFeatures::kSVE2},
- {"subhnt_z_zz", CPUFeatures::kSVE2},
- {"suqadd_z_p_zz", CPUFeatures::kSVE2},
- {"tbl_z_zz_2", CPUFeatures::kSVE2},
- {"tbx_z_zz", CPUFeatures::kSVE2},
- {"uaba_z_zzz", CPUFeatures::kSVE2},
- {"uabalb_z_zzz", CPUFeatures::kSVE2},
- {"uabalt_z_zzz", CPUFeatures::kSVE2},
- {"uabdlb_z_zz", CPUFeatures::kSVE2},
- {"uabdlt_z_zz", CPUFeatures::kSVE2},
- {"uadalp_z_p_z", CPUFeatures::kSVE2},
- {"uaddlb_z_zz", CPUFeatures::kSVE2},
- {"uaddlt_z_zz", CPUFeatures::kSVE2},
- {"uaddwb_z_zz", CPUFeatures::kSVE2},
- {"uaddwt_z_zz", CPUFeatures::kSVE2},
- {"uhadd_z_p_zz", CPUFeatures::kSVE2},
- {"uhsub_z_p_zz", CPUFeatures::kSVE2},
- {"uhsubr_z_p_zz", CPUFeatures::kSVE2},
- {"umaxp_z_p_zz", CPUFeatures::kSVE2},
- {"uminp_z_p_zz", CPUFeatures::kSVE2},
- {"umlalb_z_zzz", CPUFeatures::kSVE2},
- {"umlalb_z_zzzi_d", CPUFeatures::kSVE2},
- {"umlalb_z_zzzi_s", CPUFeatures::kSVE2},
- {"umlalt_z_zzz", CPUFeatures::kSVE2},
- {"umlalt_z_zzzi_d", CPUFeatures::kSVE2},
- {"umlalt_z_zzzi_s", CPUFeatures::kSVE2},
- {"umlslb_z_zzz", CPUFeatures::kSVE2},
- {"umlslb_z_zzzi_d", CPUFeatures::kSVE2},
- {"umlslb_z_zzzi_s", CPUFeatures::kSVE2},
- {"umlslt_z_zzz", CPUFeatures::kSVE2},
- {"umlslt_z_zzzi_d", CPUFeatures::kSVE2},
- {"umlslt_z_zzzi_s", CPUFeatures::kSVE2},
- {"umulh_z_zz", CPUFeatures::kSVE2},
- {"umullb_z_zz", CPUFeatures::kSVE2},
- {"umullb_z_zzi_d", CPUFeatures::kSVE2},
- {"umullb_z_zzi_s", CPUFeatures::kSVE2},
- {"umullt_z_zz", CPUFeatures::kSVE2},
- {"umullt_z_zzi_d", CPUFeatures::kSVE2},
- {"umullt_z_zzi_s", CPUFeatures::kSVE2},
- {"uqadd_z_p_zz", CPUFeatures::kSVE2},
- {"uqrshl_z_p_zz", CPUFeatures::kSVE2},
- {"uqrshlr_z_p_zz", CPUFeatures::kSVE2},
- {"uqrshrnb_z_zi", CPUFeatures::kSVE2},
- {"uqrshrnt_z_zi", CPUFeatures::kSVE2},
- {"uqshl_z_p_zi", CPUFeatures::kSVE2},
- {"uqshl_z_p_zz", CPUFeatures::kSVE2},
- {"uqshlr_z_p_zz", CPUFeatures::kSVE2},
- {"uqshrnb_z_zi", CPUFeatures::kSVE2},
- {"uqshrnt_z_zi", CPUFeatures::kSVE2},
- {"uqsub_z_p_zz", CPUFeatures::kSVE2},
- {"uqsubr_z_p_zz", CPUFeatures::kSVE2},
- {"uqxtnb_z_zz", CPUFeatures::kSVE2},
- {"uqxtnt_z_zz", CPUFeatures::kSVE2},
- {"urecpe_z_p_z", CPUFeatures::kSVE2},
- {"urhadd_z_p_zz", CPUFeatures::kSVE2},
- {"urshl_z_p_zz", CPUFeatures::kSVE2},
- {"urshlr_z_p_zz", CPUFeatures::kSVE2},
- {"urshr_z_p_zi", CPUFeatures::kSVE2},
- {"ursqrte_z_p_z", CPUFeatures::kSVE2},
- {"ursra_z_zi", CPUFeatures::kSVE2},
- {"ushllb_z_zi", CPUFeatures::kSVE2},
- {"ushllt_z_zi", CPUFeatures::kSVE2},
- {"usqadd_z_p_zz", CPUFeatures::kSVE2},
- {"usra_z_zi", CPUFeatures::kSVE2},
- {"usublb_z_zz", CPUFeatures::kSVE2},
- {"usublt_z_zz", CPUFeatures::kSVE2},
- {"usubwb_z_zz", CPUFeatures::kSVE2},
- {"usubwt_z_zz", CPUFeatures::kSVE2},
- {"whilege_p_p_rr", CPUFeatures::kSVE2},
- {"whilegt_p_p_rr", CPUFeatures::kSVE2},
- {"whilehi_p_p_rr", CPUFeatures::kSVE2},
- {"whilehs_p_p_rr", CPUFeatures::kSVE2},
- {"whilerw_p_rr", CPUFeatures::kSVE2},
- {"whilewr_p_rr", CPUFeatures::kSVE2},
- {"xar_z_zzi", CPUFeatures::kSVE2},
- {"smmla_z_zzz", CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
- {"ummla_z_zzz", CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
- {"usmmla_z_zzz", CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
- {"fmmla_z_zzz_s",
+ {"bsl1n_z_zzz"_h, CPUFeatures::kSVE2},
+ {"bsl2n_z_zzz"_h, CPUFeatures::kSVE2},
+ {"bsl_z_zzz"_h, CPUFeatures::kSVE2},
+ {"cadd_z_zz"_h, CPUFeatures::kSVE2},
+ {"cdot_z_zzz"_h, CPUFeatures::kSVE2},
+ {"cdot_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"cdot_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"cmla_z_zzz"_h, CPUFeatures::kSVE2},
+ {"cmla_z_zzzi_h"_h, CPUFeatures::kSVE2},
+ {"cmla_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"eor3_z_zzz"_h, CPUFeatures::kSVE2},
+ {"eorbt_z_zz"_h, CPUFeatures::kSVE2},
+ {"eortb_z_zz"_h, CPUFeatures::kSVE2},
+ {"ext_z_zi_con"_h, CPUFeatures::kSVE2},
+ {"faddp_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"fcvtlt_z_p_z_h2s"_h, CPUFeatures::kSVE2},
+ {"fcvtlt_z_p_z_s2d"_h, CPUFeatures::kSVE2},
+ {"fcvtnt_z_p_z_d2s"_h, CPUFeatures::kSVE2},
+ {"fcvtnt_z_p_z_s2h"_h, CPUFeatures::kSVE2},
+ {"fcvtx_z_p_z_d2s"_h, CPUFeatures::kSVE2},
+ {"fcvtxnt_z_p_z_d2s"_h, CPUFeatures::kSVE2},
+ {"flogb_z_p_z"_h, CPUFeatures::kSVE2},
+ {"fmaxnmp_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"fmaxp_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"fminnmp_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"fminp_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"fmlalb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"fmlalb_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"fmlalt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"fmlalt_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"fmlslb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"fmlslb_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"fmlslt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"fmlslt_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"histcnt_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"histseg_z_zz"_h, CPUFeatures::kSVE2},
+ {"ldnt1b_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
+ {"ldnt1b_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
+ {"ldnt1d_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
+ {"ldnt1h_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
+ {"ldnt1h_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
+ {"ldnt1sb_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
+ {"ldnt1sb_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
+ {"ldnt1sh_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
+ {"ldnt1sh_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
+ {"ldnt1sw_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
+ {"ldnt1w_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
+ {"ldnt1w_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
+ {"match_p_p_zz"_h, CPUFeatures::kSVE2},
+ {"mla_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"mla_z_zzzi_h"_h, CPUFeatures::kSVE2},
+ {"mla_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"mls_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"mls_z_zzzi_h"_h, CPUFeatures::kSVE2},
+ {"mls_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"mul_z_zz"_h, CPUFeatures::kSVE2},
+ {"mul_z_zzi_d"_h, CPUFeatures::kSVE2},
+ {"mul_z_zzi_h"_h, CPUFeatures::kSVE2},
+ {"mul_z_zzi_s"_h, CPUFeatures::kSVE2},
+ {"nbsl_z_zzz"_h, CPUFeatures::kSVE2},
+ {"nmatch_p_p_zz"_h, CPUFeatures::kSVE2},
+ {"pmul_z_zz"_h, CPUFeatures::kSVE2},
+ {"pmullb_z_zz"_h, CPUFeatures::kSVE2},
+ {"pmullt_z_zz"_h, CPUFeatures::kSVE2},
+ {"raddhnb_z_zz"_h, CPUFeatures::kSVE2},
+ {"raddhnt_z_zz"_h, CPUFeatures::kSVE2},
+ {"rshrnb_z_zi"_h, CPUFeatures::kSVE2},
+ {"rshrnt_z_zi"_h, CPUFeatures::kSVE2},
+ {"rsubhnb_z_zz"_h, CPUFeatures::kSVE2},
+ {"rsubhnt_z_zz"_h, CPUFeatures::kSVE2},
+ {"saba_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sabalb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sabalt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sabdlb_z_zz"_h, CPUFeatures::kSVE2},
+ {"sabdlt_z_zz"_h, CPUFeatures::kSVE2},
+ {"sadalp_z_p_z"_h, CPUFeatures::kSVE2},
+ {"saddlb_z_zz"_h, CPUFeatures::kSVE2},
+ {"saddlbt_z_zz"_h, CPUFeatures::kSVE2},
+ {"saddlt_z_zz"_h, CPUFeatures::kSVE2},
+ {"saddwb_z_zz"_h, CPUFeatures::kSVE2},
+ {"saddwt_z_zz"_h, CPUFeatures::kSVE2},
+ {"sbclb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sbclt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"shadd_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"shrnb_z_zi"_h, CPUFeatures::kSVE2},
+ {"shrnt_z_zi"_h, CPUFeatures::kSVE2},
+ {"shsub_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"shsubr_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"sli_z_zzi"_h, CPUFeatures::kSVE2},
+ {"smaxp_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"sminp_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"smlalb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"smlalb_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"smlalb_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"smlalt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"smlalt_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"smlalt_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"smlslb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"smlslb_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"smlslb_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"smlslt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"smlslt_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"smlslt_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"smulh_z_zz"_h, CPUFeatures::kSVE2},
+ {"smullb_z_zz"_h, CPUFeatures::kSVE2},
+ {"smullb_z_zzi_d"_h, CPUFeatures::kSVE2},
+ {"smullb_z_zzi_s"_h, CPUFeatures::kSVE2},
+ {"smullt_z_zz"_h, CPUFeatures::kSVE2},
+ {"smullt_z_zzi_d"_h, CPUFeatures::kSVE2},
+ {"smullt_z_zzi_s"_h, CPUFeatures::kSVE2},
+ {"splice_z_p_zz_con"_h, CPUFeatures::kSVE2},
+ {"sqabs_z_p_z"_h, CPUFeatures::kSVE2},
+ {"sqadd_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"sqcadd_z_zz"_h, CPUFeatures::kSVE2},
+ {"sqdmlalb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sqdmlalb_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"sqdmlalb_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"sqdmlalbt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sqdmlalt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sqdmlalt_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"sqdmlalt_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"sqdmlslb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sqdmlslb_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"sqdmlslb_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"sqdmlslbt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sqdmlslt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sqdmlslt_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"sqdmlslt_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"sqdmulh_z_zz"_h, CPUFeatures::kSVE2},
+ {"sqdmulh_z_zzi_d"_h, CPUFeatures::kSVE2},
+ {"sqdmulh_z_zzi_h"_h, CPUFeatures::kSVE2},
+ {"sqdmulh_z_zzi_s"_h, CPUFeatures::kSVE2},
+ {"sqdmullb_z_zz"_h, CPUFeatures::kSVE2},
+ {"sqdmullb_z_zzi_d"_h, CPUFeatures::kSVE2},
+ {"sqdmullb_z_zzi_s"_h, CPUFeatures::kSVE2},
+ {"sqdmullt_z_zz"_h, CPUFeatures::kSVE2},
+ {"sqdmullt_z_zzi_d"_h, CPUFeatures::kSVE2},
+ {"sqdmullt_z_zzi_s"_h, CPUFeatures::kSVE2},
+ {"sqneg_z_p_z"_h, CPUFeatures::kSVE2},
+ {"sqrdcmlah_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sqrdcmlah_z_zzzi_h"_h, CPUFeatures::kSVE2},
+ {"sqrdcmlah_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"sqrdmlah_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sqrdmlah_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"sqrdmlah_z_zzzi_h"_h, CPUFeatures::kSVE2},
+ {"sqrdmlah_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"sqrdmlsh_z_zzz"_h, CPUFeatures::kSVE2},
+ {"sqrdmlsh_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"sqrdmlsh_z_zzzi_h"_h, CPUFeatures::kSVE2},
+ {"sqrdmlsh_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"sqrdmulh_z_zz"_h, CPUFeatures::kSVE2},
+ {"sqrdmulh_z_zzi_d"_h, CPUFeatures::kSVE2},
+ {"sqrdmulh_z_zzi_h"_h, CPUFeatures::kSVE2},
+ {"sqrdmulh_z_zzi_s"_h, CPUFeatures::kSVE2},
+ {"sqrshl_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"sqrshlr_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"sqrshrnb_z_zi"_h, CPUFeatures::kSVE2},
+ {"sqrshrnt_z_zi"_h, CPUFeatures::kSVE2},
+ {"sqrshrunb_z_zi"_h, CPUFeatures::kSVE2},
+ {"sqrshrunt_z_zi"_h, CPUFeatures::kSVE2},
+ {"sqshl_z_p_zi"_h, CPUFeatures::kSVE2},
+ {"sqshl_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"sqshlr_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"sqshlu_z_p_zi"_h, CPUFeatures::kSVE2},
+ {"sqshrnb_z_zi"_h, CPUFeatures::kSVE2},
+ {"sqshrnt_z_zi"_h, CPUFeatures::kSVE2},
+ {"sqshrunb_z_zi"_h, CPUFeatures::kSVE2},
+ {"sqshrunt_z_zi"_h, CPUFeatures::kSVE2},
+ {"sqsub_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"sqsubr_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"sqxtnb_z_zz"_h, CPUFeatures::kSVE2},
+ {"sqxtnt_z_zz"_h, CPUFeatures::kSVE2},
+ {"sqxtunb_z_zz"_h, CPUFeatures::kSVE2},
+ {"sqxtunt_z_zz"_h, CPUFeatures::kSVE2},
+ {"srhadd_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"sri_z_zzi"_h, CPUFeatures::kSVE2},
+ {"srshl_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"srshlr_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"srshr_z_p_zi"_h, CPUFeatures::kSVE2},
+ {"srsra_z_zi"_h, CPUFeatures::kSVE2},
+ {"sshllb_z_zi"_h, CPUFeatures::kSVE2},
+ {"sshllt_z_zi"_h, CPUFeatures::kSVE2},
+ {"ssra_z_zi"_h, CPUFeatures::kSVE2},
+ {"ssublb_z_zz"_h, CPUFeatures::kSVE2},
+ {"ssublbt_z_zz"_h, CPUFeatures::kSVE2},
+ {"ssublt_z_zz"_h, CPUFeatures::kSVE2},
+ {"ssubltb_z_zz"_h, CPUFeatures::kSVE2},
+ {"ssubwb_z_zz"_h, CPUFeatures::kSVE2},
+ {"ssubwt_z_zz"_h, CPUFeatures::kSVE2},
+ {"stnt1b_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
+ {"stnt1b_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
+ {"stnt1d_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
+ {"stnt1h_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
+ {"stnt1h_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
+ {"stnt1w_z_p_ar_d_64_unscaled"_h, CPUFeatures::kSVE2},
+ {"stnt1w_z_p_ar_s_x32_unscaled"_h, CPUFeatures::kSVE2},
+ {"subhnb_z_zz"_h, CPUFeatures::kSVE2},
+ {"subhnt_z_zz"_h, CPUFeatures::kSVE2},
+ {"suqadd_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"tbl_z_zz_2"_h, CPUFeatures::kSVE2},
+ {"tbx_z_zz"_h, CPUFeatures::kSVE2},
+ {"uaba_z_zzz"_h, CPUFeatures::kSVE2},
+ {"uabalb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"uabalt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"uabdlb_z_zz"_h, CPUFeatures::kSVE2},
+ {"uabdlt_z_zz"_h, CPUFeatures::kSVE2},
+ {"uadalp_z_p_z"_h, CPUFeatures::kSVE2},
+ {"uaddlb_z_zz"_h, CPUFeatures::kSVE2},
+ {"uaddlt_z_zz"_h, CPUFeatures::kSVE2},
+ {"uaddwb_z_zz"_h, CPUFeatures::kSVE2},
+ {"uaddwt_z_zz"_h, CPUFeatures::kSVE2},
+ {"uhadd_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"uhsub_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"uhsubr_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"umaxp_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"uminp_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"umlalb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"umlalb_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"umlalb_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"umlalt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"umlalt_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"umlalt_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"umlslb_z_zzz"_h, CPUFeatures::kSVE2},
+ {"umlslb_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"umlslb_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"umlslt_z_zzz"_h, CPUFeatures::kSVE2},
+ {"umlslt_z_zzzi_d"_h, CPUFeatures::kSVE2},
+ {"umlslt_z_zzzi_s"_h, CPUFeatures::kSVE2},
+ {"umulh_z_zz"_h, CPUFeatures::kSVE2},
+ {"umullb_z_zz"_h, CPUFeatures::kSVE2},
+ {"umullb_z_zzi_d"_h, CPUFeatures::kSVE2},
+ {"umullb_z_zzi_s"_h, CPUFeatures::kSVE2},
+ {"umullt_z_zz"_h, CPUFeatures::kSVE2},
+ {"umullt_z_zzi_d"_h, CPUFeatures::kSVE2},
+ {"umullt_z_zzi_s"_h, CPUFeatures::kSVE2},
+ {"uqadd_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"uqrshl_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"uqrshlr_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"uqrshrnb_z_zi"_h, CPUFeatures::kSVE2},
+ {"uqrshrnt_z_zi"_h, CPUFeatures::kSVE2},
+ {"uqshl_z_p_zi"_h, CPUFeatures::kSVE2},
+ {"uqshl_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"uqshlr_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"uqshrnb_z_zi"_h, CPUFeatures::kSVE2},
+ {"uqshrnt_z_zi"_h, CPUFeatures::kSVE2},
+ {"uqsub_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"uqsubr_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"uqxtnb_z_zz"_h, CPUFeatures::kSVE2},
+ {"uqxtnt_z_zz"_h, CPUFeatures::kSVE2},
+ {"urecpe_z_p_z"_h, CPUFeatures::kSVE2},
+ {"urhadd_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"urshl_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"urshlr_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"urshr_z_p_zi"_h, CPUFeatures::kSVE2},
+ {"ursqrte_z_p_z"_h, CPUFeatures::kSVE2},
+ {"ursra_z_zi"_h, CPUFeatures::kSVE2},
+ {"ushllb_z_zi"_h, CPUFeatures::kSVE2},
+ {"ushllt_z_zi"_h, CPUFeatures::kSVE2},
+ {"usqadd_z_p_zz"_h, CPUFeatures::kSVE2},
+ {"usra_z_zi"_h, CPUFeatures::kSVE2},
+ {"usublb_z_zz"_h, CPUFeatures::kSVE2},
+ {"usublt_z_zz"_h, CPUFeatures::kSVE2},
+ {"usubwb_z_zz"_h, CPUFeatures::kSVE2},
+ {"usubwt_z_zz"_h, CPUFeatures::kSVE2},
+ {"whilege_p_p_rr"_h, CPUFeatures::kSVE2},
+ {"whilegt_p_p_rr"_h, CPUFeatures::kSVE2},
+ {"whilehi_p_p_rr"_h, CPUFeatures::kSVE2},
+ {"whilehs_p_p_rr"_h, CPUFeatures::kSVE2},
+ {"whilerw_p_rr"_h, CPUFeatures::kSVE2},
+ {"whilewr_p_rr"_h, CPUFeatures::kSVE2},
+ {"xar_z_zzi"_h, CPUFeatures::kSVE2},
+ {"smmla_z_zzz"_h,
+ CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
+ {"ummla_z_zzz"_h,
+ CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
+ {"usmmla_z_zzz"_h,
+ CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
+ {"fmmla_z_zzz_s"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF32MM)},
- {"fmmla_z_zzz_d",
+ {"fmmla_z_zzz_d"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
- {"smmla_asimdsame2_g",
+ {"smmla_asimdsame2_g"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
- {"ummla_asimdsame2_g",
+ {"ummla_asimdsame2_g"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
- {"usmmla_asimdsame2_g",
+ {"usmmla_asimdsame2_g"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
- {"ld1row_z_p_bi_u32",
+ {"ld1row_z_p_bi_u32"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
- {"ld1row_z_p_br_contiguous",
+ {"ld1row_z_p_br_contiguous"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
- {"ld1rod_z_p_bi_u64",
+ {"ld1rod_z_p_bi_u64"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
- {"ld1rod_z_p_br_contiguous",
+ {"ld1rod_z_p_br_contiguous"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
- {"ld1rob_z_p_bi_u8",
+ {"ld1rob_z_p_bi_u8"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
- {"ld1rob_z_p_br_contiguous",
+ {"ld1rob_z_p_br_contiguous"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
- {"ld1roh_z_p_bi_u16",
+ {"ld1roh_z_p_bi_u16"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
- {"ld1roh_z_p_br_contiguous",
+ {"ld1roh_z_p_br_contiguous"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM)},
- {"usdot_asimdsame2_d",
+ {"usdot_asimdsame2_d"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
- {"sudot_asimdelem_d",
+ {"sudot_asimdelem_d"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
- {"usdot_asimdelem_d",
+ {"usdot_asimdelem_d"_h,
CPUFeatures(CPUFeatures::kNEON, CPUFeatures::kI8MM)},
- {"usdot_z_zzz_s",
+ {"usdot_z_zzz_s"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
- {"usdot_z_zzzi_s",
+ {"usdot_z_zzzi_s"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
- {"sudot_z_zzzi_s",
+ {"sudot_z_zzzi_s"_h,
CPUFeatures(CPUFeatures::kSVE, CPUFeatures::kSVEI8MM)},
- {"addg_64_addsub_immtags", CPUFeatures::kMTE},
- {"gmi_64g_dp_2src", CPUFeatures::kMTE},
- {"irg_64i_dp_2src", CPUFeatures::kMTE},
- {"ldg_64loffset_ldsttags", CPUFeatures::kMTE},
- {"st2g_64soffset_ldsttags", CPUFeatures::kMTE},
- {"st2g_64spost_ldsttags", CPUFeatures::kMTE},
- {"st2g_64spre_ldsttags", CPUFeatures::kMTE},
- {"stgp_64_ldstpair_off", CPUFeatures::kMTE},
- {"stgp_64_ldstpair_post", CPUFeatures::kMTE},
- {"stgp_64_ldstpair_pre", CPUFeatures::kMTE},
- {"stg_64soffset_ldsttags", CPUFeatures::kMTE},
- {"stg_64spost_ldsttags", CPUFeatures::kMTE},
- {"stg_64spre_ldsttags", CPUFeatures::kMTE},
- {"stz2g_64soffset_ldsttags", CPUFeatures::kMTE},
- {"stz2g_64spost_ldsttags", CPUFeatures::kMTE},
- {"stz2g_64spre_ldsttags", CPUFeatures::kMTE},
- {"stzg_64soffset_ldsttags", CPUFeatures::kMTE},
- {"stzg_64spost_ldsttags", CPUFeatures::kMTE},
- {"stzg_64spre_ldsttags", CPUFeatures::kMTE},
- {"subg_64_addsub_immtags", CPUFeatures::kMTE},
- {"subps_64s_dp_2src", CPUFeatures::kMTE},
- {"subp_64s_dp_2src", CPUFeatures::kMTE},
+ {"addg_64_addsub_immtags"_h, CPUFeatures::kMTE},
+ {"gmi_64g_dp_2src"_h, CPUFeatures::kMTE},
+ {"irg_64i_dp_2src"_h, CPUFeatures::kMTE},
+ {"ldg_64loffset_ldsttags"_h, CPUFeatures::kMTE},
+ {"st2g_64soffset_ldsttags"_h, CPUFeatures::kMTE},
+ {"st2g_64spost_ldsttags"_h, CPUFeatures::kMTE},
+ {"st2g_64spre_ldsttags"_h, CPUFeatures::kMTE},
+ {"stgp_64_ldstpair_off"_h, CPUFeatures::kMTE},
+ {"stgp_64_ldstpair_post"_h, CPUFeatures::kMTE},
+ {"stgp_64_ldstpair_pre"_h, CPUFeatures::kMTE},
+ {"stg_64soffset_ldsttags"_h, CPUFeatures::kMTE},
+ {"stg_64spost_ldsttags"_h, CPUFeatures::kMTE},
+ {"stg_64spre_ldsttags"_h, CPUFeatures::kMTE},
+ {"stz2g_64soffset_ldsttags"_h, CPUFeatures::kMTE},
+ {"stz2g_64spost_ldsttags"_h, CPUFeatures::kMTE},
+ {"stz2g_64spre_ldsttags"_h, CPUFeatures::kMTE},
+ {"stzg_64soffset_ldsttags"_h, CPUFeatures::kMTE},
+ {"stzg_64spost_ldsttags"_h, CPUFeatures::kMTE},
+ {"stzg_64spre_ldsttags"_h, CPUFeatures::kMTE},
+ {"subg_64_addsub_immtags"_h, CPUFeatures::kMTE},
+ {"subps_64s_dp_2src"_h, CPUFeatures::kMTE},
+ {"subp_64s_dp_2src"_h, CPUFeatures::kMTE},
};
- if (features.count(form) > 0) {
- scope.Record(features[form]);
+ if (features.count(form_hash) > 0) {
+ scope.Record(features[form_hash]);
}
+ } else {
+ (it->second)(this, instr);
}
}
diff --git a/src/aarch64/cpu-features-auditor-aarch64.h b/src/aarch64/cpu-features-auditor-aarch64.h
index 7329def..041bc88 100644
--- a/src/aarch64/cpu-features-auditor-aarch64.h
+++ b/src/aarch64/cpu-features-auditor-aarch64.h
@@ -123,7 +123,7 @@
Decoder* decoder_;
using FormToVisitorFnMap = std::unordered_map<
- std::string,
+ uint32_t,
std::function<void(CPUFeaturesAuditor*, const Instruction*)>>;
static const FormToVisitorFnMap* GetFormToVisitorFnMap();
};
diff --git a/src/aarch64/decoder-aarch64.cc b/src/aarch64/decoder-aarch64.cc
index 0abea63..a4e2989 100644
--- a/src/aarch64/decoder-aarch64.cc
+++ b/src/aarch64/decoder-aarch64.cc
@@ -49,7 +49,9 @@
}
void Decoder::AddDecodeNode(const DecodeNode& node) {
- decode_nodes_.insert(std::make_pair(node.GetName(), node));
+ if (decode_nodes_.count(node.GetName()) == 0) {
+ decode_nodes_.insert(std::make_pair(node.GetName(), node));
+ }
}
DecodeNode* Decoder::GetDecodeNode(std::string name) {
@@ -64,12 +66,21 @@
// Add all of the decoding nodes to the Decoder.
for (unsigned i = 0; i < ArrayLength(kDecodeMapping); i++) {
AddDecodeNode(DecodeNode(kDecodeMapping[i], this));
+
+ // Add a node for each instruction form named, identified by having no '_'
+ // prefix on the node name.
+ const DecodeMapping& map = kDecodeMapping[i];
+ for (unsigned j = 0; j < map.mapping.size(); j++) {
+ if ((map.mapping[j].handler != NULL) &&
+ (map.mapping[j].handler[0] != '_')) {
+ AddDecodeNode(DecodeNode(map.mapping[j].handler, this));
+ }
+ }
}
- // Add the visitor function wrapping nodes to the Decoder.
- for (unsigned i = 0; i < ArrayLength(kVisitorNodes); i++) {
- AddDecodeNode(DecodeNode(kVisitorNodes[i], this));
- }
+ // Add an "unallocated" node, used when an instruction encoding is not
+ // recognised by the decoding graph.
+ AddDecodeNode(DecodeNode("unallocated", this));
// Compile the graph from the root.
compiled_decoder_root_ = GetDecodeNode("Root")->Compile(this);
@@ -122,42 +133,18 @@
visitors_.remove(visitor);
}
-#define DEFINE_VISITOR_CALLERS(A) \
- void Decoder::Visit_##A(const Instruction* instr) { \
- std::list<DecoderVisitor*>::iterator it; \
- Metadata m = {{"form", #A}}; \
- for (it = visitors_.begin(); it != visitors_.end(); it++) { \
- (*it)->Visit(&m, instr); \
- } \
- }
-INSTRUCTION_VISITOR_LIST(DEFINE_VISITOR_CALLERS)
-#undef DEFINE_VISITOR_CALLERS
-
-void DecodeNode::SetSampledBits(const uint8_t* bits, int bit_count) {
- VIXL_ASSERT(!IsCompiled());
-
- sampled_bits_.resize(bit_count);
- for (int i = 0; i < bit_count; i++) {
- sampled_bits_[i] = bits[i];
+void Decoder::VisitNamedInstruction(const Instruction* instr,
+ const std::string& name) {
+ std::list<DecoderVisitor*>::iterator it;
+ Metadata m = {{"form", name}};
+ for (it = visitors_.begin(); it != visitors_.end(); it++) {
+ (*it)->Visit(&m, instr);
}
}
-std::vector<uint8_t> DecodeNode::GetSampledBits() const {
- return sampled_bits_;
-}
-
-size_t DecodeNode::GetSampledBitsCount() const { return sampled_bits_.size(); }
-
-void DecodeNode::AddPatterns(const DecodePattern* patterns) {
- VIXL_ASSERT(!IsCompiled());
- for (unsigned i = 0; i < kMaxDecodeMappings; i++) {
- // Empty string indicates end of patterns.
- if (patterns[i].pattern == NULL) break;
- VIXL_ASSERT((strlen(patterns[i].pattern) == GetSampledBitsCount()) ||
- (strcmp(patterns[i].pattern, "otherwise") == 0));
- pattern_table_.push_back(patterns[i]);
- }
-}
+// Initialise empty vectors for sampled bits and pattern table.
+const std::vector<uint8_t> DecodeNode::kEmptySampledBits;
+const std::vector<DecodePattern> DecodeNode::kEmptyPatternTable;
void DecodeNode::CompileNodeForBits(Decoder* decoder,
std::string name,
@@ -418,21 +405,22 @@
if ((table_size <= 2) && (GetSampledBitsCount() > 1)) {
// TODO: support 'x' in this optimisation by dropping the sampled bit
// positions before making the mask/value.
- if ((strchr(pattern_table_[0].pattern, 'x') == NULL) &&
- ((table_size == 1) ||
- (strcmp(pattern_table_[1].pattern, "otherwise") == 0))) {
+ if (!PatternContainsSymbol(pattern_table_[0].pattern,
+ PatternSymbol::kSymbolX) &&
+ (table_size == 1)) {
// A pattern table consisting of a fixed pattern with no x's, and an
// "otherwise" or absent case. Optimise this into an instruction mask and
// value test.
uint32_t single_decode_mask = 0;
uint32_t single_decode_value = 0;
- std::vector<uint8_t> bits = GetSampledBits();
+ const std::vector<uint8_t>& bits = GetSampledBits();
// Construct the instruction mask and value from the pattern.
- VIXL_ASSERT(bits.size() == strlen(pattern_table_[0].pattern));
+ VIXL_ASSERT(bits.size() == GetPatternLength(pattern_table_[0].pattern));
for (size_t i = 0; i < bits.size(); i++) {
single_decode_mask |= 1U << bits[i];
- if (pattern_table_[0].pattern[i] == '1') {
+ if (GetSymbolAt(pattern_table_[0].pattern, i) ==
+ PatternSymbol::kSymbol1) {
single_decode_value |= 1U << bits[i];
}
}
@@ -445,9 +433,7 @@
// Set DecodeNode for when the instruction after masking doesn't match the
// value.
- const char* doesnt_match_handler =
- (table_size == 1) ? "Visit_Unallocated" : pattern_table_[1].handler;
- CompileNodeForBits(decoder, doesnt_match_handler, 0);
+ CompileNodeForBits(decoder, "unallocated", 0);
// Set DecodeNode for when it does match.
CompileNodeForBits(decoder, pattern_table_[0].handler, 1);
@@ -465,21 +451,14 @@
CreateVisitorNode();
} else if (!TryCompileOptimisedDecodeTable(decoder)) {
// The "otherwise" node is the default next node if no pattern matches.
- std::string otherwise = "Visit_Unallocated";
+ std::string otherwise = "unallocated";
// For each pattern in pattern_table_, create an entry in matches that
// has a corresponding mask and value for the pattern.
std::vector<MaskValuePair> matches;
for (size_t i = 0; i < pattern_table_.size(); i++) {
- if (strcmp(pattern_table_[i].pattern, "otherwise") == 0) {
- // "otherwise" must be the last pattern in the list, otherwise the
- // indices won't match for pattern_table_ and matches.
- VIXL_ASSERT(i == pattern_table_.size() - 1);
- otherwise = pattern_table_[i].handler;
- } else {
- matches.push_back(GenerateMaskValuePair(
- GenerateOrderedPattern(pattern_table_[i].pattern)));
- }
+ matches.push_back(GenerateMaskValuePair(
+ GenerateOrderedPattern(pattern_table_[i].pattern)));
}
BitExtractFn bit_extract_fn =
@@ -520,7 +499,7 @@
if (IsLeafNode()) {
// If this node is a leaf, call the registered visitor function.
VIXL_ASSERT(decoder_ != NULL);
- (decoder_->*visitor_fn_)(instr);
+ decoder_->VisitNamedInstruction(instr, instruction_name_);
} else {
// Otherwise, using the sampled bit extractor for this node, look up the
// next node in the decode tree, and call its Decode method.
@@ -532,41 +511,53 @@
}
DecodeNode::MaskValuePair DecodeNode::GenerateMaskValuePair(
- std::string pattern) const {
+ uint32_t pattern) const {
uint32_t mask = 0, value = 0;
- for (size_t i = 0; i < pattern.size(); i++) {
- mask |= ((pattern[i] == 'x') ? 0 : 1) << i;
- value |= ((pattern[i] == '1') ? 1 : 0) << i;
+ for (size_t i = 0; i < GetPatternLength(pattern); i++) {
+ PatternSymbol sym = GetSymbolAt(pattern, i);
+ mask = (mask << 1) | ((sym == PatternSymbol::kSymbolX) ? 0 : 1);
+ value = (value << 1) | (static_cast<uint32_t>(sym) & 1);
}
return std::make_pair(mask, value);
}
-std::string DecodeNode::GenerateOrderedPattern(std::string pattern) const {
- std::vector<uint8_t> sampled_bits = GetSampledBits();
- // Construct a temporary 32-character string containing '_', then at each
- // sampled bit position, set the corresponding pattern character.
- std::string temp(32, '_');
+uint32_t DecodeNode::GenerateOrderedPattern(uint32_t pattern) const {
+ const std::vector<uint8_t>& sampled_bits = GetSampledBits();
+ uint64_t temp = 0xffffffffffffffff;
+
+ // Place symbols into the field of set bits. Symbols are two bits wide and
+ // take values 0, 1 or 2, so 3 will represent "no symbol".
for (size_t i = 0; i < sampled_bits.size(); i++) {
- temp[sampled_bits[i]] = pattern[i];
+ int shift = sampled_bits[i] * 2;
+ temp ^= static_cast<uint64_t>(kEndOfPattern) << shift;
+ temp |= static_cast<uint64_t>(GetSymbolAt(pattern, i)) << shift;
}
- // Iterate through the temporary string, filtering out the non-'_' characters
- // into a new ordered pattern result string.
- std::string result;
- for (size_t i = 0; i < temp.size(); i++) {
- if (temp[i] != '_') {
- result.push_back(temp[i]);
+ // Iterate over temp and extract new pattern ordered by sample position.
+ uint32_t result = kEndOfPattern; // End of pattern marker.
+
+ // Iterate over the pattern one symbol (two bits) at a time.
+ for (int i = 62; i >= 0; i -= 2) {
+ uint32_t sym = (temp >> i) & kPatternSymbolMask;
+
+ // If this is a valid symbol, shift into the result.
+ if (sym != kEndOfPattern) {
+ result = (result << 2) | sym;
}
}
- VIXL_ASSERT(result.size() == sampled_bits.size());
+
+ // The length of the ordered pattern must be the same as the input pattern,
+ // and the number of sampled bits.
+ VIXL_ASSERT(GetPatternLength(result) == GetPatternLength(pattern));
+ VIXL_ASSERT(GetPatternLength(result) == sampled_bits.size());
+
return result;
}
uint32_t DecodeNode::GenerateSampledBitsMask() const {
- std::vector<uint8_t> sampled_bits = GetSampledBits();
uint32_t mask = 0;
- for (size_t i = 0; i < sampled_bits.size(); i++) {
- mask |= 1 << sampled_bits[i];
+ for (int bit : GetSampledBits()) {
+ mask |= 1 << bit;
}
return mask;
}
diff --git a/src/aarch64/decoder-aarch64.h b/src/aarch64/decoder-aarch64.h
index af849ac..22c66e8 100644
--- a/src/aarch64/decoder-aarch64.h
+++ b/src/aarch64/decoder-aarch64.h
@@ -36,2642 +36,6 @@
#include "instructions-aarch64.h"
// List macro containing all visitors needed by the decoder class.
-#define INSTRUCTION_VISITOR_LIST(V) \
- V(abs_asimdmisc_r) \
- V(abs_asisdmisc_r) \
- V(abs_z_p_z) \
- V(adc_32_addsub_carry) \
- V(adc_64_addsub_carry) \
- V(adclb_z_zzz) \
- V(adclt_z_zzz) \
- V(adcs_32_addsub_carry) \
- V(adcs_64_addsub_carry) \
- V(add_32_addsub_ext) \
- V(add_32_addsub_imm) \
- V(add_32_addsub_shift) \
- V(add_64_addsub_ext) \
- V(add_64_addsub_imm) \
- V(add_64_addsub_shift) \
- V(add_asimdsame_only) \
- V(add_asisdsame_only) \
- V(add_z_p_zz) \
- V(add_z_zi) \
- V(add_z_zz) \
- V(addg_64_addsub_immtags) \
- V(addhn_asimddiff_n) \
- V(addhnb_z_zz) \
- V(addhnt_z_zz) \
- V(addp_asimdsame_only) \
- V(addp_asisdpair_only) \
- V(addp_z_p_zz) \
- V(addpl_r_ri) \
- V(adds_32_addsub_shift) \
- V(adds_32s_addsub_ext) \
- V(adds_32s_addsub_imm) \
- V(adds_64_addsub_shift) \
- V(adds_64s_addsub_ext) \
- V(adds_64s_addsub_imm) \
- V(addv_asimdall_only) \
- V(addvl_r_ri) \
- V(adr_only_pcreladdr) \
- V(adr_z_az_d_s32_scaled) \
- V(adr_z_az_d_u32_scaled) \
- V(adr_z_az_sd_same_scaled) \
- V(adrp_only_pcreladdr) \
- V(aesd_b_cryptoaes) \
- V(aesd_z_zz) \
- V(aese_b_cryptoaes) \
- V(aese_z_zz) \
- V(aesimc_b_cryptoaes) \
- V(aesimc_z_z) \
- V(aesmc_b_cryptoaes) \
- V(aesmc_z_z) \
- V(and_32_log_imm) \
- V(and_32_log_shift) \
- V(and_64_log_imm) \
- V(and_64_log_shift) \
- V(and_asimdsame_only) \
- V(and_p_p_pp_z) \
- V(and_z_p_zz) \
- V(and_z_zi) \
- V(and_z_zz) \
- V(ands_32_log_shift) \
- V(ands_32s_log_imm) \
- V(ands_64_log_shift) \
- V(ands_64s_log_imm) \
- V(ands_p_p_pp_z) \
- V(andv_r_p_z) \
- V(asr_z_p_zi) \
- V(asr_z_p_zw) \
- V(asr_z_p_zz) \
- V(asr_z_zi) \
- V(asr_z_zw) \
- V(asrd_z_p_zi) \
- V(asrr_z_p_zz) \
- V(asrv_32_dp_2src) \
- V(asrv_64_dp_2src) \
- V(autda_64p_dp_1src) \
- V(autdb_64p_dp_1src) \
- V(autdza_64z_dp_1src) \
- V(autdzb_64z_dp_1src) \
- V(autia1716_hi_hints) \
- V(autia_64p_dp_1src) \
- V(autiasp_hi_hints) \
- V(autiaz_hi_hints) \
- V(autib1716_hi_hints) \
- V(autib_64p_dp_1src) \
- V(autibsp_hi_hints) \
- V(autibz_hi_hints) \
- V(autiza_64z_dp_1src) \
- V(autizb_64z_dp_1src) \
- V(axflag_m_pstate) \
- V(b_only_branch_imm) \
- V(b_only_condbranch) \
- V(bcax_vvv16_crypto4) \
- V(bcax_z_zzz) \
- V(bdep_z_zz) \
- V(bext_z_zz) \
- V(bfcvt_bs_floatdp1) \
- V(bfcvt_z_p_z_s2bf) \
- V(bfcvtn_asimdmisc_4s) \
- V(bfcvtnt_z_p_z_s2bf) \
- V(bfdot_asimdelem_e) \
- V(bfdot_asimdsame2_d) \
- V(bfdot_z_zzz) \
- V(bfdot_z_zzzi) \
- V(bfm_32m_bitfield) \
- V(bfm_64m_bitfield) \
- V(bfmlal_asimdelem_f) \
- V(bfmlal_asimdsame2_f) \
- V(bfmlalb_z_zzz) \
- V(bfmlalb_z_zzzi) \
- V(bfmlalt_z_zzz) \
- V(bfmlalt_z_zzzi) \
- V(bfmmla_asimdsame2_e) \
- V(bfmmla_z_zzz) \
- V(bgrp_z_zz) \
- V(bic_32_log_shift) \
- V(bic_64_log_shift) \
- V(bic_asimdimm_l_hl) \
- V(bic_asimdimm_l_sl) \
- V(bic_asimdsame_only) \
- V(bic_p_p_pp_z) \
- V(bic_z_p_zz) \
- V(bic_z_zz) \
- V(bics_32_log_shift) \
- V(bics_64_log_shift) \
- V(bics_p_p_pp_z) \
- V(bif_asimdsame_only) \
- V(bit_asimdsame_only) \
- V(bl_only_branch_imm) \
- V(blr_64_branch_reg) \
- V(blraa_64p_branch_reg) \
- V(blraaz_64_branch_reg) \
- V(blrab_64p_branch_reg) \
- V(blrabz_64_branch_reg) \
- V(br_64_branch_reg) \
- V(braa_64p_branch_reg) \
- V(braaz_64_branch_reg) \
- V(brab_64p_branch_reg) \
- V(brabz_64_branch_reg) \
- V(brk_ex_exception) \
- V(brka_p_p_p) \
- V(brkas_p_p_p_z) \
- V(brkb_p_p_p) \
- V(brkbs_p_p_p_z) \
- V(brkn_p_p_pp) \
- V(brkns_p_p_pp) \
- V(brkpa_p_p_pp) \
- V(brkpas_p_p_pp) \
- V(brkpb_p_p_pp) \
- V(brkpbs_p_p_pp) \
- V(bsl1n_z_zzz) \
- V(bsl2n_z_zzz) \
- V(bsl_asimdsame_only) \
- V(bsl_z_zzz) \
- V(bti_hb_hints) \
- V(cadd_z_zz) \
- V(cas_c32_ldstexcl) \
- V(cas_c64_ldstexcl) \
- V(casa_c32_ldstexcl) \
- V(casa_c64_ldstexcl) \
- V(casab_c32_ldstexcl) \
- V(casah_c32_ldstexcl) \
- V(casal_c32_ldstexcl) \
- V(casal_c64_ldstexcl) \
- V(casalb_c32_ldstexcl) \
- V(casalh_c32_ldstexcl) \
- V(casb_c32_ldstexcl) \
- V(cash_c32_ldstexcl) \
- V(casl_c32_ldstexcl) \
- V(casl_c64_ldstexcl) \
- V(caslb_c32_ldstexcl) \
- V(caslh_c32_ldstexcl) \
- V(casp_cp32_ldstexcl) \
- V(casp_cp64_ldstexcl) \
- V(caspa_cp32_ldstexcl) \
- V(caspa_cp64_ldstexcl) \
- V(caspal_cp32_ldstexcl) \
- V(caspal_cp64_ldstexcl) \
- V(caspl_cp32_ldstexcl) \
- V(caspl_cp64_ldstexcl) \
- V(cbnz_32_compbranch) \
- V(cbnz_64_compbranch) \
- V(cbz_32_compbranch) \
- V(cbz_64_compbranch) \
- V(ccmn_32_condcmp_imm) \
- V(ccmn_32_condcmp_reg) \
- V(ccmn_64_condcmp_imm) \
- V(ccmn_64_condcmp_reg) \
- V(ccmp_32_condcmp_imm) \
- V(ccmp_32_condcmp_reg) \
- V(ccmp_64_condcmp_imm) \
- V(ccmp_64_condcmp_reg) \
- V(cdot_z_zzz) \
- V(cdot_z_zzzi_d) \
- V(cdot_z_zzzi_s) \
- V(cfinv_m_pstate) \
- V(clasta_r_p_z) \
- V(clasta_v_p_z) \
- V(clasta_z_p_zz) \
- V(clastb_r_p_z) \
- V(clastb_v_p_z) \
- V(clastb_z_p_zz) \
- V(clrex_bn_barriers) \
- V(cls_32_dp_1src) \
- V(cls_64_dp_1src) \
- V(cls_asimdmisc_r) \
- V(cls_z_p_z) \
- V(clz_32_dp_1src) \
- V(clz_64_dp_1src) \
- V(clz_asimdmisc_r) \
- V(clz_z_p_z) \
- V(cmeq_asimdmisc_z) \
- V(cmeq_asimdsame_only) \
- V(cmeq_asisdmisc_z) \
- V(cmeq_asisdsame_only) \
- V(cmge_asimdmisc_z) \
- V(cmge_asimdsame_only) \
- V(cmge_asisdmisc_z) \
- V(cmge_asisdsame_only) \
- V(cmgt_asimdmisc_z) \
- V(cmgt_asimdsame_only) \
- V(cmgt_asisdmisc_z) \
- V(cmgt_asisdsame_only) \
- V(cmhi_asimdsame_only) \
- V(cmhi_asisdsame_only) \
- V(cmhs_asimdsame_only) \
- V(cmhs_asisdsame_only) \
- V(cmla_z_zzz) \
- V(cmla_z_zzzi_h) \
- V(cmla_z_zzzi_s) \
- V(cmle_asimdmisc_z) \
- V(cmle_asisdmisc_z) \
- V(cmlt_asimdmisc_z) \
- V(cmlt_asisdmisc_z) \
- V(cmpeq_p_p_zi) \
- V(cmpeq_p_p_zw) \
- V(cmpeq_p_p_zz) \
- V(cmpge_p_p_zi) \
- V(cmpge_p_p_zw) \
- V(cmpge_p_p_zz) \
- V(cmpgt_p_p_zi) \
- V(cmpgt_p_p_zw) \
- V(cmpgt_p_p_zz) \
- V(cmphi_p_p_zi) \
- V(cmphi_p_p_zw) \
- V(cmphi_p_p_zz) \
- V(cmphs_p_p_zi) \
- V(cmphs_p_p_zw) \
- V(cmphs_p_p_zz) \
- V(cmple_p_p_zi) \
- V(cmple_p_p_zw) \
- V(cmplo_p_p_zi) \
- V(cmplo_p_p_zw) \
- V(cmpls_p_p_zi) \
- V(cmpls_p_p_zw) \
- V(cmplt_p_p_zi) \
- V(cmplt_p_p_zw) \
- V(cmpne_p_p_zi) \
- V(cmpne_p_p_zw) \
- V(cmpne_p_p_zz) \
- V(cmtst_asimdsame_only) \
- V(cmtst_asisdsame_only) \
- V(cnot_z_p_z) \
- V(cnt_asimdmisc_r) \
- V(cnt_z_p_z) \
- V(cntb_r_s) \
- V(cntd_r_s) \
- V(cnth_r_s) \
- V(cntp_r_p_p) \
- V(cntw_r_s) \
- V(compact_z_p_z) \
- V(cpy_z_o_i) \
- V(cpy_z_p_i) \
- V(cpy_z_p_r) \
- V(cpy_z_p_v) \
- V(crc32b_32c_dp_2src) \
- V(crc32cb_32c_dp_2src) \
- V(crc32ch_32c_dp_2src) \
- V(crc32cw_32c_dp_2src) \
- V(crc32cx_64c_dp_2src) \
- V(crc32h_32c_dp_2src) \
- V(crc32w_32c_dp_2src) \
- V(crc32x_64c_dp_2src) \
- V(csdb_hi_hints) \
- V(csel_32_condsel) \
- V(csel_64_condsel) \
- V(csinc_32_condsel) \
- V(csinc_64_condsel) \
- V(csinv_32_condsel) \
- V(csinv_64_condsel) \
- V(csneg_32_condsel) \
- V(csneg_64_condsel) \
- V(ctermeq_rr) \
- V(ctermne_rr) \
- V(dcps1_dc_exception) \
- V(dcps2_dc_exception) \
- V(dcps3_dc_exception) \
- V(decb_r_rs) \
- V(decd_r_rs) \
- V(decd_z_zs) \
- V(dech_r_rs) \
- V(dech_z_zs) \
- V(decp_r_p_r) \
- V(decp_z_p_z) \
- V(decw_r_rs) \
- V(decw_z_zs) \
- V(dgh_hi_hints) \
- V(dmb_bo_barriers) \
- V(drps_64e_branch_reg) \
- V(dsb_bo_barriers) \
- V(dsb_bon_barriers) \
- V(dup_asimdins_dr_r) \
- V(dup_asimdins_dv_v) \
- V(dup_asisdone_only) \
- V(dup_z_i) \
- V(dup_z_r) \
- V(dup_z_zi) \
- V(dupm_z_i) \
- V(eon_32_log_shift) \
- V(eon_64_log_shift) \
- V(eor3_vvv16_crypto4) \
- V(eor3_z_zzz) \
- V(eor_32_log_imm) \
- V(eor_32_log_shift) \
- V(eor_64_log_imm) \
- V(eor_64_log_shift) \
- V(eor_asimdsame_only) \
- V(eor_p_p_pp_z) \
- V(eor_z_p_zz) \
- V(eor_z_zi) \
- V(eor_z_zz) \
- V(eorbt_z_zz) \
- V(eors_p_p_pp_z) \
- V(eortb_z_zz) \
- V(eorv_r_p_z) \
- V(eret_64e_branch_reg) \
- V(eretaa_64e_branch_reg) \
- V(eretab_64e_branch_reg) \
- V(esb_hi_hints) \
- V(ext_asimdext_only) \
- V(ext_z_zi_con) \
- V(ext_z_zi_des) \
- V(extr_32_extract) \
- V(extr_64_extract) \
- V(fabd_asimdsame_only) \
- V(fabd_asimdsamefp16_only) \
- V(fabd_asisdsame_only) \
- V(fabd_asisdsamefp16_only) \
- V(fabd_z_p_zz) \
- V(fabs_asimdmisc_r) \
- V(fabs_asimdmiscfp16_r) \
- V(fabs_d_floatdp1) \
- V(fabs_h_floatdp1) \
- V(fabs_s_floatdp1) \
- V(fabs_z_p_z) \
- V(facge_asimdsame_only) \
- V(facge_asimdsamefp16_only) \
- V(facge_asisdsame_only) \
- V(facge_asisdsamefp16_only) \
- V(facge_p_p_zz) \
- V(facgt_asimdsame_only) \
- V(facgt_asimdsamefp16_only) \
- V(facgt_asisdsame_only) \
- V(facgt_asisdsamefp16_only) \
- V(facgt_p_p_zz) \
- V(fadd_asimdsame_only) \
- V(fadd_asimdsamefp16_only) \
- V(fadd_d_floatdp2) \
- V(fadd_h_floatdp2) \
- V(fadd_s_floatdp2) \
- V(fadd_z_p_zs) \
- V(fadd_z_p_zz) \
- V(fadd_z_zz) \
- V(fadda_v_p_z) \
- V(faddp_asimdsame_only) \
- V(faddp_asimdsamefp16_only) \
- V(faddp_asisdpair_only_h) \
- V(faddp_asisdpair_only_sd) \
- V(faddp_z_p_zz) \
- V(faddv_v_p_z) \
- V(fcadd_asimdsame2_c) \
- V(fcadd_z_p_zz) \
- V(fccmp_d_floatccmp) \
- V(fccmp_h_floatccmp) \
- V(fccmp_s_floatccmp) \
- V(fccmpe_d_floatccmp) \
- V(fccmpe_h_floatccmp) \
- V(fccmpe_s_floatccmp) \
- V(fcmeq_asimdmisc_fz) \
- V(fcmeq_asimdmiscfp16_fz) \
- V(fcmeq_asimdsame_only) \
- V(fcmeq_asimdsamefp16_only) \
- V(fcmeq_asisdmisc_fz) \
- V(fcmeq_asisdmiscfp16_fz) \
- V(fcmeq_asisdsame_only) \
- V(fcmeq_asisdsamefp16_only) \
- V(fcmeq_p_p_z0) \
- V(fcmeq_p_p_zz) \
- V(fcmge_asimdmisc_fz) \
- V(fcmge_asimdmiscfp16_fz) \
- V(fcmge_asimdsame_only) \
- V(fcmge_asimdsamefp16_only) \
- V(fcmge_asisdmisc_fz) \
- V(fcmge_asisdmiscfp16_fz) \
- V(fcmge_asisdsame_only) \
- V(fcmge_asisdsamefp16_only) \
- V(fcmge_p_p_z0) \
- V(fcmge_p_p_zz) \
- V(fcmgt_asimdmisc_fz) \
- V(fcmgt_asimdmiscfp16_fz) \
- V(fcmgt_asimdsame_only) \
- V(fcmgt_asimdsamefp16_only) \
- V(fcmgt_asisdmisc_fz) \
- V(fcmgt_asisdmiscfp16_fz) \
- V(fcmgt_asisdsame_only) \
- V(fcmgt_asisdsamefp16_only) \
- V(fcmgt_p_p_z0) \
- V(fcmgt_p_p_zz) \
- V(fcmla_asimdelem_c_h) \
- V(fcmla_asimdelem_c_s) \
- V(fcmla_asimdsame2_c) \
- V(fcmla_z_p_zzz) \
- V(fcmla_z_zzzi_h) \
- V(fcmla_z_zzzi_s) \
- V(fcmle_asimdmisc_fz) \
- V(fcmle_asimdmiscfp16_fz) \
- V(fcmle_asisdmisc_fz) \
- V(fcmle_asisdmiscfp16_fz) \
- V(fcmle_p_p_z0) \
- V(fcmlt_asimdmisc_fz) \
- V(fcmlt_asimdmiscfp16_fz) \
- V(fcmlt_asisdmisc_fz) \
- V(fcmlt_asisdmiscfp16_fz) \
- V(fcmlt_p_p_z0) \
- V(fcmne_p_p_z0) \
- V(fcmne_p_p_zz) \
- V(fcmp_d_floatcmp) \
- V(fcmp_dz_floatcmp) \
- V(fcmp_h_floatcmp) \
- V(fcmp_hz_floatcmp) \
- V(fcmp_s_floatcmp) \
- V(fcmp_sz_floatcmp) \
- V(fcmpe_d_floatcmp) \
- V(fcmpe_dz_floatcmp) \
- V(fcmpe_h_floatcmp) \
- V(fcmpe_hz_floatcmp) \
- V(fcmpe_s_floatcmp) \
- V(fcmpe_sz_floatcmp) \
- V(fcmuo_p_p_zz) \
- V(fcpy_z_p_i) \
- V(fcsel_d_floatsel) \
- V(fcsel_h_floatsel) \
- V(fcsel_s_floatsel) \
- V(fcvt_dh_floatdp1) \
- V(fcvt_ds_floatdp1) \
- V(fcvt_hd_floatdp1) \
- V(fcvt_hs_floatdp1) \
- V(fcvt_sd_floatdp1) \
- V(fcvt_sh_floatdp1) \
- V(fcvt_z_p_z_d2h) \
- V(fcvt_z_p_z_d2s) \
- V(fcvt_z_p_z_h2d) \
- V(fcvt_z_p_z_h2s) \
- V(fcvt_z_p_z_s2d) \
- V(fcvt_z_p_z_s2h) \
- V(fcvtas_32d_float2int) \
- V(fcvtas_32h_float2int) \
- V(fcvtas_32s_float2int) \
- V(fcvtas_64d_float2int) \
- V(fcvtas_64h_float2int) \
- V(fcvtas_64s_float2int) \
- V(fcvtas_asimdmisc_r) \
- V(fcvtas_asimdmiscfp16_r) \
- V(fcvtas_asisdmisc_r) \
- V(fcvtas_asisdmiscfp16_r) \
- V(fcvtau_32d_float2int) \
- V(fcvtau_32h_float2int) \
- V(fcvtau_32s_float2int) \
- V(fcvtau_64d_float2int) \
- V(fcvtau_64h_float2int) \
- V(fcvtau_64s_float2int) \
- V(fcvtau_asimdmisc_r) \
- V(fcvtau_asimdmiscfp16_r) \
- V(fcvtau_asisdmisc_r) \
- V(fcvtau_asisdmiscfp16_r) \
- V(fcvtl_asimdmisc_l) \
- V(fcvtlt_z_p_z_h2s) \
- V(fcvtlt_z_p_z_s2d) \
- V(fcvtms_32d_float2int) \
- V(fcvtms_32h_float2int) \
- V(fcvtms_32s_float2int) \
- V(fcvtms_64d_float2int) \
- V(fcvtms_64h_float2int) \
- V(fcvtms_64s_float2int) \
- V(fcvtms_asimdmisc_r) \
- V(fcvtms_asimdmiscfp16_r) \
- V(fcvtms_asisdmisc_r) \
- V(fcvtms_asisdmiscfp16_r) \
- V(fcvtmu_32d_float2int) \
- V(fcvtmu_32h_float2int) \
- V(fcvtmu_32s_float2int) \
- V(fcvtmu_64d_float2int) \
- V(fcvtmu_64h_float2int) \
- V(fcvtmu_64s_float2int) \
- V(fcvtmu_asimdmisc_r) \
- V(fcvtmu_asimdmiscfp16_r) \
- V(fcvtmu_asisdmisc_r) \
- V(fcvtmu_asisdmiscfp16_r) \
- V(fcvtn_asimdmisc_n) \
- V(fcvtns_32d_float2int) \
- V(fcvtns_32h_float2int) \
- V(fcvtns_32s_float2int) \
- V(fcvtns_64d_float2int) \
- V(fcvtns_64h_float2int) \
- V(fcvtns_64s_float2int) \
- V(fcvtns_asimdmisc_r) \
- V(fcvtns_asimdmiscfp16_r) \
- V(fcvtns_asisdmisc_r) \
- V(fcvtns_asisdmiscfp16_r) \
- V(fcvtnt_z_p_z_d2s) \
- V(fcvtnt_z_p_z_s2h) \
- V(fcvtnu_32d_float2int) \
- V(fcvtnu_32h_float2int) \
- V(fcvtnu_32s_float2int) \
- V(fcvtnu_64d_float2int) \
- V(fcvtnu_64h_float2int) \
- V(fcvtnu_64s_float2int) \
- V(fcvtnu_asimdmisc_r) \
- V(fcvtnu_asimdmiscfp16_r) \
- V(fcvtnu_asisdmisc_r) \
- V(fcvtnu_asisdmiscfp16_r) \
- V(fcvtps_32d_float2int) \
- V(fcvtps_32h_float2int) \
- V(fcvtps_32s_float2int) \
- V(fcvtps_64d_float2int) \
- V(fcvtps_64h_float2int) \
- V(fcvtps_64s_float2int) \
- V(fcvtps_asimdmisc_r) \
- V(fcvtps_asimdmiscfp16_r) \
- V(fcvtps_asisdmisc_r) \
- V(fcvtps_asisdmiscfp16_r) \
- V(fcvtpu_32d_float2int) \
- V(fcvtpu_32h_float2int) \
- V(fcvtpu_32s_float2int) \
- V(fcvtpu_64d_float2int) \
- V(fcvtpu_64h_float2int) \
- V(fcvtpu_64s_float2int) \
- V(fcvtpu_asimdmisc_r) \
- V(fcvtpu_asimdmiscfp16_r) \
- V(fcvtpu_asisdmisc_r) \
- V(fcvtpu_asisdmiscfp16_r) \
- V(fcvtx_z_p_z_d2s) \
- V(fcvtxn_asimdmisc_n) \
- V(fcvtxn_asisdmisc_n) \
- V(fcvtxnt_z_p_z_d2s) \
- V(fcvtzs_32d_float2fix) \
- V(fcvtzs_32d_float2int) \
- V(fcvtzs_32h_float2fix) \
- V(fcvtzs_32h_float2int) \
- V(fcvtzs_32s_float2fix) \
- V(fcvtzs_32s_float2int) \
- V(fcvtzs_64d_float2fix) \
- V(fcvtzs_64d_float2int) \
- V(fcvtzs_64h_float2fix) \
- V(fcvtzs_64h_float2int) \
- V(fcvtzs_64s_float2fix) \
- V(fcvtzs_64s_float2int) \
- V(fcvtzs_asimdmisc_r) \
- V(fcvtzs_asimdmiscfp16_r) \
- V(fcvtzs_asimdshf_c) \
- V(fcvtzs_asisdmisc_r) \
- V(fcvtzs_asisdmiscfp16_r) \
- V(fcvtzs_asisdshf_c) \
- V(fcvtzs_z_p_z_d2w) \
- V(fcvtzs_z_p_z_d2x) \
- V(fcvtzs_z_p_z_fp162h) \
- V(fcvtzs_z_p_z_fp162w) \
- V(fcvtzs_z_p_z_fp162x) \
- V(fcvtzs_z_p_z_s2w) \
- V(fcvtzs_z_p_z_s2x) \
- V(fcvtzu_32d_float2fix) \
- V(fcvtzu_32d_float2int) \
- V(fcvtzu_32h_float2fix) \
- V(fcvtzu_32h_float2int) \
- V(fcvtzu_32s_float2fix) \
- V(fcvtzu_32s_float2int) \
- V(fcvtzu_64d_float2fix) \
- V(fcvtzu_64d_float2int) \
- V(fcvtzu_64h_float2fix) \
- V(fcvtzu_64h_float2int) \
- V(fcvtzu_64s_float2fix) \
- V(fcvtzu_64s_float2int) \
- V(fcvtzu_asimdmisc_r) \
- V(fcvtzu_asimdmiscfp16_r) \
- V(fcvtzu_asimdshf_c) \
- V(fcvtzu_asisdmisc_r) \
- V(fcvtzu_asisdmiscfp16_r) \
- V(fcvtzu_asisdshf_c) \
- V(fcvtzu_z_p_z_d2w) \
- V(fcvtzu_z_p_z_d2x) \
- V(fcvtzu_z_p_z_fp162h) \
- V(fcvtzu_z_p_z_fp162w) \
- V(fcvtzu_z_p_z_fp162x) \
- V(fcvtzu_z_p_z_s2w) \
- V(fcvtzu_z_p_z_s2x) \
- V(fdiv_asimdsame_only) \
- V(fdiv_asimdsamefp16_only) \
- V(fdiv_d_floatdp2) \
- V(fdiv_h_floatdp2) \
- V(fdiv_s_floatdp2) \
- V(fdiv_z_p_zz) \
- V(fdivr_z_p_zz) \
- V(fdup_z_i) \
- V(fexpa_z_z) \
- V(fjcvtzs_32d_float2int) \
- V(flogb_z_p_z) \
- V(fmad_z_p_zzz) \
- V(fmadd_d_floatdp3) \
- V(fmadd_h_floatdp3) \
- V(fmadd_s_floatdp3) \
- V(fmax_asimdsame_only) \
- V(fmax_asimdsamefp16_only) \
- V(fmax_d_floatdp2) \
- V(fmax_h_floatdp2) \
- V(fmax_s_floatdp2) \
- V(fmax_z_p_zs) \
- V(fmax_z_p_zz) \
- V(fmaxnm_asimdsame_only) \
- V(fmaxnm_asimdsamefp16_only) \
- V(fmaxnm_d_floatdp2) \
- V(fmaxnm_h_floatdp2) \
- V(fmaxnm_s_floatdp2) \
- V(fmaxnm_z_p_zs) \
- V(fmaxnm_z_p_zz) \
- V(fmaxnmp_asimdsame_only) \
- V(fmaxnmp_asimdsamefp16_only) \
- V(fmaxnmp_asisdpair_only_h) \
- V(fmaxnmp_asisdpair_only_sd) \
- V(fmaxnmp_z_p_zz) \
- V(fmaxnmv_asimdall_only_h) \
- V(fmaxnmv_asimdall_only_sd) \
- V(fmaxnmv_v_p_z) \
- V(fmaxp_asimdsame_only) \
- V(fmaxp_asimdsamefp16_only) \
- V(fmaxp_asisdpair_only_h) \
- V(fmaxp_asisdpair_only_sd) \
- V(fmaxp_z_p_zz) \
- V(fmaxv_asimdall_only_h) \
- V(fmaxv_asimdall_only_sd) \
- V(fmaxv_v_p_z) \
- V(fmin_asimdsame_only) \
- V(fmin_asimdsamefp16_only) \
- V(fmin_d_floatdp2) \
- V(fmin_h_floatdp2) \
- V(fmin_s_floatdp2) \
- V(fmin_z_p_zs) \
- V(fmin_z_p_zz) \
- V(fminnm_asimdsame_only) \
- V(fminnm_asimdsamefp16_only) \
- V(fminnm_d_floatdp2) \
- V(fminnm_h_floatdp2) \
- V(fminnm_s_floatdp2) \
- V(fminnm_z_p_zs) \
- V(fminnm_z_p_zz) \
- V(fminnmp_asimdsame_only) \
- V(fminnmp_asimdsamefp16_only) \
- V(fminnmp_asisdpair_only_h) \
- V(fminnmp_asisdpair_only_sd) \
- V(fminnmp_z_p_zz) \
- V(fminnmv_asimdall_only_h) \
- V(fminnmv_asimdall_only_sd) \
- V(fminnmv_v_p_z) \
- V(fminp_asimdsame_only) \
- V(fminp_asimdsamefp16_only) \
- V(fminp_asisdpair_only_h) \
- V(fminp_asisdpair_only_sd) \
- V(fminp_z_p_zz) \
- V(fminv_asimdall_only_h) \
- V(fminv_asimdall_only_sd) \
- V(fminv_v_p_z) \
- V(fmla_asimdelem_r_sd) \
- V(fmla_asimdelem_rh_h) \
- V(fmla_asimdsame_only) \
- V(fmla_asimdsamefp16_only) \
- V(fmla_asisdelem_r_sd) \
- V(fmla_asisdelem_rh_h) \
- V(fmla_z_p_zzz) \
- V(fmla_z_zzzi_d) \
- V(fmla_z_zzzi_h) \
- V(fmla_z_zzzi_s) \
- V(fmlal2_asimdelem_lh) \
- V(fmlal2_asimdsame_f) \
- V(fmlal_asimdelem_lh) \
- V(fmlal_asimdsame_f) \
- V(fmlalb_z_zzz) \
- V(fmlalb_z_zzzi_s) \
- V(fmlalt_z_zzz) \
- V(fmlalt_z_zzzi_s) \
- V(fmls_asimdelem_r_sd) \
- V(fmls_asimdelem_rh_h) \
- V(fmls_asimdsame_only) \
- V(fmls_asimdsamefp16_only) \
- V(fmls_asisdelem_r_sd) \
- V(fmls_asisdelem_rh_h) \
- V(fmls_z_p_zzz) \
- V(fmls_z_zzzi_d) \
- V(fmls_z_zzzi_h) \
- V(fmls_z_zzzi_s) \
- V(fmlsl2_asimdelem_lh) \
- V(fmlsl2_asimdsame_f) \
- V(fmlsl_asimdelem_lh) \
- V(fmlsl_asimdsame_f) \
- V(fmlslb_z_zzz) \
- V(fmlslb_z_zzzi_s) \
- V(fmlslt_z_zzz) \
- V(fmlslt_z_zzzi_s) \
- V(fmmla_z_zzz_d) \
- V(fmmla_z_zzz_s) \
- V(fmov_32h_float2int) \
- V(fmov_32s_float2int) \
- V(fmov_64d_float2int) \
- V(fmov_64h_float2int) \
- V(fmov_64vx_float2int) \
- V(fmov_asimdimm_d2_d) \
- V(fmov_asimdimm_h_h) \
- V(fmov_asimdimm_s_s) \
- V(fmov_d64_float2int) \
- V(fmov_d_floatdp1) \
- V(fmov_d_floatimm) \
- V(fmov_h32_float2int) \
- V(fmov_h64_float2int) \
- V(fmov_h_floatdp1) \
- V(fmov_h_floatimm) \
- V(fmov_s32_float2int) \
- V(fmov_s_floatdp1) \
- V(fmov_s_floatimm) \
- V(fmov_v64i_float2int) \
- V(fmsb_z_p_zzz) \
- V(fmsub_d_floatdp3) \
- V(fmsub_h_floatdp3) \
- V(fmsub_s_floatdp3) \
- V(fmul_asimdelem_r_sd) \
- V(fmul_asimdelem_rh_h) \
- V(fmul_asimdsame_only) \
- V(fmul_asimdsamefp16_only) \
- V(fmul_asisdelem_r_sd) \
- V(fmul_asisdelem_rh_h) \
- V(fmul_d_floatdp2) \
- V(fmul_h_floatdp2) \
- V(fmul_s_floatdp2) \
- V(fmul_z_p_zs) \
- V(fmul_z_p_zz) \
- V(fmul_z_zz) \
- V(fmul_z_zzi_d) \
- V(fmul_z_zzi_h) \
- V(fmul_z_zzi_s) \
- V(fmulx_asimdelem_r_sd) \
- V(fmulx_asimdelem_rh_h) \
- V(fmulx_asimdsame_only) \
- V(fmulx_asimdsamefp16_only) \
- V(fmulx_asisdelem_r_sd) \
- V(fmulx_asisdelem_rh_h) \
- V(fmulx_asisdsame_only) \
- V(fmulx_asisdsamefp16_only) \
- V(fmulx_z_p_zz) \
- V(fneg_asimdmisc_r) \
- V(fneg_asimdmiscfp16_r) \
- V(fneg_d_floatdp1) \
- V(fneg_h_floatdp1) \
- V(fneg_s_floatdp1) \
- V(fneg_z_p_z) \
- V(fnmad_z_p_zzz) \
- V(fnmadd_d_floatdp3) \
- V(fnmadd_h_floatdp3) \
- V(fnmadd_s_floatdp3) \
- V(fnmla_z_p_zzz) \
- V(fnmls_z_p_zzz) \
- V(fnmsb_z_p_zzz) \
- V(fnmsub_d_floatdp3) \
- V(fnmsub_h_floatdp3) \
- V(fnmsub_s_floatdp3) \
- V(fnmul_d_floatdp2) \
- V(fnmul_h_floatdp2) \
- V(fnmul_s_floatdp2) \
- V(frecpe_asimdmisc_r) \
- V(frecpe_asimdmiscfp16_r) \
- V(frecpe_asisdmisc_r) \
- V(frecpe_asisdmiscfp16_r) \
- V(frecpe_z_z) \
- V(frecps_asimdsame_only) \
- V(frecps_asimdsamefp16_only) \
- V(frecps_asisdsame_only) \
- V(frecps_asisdsamefp16_only) \
- V(frecps_z_zz) \
- V(frecpx_asisdmisc_r) \
- V(frecpx_asisdmiscfp16_r) \
- V(frecpx_z_p_z) \
- V(frint32x_asimdmisc_r) \
- V(frint32x_d_floatdp1) \
- V(frint32x_s_floatdp1) \
- V(frint32z_asimdmisc_r) \
- V(frint32z_d_floatdp1) \
- V(frint32z_s_floatdp1) \
- V(frint64x_asimdmisc_r) \
- V(frint64x_d_floatdp1) \
- V(frint64x_s_floatdp1) \
- V(frint64z_asimdmisc_r) \
- V(frint64z_d_floatdp1) \
- V(frint64z_s_floatdp1) \
- V(frinta_asimdmisc_r) \
- V(frinta_asimdmiscfp16_r) \
- V(frinta_d_floatdp1) \
- V(frinta_h_floatdp1) \
- V(frinta_s_floatdp1) \
- V(frinta_z_p_z) \
- V(frinti_asimdmisc_r) \
- V(frinti_asimdmiscfp16_r) \
- V(frinti_d_floatdp1) \
- V(frinti_h_floatdp1) \
- V(frinti_s_floatdp1) \
- V(frinti_z_p_z) \
- V(frintm_asimdmisc_r) \
- V(frintm_asimdmiscfp16_r) \
- V(frintm_d_floatdp1) \
- V(frintm_h_floatdp1) \
- V(frintm_s_floatdp1) \
- V(frintm_z_p_z) \
- V(frintn_asimdmisc_r) \
- V(frintn_asimdmiscfp16_r) \
- V(frintn_d_floatdp1) \
- V(frintn_h_floatdp1) \
- V(frintn_s_floatdp1) \
- V(frintn_z_p_z) \
- V(frintp_asimdmisc_r) \
- V(frintp_asimdmiscfp16_r) \
- V(frintp_d_floatdp1) \
- V(frintp_h_floatdp1) \
- V(frintp_s_floatdp1) \
- V(frintp_z_p_z) \
- V(frintx_asimdmisc_r) \
- V(frintx_asimdmiscfp16_r) \
- V(frintx_d_floatdp1) \
- V(frintx_h_floatdp1) \
- V(frintx_s_floatdp1) \
- V(frintx_z_p_z) \
- V(frintz_asimdmisc_r) \
- V(frintz_asimdmiscfp16_r) \
- V(frintz_d_floatdp1) \
- V(frintz_h_floatdp1) \
- V(frintz_s_floatdp1) \
- V(frintz_z_p_z) \
- V(frsqrte_asimdmisc_r) \
- V(frsqrte_asimdmiscfp16_r) \
- V(frsqrte_asisdmisc_r) \
- V(frsqrte_asisdmiscfp16_r) \
- V(frsqrte_z_z) \
- V(frsqrts_asimdsame_only) \
- V(frsqrts_asimdsamefp16_only) \
- V(frsqrts_asisdsame_only) \
- V(frsqrts_asisdsamefp16_only) \
- V(frsqrts_z_zz) \
- V(fscale_z_p_zz) \
- V(fsqrt_asimdmisc_r) \
- V(fsqrt_asimdmiscfp16_r) \
- V(fsqrt_d_floatdp1) \
- V(fsqrt_h_floatdp1) \
- V(fsqrt_s_floatdp1) \
- V(fsqrt_z_p_z) \
- V(fsub_asimdsame_only) \
- V(fsub_asimdsamefp16_only) \
- V(fsub_d_floatdp2) \
- V(fsub_h_floatdp2) \
- V(fsub_s_floatdp2) \
- V(fsub_z_p_zs) \
- V(fsub_z_p_zz) \
- V(fsub_z_zz) \
- V(fsubr_z_p_zs) \
- V(fsubr_z_p_zz) \
- V(ftmad_z_zzi) \
- V(ftsmul_z_zz) \
- V(ftssel_z_zz) \
- V(gmi_64g_dp_2src) \
- V(hint_hm_hints) \
- V(histcnt_z_p_zz) \
- V(histseg_z_zz) \
- V(hlt_ex_exception) \
- V(hvc_ex_exception) \
- V(incb_r_rs) \
- V(incd_r_rs) \
- V(incd_z_zs) \
- V(inch_r_rs) \
- V(inch_z_zs) \
- V(incp_r_p_r) \
- V(incp_z_p_z) \
- V(incw_r_rs) \
- V(incw_z_zs) \
- V(index_z_ii) \
- V(index_z_ir) \
- V(index_z_ri) \
- V(index_z_rr) \
- V(ins_asimdins_ir_r) \
- V(ins_asimdins_iv_v) \
- V(insr_z_r) \
- V(insr_z_v) \
- V(irg_64i_dp_2src) \
- V(isb_bi_barriers) \
- V(lasta_r_p_z) \
- V(lasta_v_p_z) \
- V(lastb_r_p_z) \
- V(lastb_v_p_z) \
- V(ld1_asisdlse_r1_1v) \
- V(ld1_asisdlse_r2_2v) \
- V(ld1_asisdlse_r3_3v) \
- V(ld1_asisdlse_r4_4v) \
- V(ld1_asisdlsep_i1_i1) \
- V(ld1_asisdlsep_i2_i2) \
- V(ld1_asisdlsep_i3_i3) \
- V(ld1_asisdlsep_i4_i4) \
- V(ld1_asisdlsep_r1_r1) \
- V(ld1_asisdlsep_r2_r2) \
- V(ld1_asisdlsep_r3_r3) \
- V(ld1_asisdlsep_r4_r4) \
- V(ld1_asisdlso_b1_1b) \
- V(ld1_asisdlso_d1_1d) \
- V(ld1_asisdlso_h1_1h) \
- V(ld1_asisdlso_s1_1s) \
- V(ld1_asisdlsop_b1_i1b) \
- V(ld1_asisdlsop_bx1_r1b) \
- V(ld1_asisdlsop_d1_i1d) \
- V(ld1_asisdlsop_dx1_r1d) \
- V(ld1_asisdlsop_h1_i1h) \
- V(ld1_asisdlsop_hx1_r1h) \
- V(ld1_asisdlsop_s1_i1s) \
- V(ld1_asisdlsop_sx1_r1s) \
- V(ld1b_z_p_ai_d) \
- V(ld1b_z_p_ai_s) \
- V(ld1b_z_p_bi_u16) \
- V(ld1b_z_p_bi_u32) \
- V(ld1b_z_p_bi_u64) \
- V(ld1b_z_p_bi_u8) \
- V(ld1b_z_p_br_u16) \
- V(ld1b_z_p_br_u32) \
- V(ld1b_z_p_br_u64) \
- V(ld1b_z_p_br_u8) \
- V(ld1b_z_p_bz_d_64_unscaled) \
- V(ld1b_z_p_bz_d_x32_unscaled) \
- V(ld1b_z_p_bz_s_x32_unscaled) \
- V(ld1d_z_p_ai_d) \
- V(ld1d_z_p_bi_u64) \
- V(ld1d_z_p_br_u64) \
- V(ld1d_z_p_bz_d_64_scaled) \
- V(ld1d_z_p_bz_d_64_unscaled) \
- V(ld1d_z_p_bz_d_x32_scaled) \
- V(ld1d_z_p_bz_d_x32_unscaled) \
- V(ld1h_z_p_ai_d) \
- V(ld1h_z_p_ai_s) \
- V(ld1h_z_p_bi_u16) \
- V(ld1h_z_p_bi_u32) \
- V(ld1h_z_p_bi_u64) \
- V(ld1h_z_p_br_u16) \
- V(ld1h_z_p_br_u32) \
- V(ld1h_z_p_br_u64) \
- V(ld1h_z_p_bz_d_64_scaled) \
- V(ld1h_z_p_bz_d_64_unscaled) \
- V(ld1h_z_p_bz_d_x32_scaled) \
- V(ld1h_z_p_bz_d_x32_unscaled) \
- V(ld1h_z_p_bz_s_x32_scaled) \
- V(ld1h_z_p_bz_s_x32_unscaled) \
- V(ld1r_asisdlso_r1) \
- V(ld1r_asisdlsop_r1_i) \
- V(ld1r_asisdlsop_rx1_r) \
- V(ld1rb_z_p_bi_u16) \
- V(ld1rb_z_p_bi_u32) \
- V(ld1rb_z_p_bi_u64) \
- V(ld1rb_z_p_bi_u8) \
- V(ld1rd_z_p_bi_u64) \
- V(ld1rh_z_p_bi_u16) \
- V(ld1rh_z_p_bi_u32) \
- V(ld1rh_z_p_bi_u64) \
- V(ld1rob_z_p_bi_u8) \
- V(ld1rob_z_p_br_contiguous) \
- V(ld1rod_z_p_bi_u64) \
- V(ld1rod_z_p_br_contiguous) \
- V(ld1roh_z_p_bi_u16) \
- V(ld1roh_z_p_br_contiguous) \
- V(ld1row_z_p_bi_u32) \
- V(ld1row_z_p_br_contiguous) \
- V(ld1rqb_z_p_bi_u8) \
- V(ld1rqb_z_p_br_contiguous) \
- V(ld1rqd_z_p_bi_u64) \
- V(ld1rqd_z_p_br_contiguous) \
- V(ld1rqh_z_p_bi_u16) \
- V(ld1rqh_z_p_br_contiguous) \
- V(ld1rqw_z_p_bi_u32) \
- V(ld1rqw_z_p_br_contiguous) \
- V(ld1rsb_z_p_bi_s16) \
- V(ld1rsb_z_p_bi_s32) \
- V(ld1rsb_z_p_bi_s64) \
- V(ld1rsh_z_p_bi_s32) \
- V(ld1rsh_z_p_bi_s64) \
- V(ld1rsw_z_p_bi_s64) \
- V(ld1rw_z_p_bi_u32) \
- V(ld1rw_z_p_bi_u64) \
- V(ld1sb_z_p_ai_d) \
- V(ld1sb_z_p_ai_s) \
- V(ld1sb_z_p_bi_s16) \
- V(ld1sb_z_p_bi_s32) \
- V(ld1sb_z_p_bi_s64) \
- V(ld1sb_z_p_br_s16) \
- V(ld1sb_z_p_br_s32) \
- V(ld1sb_z_p_br_s64) \
- V(ld1sb_z_p_bz_d_64_unscaled) \
- V(ld1sb_z_p_bz_d_x32_unscaled) \
- V(ld1sb_z_p_bz_s_x32_unscaled) \
- V(ld1sh_z_p_ai_d) \
- V(ld1sh_z_p_ai_s) \
- V(ld1sh_z_p_bi_s32) \
- V(ld1sh_z_p_bi_s64) \
- V(ld1sh_z_p_br_s32) \
- V(ld1sh_z_p_br_s64) \
- V(ld1sh_z_p_bz_d_64_scaled) \
- V(ld1sh_z_p_bz_d_64_unscaled) \
- V(ld1sh_z_p_bz_d_x32_scaled) \
- V(ld1sh_z_p_bz_d_x32_unscaled) \
- V(ld1sh_z_p_bz_s_x32_scaled) \
- V(ld1sh_z_p_bz_s_x32_unscaled) \
- V(ld1sw_z_p_ai_d) \
- V(ld1sw_z_p_bi_s64) \
- V(ld1sw_z_p_br_s64) \
- V(ld1sw_z_p_bz_d_64_scaled) \
- V(ld1sw_z_p_bz_d_64_unscaled) \
- V(ld1sw_z_p_bz_d_x32_scaled) \
- V(ld1sw_z_p_bz_d_x32_unscaled) \
- V(ld1w_z_p_ai_d) \
- V(ld1w_z_p_ai_s) \
- V(ld1w_z_p_bi_u32) \
- V(ld1w_z_p_bi_u64) \
- V(ld1w_z_p_br_u32) \
- V(ld1w_z_p_br_u64) \
- V(ld1w_z_p_bz_d_64_scaled) \
- V(ld1w_z_p_bz_d_64_unscaled) \
- V(ld1w_z_p_bz_d_x32_scaled) \
- V(ld1w_z_p_bz_d_x32_unscaled) \
- V(ld1w_z_p_bz_s_x32_scaled) \
- V(ld1w_z_p_bz_s_x32_unscaled) \
- V(ld2_asisdlse_r2) \
- V(ld2_asisdlsep_i2_i) \
- V(ld2_asisdlsep_r2_r) \
- V(ld2_asisdlso_b2_2b) \
- V(ld2_asisdlso_d2_2d) \
- V(ld2_asisdlso_h2_2h) \
- V(ld2_asisdlso_s2_2s) \
- V(ld2_asisdlsop_b2_i2b) \
- V(ld2_asisdlsop_bx2_r2b) \
- V(ld2_asisdlsop_d2_i2d) \
- V(ld2_asisdlsop_dx2_r2d) \
- V(ld2_asisdlsop_h2_i2h) \
- V(ld2_asisdlsop_hx2_r2h) \
- V(ld2_asisdlsop_s2_i2s) \
- V(ld2_asisdlsop_sx2_r2s) \
- V(ld2b_z_p_bi_contiguous) \
- V(ld2b_z_p_br_contiguous) \
- V(ld2d_z_p_bi_contiguous) \
- V(ld2d_z_p_br_contiguous) \
- V(ld2h_z_p_bi_contiguous) \
- V(ld2h_z_p_br_contiguous) \
- V(ld2r_asisdlso_r2) \
- V(ld2r_asisdlsop_r2_i) \
- V(ld2r_asisdlsop_rx2_r) \
- V(ld2w_z_p_bi_contiguous) \
- V(ld2w_z_p_br_contiguous) \
- V(ld3_asisdlse_r3) \
- V(ld3_asisdlsep_i3_i) \
- V(ld3_asisdlsep_r3_r) \
- V(ld3_asisdlso_b3_3b) \
- V(ld3_asisdlso_d3_3d) \
- V(ld3_asisdlso_h3_3h) \
- V(ld3_asisdlso_s3_3s) \
- V(ld3_asisdlsop_b3_i3b) \
- V(ld3_asisdlsop_bx3_r3b) \
- V(ld3_asisdlsop_d3_i3d) \
- V(ld3_asisdlsop_dx3_r3d) \
- V(ld3_asisdlsop_h3_i3h) \
- V(ld3_asisdlsop_hx3_r3h) \
- V(ld3_asisdlsop_s3_i3s) \
- V(ld3_asisdlsop_sx3_r3s) \
- V(ld3b_z_p_bi_contiguous) \
- V(ld3b_z_p_br_contiguous) \
- V(ld3d_z_p_bi_contiguous) \
- V(ld3d_z_p_br_contiguous) \
- V(ld3h_z_p_bi_contiguous) \
- V(ld3h_z_p_br_contiguous) \
- V(ld3r_asisdlso_r3) \
- V(ld3r_asisdlsop_r3_i) \
- V(ld3r_asisdlsop_rx3_r) \
- V(ld3w_z_p_bi_contiguous) \
- V(ld3w_z_p_br_contiguous) \
- V(ld4_asisdlse_r4) \
- V(ld4_asisdlsep_i4_i) \
- V(ld4_asisdlsep_r4_r) \
- V(ld4_asisdlso_b4_4b) \
- V(ld4_asisdlso_d4_4d) \
- V(ld4_asisdlso_h4_4h) \
- V(ld4_asisdlso_s4_4s) \
- V(ld4_asisdlsop_b4_i4b) \
- V(ld4_asisdlsop_bx4_r4b) \
- V(ld4_asisdlsop_d4_i4d) \
- V(ld4_asisdlsop_dx4_r4d) \
- V(ld4_asisdlsop_h4_i4h) \
- V(ld4_asisdlsop_hx4_r4h) \
- V(ld4_asisdlsop_s4_i4s) \
- V(ld4_asisdlsop_sx4_r4s) \
- V(ld4b_z_p_bi_contiguous) \
- V(ld4b_z_p_br_contiguous) \
- V(ld4d_z_p_bi_contiguous) \
- V(ld4d_z_p_br_contiguous) \
- V(ld4h_z_p_bi_contiguous) \
- V(ld4h_z_p_br_contiguous) \
- V(ld4r_asisdlso_r4) \
- V(ld4r_asisdlsop_r4_i) \
- V(ld4r_asisdlsop_rx4_r) \
- V(ld4w_z_p_bi_contiguous) \
- V(ld4w_z_p_br_contiguous) \
- V(ld64b_64l_memop) \
- V(ldadd_32_memop) \
- V(ldadd_64_memop) \
- V(ldadda_32_memop) \
- V(ldadda_64_memop) \
- V(ldaddab_32_memop) \
- V(ldaddah_32_memop) \
- V(ldaddal_32_memop) \
- V(ldaddal_64_memop) \
- V(ldaddalb_32_memop) \
- V(ldaddalh_32_memop) \
- V(ldaddb_32_memop) \
- V(ldaddh_32_memop) \
- V(ldaddl_32_memop) \
- V(ldaddl_64_memop) \
- V(ldaddlb_32_memop) \
- V(ldaddlh_32_memop) \
- V(ldapr_32l_memop) \
- V(ldapr_64l_memop) \
- V(ldaprb_32l_memop) \
- V(ldaprh_32l_memop) \
- V(ldapur_32_ldapstl_unscaled) \
- V(ldapur_64_ldapstl_unscaled) \
- V(ldapurb_32_ldapstl_unscaled) \
- V(ldapurh_32_ldapstl_unscaled) \
- V(ldapursb_32_ldapstl_unscaled) \
- V(ldapursb_64_ldapstl_unscaled) \
- V(ldapursh_32_ldapstl_unscaled) \
- V(ldapursh_64_ldapstl_unscaled) \
- V(ldapursw_64_ldapstl_unscaled) \
- V(ldar_lr32_ldstexcl) \
- V(ldar_lr64_ldstexcl) \
- V(ldarb_lr32_ldstexcl) \
- V(ldarh_lr32_ldstexcl) \
- V(ldaxp_lp32_ldstexcl) \
- V(ldaxp_lp64_ldstexcl) \
- V(ldaxr_lr32_ldstexcl) \
- V(ldaxr_lr64_ldstexcl) \
- V(ldaxrb_lr32_ldstexcl) \
- V(ldaxrh_lr32_ldstexcl) \
- V(ldclr_32_memop) \
- V(ldclr_64_memop) \
- V(ldclra_32_memop) \
- V(ldclra_64_memop) \
- V(ldclrab_32_memop) \
- V(ldclrah_32_memop) \
- V(ldclral_32_memop) \
- V(ldclral_64_memop) \
- V(ldclralb_32_memop) \
- V(ldclralh_32_memop) \
- V(ldclrb_32_memop) \
- V(ldclrh_32_memop) \
- V(ldclrl_32_memop) \
- V(ldclrl_64_memop) \
- V(ldclrlb_32_memop) \
- V(ldclrlh_32_memop) \
- V(ldeor_32_memop) \
- V(ldeor_64_memop) \
- V(ldeora_32_memop) \
- V(ldeora_64_memop) \
- V(ldeorab_32_memop) \
- V(ldeorah_32_memop) \
- V(ldeoral_32_memop) \
- V(ldeoral_64_memop) \
- V(ldeoralb_32_memop) \
- V(ldeoralh_32_memop) \
- V(ldeorb_32_memop) \
- V(ldeorh_32_memop) \
- V(ldeorl_32_memop) \
- V(ldeorl_64_memop) \
- V(ldeorlb_32_memop) \
- V(ldeorlh_32_memop) \
- V(ldff1b_z_p_ai_d) \
- V(ldff1b_z_p_ai_s) \
- V(ldff1b_z_p_br_u16) \
- V(ldff1b_z_p_br_u32) \
- V(ldff1b_z_p_br_u64) \
- V(ldff1b_z_p_br_u8) \
- V(ldff1b_z_p_bz_d_64_unscaled) \
- V(ldff1b_z_p_bz_d_x32_unscaled) \
- V(ldff1b_z_p_bz_s_x32_unscaled) \
- V(ldff1d_z_p_ai_d) \
- V(ldff1d_z_p_br_u64) \
- V(ldff1d_z_p_bz_d_64_scaled) \
- V(ldff1d_z_p_bz_d_64_unscaled) \
- V(ldff1d_z_p_bz_d_x32_scaled) \
- V(ldff1d_z_p_bz_d_x32_unscaled) \
- V(ldff1h_z_p_ai_d) \
- V(ldff1h_z_p_ai_s) \
- V(ldff1h_z_p_br_u16) \
- V(ldff1h_z_p_br_u32) \
- V(ldff1h_z_p_br_u64) \
- V(ldff1h_z_p_bz_d_64_scaled) \
- V(ldff1h_z_p_bz_d_64_unscaled) \
- V(ldff1h_z_p_bz_d_x32_scaled) \
- V(ldff1h_z_p_bz_d_x32_unscaled) \
- V(ldff1h_z_p_bz_s_x32_scaled) \
- V(ldff1h_z_p_bz_s_x32_unscaled) \
- V(ldff1sb_z_p_ai_d) \
- V(ldff1sb_z_p_ai_s) \
- V(ldff1sb_z_p_br_s16) \
- V(ldff1sb_z_p_br_s32) \
- V(ldff1sb_z_p_br_s64) \
- V(ldff1sb_z_p_bz_d_64_unscaled) \
- V(ldff1sb_z_p_bz_d_x32_unscaled) \
- V(ldff1sb_z_p_bz_s_x32_unscaled) \
- V(ldff1sh_z_p_ai_d) \
- V(ldff1sh_z_p_ai_s) \
- V(ldff1sh_z_p_br_s32) \
- V(ldff1sh_z_p_br_s64) \
- V(ldff1sh_z_p_bz_d_64_scaled) \
- V(ldff1sh_z_p_bz_d_64_unscaled) \
- V(ldff1sh_z_p_bz_d_x32_scaled) \
- V(ldff1sh_z_p_bz_d_x32_unscaled) \
- V(ldff1sh_z_p_bz_s_x32_scaled) \
- V(ldff1sh_z_p_bz_s_x32_unscaled) \
- V(ldff1sw_z_p_ai_d) \
- V(ldff1sw_z_p_br_s64) \
- V(ldff1sw_z_p_bz_d_64_scaled) \
- V(ldff1sw_z_p_bz_d_64_unscaled) \
- V(ldff1sw_z_p_bz_d_x32_scaled) \
- V(ldff1sw_z_p_bz_d_x32_unscaled) \
- V(ldff1w_z_p_ai_d) \
- V(ldff1w_z_p_ai_s) \
- V(ldff1w_z_p_br_u32) \
- V(ldff1w_z_p_br_u64) \
- V(ldff1w_z_p_bz_d_64_scaled) \
- V(ldff1w_z_p_bz_d_64_unscaled) \
- V(ldff1w_z_p_bz_d_x32_scaled) \
- V(ldff1w_z_p_bz_d_x32_unscaled) \
- V(ldff1w_z_p_bz_s_x32_scaled) \
- V(ldff1w_z_p_bz_s_x32_unscaled) \
- V(ldg_64loffset_ldsttags) \
- V(ldgm_64bulk_ldsttags) \
- V(ldlar_lr32_ldstexcl) \
- V(ldlar_lr64_ldstexcl) \
- V(ldlarb_lr32_ldstexcl) \
- V(ldlarh_lr32_ldstexcl) \
- V(ldnf1b_z_p_bi_u16) \
- V(ldnf1b_z_p_bi_u32) \
- V(ldnf1b_z_p_bi_u64) \
- V(ldnf1b_z_p_bi_u8) \
- V(ldnf1d_z_p_bi_u64) \
- V(ldnf1h_z_p_bi_u16) \
- V(ldnf1h_z_p_bi_u32) \
- V(ldnf1h_z_p_bi_u64) \
- V(ldnf1sb_z_p_bi_s16) \
- V(ldnf1sb_z_p_bi_s32) \
- V(ldnf1sb_z_p_bi_s64) \
- V(ldnf1sh_z_p_bi_s32) \
- V(ldnf1sh_z_p_bi_s64) \
- V(ldnf1sw_z_p_bi_s64) \
- V(ldnf1w_z_p_bi_u32) \
- V(ldnf1w_z_p_bi_u64) \
- V(ldnp_32_ldstnapair_offs) \
- V(ldnp_64_ldstnapair_offs) \
- V(ldnp_d_ldstnapair_offs) \
- V(ldnp_q_ldstnapair_offs) \
- V(ldnp_s_ldstnapair_offs) \
- V(ldnt1b_z_p_ar_d_64_unscaled) \
- V(ldnt1b_z_p_ar_s_x32_unscaled) \
- V(ldnt1b_z_p_bi_contiguous) \
- V(ldnt1b_z_p_br_contiguous) \
- V(ldnt1d_z_p_ar_d_64_unscaled) \
- V(ldnt1d_z_p_bi_contiguous) \
- V(ldnt1d_z_p_br_contiguous) \
- V(ldnt1h_z_p_ar_d_64_unscaled) \
- V(ldnt1h_z_p_ar_s_x32_unscaled) \
- V(ldnt1h_z_p_bi_contiguous) \
- V(ldnt1h_z_p_br_contiguous) \
- V(ldnt1sb_z_p_ar_d_64_unscaled) \
- V(ldnt1sb_z_p_ar_s_x32_unscaled) \
- V(ldnt1sh_z_p_ar_d_64_unscaled) \
- V(ldnt1sh_z_p_ar_s_x32_unscaled) \
- V(ldnt1sw_z_p_ar_d_64_unscaled) \
- V(ldnt1w_z_p_ar_d_64_unscaled) \
- V(ldnt1w_z_p_ar_s_x32_unscaled) \
- V(ldnt1w_z_p_bi_contiguous) \
- V(ldnt1w_z_p_br_contiguous) \
- V(ldp_32_ldstpair_off) \
- V(ldp_32_ldstpair_post) \
- V(ldp_32_ldstpair_pre) \
- V(ldp_64_ldstpair_off) \
- V(ldp_64_ldstpair_post) \
- V(ldp_64_ldstpair_pre) \
- V(ldp_d_ldstpair_off) \
- V(ldp_d_ldstpair_post) \
- V(ldp_d_ldstpair_pre) \
- V(ldp_q_ldstpair_off) \
- V(ldp_q_ldstpair_post) \
- V(ldp_q_ldstpair_pre) \
- V(ldp_s_ldstpair_off) \
- V(ldp_s_ldstpair_post) \
- V(ldp_s_ldstpair_pre) \
- V(ldpsw_64_ldstpair_off) \
- V(ldpsw_64_ldstpair_post) \
- V(ldpsw_64_ldstpair_pre) \
- V(ldr_32_ldst_immpost) \
- V(ldr_32_ldst_immpre) \
- V(ldr_32_ldst_pos) \
- V(ldr_32_ldst_regoff) \
- V(ldr_32_loadlit) \
- V(ldr_64_ldst_immpost) \
- V(ldr_64_ldst_immpre) \
- V(ldr_64_ldst_pos) \
- V(ldr_64_ldst_regoff) \
- V(ldr_64_loadlit) \
- V(ldr_b_ldst_immpost) \
- V(ldr_b_ldst_immpre) \
- V(ldr_b_ldst_pos) \
- V(ldr_b_ldst_regoff) \
- V(ldr_bl_ldst_regoff) \
- V(ldr_d_ldst_immpost) \
- V(ldr_d_ldst_immpre) \
- V(ldr_d_ldst_pos) \
- V(ldr_d_ldst_regoff) \
- V(ldr_d_loadlit) \
- V(ldr_h_ldst_immpost) \
- V(ldr_h_ldst_immpre) \
- V(ldr_h_ldst_pos) \
- V(ldr_h_ldst_regoff) \
- V(ldr_p_bi) \
- V(ldr_q_ldst_immpost) \
- V(ldr_q_ldst_immpre) \
- V(ldr_q_ldst_pos) \
- V(ldr_q_ldst_regoff) \
- V(ldr_q_loadlit) \
- V(ldr_s_ldst_immpost) \
- V(ldr_s_ldst_immpre) \
- V(ldr_s_ldst_pos) \
- V(ldr_s_ldst_regoff) \
- V(ldr_s_loadlit) \
- V(ldr_z_bi) \
- V(ldraa_64_ldst_pac) \
- V(ldraa_64w_ldst_pac) \
- V(ldrab_64_ldst_pac) \
- V(ldrab_64w_ldst_pac) \
- V(ldrb_32_ldst_immpost) \
- V(ldrb_32_ldst_immpre) \
- V(ldrb_32_ldst_pos) \
- V(ldrb_32b_ldst_regoff) \
- V(ldrb_32bl_ldst_regoff) \
- V(ldrh_32_ldst_immpost) \
- V(ldrh_32_ldst_immpre) \
- V(ldrh_32_ldst_pos) \
- V(ldrh_32_ldst_regoff) \
- V(ldrsb_32_ldst_immpost) \
- V(ldrsb_32_ldst_immpre) \
- V(ldrsb_32_ldst_pos) \
- V(ldrsb_32b_ldst_regoff) \
- V(ldrsb_32bl_ldst_regoff) \
- V(ldrsb_64_ldst_immpost) \
- V(ldrsb_64_ldst_immpre) \
- V(ldrsb_64_ldst_pos) \
- V(ldrsb_64b_ldst_regoff) \
- V(ldrsb_64bl_ldst_regoff) \
- V(ldrsh_32_ldst_immpost) \
- V(ldrsh_32_ldst_immpre) \
- V(ldrsh_32_ldst_pos) \
- V(ldrsh_32_ldst_regoff) \
- V(ldrsh_64_ldst_immpost) \
- V(ldrsh_64_ldst_immpre) \
- V(ldrsh_64_ldst_pos) \
- V(ldrsh_64_ldst_regoff) \
- V(ldrsw_64_ldst_immpost) \
- V(ldrsw_64_ldst_immpre) \
- V(ldrsw_64_ldst_pos) \
- V(ldrsw_64_ldst_regoff) \
- V(ldrsw_64_loadlit) \
- V(ldset_32_memop) \
- V(ldset_64_memop) \
- V(ldseta_32_memop) \
- V(ldseta_64_memop) \
- V(ldsetab_32_memop) \
- V(ldsetah_32_memop) \
- V(ldsetal_32_memop) \
- V(ldsetal_64_memop) \
- V(ldsetalb_32_memop) \
- V(ldsetalh_32_memop) \
- V(ldsetb_32_memop) \
- V(ldseth_32_memop) \
- V(ldsetl_32_memop) \
- V(ldsetl_64_memop) \
- V(ldsetlb_32_memop) \
- V(ldsetlh_32_memop) \
- V(ldsmax_32_memop) \
- V(ldsmax_64_memop) \
- V(ldsmaxa_32_memop) \
- V(ldsmaxa_64_memop) \
- V(ldsmaxab_32_memop) \
- V(ldsmaxah_32_memop) \
- V(ldsmaxal_32_memop) \
- V(ldsmaxal_64_memop) \
- V(ldsmaxalb_32_memop) \
- V(ldsmaxalh_32_memop) \
- V(ldsmaxb_32_memop) \
- V(ldsmaxh_32_memop) \
- V(ldsmaxl_32_memop) \
- V(ldsmaxl_64_memop) \
- V(ldsmaxlb_32_memop) \
- V(ldsmaxlh_32_memop) \
- V(ldsmin_32_memop) \
- V(ldsmin_64_memop) \
- V(ldsmina_32_memop) \
- V(ldsmina_64_memop) \
- V(ldsminab_32_memop) \
- V(ldsminah_32_memop) \
- V(ldsminal_32_memop) \
- V(ldsminal_64_memop) \
- V(ldsminalb_32_memop) \
- V(ldsminalh_32_memop) \
- V(ldsminb_32_memop) \
- V(ldsminh_32_memop) \
- V(ldsminl_32_memop) \
- V(ldsminl_64_memop) \
- V(ldsminlb_32_memop) \
- V(ldsminlh_32_memop) \
- V(ldtr_32_ldst_unpriv) \
- V(ldtr_64_ldst_unpriv) \
- V(ldtrb_32_ldst_unpriv) \
- V(ldtrh_32_ldst_unpriv) \
- V(ldtrsb_32_ldst_unpriv) \
- V(ldtrsb_64_ldst_unpriv) \
- V(ldtrsh_32_ldst_unpriv) \
- V(ldtrsh_64_ldst_unpriv) \
- V(ldtrsw_64_ldst_unpriv) \
- V(ldumax_32_memop) \
- V(ldumax_64_memop) \
- V(ldumaxa_32_memop) \
- V(ldumaxa_64_memop) \
- V(ldumaxab_32_memop) \
- V(ldumaxah_32_memop) \
- V(ldumaxal_32_memop) \
- V(ldumaxal_64_memop) \
- V(ldumaxalb_32_memop) \
- V(ldumaxalh_32_memop) \
- V(ldumaxb_32_memop) \
- V(ldumaxh_32_memop) \
- V(ldumaxl_32_memop) \
- V(ldumaxl_64_memop) \
- V(ldumaxlb_32_memop) \
- V(ldumaxlh_32_memop) \
- V(ldumin_32_memop) \
- V(ldumin_64_memop) \
- V(ldumina_32_memop) \
- V(ldumina_64_memop) \
- V(lduminab_32_memop) \
- V(lduminah_32_memop) \
- V(lduminal_32_memop) \
- V(lduminal_64_memop) \
- V(lduminalb_32_memop) \
- V(lduminalh_32_memop) \
- V(lduminb_32_memop) \
- V(lduminh_32_memop) \
- V(lduminl_32_memop) \
- V(lduminl_64_memop) \
- V(lduminlb_32_memop) \
- V(lduminlh_32_memop) \
- V(ldur_32_ldst_unscaled) \
- V(ldur_64_ldst_unscaled) \
- V(ldur_b_ldst_unscaled) \
- V(ldur_d_ldst_unscaled) \
- V(ldur_h_ldst_unscaled) \
- V(ldur_q_ldst_unscaled) \
- V(ldur_s_ldst_unscaled) \
- V(ldurb_32_ldst_unscaled) \
- V(ldurh_32_ldst_unscaled) \
- V(ldursb_32_ldst_unscaled) \
- V(ldursb_64_ldst_unscaled) \
- V(ldursh_32_ldst_unscaled) \
- V(ldursh_64_ldst_unscaled) \
- V(ldursw_64_ldst_unscaled) \
- V(ldxp_lp32_ldstexcl) \
- V(ldxp_lp64_ldstexcl) \
- V(ldxr_lr32_ldstexcl) \
- V(ldxr_lr64_ldstexcl) \
- V(ldxrb_lr32_ldstexcl) \
- V(ldxrh_lr32_ldstexcl) \
- V(lsl_z_p_zi) \
- V(lsl_z_p_zw) \
- V(lsl_z_p_zz) \
- V(lsl_z_zi) \
- V(lsl_z_zw) \
- V(lslr_z_p_zz) \
- V(lslv_32_dp_2src) \
- V(lslv_64_dp_2src) \
- V(lsr_z_p_zi) \
- V(lsr_z_p_zw) \
- V(lsr_z_p_zz) \
- V(lsr_z_zi) \
- V(lsr_z_zw) \
- V(lsrr_z_p_zz) \
- V(lsrv_32_dp_2src) \
- V(lsrv_64_dp_2src) \
- V(mad_z_p_zzz) \
- V(madd_32a_dp_3src) \
- V(madd_64a_dp_3src) \
- V(match_p_p_zz) \
- V(mla_asimdelem_r) \
- V(mla_asimdsame_only) \
- V(mla_z_p_zzz) \
- V(mla_z_zzzi_d) \
- V(mla_z_zzzi_h) \
- V(mla_z_zzzi_s) \
- V(mls_asimdelem_r) \
- V(mls_asimdsame_only) \
- V(mls_z_p_zzz) \
- V(mls_z_zzzi_d) \
- V(mls_z_zzzi_h) \
- V(mls_z_zzzi_s) \
- V(movi_asimdimm_d2_d) \
- V(movi_asimdimm_d_ds) \
- V(movi_asimdimm_l_hl) \
- V(movi_asimdimm_l_sl) \
- V(movi_asimdimm_m_sm) \
- V(movi_asimdimm_n_b) \
- V(movk_32_movewide) \
- V(movk_64_movewide) \
- V(movn_32_movewide) \
- V(movn_64_movewide) \
- V(movprfx_z_p_z) \
- V(movprfx_z_z) \
- V(movz_32_movewide) \
- V(movz_64_movewide) \
- V(mrs_rs_systemmove) \
- V(msb_z_p_zzz) \
- V(msr_sr_systemmove) \
- V(msub_32a_dp_3src) \
- V(msub_64a_dp_3src) \
- V(mul_asimdelem_r) \
- V(mul_asimdsame_only) \
- V(mul_z_p_zz) \
- V(mul_z_zi) \
- V(mul_z_zz) \
- V(mul_z_zzi_d) \
- V(mul_z_zzi_h) \
- V(mul_z_zzi_s) \
- V(mvni_asimdimm_l_hl) \
- V(mvni_asimdimm_l_sl) \
- V(mvni_asimdimm_m_sm) \
- V(nand_p_p_pp_z) \
- V(nands_p_p_pp_z) \
- V(nbsl_z_zzz) \
- V(neg_asimdmisc_r) \
- V(neg_asisdmisc_r) \
- V(neg_z_p_z) \
- V(nmatch_p_p_zz) \
- V(nop_hi_hints) \
- V(nor_p_p_pp_z) \
- V(nors_p_p_pp_z) \
- V(not_asimdmisc_r) \
- V(not_z_p_z) \
- V(orn_32_log_shift) \
- V(orn_64_log_shift) \
- V(orn_asimdsame_only) \
- V(orn_p_p_pp_z) \
- V(orns_p_p_pp_z) \
- V(orr_32_log_imm) \
- V(orr_32_log_shift) \
- V(orr_64_log_imm) \
- V(orr_64_log_shift) \
- V(orr_asimdimm_l_hl) \
- V(orr_asimdimm_l_sl) \
- V(orr_asimdsame_only) \
- V(orr_p_p_pp_z) \
- V(orr_z_p_zz) \
- V(orr_z_zi) \
- V(orr_z_zz) \
- V(orrs_p_p_pp_z) \
- V(orv_r_p_z) \
- V(pacda_64p_dp_1src) \
- V(pacdb_64p_dp_1src) \
- V(pacdza_64z_dp_1src) \
- V(pacdzb_64z_dp_1src) \
- V(pacga_64p_dp_2src) \
- V(pacia1716_hi_hints) \
- V(pacia_64p_dp_1src) \
- V(paciasp_hi_hints) \
- V(paciaz_hi_hints) \
- V(pacib1716_hi_hints) \
- V(pacib_64p_dp_1src) \
- V(pacibsp_hi_hints) \
- V(pacibz_hi_hints) \
- V(paciza_64z_dp_1src) \
- V(pacizb_64z_dp_1src) \
- V(pfalse_p) \
- V(pfirst_p_p_p) \
- V(pmul_asimdsame_only) \
- V(pmul_z_zz) \
- V(pmull_asimddiff_l) \
- V(pmullb_z_zz) \
- V(pmullt_z_zz) \
- V(pnext_p_p_p) \
- V(prfb_i_p_ai_d) \
- V(prfb_i_p_ai_s) \
- V(prfb_i_p_bi_s) \
- V(prfb_i_p_br_s) \
- V(prfb_i_p_bz_d_64_scaled) \
- V(prfb_i_p_bz_d_x32_scaled) \
- V(prfb_i_p_bz_s_x32_scaled) \
- V(prfd_i_p_ai_d) \
- V(prfd_i_p_ai_s) \
- V(prfd_i_p_bi_s) \
- V(prfd_i_p_br_s) \
- V(prfd_i_p_bz_d_64_scaled) \
- V(prfd_i_p_bz_d_x32_scaled) \
- V(prfd_i_p_bz_s_x32_scaled) \
- V(prfh_i_p_ai_d) \
- V(prfh_i_p_ai_s) \
- V(prfh_i_p_bi_s) \
- V(prfh_i_p_br_s) \
- V(prfh_i_p_bz_d_64_scaled) \
- V(prfh_i_p_bz_d_x32_scaled) \
- V(prfh_i_p_bz_s_x32_scaled) \
- V(prfm_p_ldst_pos) \
- V(prfm_p_ldst_regoff) \
- V(prfm_p_loadlit) \
- V(prfum_p_ldst_unscaled) \
- V(prfw_i_p_ai_d) \
- V(prfw_i_p_ai_s) \
- V(prfw_i_p_bi_s) \
- V(prfw_i_p_br_s) \
- V(prfw_i_p_bz_d_64_scaled) \
- V(prfw_i_p_bz_d_x32_scaled) \
- V(prfw_i_p_bz_s_x32_scaled) \
- V(psb_hc_hints) \
- V(pssbb_only_barriers) \
- V(ptest_p_p) \
- V(ptrue_p_s) \
- V(ptrues_p_s) \
- V(punpkhi_p_p) \
- V(punpklo_p_p) \
- V(raddhn_asimddiff_n) \
- V(raddhnb_z_zz) \
- V(raddhnt_z_zz) \
- V(rax1_vvv2_cryptosha512_3) \
- V(rax1_z_zz) \
- V(rbit_32_dp_1src) \
- V(rbit_64_dp_1src) \
- V(rbit_asimdmisc_r) \
- V(rbit_z_p_z) \
- V(rdffr_p_f) \
- V(rdffr_p_p_f) \
- V(rdffrs_p_p_f) \
- V(rdvl_r_i) \
- V(ret_64r_branch_reg) \
- V(retaa_64e_branch_reg) \
- V(retab_64e_branch_reg) \
- V(rev16_32_dp_1src) \
- V(rev16_64_dp_1src) \
- V(rev16_asimdmisc_r) \
- V(rev32_64_dp_1src) \
- V(rev32_asimdmisc_r) \
- V(rev64_asimdmisc_r) \
- V(rev_32_dp_1src) \
- V(rev_64_dp_1src) \
- V(rev_p_p) \
- V(rev_z_z) \
- V(revb_z_z) \
- V(revh_z_z) \
- V(revw_z_z) \
- V(rmif_only_rmif) \
- V(rorv_32_dp_2src) \
- V(rorv_64_dp_2src) \
- V(rshrn_asimdshf_n) \
- V(rshrnb_z_zi) \
- V(rshrnt_z_zi) \
- V(rsubhn_asimddiff_n) \
- V(rsubhnb_z_zz) \
- V(rsubhnt_z_zz) \
- V(saba_asimdsame_only) \
- V(saba_z_zzz) \
- V(sabal_asimddiff_l) \
- V(sabalb_z_zzz) \
- V(sabalt_z_zzz) \
- V(sabd_asimdsame_only) \
- V(sabd_z_p_zz) \
- V(sabdl_asimddiff_l) \
- V(sabdlb_z_zz) \
- V(sabdlt_z_zz) \
- V(sadalp_asimdmisc_p) \
- V(sadalp_z_p_z) \
- V(saddl_asimddiff_l) \
- V(saddlb_z_zz) \
- V(saddlbt_z_zz) \
- V(saddlp_asimdmisc_p) \
- V(saddlt_z_zz) \
- V(saddlv_asimdall_only) \
- V(saddv_r_p_z) \
- V(saddw_asimddiff_w) \
- V(saddwb_z_zz) \
- V(saddwt_z_zz) \
- V(sb_only_barriers) \
- V(sbc_32_addsub_carry) \
- V(sbc_64_addsub_carry) \
- V(sbclb_z_zzz) \
- V(sbclt_z_zzz) \
- V(sbcs_32_addsub_carry) \
- V(sbcs_64_addsub_carry) \
- V(sbfm_32m_bitfield) \
- V(sbfm_64m_bitfield) \
- V(scvtf_asimdmisc_r) \
- V(scvtf_asimdmiscfp16_r) \
- V(scvtf_asimdshf_c) \
- V(scvtf_asisdmisc_r) \
- V(scvtf_asisdmiscfp16_r) \
- V(scvtf_asisdshf_c) \
- V(scvtf_d32_float2fix) \
- V(scvtf_d32_float2int) \
- V(scvtf_d64_float2fix) \
- V(scvtf_d64_float2int) \
- V(scvtf_h32_float2fix) \
- V(scvtf_h32_float2int) \
- V(scvtf_h64_float2fix) \
- V(scvtf_h64_float2int) \
- V(scvtf_s32_float2fix) \
- V(scvtf_s32_float2int) \
- V(scvtf_s64_float2fix) \
- V(scvtf_s64_float2int) \
- V(scvtf_z_p_z_h2fp16) \
- V(scvtf_z_p_z_w2d) \
- V(scvtf_z_p_z_w2fp16) \
- V(scvtf_z_p_z_w2s) \
- V(scvtf_z_p_z_x2d) \
- V(scvtf_z_p_z_x2fp16) \
- V(scvtf_z_p_z_x2s) \
- V(sdiv_32_dp_2src) \
- V(sdiv_64_dp_2src) \
- V(sdiv_z_p_zz) \
- V(sdivr_z_p_zz) \
- V(sdot_asimdelem_d) \
- V(sdot_asimdsame2_d) \
- V(sdot_z_zzz) \
- V(sdot_z_zzzi_d) \
- V(sdot_z_zzzi_s) \
- V(sel_p_p_pp) \
- V(sel_z_p_zz) \
- V(setf16_only_setf) \
- V(setf8_only_setf) \
- V(setffr_f) \
- V(sev_hi_hints) \
- V(sevl_hi_hints) \
- V(sha1c_qsv_cryptosha3) \
- V(sha1h_ss_cryptosha2) \
- V(sha1m_qsv_cryptosha3) \
- V(sha1p_qsv_cryptosha3) \
- V(sha1su0_vvv_cryptosha3) \
- V(sha1su1_vv_cryptosha2) \
- V(sha256h2_qqv_cryptosha3) \
- V(sha256h_qqv_cryptosha3) \
- V(sha256su0_vv_cryptosha2) \
- V(sha256su1_vvv_cryptosha3) \
- V(sha512h2_qqv_cryptosha512_3) \
- V(sha512h_qqv_cryptosha512_3) \
- V(sha512su0_vv2_cryptosha512_2) \
- V(sha512su1_vvv2_cryptosha512_3) \
- V(shadd_asimdsame_only) \
- V(shadd_z_p_zz) \
- V(shl_asimdshf_r) \
- V(shl_asisdshf_r) \
- V(shll_asimdmisc_s) \
- V(shrn_asimdshf_n) \
- V(shrnb_z_zi) \
- V(shrnt_z_zi) \
- V(shsub_asimdsame_only) \
- V(shsub_z_p_zz) \
- V(shsubr_z_p_zz) \
- V(sli_asimdshf_r) \
- V(sli_asisdshf_r) \
- V(sli_z_zzi) \
- V(sm3partw1_vvv4_cryptosha512_3) \
- V(sm3partw2_vvv4_cryptosha512_3) \
- V(sm3ss1_vvv4_crypto4) \
- V(sm3tt1a_vvv4_crypto3_imm2) \
- V(sm3tt1b_vvv4_crypto3_imm2) \
- V(sm3tt2a_vvv4_crypto3_imm2) \
- V(sm3tt2b_vvv_crypto3_imm2) \
- V(sm4e_vv4_cryptosha512_2) \
- V(sm4e_z_zz) \
- V(sm4ekey_vvv4_cryptosha512_3) \
- V(sm4ekey_z_zz) \
- V(smaddl_64wa_dp_3src) \
- V(smax_asimdsame_only) \
- V(smax_z_p_zz) \
- V(smax_z_zi) \
- V(smaxp_asimdsame_only) \
- V(smaxp_z_p_zz) \
- V(smaxv_asimdall_only) \
- V(smaxv_r_p_z) \
- V(smc_ex_exception) \
- V(smin_asimdsame_only) \
- V(smin_z_p_zz) \
- V(smin_z_zi) \
- V(sminp_asimdsame_only) \
- V(sminp_z_p_zz) \
- V(sminv_asimdall_only) \
- V(sminv_r_p_z) \
- V(smlal_asimddiff_l) \
- V(smlal_asimdelem_l) \
- V(smlalb_z_zzz) \
- V(smlalb_z_zzzi_d) \
- V(smlalb_z_zzzi_s) \
- V(smlalt_z_zzz) \
- V(smlalt_z_zzzi_d) \
- V(smlalt_z_zzzi_s) \
- V(smlsl_asimddiff_l) \
- V(smlsl_asimdelem_l) \
- V(smlslb_z_zzz) \
- V(smlslb_z_zzzi_d) \
- V(smlslb_z_zzzi_s) \
- V(smlslt_z_zzz) \
- V(smlslt_z_zzzi_d) \
- V(smlslt_z_zzzi_s) \
- V(smmla_asimdsame2_g) \
- V(smmla_z_zzz) \
- V(smov_asimdins_w_w) \
- V(smov_asimdins_x_x) \
- V(smsubl_64wa_dp_3src) \
- V(smulh_64_dp_3src) \
- V(smulh_z_p_zz) \
- V(smulh_z_zz) \
- V(smull_asimddiff_l) \
- V(smull_asimdelem_l) \
- V(smullb_z_zz) \
- V(smullb_z_zzi_d) \
- V(smullb_z_zzi_s) \
- V(smullt_z_zz) \
- V(smullt_z_zzi_d) \
- V(smullt_z_zzi_s) \
- V(splice_z_p_zz_con) \
- V(splice_z_p_zz_des) \
- V(sqabs_asimdmisc_r) \
- V(sqabs_asisdmisc_r) \
- V(sqabs_z_p_z) \
- V(sqadd_asimdsame_only) \
- V(sqadd_asisdsame_only) \
- V(sqadd_z_p_zz) \
- V(sqadd_z_zi) \
- V(sqadd_z_zz) \
- V(sqcadd_z_zz) \
- V(sqdecb_r_rs_sx) \
- V(sqdecb_r_rs_x) \
- V(sqdecd_r_rs_sx) \
- V(sqdecd_r_rs_x) \
- V(sqdecd_z_zs) \
- V(sqdech_r_rs_sx) \
- V(sqdech_r_rs_x) \
- V(sqdech_z_zs) \
- V(sqdecp_r_p_r_sx) \
- V(sqdecp_r_p_r_x) \
- V(sqdecp_z_p_z) \
- V(sqdecw_r_rs_sx) \
- V(sqdecw_r_rs_x) \
- V(sqdecw_z_zs) \
- V(sqdmlal_asimddiff_l) \
- V(sqdmlal_asimdelem_l) \
- V(sqdmlal_asisddiff_only) \
- V(sqdmlal_asisdelem_l) \
- V(sqdmlalb_z_zzz) \
- V(sqdmlalb_z_zzzi_d) \
- V(sqdmlalb_z_zzzi_s) \
- V(sqdmlalbt_z_zzz) \
- V(sqdmlalt_z_zzz) \
- V(sqdmlalt_z_zzzi_d) \
- V(sqdmlalt_z_zzzi_s) \
- V(sqdmlsl_asimddiff_l) \
- V(sqdmlsl_asimdelem_l) \
- V(sqdmlsl_asisddiff_only) \
- V(sqdmlsl_asisdelem_l) \
- V(sqdmlslb_z_zzz) \
- V(sqdmlslb_z_zzzi_d) \
- V(sqdmlslb_z_zzzi_s) \
- V(sqdmlslbt_z_zzz) \
- V(sqdmlslt_z_zzz) \
- V(sqdmlslt_z_zzzi_d) \
- V(sqdmlslt_z_zzzi_s) \
- V(sqdmulh_asimdelem_r) \
- V(sqdmulh_asimdsame_only) \
- V(sqdmulh_asisdelem_r) \
- V(sqdmulh_asisdsame_only) \
- V(sqdmulh_z_zz) \
- V(sqdmulh_z_zzi_d) \
- V(sqdmulh_z_zzi_h) \
- V(sqdmulh_z_zzi_s) \
- V(sqdmull_asimddiff_l) \
- V(sqdmull_asimdelem_l) \
- V(sqdmull_asisddiff_only) \
- V(sqdmull_asisdelem_l) \
- V(sqdmullb_z_zz) \
- V(sqdmullb_z_zzi_d) \
- V(sqdmullb_z_zzi_s) \
- V(sqdmullt_z_zz) \
- V(sqdmullt_z_zzi_d) \
- V(sqdmullt_z_zzi_s) \
- V(sqincb_r_rs_sx) \
- V(sqincb_r_rs_x) \
- V(sqincd_r_rs_sx) \
- V(sqincd_r_rs_x) \
- V(sqincd_z_zs) \
- V(sqinch_r_rs_sx) \
- V(sqinch_r_rs_x) \
- V(sqinch_z_zs) \
- V(sqincp_r_p_r_sx) \
- V(sqincp_r_p_r_x) \
- V(sqincp_z_p_z) \
- V(sqincw_r_rs_sx) \
- V(sqincw_r_rs_x) \
- V(sqincw_z_zs) \
- V(sqneg_asimdmisc_r) \
- V(sqneg_asisdmisc_r) \
- V(sqneg_z_p_z) \
- V(sqrdcmlah_z_zzz) \
- V(sqrdcmlah_z_zzzi_h) \
- V(sqrdcmlah_z_zzzi_s) \
- V(sqrdmlah_asimdelem_r) \
- V(sqrdmlah_asimdsame2_only) \
- V(sqrdmlah_asisdelem_r) \
- V(sqrdmlah_asisdsame2_only) \
- V(sqrdmlah_z_zzz) \
- V(sqrdmlah_z_zzzi_d) \
- V(sqrdmlah_z_zzzi_h) \
- V(sqrdmlah_z_zzzi_s) \
- V(sqrdmlsh_asimdelem_r) \
- V(sqrdmlsh_asimdsame2_only) \
- V(sqrdmlsh_asisdelem_r) \
- V(sqrdmlsh_asisdsame2_only) \
- V(sqrdmlsh_z_zzz) \
- V(sqrdmlsh_z_zzzi_d) \
- V(sqrdmlsh_z_zzzi_h) \
- V(sqrdmlsh_z_zzzi_s) \
- V(sqrdmulh_asimdelem_r) \
- V(sqrdmulh_asimdsame_only) \
- V(sqrdmulh_asisdelem_r) \
- V(sqrdmulh_asisdsame_only) \
- V(sqrdmulh_z_zz) \
- V(sqrdmulh_z_zzi_d) \
- V(sqrdmulh_z_zzi_h) \
- V(sqrdmulh_z_zzi_s) \
- V(sqrshl_asimdsame_only) \
- V(sqrshl_asisdsame_only) \
- V(sqrshl_z_p_zz) \
- V(sqrshlr_z_p_zz) \
- V(sqrshrn_asimdshf_n) \
- V(sqrshrn_asisdshf_n) \
- V(sqrshrnb_z_zi) \
- V(sqrshrnt_z_zi) \
- V(sqrshrun_asimdshf_n) \
- V(sqrshrun_asisdshf_n) \
- V(sqrshrunb_z_zi) \
- V(sqrshrunt_z_zi) \
- V(sqshl_asimdsame_only) \
- V(sqshl_asimdshf_r) \
- V(sqshl_asisdsame_only) \
- V(sqshl_asisdshf_r) \
- V(sqshl_z_p_zi) \
- V(sqshl_z_p_zz) \
- V(sqshlr_z_p_zz) \
- V(sqshlu_asimdshf_r) \
- V(sqshlu_asisdshf_r) \
- V(sqshlu_z_p_zi) \
- V(sqshrn_asimdshf_n) \
- V(sqshrn_asisdshf_n) \
- V(sqshrnb_z_zi) \
- V(sqshrnt_z_zi) \
- V(sqshrun_asimdshf_n) \
- V(sqshrun_asisdshf_n) \
- V(sqshrunb_z_zi) \
- V(sqshrunt_z_zi) \
- V(sqsub_asimdsame_only) \
- V(sqsub_asisdsame_only) \
- V(sqsub_z_p_zz) \
- V(sqsub_z_zi) \
- V(sqsub_z_zz) \
- V(sqsubr_z_p_zz) \
- V(sqxtn_asimdmisc_n) \
- V(sqxtn_asisdmisc_n) \
- V(sqxtnb_z_zz) \
- V(sqxtnt_z_zz) \
- V(sqxtun_asimdmisc_n) \
- V(sqxtun_asisdmisc_n) \
- V(sqxtunb_z_zz) \
- V(sqxtunt_z_zz) \
- V(srhadd_asimdsame_only) \
- V(srhadd_z_p_zz) \
- V(sri_asimdshf_r) \
- V(sri_asisdshf_r) \
- V(sri_z_zzi) \
- V(srshl_asimdsame_only) \
- V(srshl_asisdsame_only) \
- V(srshl_z_p_zz) \
- V(srshlr_z_p_zz) \
- V(srshr_asimdshf_r) \
- V(srshr_asisdshf_r) \
- V(srshr_z_p_zi) \
- V(srsra_asimdshf_r) \
- V(srsra_asisdshf_r) \
- V(srsra_z_zi) \
- V(ssbb_only_barriers) \
- V(sshl_asimdsame_only) \
- V(sshl_asisdsame_only) \
- V(sshll_asimdshf_l) \
- V(sshllb_z_zi) \
- V(sshllt_z_zi) \
- V(sshr_asimdshf_r) \
- V(sshr_asisdshf_r) \
- V(ssra_asimdshf_r) \
- V(ssra_asisdshf_r) \
- V(ssra_z_zi) \
- V(ssubl_asimddiff_l) \
- V(ssublb_z_zz) \
- V(ssublbt_z_zz) \
- V(ssublt_z_zz) \
- V(ssubltb_z_zz) \
- V(ssubw_asimddiff_w) \
- V(ssubwb_z_zz) \
- V(ssubwt_z_zz) \
- V(st1_asisdlse_r1_1v) \
- V(st1_asisdlse_r2_2v) \
- V(st1_asisdlse_r3_3v) \
- V(st1_asisdlse_r4_4v) \
- V(st1_asisdlsep_i1_i1) \
- V(st1_asisdlsep_i2_i2) \
- V(st1_asisdlsep_i3_i3) \
- V(st1_asisdlsep_i4_i4) \
- V(st1_asisdlsep_r1_r1) \
- V(st1_asisdlsep_r2_r2) \
- V(st1_asisdlsep_r3_r3) \
- V(st1_asisdlsep_r4_r4) \
- V(st1_asisdlso_b1_1b) \
- V(st1_asisdlso_d1_1d) \
- V(st1_asisdlso_h1_1h) \
- V(st1_asisdlso_s1_1s) \
- V(st1_asisdlsop_b1_i1b) \
- V(st1_asisdlsop_bx1_r1b) \
- V(st1_asisdlsop_d1_i1d) \
- V(st1_asisdlsop_dx1_r1d) \
- V(st1_asisdlsop_h1_i1h) \
- V(st1_asisdlsop_hx1_r1h) \
- V(st1_asisdlsop_s1_i1s) \
- V(st1_asisdlsop_sx1_r1s) \
- V(st1b_z_p_ai_d) \
- V(st1b_z_p_ai_s) \
- V(st1b_z_p_bi) \
- V(st1b_z_p_br) \
- V(st1b_z_p_bz_d_64_unscaled) \
- V(st1b_z_p_bz_d_x32_unscaled) \
- V(st1b_z_p_bz_s_x32_unscaled) \
- V(st1d_z_p_ai_d) \
- V(st1d_z_p_bi) \
- V(st1d_z_p_br) \
- V(st1d_z_p_bz_d_64_scaled) \
- V(st1d_z_p_bz_d_64_unscaled) \
- V(st1d_z_p_bz_d_x32_scaled) \
- V(st1d_z_p_bz_d_x32_unscaled) \
- V(st1h_z_p_ai_d) \
- V(st1h_z_p_ai_s) \
- V(st1h_z_p_bi) \
- V(st1h_z_p_br) \
- V(st1h_z_p_bz_d_64_scaled) \
- V(st1h_z_p_bz_d_64_unscaled) \
- V(st1h_z_p_bz_d_x32_scaled) \
- V(st1h_z_p_bz_d_x32_unscaled) \
- V(st1h_z_p_bz_s_x32_scaled) \
- V(st1h_z_p_bz_s_x32_unscaled) \
- V(st1w_z_p_ai_d) \
- V(st1w_z_p_ai_s) \
- V(st1w_z_p_bi) \
- V(st1w_z_p_br) \
- V(st1w_z_p_bz_d_64_scaled) \
- V(st1w_z_p_bz_d_64_unscaled) \
- V(st1w_z_p_bz_d_x32_scaled) \
- V(st1w_z_p_bz_d_x32_unscaled) \
- V(st1w_z_p_bz_s_x32_scaled) \
- V(st1w_z_p_bz_s_x32_unscaled) \
- V(st2_asisdlse_r2) \
- V(st2_asisdlsep_i2_i) \
- V(st2_asisdlsep_r2_r) \
- V(st2_asisdlso_b2_2b) \
- V(st2_asisdlso_d2_2d) \
- V(st2_asisdlso_h2_2h) \
- V(st2_asisdlso_s2_2s) \
- V(st2_asisdlsop_b2_i2b) \
- V(st2_asisdlsop_bx2_r2b) \
- V(st2_asisdlsop_d2_i2d) \
- V(st2_asisdlsop_dx2_r2d) \
- V(st2_asisdlsop_h2_i2h) \
- V(st2_asisdlsop_hx2_r2h) \
- V(st2_asisdlsop_s2_i2s) \
- V(st2_asisdlsop_sx2_r2s) \
- V(st2b_z_p_bi_contiguous) \
- V(st2b_z_p_br_contiguous) \
- V(st2d_z_p_bi_contiguous) \
- V(st2d_z_p_br_contiguous) \
- V(st2g_64soffset_ldsttags) \
- V(st2g_64spost_ldsttags) \
- V(st2g_64spre_ldsttags) \
- V(st2h_z_p_bi_contiguous) \
- V(st2h_z_p_br_contiguous) \
- V(st2w_z_p_bi_contiguous) \
- V(st2w_z_p_br_contiguous) \
- V(st3_asisdlse_r3) \
- V(st3_asisdlsep_i3_i) \
- V(st3_asisdlsep_r3_r) \
- V(st3_asisdlso_b3_3b) \
- V(st3_asisdlso_d3_3d) \
- V(st3_asisdlso_h3_3h) \
- V(st3_asisdlso_s3_3s) \
- V(st3_asisdlsop_b3_i3b) \
- V(st3_asisdlsop_bx3_r3b) \
- V(st3_asisdlsop_d3_i3d) \
- V(st3_asisdlsop_dx3_r3d) \
- V(st3_asisdlsop_h3_i3h) \
- V(st3_asisdlsop_hx3_r3h) \
- V(st3_asisdlsop_s3_i3s) \
- V(st3_asisdlsop_sx3_r3s) \
- V(st3b_z_p_bi_contiguous) \
- V(st3b_z_p_br_contiguous) \
- V(st3d_z_p_bi_contiguous) \
- V(st3d_z_p_br_contiguous) \
- V(st3h_z_p_bi_contiguous) \
- V(st3h_z_p_br_contiguous) \
- V(st3w_z_p_bi_contiguous) \
- V(st3w_z_p_br_contiguous) \
- V(st4_asisdlse_r4) \
- V(st4_asisdlsep_i4_i) \
- V(st4_asisdlsep_r4_r) \
- V(st4_asisdlso_b4_4b) \
- V(st4_asisdlso_d4_4d) \
- V(st4_asisdlso_h4_4h) \
- V(st4_asisdlso_s4_4s) \
- V(st4_asisdlsop_b4_i4b) \
- V(st4_asisdlsop_bx4_r4b) \
- V(st4_asisdlsop_d4_i4d) \
- V(st4_asisdlsop_dx4_r4d) \
- V(st4_asisdlsop_h4_i4h) \
- V(st4_asisdlsop_hx4_r4h) \
- V(st4_asisdlsop_s4_i4s) \
- V(st4_asisdlsop_sx4_r4s) \
- V(st4b_z_p_bi_contiguous) \
- V(st4b_z_p_br_contiguous) \
- V(st4d_z_p_bi_contiguous) \
- V(st4d_z_p_br_contiguous) \
- V(st4h_z_p_bi_contiguous) \
- V(st4h_z_p_br_contiguous) \
- V(st4w_z_p_bi_contiguous) \
- V(st4w_z_p_br_contiguous) \
- V(st64b_64l_memop) \
- V(st64bv0_64_memop) \
- V(st64bv_64_memop) \
- V(stg_64soffset_ldsttags) \
- V(stg_64spost_ldsttags) \
- V(stg_64spre_ldsttags) \
- V(stgm_64bulk_ldsttags) \
- V(stgp_64_ldstpair_off) \
- V(stgp_64_ldstpair_post) \
- V(stgp_64_ldstpair_pre) \
- V(stllr_sl32_ldstexcl) \
- V(stllr_sl64_ldstexcl) \
- V(stllrb_sl32_ldstexcl) \
- V(stllrh_sl32_ldstexcl) \
- V(stlr_sl32_ldstexcl) \
- V(stlr_sl64_ldstexcl) \
- V(stlrb_sl32_ldstexcl) \
- V(stlrh_sl32_ldstexcl) \
- V(stlur_32_ldapstl_unscaled) \
- V(stlur_64_ldapstl_unscaled) \
- V(stlurb_32_ldapstl_unscaled) \
- V(stlurh_32_ldapstl_unscaled) \
- V(stlxp_sp32_ldstexcl) \
- V(stlxp_sp64_ldstexcl) \
- V(stlxr_sr32_ldstexcl) \
- V(stlxr_sr64_ldstexcl) \
- V(stlxrb_sr32_ldstexcl) \
- V(stlxrh_sr32_ldstexcl) \
- V(stnp_32_ldstnapair_offs) \
- V(stnp_64_ldstnapair_offs) \
- V(stnp_d_ldstnapair_offs) \
- V(stnp_q_ldstnapair_offs) \
- V(stnp_s_ldstnapair_offs) \
- V(stnt1b_z_p_ar_d_64_unscaled) \
- V(stnt1b_z_p_ar_s_x32_unscaled) \
- V(stnt1b_z_p_bi_contiguous) \
- V(stnt1b_z_p_br_contiguous) \
- V(stnt1d_z_p_ar_d_64_unscaled) \
- V(stnt1d_z_p_bi_contiguous) \
- V(stnt1d_z_p_br_contiguous) \
- V(stnt1h_z_p_ar_d_64_unscaled) \
- V(stnt1h_z_p_ar_s_x32_unscaled) \
- V(stnt1h_z_p_bi_contiguous) \
- V(stnt1h_z_p_br_contiguous) \
- V(stnt1w_z_p_ar_d_64_unscaled) \
- V(stnt1w_z_p_ar_s_x32_unscaled) \
- V(stnt1w_z_p_bi_contiguous) \
- V(stnt1w_z_p_br_contiguous) \
- V(stp_32_ldstpair_off) \
- V(stp_32_ldstpair_post) \
- V(stp_32_ldstpair_pre) \
- V(stp_64_ldstpair_off) \
- V(stp_64_ldstpair_post) \
- V(stp_64_ldstpair_pre) \
- V(stp_d_ldstpair_off) \
- V(stp_d_ldstpair_post) \
- V(stp_d_ldstpair_pre) \
- V(stp_q_ldstpair_off) \
- V(stp_q_ldstpair_post) \
- V(stp_q_ldstpair_pre) \
- V(stp_s_ldstpair_off) \
- V(stp_s_ldstpair_post) \
- V(stp_s_ldstpair_pre) \
- V(str_32_ldst_immpost) \
- V(str_32_ldst_immpre) \
- V(str_32_ldst_pos) \
- V(str_32_ldst_regoff) \
- V(str_64_ldst_immpost) \
- V(str_64_ldst_immpre) \
- V(str_64_ldst_pos) \
- V(str_64_ldst_regoff) \
- V(str_b_ldst_immpost) \
- V(str_b_ldst_immpre) \
- V(str_b_ldst_pos) \
- V(str_b_ldst_regoff) \
- V(str_bl_ldst_regoff) \
- V(str_d_ldst_immpost) \
- V(str_d_ldst_immpre) \
- V(str_d_ldst_pos) \
- V(str_d_ldst_regoff) \
- V(str_h_ldst_immpost) \
- V(str_h_ldst_immpre) \
- V(str_h_ldst_pos) \
- V(str_h_ldst_regoff) \
- V(str_p_bi) \
- V(str_q_ldst_immpost) \
- V(str_q_ldst_immpre) \
- V(str_q_ldst_pos) \
- V(str_q_ldst_regoff) \
- V(str_s_ldst_immpost) \
- V(str_s_ldst_immpre) \
- V(str_s_ldst_pos) \
- V(str_s_ldst_regoff) \
- V(str_z_bi) \
- V(strb_32_ldst_immpost) \
- V(strb_32_ldst_immpre) \
- V(strb_32_ldst_pos) \
- V(strb_32b_ldst_regoff) \
- V(strb_32bl_ldst_regoff) \
- V(strh_32_ldst_immpost) \
- V(strh_32_ldst_immpre) \
- V(strh_32_ldst_pos) \
- V(strh_32_ldst_regoff) \
- V(sttr_32_ldst_unpriv) \
- V(sttr_64_ldst_unpriv) \
- V(sttrb_32_ldst_unpriv) \
- V(sttrh_32_ldst_unpriv) \
- V(stur_32_ldst_unscaled) \
- V(stur_64_ldst_unscaled) \
- V(stur_b_ldst_unscaled) \
- V(stur_d_ldst_unscaled) \
- V(stur_h_ldst_unscaled) \
- V(stur_q_ldst_unscaled) \
- V(stur_s_ldst_unscaled) \
- V(sturb_32_ldst_unscaled) \
- V(sturh_32_ldst_unscaled) \
- V(stxp_sp32_ldstexcl) \
- V(stxp_sp64_ldstexcl) \
- V(stxr_sr32_ldstexcl) \
- V(stxr_sr64_ldstexcl) \
- V(stxrb_sr32_ldstexcl) \
- V(stxrh_sr32_ldstexcl) \
- V(stz2g_64soffset_ldsttags) \
- V(stz2g_64spost_ldsttags) \
- V(stz2g_64spre_ldsttags) \
- V(stzg_64soffset_ldsttags) \
- V(stzg_64spost_ldsttags) \
- V(stzg_64spre_ldsttags) \
- V(stzgm_64bulk_ldsttags) \
- V(sub_32_addsub_ext) \
- V(sub_32_addsub_imm) \
- V(sub_32_addsub_shift) \
- V(sub_64_addsub_ext) \
- V(sub_64_addsub_imm) \
- V(sub_64_addsub_shift) \
- V(sub_asimdsame_only) \
- V(sub_asisdsame_only) \
- V(sub_z_p_zz) \
- V(sub_z_zi) \
- V(sub_z_zz) \
- V(subg_64_addsub_immtags) \
- V(subhn_asimddiff_n) \
- V(subhnb_z_zz) \
- V(subhnt_z_zz) \
- V(subp_64s_dp_2src) \
- V(subps_64s_dp_2src) \
- V(subr_z_p_zz) \
- V(subr_z_zi) \
- V(subs_32_addsub_shift) \
- V(subs_32s_addsub_ext) \
- V(subs_32s_addsub_imm) \
- V(subs_64_addsub_shift) \
- V(subs_64s_addsub_ext) \
- V(subs_64s_addsub_imm) \
- V(sudot_asimdelem_d) \
- V(sudot_z_zzzi_s) \
- V(sunpkhi_z_z) \
- V(sunpklo_z_z) \
- V(suqadd_asimdmisc_r) \
- V(suqadd_asisdmisc_r) \
- V(suqadd_z_p_zz) \
- V(svc_ex_exception) \
- V(swp_32_memop) \
- V(swp_64_memop) \
- V(swpa_32_memop) \
- V(swpa_64_memop) \
- V(swpab_32_memop) \
- V(swpah_32_memop) \
- V(swpal_32_memop) \
- V(swpal_64_memop) \
- V(swpalb_32_memop) \
- V(swpalh_32_memop) \
- V(swpb_32_memop) \
- V(swph_32_memop) \
- V(swpl_32_memop) \
- V(swpl_64_memop) \
- V(swplb_32_memop) \
- V(swplh_32_memop) \
- V(sxtb_z_p_z) \
- V(sxth_z_p_z) \
- V(sxtw_z_p_z) \
- V(sys_cr_systeminstrs) \
- V(sysl_rc_systeminstrs) \
- V(tbl_asimdtbl_l1_1) \
- V(tbl_asimdtbl_l2_2) \
- V(tbl_asimdtbl_l3_3) \
- V(tbl_asimdtbl_l4_4) \
- V(tbl_z_zz_1) \
- V(tbl_z_zz_2) \
- V(tbnz_only_testbranch) \
- V(tbx_asimdtbl_l1_1) \
- V(tbx_asimdtbl_l2_2) \
- V(tbx_asimdtbl_l3_3) \
- V(tbx_asimdtbl_l4_4) \
- V(tbx_z_zz) \
- V(tbz_only_testbranch) \
- V(tcancel_ex_exception) \
- V(tcommit_only_barriers) \
- V(trn1_asimdperm_only) \
- V(trn1_p_pp) \
- V(trn1_z_zz) \
- V(trn1_z_zz_q) \
- V(trn2_asimdperm_only) \
- V(trn2_p_pp) \
- V(trn2_z_zz) \
- V(trn2_z_zz_q) \
- V(tsb_hc_hints) \
- V(tstart_br_systemresult) \
- V(ttest_br_systemresult) \
- V(uaba_asimdsame_only) \
- V(uaba_z_zzz) \
- V(uabal_asimddiff_l) \
- V(uabalb_z_zzz) \
- V(uabalt_z_zzz) \
- V(uabd_asimdsame_only) \
- V(uabd_z_p_zz) \
- V(uabdl_asimddiff_l) \
- V(uabdlb_z_zz) \
- V(uabdlt_z_zz) \
- V(uadalp_asimdmisc_p) \
- V(uadalp_z_p_z) \
- V(uaddl_asimddiff_l) \
- V(uaddlb_z_zz) \
- V(uaddlp_asimdmisc_p) \
- V(uaddlt_z_zz) \
- V(uaddlv_asimdall_only) \
- V(uaddv_r_p_z) \
- V(uaddw_asimddiff_w) \
- V(uaddwb_z_zz) \
- V(uaddwt_z_zz) \
- V(ubfm_32m_bitfield) \
- V(ubfm_64m_bitfield) \
- V(ucvtf_asimdmisc_r) \
- V(ucvtf_asimdmiscfp16_r) \
- V(ucvtf_asimdshf_c) \
- V(ucvtf_asisdmisc_r) \
- V(ucvtf_asisdmiscfp16_r) \
- V(ucvtf_asisdshf_c) \
- V(ucvtf_d32_float2fix) \
- V(ucvtf_d32_float2int) \
- V(ucvtf_d64_float2fix) \
- V(ucvtf_d64_float2int) \
- V(ucvtf_h32_float2fix) \
- V(ucvtf_h32_float2int) \
- V(ucvtf_h64_float2fix) \
- V(ucvtf_h64_float2int) \
- V(ucvtf_s32_float2fix) \
- V(ucvtf_s32_float2int) \
- V(ucvtf_s64_float2fix) \
- V(ucvtf_s64_float2int) \
- V(ucvtf_z_p_z_h2fp16) \
- V(ucvtf_z_p_z_w2d) \
- V(ucvtf_z_p_z_w2fp16) \
- V(ucvtf_z_p_z_w2s) \
- V(ucvtf_z_p_z_x2d) \
- V(ucvtf_z_p_z_x2fp16) \
- V(ucvtf_z_p_z_x2s) \
- V(udf_only_perm_undef) \
- V(udiv_32_dp_2src) \
- V(udiv_64_dp_2src) \
- V(udiv_z_p_zz) \
- V(udivr_z_p_zz) \
- V(udot_asimdelem_d) \
- V(udot_asimdsame2_d) \
- V(udot_z_zzz) \
- V(udot_z_zzzi_d) \
- V(udot_z_zzzi_s) \
- V(uhadd_asimdsame_only) \
- V(uhadd_z_p_zz) \
- V(uhsub_asimdsame_only) \
- V(uhsub_z_p_zz) \
- V(uhsubr_z_p_zz) \
- V(umaddl_64wa_dp_3src) \
- V(umax_asimdsame_only) \
- V(umax_z_p_zz) \
- V(umax_z_zi) \
- V(umaxp_asimdsame_only) \
- V(umaxp_z_p_zz) \
- V(umaxv_asimdall_only) \
- V(umaxv_r_p_z) \
- V(umin_asimdsame_only) \
- V(umin_z_p_zz) \
- V(umin_z_zi) \
- V(uminp_asimdsame_only) \
- V(uminp_z_p_zz) \
- V(uminv_asimdall_only) \
- V(uminv_r_p_z) \
- V(umlal_asimddiff_l) \
- V(umlal_asimdelem_l) \
- V(umlalb_z_zzz) \
- V(umlalb_z_zzzi_d) \
- V(umlalb_z_zzzi_s) \
- V(umlalt_z_zzz) \
- V(umlalt_z_zzzi_d) \
- V(umlalt_z_zzzi_s) \
- V(umlsl_asimddiff_l) \
- V(umlsl_asimdelem_l) \
- V(umlslb_z_zzz) \
- V(umlslb_z_zzzi_d) \
- V(umlslb_z_zzzi_s) \
- V(umlslt_z_zzz) \
- V(umlslt_z_zzzi_d) \
- V(umlslt_z_zzzi_s) \
- V(ummla_asimdsame2_g) \
- V(ummla_z_zzz) \
- V(umov_asimdins_w_w) \
- V(umov_asimdins_x_x) \
- V(umsubl_64wa_dp_3src) \
- V(umulh_64_dp_3src) \
- V(umulh_z_p_zz) \
- V(umulh_z_zz) \
- V(umull_asimddiff_l) \
- V(umull_asimdelem_l) \
- V(umullb_z_zz) \
- V(umullb_z_zzi_d) \
- V(umullb_z_zzi_s) \
- V(umullt_z_zz) \
- V(umullt_z_zzi_d) \
- V(umullt_z_zzi_s) \
- V(uqadd_asimdsame_only) \
- V(uqadd_asisdsame_only) \
- V(uqadd_z_p_zz) \
- V(uqadd_z_zi) \
- V(uqadd_z_zz) \
- V(uqdecb_r_rs_uw) \
- V(uqdecb_r_rs_x) \
- V(uqdecd_r_rs_uw) \
- V(uqdecd_r_rs_x) \
- V(uqdecd_z_zs) \
- V(uqdech_r_rs_uw) \
- V(uqdech_r_rs_x) \
- V(uqdech_z_zs) \
- V(uqdecp_r_p_r_uw) \
- V(uqdecp_r_p_r_x) \
- V(uqdecp_z_p_z) \
- V(uqdecw_r_rs_uw) \
- V(uqdecw_r_rs_x) \
- V(uqdecw_z_zs) \
- V(uqincb_r_rs_uw) \
- V(uqincb_r_rs_x) \
- V(uqincd_r_rs_uw) \
- V(uqincd_r_rs_x) \
- V(uqincd_z_zs) \
- V(uqinch_r_rs_uw) \
- V(uqinch_r_rs_x) \
- V(uqinch_z_zs) \
- V(uqincp_r_p_r_uw) \
- V(uqincp_r_p_r_x) \
- V(uqincp_z_p_z) \
- V(uqincw_r_rs_uw) \
- V(uqincw_r_rs_x) \
- V(uqincw_z_zs) \
- V(uqrshl_asimdsame_only) \
- V(uqrshl_asisdsame_only) \
- V(uqrshl_z_p_zz) \
- V(uqrshlr_z_p_zz) \
- V(uqrshrn_asimdshf_n) \
- V(uqrshrn_asisdshf_n) \
- V(uqrshrnb_z_zi) \
- V(uqrshrnt_z_zi) \
- V(uqshl_asimdsame_only) \
- V(uqshl_asimdshf_r) \
- V(uqshl_asisdsame_only) \
- V(uqshl_asisdshf_r) \
- V(uqshl_z_p_zi) \
- V(uqshl_z_p_zz) \
- V(uqshlr_z_p_zz) \
- V(uqshrn_asimdshf_n) \
- V(uqshrn_asisdshf_n) \
- V(uqshrnb_z_zi) \
- V(uqshrnt_z_zi) \
- V(uqsub_asimdsame_only) \
- V(uqsub_asisdsame_only) \
- V(uqsub_z_p_zz) \
- V(uqsub_z_zi) \
- V(uqsub_z_zz) \
- V(uqsubr_z_p_zz) \
- V(uqxtn_asimdmisc_n) \
- V(uqxtn_asisdmisc_n) \
- V(uqxtnb_z_zz) \
- V(uqxtnt_z_zz) \
- V(urecpe_asimdmisc_r) \
- V(urecpe_z_p_z) \
- V(urhadd_asimdsame_only) \
- V(urhadd_z_p_zz) \
- V(urshl_asimdsame_only) \
- V(urshl_asisdsame_only) \
- V(urshl_z_p_zz) \
- V(urshlr_z_p_zz) \
- V(urshr_asimdshf_r) \
- V(urshr_asisdshf_r) \
- V(urshr_z_p_zi) \
- V(ursqrte_asimdmisc_r) \
- V(ursqrte_z_p_z) \
- V(ursra_asimdshf_r) \
- V(ursra_asisdshf_r) \
- V(ursra_z_zi) \
- V(usdot_asimdelem_d) \
- V(usdot_asimdsame2_d) \
- V(usdot_z_zzz_s) \
- V(usdot_z_zzzi_s) \
- V(ushl_asimdsame_only) \
- V(ushl_asisdsame_only) \
- V(ushll_asimdshf_l) \
- V(ushllb_z_zi) \
- V(ushllt_z_zi) \
- V(ushr_asimdshf_r) \
- V(ushr_asisdshf_r) \
- V(usmmla_asimdsame2_g) \
- V(usmmla_z_zzz) \
- V(usqadd_asimdmisc_r) \
- V(usqadd_asisdmisc_r) \
- V(usqadd_z_p_zz) \
- V(usra_asimdshf_r) \
- V(usra_asisdshf_r) \
- V(usra_z_zi) \
- V(usubl_asimddiff_l) \
- V(usublb_z_zz) \
- V(usublt_z_zz) \
- V(usubw_asimddiff_w) \
- V(usubwb_z_zz) \
- V(usubwt_z_zz) \
- V(uunpkhi_z_z) \
- V(uunpklo_z_z) \
- V(uxtb_z_p_z) \
- V(uxth_z_p_z) \
- V(uxtw_z_p_z) \
- V(uzp1_asimdperm_only) \
- V(uzp1_p_pp) \
- V(uzp1_z_zz) \
- V(uzp1_z_zz_q) \
- V(uzp2_asimdperm_only) \
- V(uzp2_p_pp) \
- V(uzp2_z_zz) \
- V(uzp2_z_zz_q) \
- V(wfe_hi_hints) \
- V(wfet_only_systeminstrswithreg) \
- V(wfi_hi_hints) \
- V(wfit_only_systeminstrswithreg) \
- V(whilege_p_p_rr) \
- V(whilegt_p_p_rr) \
- V(whilehi_p_p_rr) \
- V(whilehs_p_p_rr) \
- V(whilele_p_p_rr) \
- V(whilelo_p_p_rr) \
- V(whilels_p_p_rr) \
- V(whilelt_p_p_rr) \
- V(whilerw_p_rr) \
- V(whilewr_p_rr) \
- V(wrffr_f_p) \
- V(xaflag_m_pstate) \
- V(xar_vvv2_crypto3_imm6) \
- V(xar_z_zzi) \
- V(xpacd_64z_dp_1src) \
- V(xpaci_64z_dp_1src) \
- V(xpaclri_hi_hints) \
- V(xtn_asimdmisc_n) \
- V(yield_hi_hints) \
- V(zip1_asimdperm_only) \
- V(zip1_p_pp) \
- V(zip1_z_zz) \
- V(zip1_z_zz_q) \
- V(zip2_asimdperm_only) \
- V(zip2_p_pp) \
- V(zip2_z_zz) \
- V(zip2_z_zz_q) \
- V(Unallocated)
-
#define VISITOR_LIST_THAT_RETURN(V) \
V(AddSubExtended) \
V(AddSubImmediate) \
@@ -3000,9 +364,7 @@
// of visitors stored by the decoder.
void RemoveVisitor(DecoderVisitor* visitor);
-#define DECLARE(A) void Visit_##A(const Instruction* instr);
- INSTRUCTION_VISITOR_LIST(DECLARE)
-#undef DECLARE
+ void VisitNamedInstruction(const Instruction* instr, const std::string& name);
std::list<DecoderVisitor*>* visitors() { return &visitors_; }
@@ -3032,8 +394,6 @@
std::map<std::string, DecodeNode> decode_nodes_;
};
-const int kMaxDecodeSampledBits = 24;
-const int kMaxDecodeMappings = 280;
typedef void (Decoder::*DecodeFnPtr)(const Instruction*);
typedef uint32_t (Instruction::*BitExtractFn)(void) const;
@@ -3047,10 +407,14 @@
// compilation stage. After compilation, the decoder is embodied in the graph
// of CompiledDecodeNodes pointer to by compiled_decoder_root_.
-// A DecodePattern maps a pattern of set/unset/don't care (1, 0, x) bits as a
-// string to the name of its handler.
+// A DecodePattern maps a pattern of set/unset/don't care (1, 0, x) bits encoded
+// as uint32_t to its handler.
+// The encoding uses two bits per symbol: 0 => 0b00, 1 => 0b01, x => 0b10.
+// 0b11 marks the edge of the most-significant bits of the pattern, which is
+// required to determine the length. For example, the pattern "1x01"_b is
+// encoded in a uint32_t as 0b11_01_10_00_01.
struct DecodePattern {
- const char* pattern;
+ uint32_t pattern;
const char* handler;
};
@@ -3059,8 +423,8 @@
// sampled bits match to the corresponding name of a node.
struct DecodeMapping {
const char* name;
- const uint8_t sampled_bits[kMaxDecodeSampledBits];
- const DecodePattern mapping[kMaxDecodeMappings];
+ const std::vector<uint8_t> sampled_bits;
+ const std::vector<DecodePattern> mapping;
};
// For speed, before nodes can be used for decoding instructions, they must
@@ -3074,7 +438,7 @@
// function that extracts the bits to be sampled.
CompiledDecodeNode(BitExtractFn bit_extract_fn, size_t decode_table_size)
: bit_extract_fn_(bit_extract_fn),
- visitor_fn_(NULL),
+ instruction_name_("node"),
decode_table_size_(decode_table_size),
decoder_(NULL) {
decode_table_ = new CompiledDecodeNode*[decode_table_size_];
@@ -3083,9 +447,9 @@
// Constructor for wrappers around visitor functions. These require no
// decoding, so no bit extraction function or decode table is assigned.
- explicit CompiledDecodeNode(DecodeFnPtr visitor_fn, Decoder* decoder)
+ explicit CompiledDecodeNode(std::string iname, Decoder* decoder)
: bit_extract_fn_(NULL),
- visitor_fn_(visitor_fn),
+ instruction_name_(iname),
decode_table_(NULL),
decode_table_size_(0),
decoder_(decoder) {}
@@ -3105,9 +469,9 @@
// A leaf node is a wrapper for a visitor function.
bool IsLeafNode() const {
- VIXL_ASSERT(((visitor_fn_ == NULL) && (bit_extract_fn_ != NULL)) ||
- ((visitor_fn_ != NULL) && (bit_extract_fn_ == NULL)));
- return visitor_fn_ != NULL;
+ VIXL_ASSERT(((instruction_name_ == "node") && (bit_extract_fn_ != NULL)) ||
+ ((instruction_name_ != "node") && (bit_extract_fn_ == NULL)));
+ return instruction_name_ != "node";
}
// Get a pointer to the next node required in the decode process, based on the
@@ -3132,7 +496,7 @@
// Visitor function that handles the instruction identified. Set only for
// leaf nodes, where no extra decoding is required, otherwise NULL.
- const DecodeFnPtr visitor_fn_;
+ std::string instruction_name_;
// Mapping table from instruction bits to next decode stage.
CompiledDecodeNode** decode_table_;
@@ -3146,30 +510,35 @@
class DecodeNode {
public:
// Default constructor needed for map initialisation.
- DecodeNode() : compiled_node_(NULL) {}
+ DecodeNode()
+ : sampled_bits_(DecodeNode::kEmptySampledBits),
+ pattern_table_(DecodeNode::kEmptyPatternTable),
+ compiled_node_(NULL) {}
// Constructor for DecodeNode wrappers around visitor functions. These are
// marked as "compiled", as there is no decoding left to do.
- explicit DecodeNode(const VisitorNode& visitor, Decoder* decoder)
- : name_(visitor.name),
- visitor_fn_(visitor.visitor_fn),
+ explicit DecodeNode(const std::string& iname, Decoder* decoder)
+ : name_(iname),
+ sampled_bits_(DecodeNode::kEmptySampledBits),
+ instruction_name_(iname),
+ pattern_table_(DecodeNode::kEmptyPatternTable),
decoder_(decoder),
compiled_node_(NULL) {}
// Constructor for DecodeNodes that map bit patterns to other DecodeNodes.
explicit DecodeNode(const DecodeMapping& map, Decoder* decoder = NULL)
: name_(map.name),
- visitor_fn_(NULL),
+ sampled_bits_(map.sampled_bits),
+ instruction_name_("node"),
+ pattern_table_(map.mapping),
decoder_(decoder),
compiled_node_(NULL) {
- // The length of the bit string in the first mapping determines the number
- // of sampled bits. When adding patterns later, we assert that all mappings
- // sample the same number of bits.
- VIXL_CHECK(strcmp(map.mapping[0].pattern, "otherwise") != 0);
- int bit_count = static_cast<int>(strlen(map.mapping[0].pattern));
- VIXL_CHECK((bit_count > 0) && (bit_count <= 32));
- SetSampledBits(map.sampled_bits, bit_count);
- AddPatterns(map.mapping);
+ // With the current two bits per symbol encoding scheme, the maximum pattern
+ // length is (32 - 2) / 2 = 15 bits.
+ VIXL_CHECK(GetPatternLength(map.mapping[0].pattern) <= 15);
+ for (const DecodePattern& p : map.mapping) {
+ VIXL_CHECK(GetPatternLength(p.pattern) == map.sampled_bits.size());
+ }
}
~DecodeNode() {
@@ -3179,21 +548,15 @@
}
}
- // Set the bits sampled from the instruction by this node.
- void SetSampledBits(const uint8_t* bits, int bit_count);
-
// Get the bits sampled from the instruction by this node.
- std::vector<uint8_t> GetSampledBits() const;
+ const std::vector<uint8_t>& GetSampledBits() const { return sampled_bits_; }
// Get the number of bits sampled from the instruction by this node.
- size_t GetSampledBitsCount() const;
-
- // Add patterns to this node's internal pattern table.
- void AddPatterns(const DecodePattern* patterns);
+ size_t GetSampledBitsCount() const { return sampled_bits_.size(); }
// A leaf node is a DecodeNode that wraps the visitor function for the
// identified instruction class.
- bool IsLeafNode() const { return visitor_fn_ != NULL; }
+ bool IsLeafNode() const { return instruction_name_ != "node"; }
std::string GetName() const { return name_; }
@@ -3208,7 +571,7 @@
// Create a CompiledDecodeNode wrapping a visitor function. No decoding is
// required for this node; the visitor function is called instead.
void CreateVisitorNode() {
- compiled_node_ = new CompiledDecodeNode(visitor_fn_, decoder_);
+ compiled_node_ = new CompiledDecodeNode(instruction_name_, decoder_);
}
// Find and compile the DecodeNode named "name", and set it as the node for
@@ -3241,22 +604,53 @@
CompiledDecodeNode* GetCompiledNode() const { return compiled_node_; }
bool IsCompiled() const { return GetCompiledNode() != NULL; }
- private:
- // Generate a mask and value pair from a string constructed from 0, 1 and x
- // (don't care) characters.
- // For example "10x1" should return mask = 0b1101, value = 0b1001.
- typedef std::pair<Instr, Instr> MaskValuePair;
- MaskValuePair GenerateMaskValuePair(std::string pattern) const;
+ enum class PatternSymbol { kSymbol0 = 0, kSymbol1 = 1, kSymbolX = 2 };
+ static const uint32_t kEndOfPattern = 3;
+ static const uint32_t kPatternSymbolMask = 3;
- // Generate a pattern string ordered by the bit positions sampled by this
- // node. The first character in the string corresponds to the lowest sampled
- // bit.
- // For example, a pattern of "1x0" expected when sampling bits 31, 1 and 30
- // returns the pattern "x01"; bit 1 should be 'x', bit 30 '0' and bit 31 '1'.
+ size_t GetPatternLength(uint32_t pattern) const {
+ uint32_t hsb = HighestSetBitPosition(pattern);
+ // The pattern length is signified by two set bits in a two bit-aligned
+ // position. Ensure that the pattern has a highest set bit, it's at an odd
+ // bit position, and that the bit to the right of the hsb is also set.
+ VIXL_ASSERT(((hsb % 2) == 1) && (pattern >> (hsb - 1)) == kEndOfPattern);
+ return hsb / 2;
+ }
+
+ bool PatternContainsSymbol(uint32_t pattern, PatternSymbol symbol) const {
+ while ((pattern & kPatternSymbolMask) != kEndOfPattern) {
+ if (static_cast<PatternSymbol>(pattern & kPatternSymbolMask) == symbol)
+ return true;
+ pattern >>= 2;
+ }
+ return false;
+ }
+
+ PatternSymbol GetSymbolAt(uint32_t pattern, size_t pos) const {
+ size_t len = GetPatternLength(pattern);
+ VIXL_ASSERT((pos < 15) && (pos < len));
+ uint32_t shift = static_cast<uint32_t>(2 * (len - pos - 1));
+ uint32_t sym = (pattern >> shift) & kPatternSymbolMask;
+ return static_cast<PatternSymbol>(sym);
+ }
+
+ private:
+ // Generate a mask and value pair from a pattern constructed from 0, 1 and x
+ // (don't care) 2-bit symbols.
+ // For example "10x1"_b should return mask = 0b1101, value = 0b1001.
+ typedef std::pair<Instr, Instr> MaskValuePair;
+ MaskValuePair GenerateMaskValuePair(uint32_t pattern) const;
+
+ // Generate a pattern ordered by the bit positions sampled by this node.
+ // The symbol corresponding to the lowest sample position is placed in the
+ // least-significant bits of the result pattern.
+ // For example, a pattern of "1x0"_b expected when sampling bits 31, 1 and 30
+ // returns the pattern "x01"_b; bit 1 should be 'x', bit 30 '0' and bit 31
+ // '1'.
// This output makes comparisons easier between the pattern and bits sampled
// from an instruction using the fast "compress" algorithm. See
// Instruction::Compress().
- std::string GenerateOrderedPattern(std::string pattern) const;
+ uint32_t GenerateOrderedPattern(uint32_t pattern) const;
// Generate a mask with a bit set at each sample position.
uint32_t GenerateSampledBitsMask() const;
@@ -3275,15 +669,16 @@
// Vector of bits sampled from an instruction to determine which node to look
// up next in the decode process.
- std::vector<uint8_t> sampled_bits_;
+ const std::vector<uint8_t>& sampled_bits_;
+ static const std::vector<uint8_t> kEmptySampledBits;
- // Visitor function that handles the instruction identified. Set only for leaf
- // nodes, where no extra decoding is required. For non-leaf decoding nodes,
- // this pointer is NULL.
- DecodeFnPtr visitor_fn_;
+ // For leaf nodes, this is the name of the instruction form that the node
+ // represents. For other nodes, this is always set to "node".
+ std::string instruction_name_;
// Source mapping from bit pattern to name of next decode stage.
- std::vector<DecodePattern> pattern_table_;
+ const std::vector<DecodePattern>& pattern_table_;
+ static const std::vector<DecodePattern> kEmptyPatternTable;
// Pointer to the decoder containing this node, used to call its visitor
// function for leaf nodes.
diff --git a/src/aarch64/decoder-constants-aarch64.h b/src/aarch64/decoder-constants-aarch64.h
index 8c97cb6..ddfdff6 100644
--- a/src/aarch64/decoder-constants-aarch64.h
+++ b/src/aarch64/decoder-constants-aarch64.h
@@ -27,8805 +27,8816 @@
namespace vixl {
namespace aarch64 {
+// Recursively construct a uint32_t encoded bit pattern from a string literal.
+// The string characters are mapped as two-bit symbols '0'=>0, '1'=>1, 'x'=>2.
+// The remaining symbol, 3, is used to mark the end of the pattern, allowing
+// its length to be found. For example, the pattern "1x01"_b is encoded in a
+// uint32_t as 0b11_01_00_01. The maximum pattern string length is 15
+// characters, encoded as 3 in the most significant bits, followed by 15 2-bit
+// symbols.
+constexpr uint32_t str_to_two_bit_pattern(const char* x, size_t s, uint32_t a) {
+ if (s == 0) return a;
+ uint32_t r = (x[0] == 'x') ? 2 : (x[0] - '0');
+ return str_to_two_bit_pattern(x + 1, s - 1, (a << 2) | r);
+}
+
+constexpr uint32_t operator"" _b(const char* x, size_t s) {
+ return str_to_two_bit_pattern(x, s, DecodeNode::kEndOfPattern);
+}
+
// This decode table is derived from the AArch64 ISA XML specification,
// available from https://developer.arm.com/products/architecture/a-profile/
// clang-format off
static const DecodeMapping kDecodeMapping[] = {
- { "Decode_gggyqx",
+ { "_gggyqx",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_fcvtnu_asimdmiscfp16_r"},
- {"0x00001", "Visit_fcvtnu_asimdmisc_r"},
- {"1111001", "Visit_fcvtpu_asimdmiscfp16_r"},
- {"1x00001", "Visit_fcvtpu_asimdmisc_r"},
- {"xx10000", "Visit_umaxv_asimdall_only"},
- {"xx10001", "Visit_uminv_asimdall_only"},
+ { {"0111001"_b, "fcvtnu_asimdmiscfp16_r"},
+ {"0x00001"_b, "fcvtnu_asimdmisc_r"},
+ {"1111001"_b, "fcvtpu_asimdmiscfp16_r"},
+ {"1x00001"_b, "fcvtpu_asimdmisc_r"},
+ {"xx10000"_b, "umaxv_asimdall_only"},
+ {"xx10001"_b, "uminv_asimdall_only"},
},
},
- { "Decode_ggvztl",
+ { "_ggvztl",
{30},
- { {"0", "Visit_bl_only_branch_imm"},
- {"1", "Decode_qpzynz"},
+ { {"0"_b, "bl_only_branch_imm"},
+ {"1"_b, "_qpzynz"},
},
},
- { "Decode_ghmzhr",
+ { "_ghmzhr",
{20, 19, 18, 17, 16, 13, 12},
- { {"0000000", "Visit_rbit_32_dp_1src"},
- {"0000001", "Visit_clz_32_dp_1src"},
+ { {"0000000"_b, "rbit_32_dp_1src"},
+ {"0000001"_b, "clz_32_dp_1src"},
},
},
- { "Decode_ghnljt",
+ { "_ghnljt",
{23, 22, 20, 19, 18, 17, 16},
- { {"0000000", "Visit_fcvtns_64s_float2int"},
- {"0000001", "Visit_fcvtnu_64s_float2int"},
- {"0000010", "Visit_scvtf_s64_float2int"},
- {"0000011", "Visit_ucvtf_s64_float2int"},
- {"0000100", "Visit_fcvtas_64s_float2int"},
- {"0000101", "Visit_fcvtau_64s_float2int"},
- {"0001000", "Visit_fcvtps_64s_float2int"},
- {"0001001", "Visit_fcvtpu_64s_float2int"},
- {"0010000", "Visit_fcvtms_64s_float2int"},
- {"0010001", "Visit_fcvtmu_64s_float2int"},
- {"0011000", "Visit_fcvtzs_64s_float2int"},
- {"0011001", "Visit_fcvtzu_64s_float2int"},
- {"0100000", "Visit_fcvtns_64d_float2int"},
- {"0100001", "Visit_fcvtnu_64d_float2int"},
- {"0100010", "Visit_scvtf_d64_float2int"},
- {"0100011", "Visit_ucvtf_d64_float2int"},
- {"0100100", "Visit_fcvtas_64d_float2int"},
- {"0100101", "Visit_fcvtau_64d_float2int"},
- {"0100110", "Visit_fmov_64d_float2int"},
- {"0100111", "Visit_fmov_d64_float2int"},
- {"0101000", "Visit_fcvtps_64d_float2int"},
- {"0101001", "Visit_fcvtpu_64d_float2int"},
- {"0110000", "Visit_fcvtms_64d_float2int"},
- {"0110001", "Visit_fcvtmu_64d_float2int"},
- {"0111000", "Visit_fcvtzs_64d_float2int"},
- {"0111001", "Visit_fcvtzu_64d_float2int"},
- {"1001110", "Visit_fmov_64vx_float2int"},
- {"1001111", "Visit_fmov_v64i_float2int"},
- {"1100000", "Visit_fcvtns_64h_float2int"},
- {"1100001", "Visit_fcvtnu_64h_float2int"},
- {"1100010", "Visit_scvtf_h64_float2int"},
- {"1100011", "Visit_ucvtf_h64_float2int"},
- {"1100100", "Visit_fcvtas_64h_float2int"},
- {"1100101", "Visit_fcvtau_64h_float2int"},
- {"1100110", "Visit_fmov_64h_float2int"},
- {"1100111", "Visit_fmov_h64_float2int"},
- {"1101000", "Visit_fcvtps_64h_float2int"},
- {"1101001", "Visit_fcvtpu_64h_float2int"},
- {"1110000", "Visit_fcvtms_64h_float2int"},
- {"1110001", "Visit_fcvtmu_64h_float2int"},
- {"1111000", "Visit_fcvtzs_64h_float2int"},
- {"1111001", "Visit_fcvtzu_64h_float2int"},
+ { {"0000000"_b, "fcvtns_64s_float2int"},
+ {"0000001"_b, "fcvtnu_64s_float2int"},
+ {"0000010"_b, "scvtf_s64_float2int"},
+ {"0000011"_b, "ucvtf_s64_float2int"},
+ {"0000100"_b, "fcvtas_64s_float2int"},
+ {"0000101"_b, "fcvtau_64s_float2int"},
+ {"0001000"_b, "fcvtps_64s_float2int"},
+ {"0001001"_b, "fcvtpu_64s_float2int"},
+ {"0010000"_b, "fcvtms_64s_float2int"},
+ {"0010001"_b, "fcvtmu_64s_float2int"},
+ {"0011000"_b, "fcvtzs_64s_float2int"},
+ {"0011001"_b, "fcvtzu_64s_float2int"},
+ {"0100000"_b, "fcvtns_64d_float2int"},
+ {"0100001"_b, "fcvtnu_64d_float2int"},
+ {"0100010"_b, "scvtf_d64_float2int"},
+ {"0100011"_b, "ucvtf_d64_float2int"},
+ {"0100100"_b, "fcvtas_64d_float2int"},
+ {"0100101"_b, "fcvtau_64d_float2int"},
+ {"0100110"_b, "fmov_64d_float2int"},
+ {"0100111"_b, "fmov_d64_float2int"},
+ {"0101000"_b, "fcvtps_64d_float2int"},
+ {"0101001"_b, "fcvtpu_64d_float2int"},
+ {"0110000"_b, "fcvtms_64d_float2int"},
+ {"0110001"_b, "fcvtmu_64d_float2int"},
+ {"0111000"_b, "fcvtzs_64d_float2int"},
+ {"0111001"_b, "fcvtzu_64d_float2int"},
+ {"1001110"_b, "fmov_64vx_float2int"},
+ {"1001111"_b, "fmov_v64i_float2int"},
+ {"1100000"_b, "fcvtns_64h_float2int"},
+ {"1100001"_b, "fcvtnu_64h_float2int"},
+ {"1100010"_b, "scvtf_h64_float2int"},
+ {"1100011"_b, "ucvtf_h64_float2int"},
+ {"1100100"_b, "fcvtas_64h_float2int"},
+ {"1100101"_b, "fcvtau_64h_float2int"},
+ {"1100110"_b, "fmov_64h_float2int"},
+ {"1100111"_b, "fmov_h64_float2int"},
+ {"1101000"_b, "fcvtps_64h_float2int"},
+ {"1101001"_b, "fcvtpu_64h_float2int"},
+ {"1110000"_b, "fcvtms_64h_float2int"},
+ {"1110001"_b, "fcvtmu_64h_float2int"},
+ {"1111000"_b, "fcvtzs_64h_float2int"},
+ {"1111001"_b, "fcvtzu_64h_float2int"},
},
},
- { "Decode_gjprmg",
+ { "_gjprmg",
{11},
- { {"0", "Decode_llpsqq"},
+ { {"0"_b, "_llpsqq"},
},
},
- { "Decode_gjsnly",
+ { "_gjsnly",
{16, 13, 12},
- { {"000", "Visit_rev16_64_dp_1src"},
- {"001", "Visit_cls_64_dp_1src"},
- {"100", "Visit_pacib_64p_dp_1src"},
- {"101", "Visit_autib_64p_dp_1src"},
- {"110", "Decode_ksvxxm"},
- {"111", "Decode_xsgxyy"},
+ { {"000"_b, "rev16_64_dp_1src"},
+ {"001"_b, "cls_64_dp_1src"},
+ {"100"_b, "pacib_64p_dp_1src"},
+ {"101"_b, "autib_64p_dp_1src"},
+ {"110"_b, "_ksvxxm"},
+ {"111"_b, "_xsgxyy"},
},
},
- { "Decode_gjylrt",
+ { "_gjylrt",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_fcvtns_32h_float2int"},
- {"00001", "Visit_fcvtnu_32h_float2int"},
- {"00010", "Visit_scvtf_h32_float2int"},
- {"00011", "Visit_ucvtf_h32_float2int"},
- {"00100", "Visit_fcvtas_32h_float2int"},
- {"00101", "Visit_fcvtau_32h_float2int"},
- {"00110", "Visit_fmov_32h_float2int"},
- {"00111", "Visit_fmov_h32_float2int"},
- {"01000", "Visit_fcvtps_32h_float2int"},
- {"01001", "Visit_fcvtpu_32h_float2int"},
- {"10000", "Visit_fcvtms_32h_float2int"},
- {"10001", "Visit_fcvtmu_32h_float2int"},
- {"11000", "Visit_fcvtzs_32h_float2int"},
- {"11001", "Visit_fcvtzu_32h_float2int"},
+ { {"00000"_b, "fcvtns_32h_float2int"},
+ {"00001"_b, "fcvtnu_32h_float2int"},
+ {"00010"_b, "scvtf_h32_float2int"},
+ {"00011"_b, "ucvtf_h32_float2int"},
+ {"00100"_b, "fcvtas_32h_float2int"},
+ {"00101"_b, "fcvtau_32h_float2int"},
+ {"00110"_b, "fmov_32h_float2int"},
+ {"00111"_b, "fmov_h32_float2int"},
+ {"01000"_b, "fcvtps_32h_float2int"},
+ {"01001"_b, "fcvtpu_32h_float2int"},
+ {"10000"_b, "fcvtms_32h_float2int"},
+ {"10001"_b, "fcvtmu_32h_float2int"},
+ {"11000"_b, "fcvtzs_32h_float2int"},
+ {"11001"_b, "fcvtzu_32h_float2int"},
},
},
- { "Decode_gkhhjm",
+ { "_gkhhjm",
{30, 23, 22},
- { {"000", "Visit_sbfm_32m_bitfield"},
- {"100", "Visit_ubfm_32m_bitfield"},
+ { {"000"_b, "sbfm_32m_bitfield"},
+ {"100"_b, "ubfm_32m_bitfield"},
},
},
- { "Decode_gkkpjz",
+ { "_gkkpjz",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_fcvtmu_asisdmiscfp16_r"},
- {"0x00001", "Visit_fcvtmu_asisdmisc_r"},
- {"1111001", "Visit_fcvtzu_asisdmiscfp16_r"},
- {"1x00001", "Visit_fcvtzu_asisdmisc_r"},
- {"xx00000", "Visit_neg_asisdmisc_r"},
+ { {"0111001"_b, "fcvtmu_asisdmiscfp16_r"},
+ {"0x00001"_b, "fcvtmu_asisdmisc_r"},
+ {"1111001"_b, "fcvtzu_asisdmiscfp16_r"},
+ {"1x00001"_b, "fcvtzu_asisdmisc_r"},
+ {"xx00000"_b, "neg_asisdmisc_r"},
},
},
- { "Decode_gkpvxz",
+ { "_gkpvxz",
{10},
- { {"0", "Visit_blraa_64p_branch_reg"},
- {"1", "Visit_blrab_64p_branch_reg"},
+ { {"0"_b, "blraa_64p_branch_reg"},
+ {"1"_b, "blrab_64p_branch_reg"},
},
},
- { "Decode_gkpzhr",
+ { "_gkpzhr",
{30, 23, 22, 13, 12, 11, 10},
- { {"000xxxx", "Visit_fnmsub_s_floatdp3"},
- {"001xxxx", "Visit_fnmsub_d_floatdp3"},
- {"011xxxx", "Visit_fnmsub_h_floatdp3"},
- {"10001x0", "Visit_fmul_asisdelem_rh_h"},
- {"10x0101", "Visit_sqshrn_asisdshf_n"},
- {"10x0111", "Visit_sqrshrn_asisdshf_n"},
- {"11x01x0", "Visit_fmul_asisdelem_r_sd"},
- {"1xx11x0", "Visit_sqdmull_asisdelem_l"},
+ { {"000xxxx"_b, "fnmsub_s_floatdp3"},
+ {"001xxxx"_b, "fnmsub_d_floatdp3"},
+ {"011xxxx"_b, "fnmsub_h_floatdp3"},
+ {"10001x0"_b, "fmul_asisdelem_rh_h"},
+ {"10x0101"_b, "sqshrn_asisdshf_n"},
+ {"10x0111"_b, "sqrshrn_asisdshf_n"},
+ {"11x01x0"_b, "fmul_asisdelem_r_sd"},
+ {"1xx11x0"_b, "sqdmull_asisdelem_l"},
},
},
- { "Decode_gkxgsn",
+ { "_gkxgsn",
{30, 23, 22, 11, 10},
- { {"00000", "Visit_stlur_32_ldapstl_unscaled"},
- {"00100", "Visit_ldapur_32_ldapstl_unscaled"},
- {"01000", "Visit_ldapursw_64_ldapstl_unscaled"},
- {"10000", "Visit_stlur_64_ldapstl_unscaled"},
- {"10100", "Visit_ldapur_64_ldapstl_unscaled"},
+ { {"00000"_b, "stlur_32_ldapstl_unscaled"},
+ {"00100"_b, "ldapur_32_ldapstl_unscaled"},
+ {"01000"_b, "ldapursw_64_ldapstl_unscaled"},
+ {"10000"_b, "stlur_64_ldapstl_unscaled"},
+ {"10100"_b, "ldapur_64_ldapstl_unscaled"},
},
},
- { "Decode_glgrjy",
+ { "_glgrjy",
{23, 22, 20, 19, 18, 17, 16},
- { {"0000000", "Visit_not_asimdmisc_r"},
- {"0100000", "Visit_rbit_asimdmisc_r"},
+ { {"0000000"_b, "not_asimdmisc_r"},
+ {"0100000"_b, "rbit_asimdmisc_r"},
},
},
- { "Decode_glhxyj",
+ { "_glhxyj",
{17},
- { {"0", "Visit_ld3_asisdlsop_bx3_r3b"},
- {"1", "Visit_ld3_asisdlsop_b3_i3b"},
+ { {"0"_b, "ld3_asisdlsop_bx3_r3b"},
+ {"1"_b, "ld3_asisdlsop_b3_i3b"},
},
},
- { "Decode_glkzlv",
+ { "_glkzlv",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_rev16_asimdmisc_r"},
+ { {"00000"_b, "rev16_asimdmisc_r"},
},
},
- { "Decode_gmjhll",
+ { "_gmjhll",
{17},
- { {"0", "Visit_st1_asisdlsep_r4_r4"},
- {"1", "Visit_st1_asisdlsep_i4_i4"},
+ { {"0"_b, "st1_asisdlsep_r4_r4"},
+ {"1"_b, "st1_asisdlsep_i4_i4"},
},
},
- { "Decode_gmrxlp",
+ { "_gmrxlp",
{30},
- { {"0", "Visit_orr_32_log_shift"},
- {"1", "Visit_ands_32_log_shift"},
+ { {"0"_b, "orr_32_log_shift"},
+ {"1"_b, "ands_32_log_shift"},
},
},
- { "Decode_gmrxqq",
+ { "_gmrxqq",
{30, 23, 22},
- { {"000", "Visit_stp_q_ldstpair_off"},
- {"001", "Visit_ldp_q_ldstpair_off"},
- {"010", "Visit_stp_q_ldstpair_pre"},
- {"011", "Visit_ldp_q_ldstpair_pre"},
+ { {"000"_b, "stp_q_ldstpair_off"},
+ {"001"_b, "ldp_q_ldstpair_off"},
+ {"010"_b, "stp_q_ldstpair_pre"},
+ {"011"_b, "ldp_q_ldstpair_pre"},
},
},
- { "Decode_gmsgqz",
+ { "_gmsgqz",
{30, 23, 22},
- { {"100", "Visit_eor3_vvv16_crypto4"},
- {"101", "Visit_sm3ss1_vvv4_crypto4"},
- {"110", "Visit_xar_vvv2_crypto3_imm6"},
+ { {"100"_b, "eor3_vvv16_crypto4"},
+ {"101"_b, "sm3ss1_vvv4_crypto4"},
+ {"110"_b, "xar_vvv2_crypto3_imm6"},
},
},
- { "Decode_gmvjgn",
+ { "_gmvjgn",
{23},
- { {"0", "Visit_fmax_asimdsame_only"},
- {"1", "Visit_fmin_asimdsame_only"},
+ { {"0"_b, "fmax_asimdsame_only"},
+ {"1"_b, "fmin_asimdsame_only"},
},
},
- { "Decode_gmvrxn",
+ { "_gmvrxn",
{18, 17, 12},
- { {"000", "Visit_st4_asisdlso_d4_4d"},
+ { {"000"_b, "st4_asisdlso_d4_4d"},
},
},
- { "Decode_gmvtss",
+ { "_gmvtss",
{30},
- { {"0", "Visit_ldr_q_loadlit"},
+ { {"0"_b, "ldr_q_loadlit"},
},
},
- { "Decode_gngjxr",
+ { "_gngjxr",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_cadd_z_zz"},
- {"00001", "Visit_sqcadd_z_zz"},
+ { {"00000"_b, "cadd_z_zz"},
+ {"00001"_b, "sqcadd_z_zz"},
},
},
- { "Decode_gnqhsl",
+ { "_gnqhsl",
{23, 22, 20, 19, 18, 17, 16},
- { {"0010000", "Visit_punpklo_p_p"},
- {"0010001", "Visit_punpkhi_p_p"},
- {"xx0xxxx", "Visit_zip1_p_pp"},
- {"xx10100", "Visit_rev_p_p"},
+ { {"0010000"_b, "punpklo_p_p"},
+ {"0010001"_b, "punpkhi_p_p"},
+ {"xx0xxxx"_b, "zip1_p_pp"},
+ {"xx10100"_b, "rev_p_p"},
},
},
- { "Decode_gnqjhz",
+ { "_gnqjhz",
{20, 19, 18, 17, 16, 13, 12},
- { {"0000000", "Visit_rev16_32_dp_1src"},
- {"0000001", "Visit_cls_32_dp_1src"},
+ { {"0000000"_b, "rev16_32_dp_1src"},
+ {"0000001"_b, "cls_32_dp_1src"},
},
},
- { "Decode_gntpyh",
+ { "_gntpyh",
{23, 13, 12, 11, 10},
- { {"00010", "Decode_gqspys"},
- {"00110", "Decode_ymgrgx"},
- {"01001", "Visit_fcmge_asisdsame_only"},
- {"01011", "Visit_facge_asisdsame_only"},
- {"01110", "Decode_kjyphv"},
- {"10010", "Decode_myjqrl"},
- {"10101", "Visit_fabd_asisdsame_only"},
- {"10110", "Decode_vlsmsn"},
- {"11001", "Visit_fcmgt_asisdsame_only"},
- {"11011", "Visit_facgt_asisdsame_only"},
- {"11110", "Decode_pxtsvn"},
+ { {"00010"_b, "_gqspys"},
+ {"00110"_b, "_ymgrgx"},
+ {"01001"_b, "fcmge_asisdsame_only"},
+ {"01011"_b, "facge_asisdsame_only"},
+ {"01110"_b, "_kjyphv"},
+ {"10010"_b, "_myjqrl"},
+ {"10101"_b, "fabd_asisdsame_only"},
+ {"10110"_b, "_vlsmsn"},
+ {"11001"_b, "fcmgt_asisdsame_only"},
+ {"11011"_b, "facgt_asisdsame_only"},
+ {"11110"_b, "_pxtsvn"},
},
},
- { "Decode_gnxgxs",
+ { "_gnxgxs",
{30, 18},
- { {"00", "Decode_krlpjl"},
+ { {"00"_b, "_krlpjl"},
},
},
- { "Decode_gnytkh",
+ { "_gnytkh",
{1, 0},
- { {"11", "Visit_braaz_64_branch_reg"},
+ { {"11"_b, "braaz_64_branch_reg"},
},
},
- { "Decode_gpxltv",
+ { "_gpxltv",
{23, 18, 17, 16},
- { {"0000", "Visit_uqxtnt_z_zz"},
+ { {"0000"_b, "uqxtnt_z_zz"},
},
},
- { "Decode_gqspys",
+ { "_gqspys",
{22, 20, 19, 18, 17, 16},
- { {"111001", "Visit_fcvtau_asisdmiscfp16_r"},
- {"x00001", "Visit_fcvtau_asisdmisc_r"},
- {"x10000", "Visit_fmaxnmp_asisdpair_only_sd"},
+ { {"111001"_b, "fcvtau_asisdmiscfp16_r"},
+ {"x00001"_b, "fcvtau_asisdmisc_r"},
+ {"x10000"_b, "fmaxnmp_asisdpair_only_sd"},
},
},
- { "Decode_gqykqv",
+ { "_gqykqv",
{23, 22, 12},
- { {"000", "Decode_rjmyyl"},
- {"001", "Decode_zqltpy"},
- {"010", "Decode_hstvrp"},
- {"011", "Decode_yhqyzj"},
- {"110", "Decode_mxtskk"},
- {"111", "Decode_qmjqhq"},
+ { {"000"_b, "_rjmyyl"},
+ {"001"_b, "_zqltpy"},
+ {"010"_b, "_hstvrp"},
+ {"011"_b, "_yhqyzj"},
+ {"110"_b, "_mxtskk"},
+ {"111"_b, "_qmjqhq"},
},
},
- { "Decode_grqnlm",
+ { "_grqnlm",
{30, 23, 22, 13, 12, 11, 10},
- { {"000xxxx", "Visit_fnmadd_s_floatdp3"},
- {"001xxxx", "Visit_fnmadd_d_floatdp3"},
- {"011xxxx", "Visit_fnmadd_h_floatdp3"},
- {"10001x0", "Visit_fmla_asisdelem_rh_h"},
- {"10x0001", "Visit_sshr_asisdshf_r"},
- {"10x0101", "Visit_ssra_asisdshf_r"},
- {"10x1001", "Visit_srshr_asisdshf_r"},
- {"10x1101", "Visit_srsra_asisdshf_r"},
- {"11x01x0", "Visit_fmla_asisdelem_r_sd"},
- {"1xx11x0", "Visit_sqdmlal_asisdelem_l"},
+ { {"000xxxx"_b, "fnmadd_s_floatdp3"},
+ {"001xxxx"_b, "fnmadd_d_floatdp3"},
+ {"011xxxx"_b, "fnmadd_h_floatdp3"},
+ {"10001x0"_b, "fmla_asisdelem_rh_h"},
+ {"10x0001"_b, "sshr_asisdshf_r"},
+ {"10x0101"_b, "ssra_asisdshf_r"},
+ {"10x1001"_b, "srshr_asisdshf_r"},
+ {"10x1101"_b, "srsra_asisdshf_r"},
+ {"11x01x0"_b, "fmla_asisdelem_r_sd"},
+ {"1xx11x0"_b, "sqdmlal_asisdelem_l"},
},
},
- { "Decode_grrjlh",
+ { "_grrjlh",
{30},
- { {"1", "Decode_jlqxvj"},
+ { {"1"_b, "_jlqxvj"},
},
},
- { "Decode_grxzzg",
+ { "_grxzzg",
{23, 22},
- { {"00", "Visit_tbx_asimdtbl_l2_2"},
+ { {"00"_b, "tbx_asimdtbl_l2_2"},
},
},
- { "Decode_gsgzpg",
+ { "_gsgzpg",
{17},
- { {"0", "Visit_ld2_asisdlso_h2_2h"},
+ { {"0"_b, "ld2_asisdlso_h2_2h"},
},
},
- { "Decode_gshrzq",
+ { "_gshrzq",
{22, 20, 11},
- { {"010", "Visit_decb_r_rs"},
- {"110", "Visit_dech_r_rs"},
+ { {"010"_b, "decb_r_rs"},
+ {"110"_b, "dech_r_rs"},
},
},
- { "Decode_gskkxk",
+ { "_gskkxk",
{17},
- { {"0", "Visit_st1_asisdlso_h1_1h"},
+ { {"0"_b, "st1_asisdlso_h1_1h"},
},
},
- { "Decode_gsttpm",
+ { "_gsttpm",
{12},
- { {"0", "Visit_ld3_asisdlsop_dx3_r3d"},
+ { {"0"_b, "ld3_asisdlsop_dx3_r3d"},
},
},
- { "Decode_gszlvl",
+ { "_gszlvl",
{30},
- { {"0", "Decode_tvsszp"},
- {"1", "Decode_njtngm"},
+ { {"0"_b, "_tvsszp"},
+ {"1"_b, "_njtngm"},
},
},
- { "Decode_gszxkp",
+ { "_gszxkp",
{13, 12},
- { {"11", "Visit_cmgt_asisdsame_only"},
+ { {"11"_b, "cmgt_asisdsame_only"},
},
},
- { "Decode_gtjskz",
+ { "_gtjskz",
{30, 23, 22, 13, 12, 11, 10},
- { {"1011011", "Visit_bfmmla_asimdsame2_e"},
- {"x011111", "Visit_bfdot_asimdsame2_d"},
- {"x111111", "Visit_bfmlal_asimdsame2_f"},
- {"xxx0xx1", "Visit_fcmla_asimdsame2_c"},
- {"xxx1x01", "Visit_fcadd_asimdsame2_c"},
+ { {"1011011"_b, "bfmmla_asimdsame2_e"},
+ {"x011111"_b, "bfdot_asimdsame2_d"},
+ {"x111111"_b, "bfmlal_asimdsame2_f"},
+ {"xxx0xx1"_b, "fcmla_asimdsame2_c"},
+ {"xxx1x01"_b, "fcadd_asimdsame2_c"},
},
},
- { "Decode_gttglx",
+ { "_gttglx",
{17},
- { {"0", "Visit_st4_asisdlso_h4_4h"},
+ { {"0"_b, "st4_asisdlso_h4_4h"},
},
},
- { "Decode_gtvhmp",
+ { "_gtvhmp",
{30, 13},
- { {"00", "Decode_rjyrnt"},
- {"01", "Decode_mzhsrq"},
- {"10", "Decode_xtzlzy"},
- {"11", "Decode_kqxhzx"},
+ { {"00"_b, "_rjyrnt"},
+ {"01"_b, "_mzhsrq"},
+ {"10"_b, "_xtzlzy"},
+ {"11"_b, "_kqxhzx"},
},
},
- { "Decode_gtxpgx",
+ { "_gtxpgx",
{30, 23, 13, 4},
- { {"0000", "Visit_prfw_i_p_bz_s_x32_scaled"},
- {"0010", "Visit_prfd_i_p_bz_s_x32_scaled"},
- {"010x", "Visit_ld1h_z_p_bz_s_x32_scaled"},
- {"011x", "Visit_ldff1h_z_p_bz_s_x32_scaled"},
- {"1000", "Visit_prfw_i_p_bz_d_x32_scaled"},
- {"1010", "Visit_prfd_i_p_bz_d_x32_scaled"},
- {"110x", "Visit_ld1h_z_p_bz_d_x32_scaled"},
- {"111x", "Visit_ldff1h_z_p_bz_d_x32_scaled"},
+ { {"0000"_b, "prfw_i_p_bz_s_x32_scaled"},
+ {"0010"_b, "prfd_i_p_bz_s_x32_scaled"},
+ {"010x"_b, "ld1h_z_p_bz_s_x32_scaled"},
+ {"011x"_b, "ldff1h_z_p_bz_s_x32_scaled"},
+ {"1000"_b, "prfw_i_p_bz_d_x32_scaled"},
+ {"1010"_b, "prfd_i_p_bz_d_x32_scaled"},
+ {"110x"_b, "ld1h_z_p_bz_d_x32_scaled"},
+ {"111x"_b, "ldff1h_z_p_bz_d_x32_scaled"},
},
},
- { "Decode_gvjgyp",
+ { "_gvjgyp",
{23, 22, 13, 12, 11, 10},
- { {"0001x0", "Visit_fmls_asimdelem_rh_h"},
- {"0x0101", "Visit_shl_asimdshf_r"},
- {"0x1101", "Visit_sqshl_asimdshf_r"},
- {"1000x0", "Visit_fmlsl_asimdelem_lh"},
- {"1x01x0", "Visit_fmls_asimdelem_r_sd"},
- {"xx10x0", "Visit_smlsl_asimdelem_l"},
- {"xx11x0", "Visit_sqdmlsl_asimdelem_l"},
+ { {"0001x0"_b, "fmls_asimdelem_rh_h"},
+ {"0x0101"_b, "shl_asimdshf_r"},
+ {"0x1101"_b, "sqshl_asimdshf_r"},
+ {"1000x0"_b, "fmlsl_asimdelem_lh"},
+ {"1x01x0"_b, "fmls_asimdelem_r_sd"},
+ {"xx10x0"_b, "smlsl_asimdelem_l"},
+ {"xx11x0"_b, "sqdmlsl_asimdelem_l"},
},
},
- { "Decode_gvstrp",
+ { "_gvstrp",
{17},
- { {"0", "Visit_ld2_asisdlsop_bx2_r2b"},
- {"1", "Visit_ld2_asisdlsop_b2_i2b"},
+ { {"0"_b, "ld2_asisdlsop_bx2_r2b"},
+ {"1"_b, "ld2_asisdlsop_b2_i2b"},
},
},
- { "Decode_gvykrp",
+ { "_gvykrp",
{30, 23, 22, 13, 12, 11, 10},
- { {"10001x0", "Visit_fmulx_asisdelem_rh_h"},
- {"10x0001", "Visit_sqshrun_asisdshf_n"},
- {"10x0011", "Visit_sqrshrun_asisdshf_n"},
- {"10x0101", "Visit_uqshrn_asisdshf_n"},
- {"10x0111", "Visit_uqrshrn_asisdshf_n"},
- {"11x01x0", "Visit_fmulx_asisdelem_r_sd"},
+ { {"10001x0"_b, "fmulx_asisdelem_rh_h"},
+ {"10x0001"_b, "sqshrun_asisdshf_n"},
+ {"10x0011"_b, "sqrshrun_asisdshf_n"},
+ {"10x0101"_b, "uqshrn_asisdshf_n"},
+ {"10x0111"_b, "uqrshrn_asisdshf_n"},
+ {"11x01x0"_b, "fmulx_asisdelem_r_sd"},
},
},
- { "Decode_gxlvsg",
+ { "_gxlvsg",
{13},
- { {"0", "Decode_vpxvjs"},
- {"1", "Decode_lpslrz"},
+ { {"0"_b, "_vpxvjs"},
+ {"1"_b, "_lpslrz"},
},
},
- { "Decode_gxmnkl",
+ { "_gxmnkl",
{23, 22},
- { {"10", "Visit_cdot_z_zzzi_s"},
- {"11", "Visit_cdot_z_zzzi_d"},
+ { {"10"_b, "cdot_z_zzzi_s"},
+ {"11"_b, "cdot_z_zzzi_d"},
},
},
- { "Decode_gxnlxg",
+ { "_gxnlxg",
{20, 19, 18, 17, 16},
- { {"00001", "Visit_uqxtn_asisdmisc_n"},
+ { {"00001"_b, "uqxtn_asisdmisc_n"},
},
},
- { "Decode_gxslgq",
+ { "_gxslgq",
{23, 22, 20, 19, 17, 16},
- { {"000010", "Visit_scvtf_s32_float2fix"},
- {"000011", "Visit_ucvtf_s32_float2fix"},
- {"001100", "Visit_fcvtzs_32s_float2fix"},
- {"001101", "Visit_fcvtzu_32s_float2fix"},
- {"010010", "Visit_scvtf_d32_float2fix"},
- {"010011", "Visit_ucvtf_d32_float2fix"},
- {"011100", "Visit_fcvtzs_32d_float2fix"},
- {"011101", "Visit_fcvtzu_32d_float2fix"},
- {"110010", "Visit_scvtf_h32_float2fix"},
- {"110011", "Visit_ucvtf_h32_float2fix"},
- {"111100", "Visit_fcvtzs_32h_float2fix"},
- {"111101", "Visit_fcvtzu_32h_float2fix"},
+ { {"000010"_b, "scvtf_s32_float2fix"},
+ {"000011"_b, "ucvtf_s32_float2fix"},
+ {"001100"_b, "fcvtzs_32s_float2fix"},
+ {"001101"_b, "fcvtzu_32s_float2fix"},
+ {"010010"_b, "scvtf_d32_float2fix"},
+ {"010011"_b, "ucvtf_d32_float2fix"},
+ {"011100"_b, "fcvtzs_32d_float2fix"},
+ {"011101"_b, "fcvtzu_32d_float2fix"},
+ {"110010"_b, "scvtf_h32_float2fix"},
+ {"110011"_b, "ucvtf_h32_float2fix"},
+ {"111100"_b, "fcvtzs_32h_float2fix"},
+ {"111101"_b, "fcvtzu_32h_float2fix"},
},
},
- { "Decode_gygnsz",
+ { "_gygnsz",
{17},
- { {"0", "Visit_ld2_asisdlsop_hx2_r2h"},
- {"1", "Visit_ld2_asisdlsop_h2_i2h"},
+ { {"0"_b, "ld2_asisdlsop_hx2_r2h"},
+ {"1"_b, "ld2_asisdlsop_h2_i2h"},
},
},
- { "Decode_gymljg",
+ { "_gymljg",
{23},
- { {"0", "Visit_fmulx_asimdsame_only"},
+ { {"0"_b, "fmulx_asimdsame_only"},
},
},
- { "Decode_gyrjrm",
+ { "_gyrjrm",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_cpy_z_p_v"},
- {"00001", "Visit_compact_z_p_z"},
- {"00010", "Visit_lasta_v_p_z"},
- {"00011", "Visit_lastb_v_p_z"},
- {"00100", "Visit_revb_z_z"},
- {"00101", "Visit_revh_z_z"},
- {"00110", "Visit_revw_z_z"},
- {"00111", "Visit_rbit_z_p_z"},
- {"01000", "Visit_clasta_z_p_zz"},
- {"01001", "Visit_clastb_z_p_zz"},
- {"01010", "Visit_clasta_v_p_z"},
- {"01011", "Visit_clastb_v_p_z"},
- {"01100", "Visit_splice_z_p_zz_des"},
- {"01101", "Visit_splice_z_p_zz_con"},
+ { {"00000"_b, "cpy_z_p_v"},
+ {"00001"_b, "compact_z_p_z"},
+ {"00010"_b, "lasta_v_p_z"},
+ {"00011"_b, "lastb_v_p_z"},
+ {"00100"_b, "revb_z_z"},
+ {"00101"_b, "revh_z_z"},
+ {"00110"_b, "revw_z_z"},
+ {"00111"_b, "rbit_z_p_z"},
+ {"01000"_b, "clasta_z_p_zz"},
+ {"01001"_b, "clastb_z_p_zz"},
+ {"01010"_b, "clasta_v_p_z"},
+ {"01011"_b, "clastb_v_p_z"},
+ {"01100"_b, "splice_z_p_zz_des"},
+ {"01101"_b, "splice_z_p_zz_con"},
},
},
- { "Decode_gznnvh",
+ { "_gznnvh",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_frinta_asimdmiscfp16_r"},
- {"0x00001", "Visit_frinta_asimdmisc_r"},
- {"xx00000", "Visit_cmge_asimdmisc_z"},
+ { {"0111001"_b, "frinta_asimdmiscfp16_r"},
+ {"0x00001"_b, "frinta_asimdmisc_r"},
+ {"xx00000"_b, "cmge_asimdmisc_z"},
},
},
- { "Decode_gzqvnk",
+ { "_gzqvnk",
{23, 12, 4, 3, 2, 1, 0},
- { {"1000000", "Visit_ctermeq_rr"},
- {"1010000", "Visit_ctermne_rr"},
- {"x10xxxx", "Visit_whilewr_p_rr"},
- {"x11xxxx", "Visit_whilerw_p_rr"},
+ { {"1000000"_b, "ctermeq_rr"},
+ {"1010000"_b, "ctermne_rr"},
+ {"x10xxxx"_b, "whilewr_p_rr"},
+ {"x11xxxx"_b, "whilerw_p_rr"},
},
},
- { "Decode_gzvgmh",
+ { "_gzvgmh",
{18, 17, 12},
- { {"0x0", "Visit_ld4_asisdlsop_dx4_r4d"},
- {"100", "Visit_ld4_asisdlsop_dx4_r4d"},
- {"110", "Visit_ld4_asisdlsop_d4_i4d"},
+ { {"0x0"_b, "ld4_asisdlsop_dx4_r4d"},
+ {"100"_b, "ld4_asisdlsop_dx4_r4d"},
+ {"110"_b, "ld4_asisdlsop_d4_i4d"},
},
},
- { "Decode_gzylzp",
+ { "_gzylzp",
{17},
- { {"0", "Visit_st3_asisdlsop_hx3_r3h"},
- {"1", "Visit_st3_asisdlsop_h3_i3h"},
+ { {"0"_b, "st3_asisdlsop_hx3_r3h"},
+ {"1"_b, "st3_asisdlsop_h3_i3h"},
},
},
- { "Decode_hggmnk",
+ { "_hggmnk",
{13, 12},
- { {"10", "Visit_lslv_32_dp_2src"},
+ { {"10"_b, "lslv_32_dp_2src"},
},
},
- { "Decode_hgxqpp",
+ { "_hgxqpp",
{18, 17},
- { {"00", "Visit_st3_asisdlso_s3_3s"},
+ { {"00"_b, "st3_asisdlso_s3_3s"},
},
},
- { "Decode_hgxtqy",
+ { "_hgxtqy",
{30, 23, 22, 13},
- { {"0001", "Visit_ldnt1w_z_p_ar_s_x32_unscaled"},
- {"0010", "Visit_ld1rsh_z_p_bi_s64"},
- {"0011", "Visit_ld1rsh_z_p_bi_s32"},
- {"0110", "Visit_ld1rsb_z_p_bi_s64"},
- {"0111", "Visit_ld1rsb_z_p_bi_s32"},
- {"1000", "Visit_ldnt1sw_z_p_ar_d_64_unscaled"},
- {"1010", "Visit_ld1sw_z_p_bz_d_64_unscaled"},
- {"1011", "Visit_ldff1sw_z_p_bz_d_64_unscaled"},
+ { {"0001"_b, "ldnt1w_z_p_ar_s_x32_unscaled"},
+ {"0010"_b, "ld1rsh_z_p_bi_s64"},
+ {"0011"_b, "ld1rsh_z_p_bi_s32"},
+ {"0110"_b, "ld1rsb_z_p_bi_s64"},
+ {"0111"_b, "ld1rsb_z_p_bi_s32"},
+ {"1000"_b, "ldnt1sw_z_p_ar_d_64_unscaled"},
+ {"1010"_b, "ld1sw_z_p_bz_d_64_unscaled"},
+ {"1011"_b, "ldff1sw_z_p_bz_d_64_unscaled"},
},
},
- { "Decode_hhhqjk",
+ { "_hhhqjk",
{4, 3, 2, 1, 0},
- { {"11111", "Decode_pqpzkt"},
+ { {"11111"_b, "_pqpzkt"},
},
},
- { "Decode_hhkhkk",
+ { "_hhkhkk",
{30, 23, 11, 10},
- { {"1001", "Decode_lkvynm"},
+ { {"1001"_b, "_lkvynm"},
},
},
- { "Decode_hhkqtn",
+ { "_hhkqtn",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_lasta_r_p_z"},
- {"00001", "Visit_lastb_r_p_z"},
- {"01000", "Visit_cpy_z_p_r"},
- {"10000", "Visit_clasta_r_p_z"},
- {"10001", "Visit_clastb_r_p_z"},
+ { {"00000"_b, "lasta_r_p_z"},
+ {"00001"_b, "lastb_r_p_z"},
+ {"01000"_b, "cpy_z_p_r"},
+ {"10000"_b, "clasta_r_p_z"},
+ {"10001"_b, "clastb_r_p_z"},
},
},
- { "Decode_hhnjjk",
+ { "_hhnjjk",
{9, 8, 7, 6, 5},
- { {"11111", "Visit_pacdzb_64z_dp_1src"},
+ { {"11111"_b, "pacdzb_64z_dp_1src"},
},
},
- { "Decode_hhymvj",
+ { "_hhymvj",
{20, 19, 18, 17, 16, 13, 12},
- { {"0000011", "Visit_sqabs_asisdmisc_r"},
- {"0000100", "Visit_sqxtn_asisdmisc_n"},
+ { {"0000011"_b, "sqabs_asisdmisc_r"},
+ {"0000100"_b, "sqxtn_asisdmisc_n"},
},
},
- { "Decode_hjgylh",
+ { "_hjgylh",
{30, 23, 22},
- { {"000", "Visit_str_s_ldst_pos"},
- {"001", "Visit_ldr_s_ldst_pos"},
- {"100", "Visit_str_d_ldst_pos"},
- {"101", "Visit_ldr_d_ldst_pos"},
+ { {"000"_b, "str_s_ldst_pos"},
+ {"001"_b, "ldr_s_ldst_pos"},
+ {"100"_b, "str_d_ldst_pos"},
+ {"101"_b, "ldr_d_ldst_pos"},
},
},
- { "Decode_hjqtrt",
+ { "_hjqtrt",
{12},
- { {"0", "Visit_st1_asisdlsop_dx1_r1d"},
+ { {"0"_b, "st1_asisdlsop_dx1_r1d"},
},
},
- { "Decode_hjtvvm",
+ { "_hjtvvm",
{13, 12},
- { {"00", "Visit_sdiv_64_dp_2src"},
- {"10", "Visit_rorv_64_dp_2src"},
+ { {"00"_b, "sdiv_64_dp_2src"},
+ {"10"_b, "rorv_64_dp_2src"},
},
},
- { "Decode_hljrqn",
+ { "_hljrqn",
{22},
- { {"0", "Visit_str_32_ldst_regoff"},
- {"1", "Visit_ldr_32_ldst_regoff"},
+ { {"0"_b, "str_32_ldst_regoff"},
+ {"1"_b, "ldr_32_ldst_regoff"},
},
},
- { "Decode_hlshjk",
+ { "_hlshjk",
{23, 22},
- { {"00", "Visit_fmlal_asimdsame_f"},
- {"10", "Visit_fmlsl_asimdsame_f"},
+ { {"00"_b, "fmlal_asimdsame_f"},
+ {"10"_b, "fmlsl_asimdsame_f"},
},
},
- { "Decode_hmsgpj",
+ { "_hmsgpj",
{13, 12, 10},
- { {"000", "Decode_hthxvr"},
- {"100", "Visit_ptrue_p_s"},
- {"101", "Decode_kkvrzq"},
- {"110", "Decode_xxjrsy"},
+ { {"000"_b, "_hthxvr"},
+ {"100"_b, "ptrue_p_s"},
+ {"101"_b, "_kkvrzq"},
+ {"110"_b, "_xxjrsy"},
},
},
- { "Decode_hmtmlq",
+ { "_hmtmlq",
{4},
- { {"0", "Visit_nor_p_p_pp_z"},
- {"1", "Visit_nand_p_p_pp_z"},
+ { {"0"_b, "nor_p_p_pp_z"},
+ {"1"_b, "nand_p_p_pp_z"},
},
},
- { "Decode_hmtxlh",
+ { "_hmtxlh",
{9, 8, 7, 6, 5, 1, 0},
- { {"1111111", "Visit_retaa_64e_branch_reg"},
+ { {"1111111"_b, "retaa_64e_branch_reg"},
},
},
- { "Decode_hmxlny",
+ { "_hmxlny",
{13, 12, 11, 10},
- { {"0000", "Visit_addhn_asimddiff_n"},
- {"0001", "Visit_sshl_asimdsame_only"},
- {"0010", "Decode_lyghyg"},
- {"0011", "Visit_sqshl_asimdsame_only"},
- {"0100", "Visit_sabal_asimddiff_l"},
- {"0101", "Visit_srshl_asimdsame_only"},
- {"0110", "Decode_htgzzx"},
- {"0111", "Visit_sqrshl_asimdsame_only"},
- {"1000", "Visit_subhn_asimddiff_n"},
- {"1001", "Visit_smax_asimdsame_only"},
- {"1010", "Decode_sqpjtr"},
- {"1011", "Visit_smin_asimdsame_only"},
- {"1100", "Visit_sabdl_asimddiff_l"},
- {"1101", "Visit_sabd_asimdsame_only"},
- {"1110", "Decode_rnrzsj"},
- {"1111", "Visit_saba_asimdsame_only"},
+ { {"0000"_b, "addhn_asimddiff_n"},
+ {"0001"_b, "sshl_asimdsame_only"},
+ {"0010"_b, "_lyghyg"},
+ {"0011"_b, "sqshl_asimdsame_only"},
+ {"0100"_b, "sabal_asimddiff_l"},
+ {"0101"_b, "srshl_asimdsame_only"},
+ {"0110"_b, "_htgzzx"},
+ {"0111"_b, "sqrshl_asimdsame_only"},
+ {"1000"_b, "subhn_asimddiff_n"},
+ {"1001"_b, "smax_asimdsame_only"},
+ {"1010"_b, "_sqpjtr"},
+ {"1011"_b, "smin_asimdsame_only"},
+ {"1100"_b, "sabdl_asimddiff_l"},
+ {"1101"_b, "sabd_asimdsame_only"},
+ {"1110"_b, "_rnrzsj"},
+ {"1111"_b, "saba_asimdsame_only"},
},
},
- { "Decode_hngpgx",
+ { "_hngpgx",
{23, 10, 4},
- { {"000", "Decode_vxsjgg"},
+ { {"000"_b, "_vxsjgg"},
},
},
- { "Decode_hngpxg",
+ { "_hngpxg",
{1, 0},
- { {"00", "Visit_br_64_branch_reg"},
+ { {"00"_b, "br_64_branch_reg"},
},
},
- { "Decode_hnjrmp",
+ { "_hnjrmp",
{4},
- { {"0", "Visit_cmplo_p_p_zi"},
- {"1", "Visit_cmpls_p_p_zi"},
+ { {"0"_b, "cmplo_p_p_zi"},
+ {"1"_b, "cmpls_p_p_zi"},
},
},
- { "Decode_hnzzkj",
+ { "_hnzzkj",
{30, 18},
- { {"00", "Decode_gxslgq"},
+ { {"00"_b, "_gxslgq"},
},
},
- { "Decode_hpgqlp",
+ { "_hpgqlp",
{9, 8, 7, 6, 5},
- { {"00000", "Visit_fmov_s_floatimm"},
+ { {"00000"_b, "fmov_s_floatimm"},
},
},
- { "Decode_hqhzgj",
+ { "_hqhzgj",
{17},
- { {"0", "Visit_ld2_asisdlso_b2_2b"},
+ { {"0"_b, "ld2_asisdlso_b2_2b"},
},
},
- { "Decode_hqlskj",
+ { "_hqlskj",
{18, 17},
- { {"00", "Visit_ld1_asisdlse_r1_1v"},
+ { {"00"_b, "ld1_asisdlse_r1_1v"},
},
},
- { "Decode_hqnxvt",
+ { "_hqnxvt",
{13, 12, 11, 10},
- { {"0000", "Visit_saddl_asimddiff_l"},
- {"0001", "Visit_shadd_asimdsame_only"},
- {"0010", "Decode_rykykh"},
- {"0011", "Visit_sqadd_asimdsame_only"},
- {"0100", "Visit_saddw_asimddiff_w"},
- {"0101", "Visit_srhadd_asimdsame_only"},
- {"0110", "Decode_glkzlv"},
- {"0111", "Decode_rnktts"},
- {"1000", "Visit_ssubl_asimddiff_l"},
- {"1001", "Visit_shsub_asimdsame_only"},
- {"1010", "Decode_rgztzl"},
- {"1011", "Visit_sqsub_asimdsame_only"},
- {"1100", "Visit_ssubw_asimddiff_w"},
- {"1101", "Visit_cmgt_asimdsame_only"},
- {"1110", "Decode_nyxxks"},
- {"1111", "Visit_cmge_asimdsame_only"},
+ { {"0000"_b, "saddl_asimddiff_l"},
+ {"0001"_b, "shadd_asimdsame_only"},
+ {"0010"_b, "_rykykh"},
+ {"0011"_b, "sqadd_asimdsame_only"},
+ {"0100"_b, "saddw_asimddiff_w"},
+ {"0101"_b, "srhadd_asimdsame_only"},
+ {"0110"_b, "_glkzlv"},
+ {"0111"_b, "_rnktts"},
+ {"1000"_b, "ssubl_asimddiff_l"},
+ {"1001"_b, "shsub_asimdsame_only"},
+ {"1010"_b, "_rgztzl"},
+ {"1011"_b, "sqsub_asimdsame_only"},
+ {"1100"_b, "ssubw_asimddiff_w"},
+ {"1101"_b, "cmgt_asimdsame_only"},
+ {"1110"_b, "_nyxxks"},
+ {"1111"_b, "cmge_asimdsame_only"},
},
},
- { "Decode_hqsvmh",
+ { "_hqsvmh",
{18, 17},
- { {"00", "Visit_st4_asisdlso_s4_4s"},
+ { {"00"_b, "st4_asisdlso_s4_4s"},
},
},
- { "Decode_hrhzqy",
+ { "_hrhzqy",
{17},
- { {"0", "Visit_ld4_asisdlse_r4"},
+ { {"0"_b, "ld4_asisdlse_r4"},
},
},
- { "Decode_hrktgs",
+ { "_hrktgs",
{12},
- { {"0", "Visit_st2_asisdlsop_dx2_r2d"},
+ { {"0"_b, "st2_asisdlsop_dx2_r2d"},
},
},
- { "Decode_hrllsn",
+ { "_hrllsn",
{18, 17, 16},
- { {"000", "Visit_fadd_z_p_zz"},
- {"001", "Visit_fsub_z_p_zz"},
- {"010", "Visit_fmul_z_p_zz"},
- {"011", "Visit_fsubr_z_p_zz"},
- {"100", "Visit_fmaxnm_z_p_zz"},
- {"101", "Visit_fminnm_z_p_zz"},
- {"110", "Visit_fmax_z_p_zz"},
- {"111", "Visit_fmin_z_p_zz"},
+ { {"000"_b, "fadd_z_p_zz"},
+ {"001"_b, "fsub_z_p_zz"},
+ {"010"_b, "fmul_z_p_zz"},
+ {"011"_b, "fsubr_z_p_zz"},
+ {"100"_b, "fmaxnm_z_p_zz"},
+ {"101"_b, "fminnm_z_p_zz"},
+ {"110"_b, "fmax_z_p_zz"},
+ {"111"_b, "fmin_z_p_zz"},
},
},
- { "Decode_hrxyts",
+ { "_hrxyts",
{23, 22, 20, 19, 18, 13},
- { {"00000x", "Visit_orr_z_zi"},
- {"01000x", "Visit_eor_z_zi"},
- {"10000x", "Visit_and_z_zi"},
- {"11000x", "Visit_dupm_z_i"},
- {"xx1xx0", "Visit_fcpy_z_p_i"},
+ { {"00000x"_b, "orr_z_zi"},
+ {"01000x"_b, "eor_z_zi"},
+ {"10000x"_b, "and_z_zi"},
+ {"11000x"_b, "dupm_z_i"},
+ {"xx1xx0"_b, "fcpy_z_p_i"},
},
},
- { "Decode_hsjynv",
+ { "_hsjynv",
{30},
- { {"0", "Visit_bl_only_branch_imm"},
+ { {"0"_b, "bl_only_branch_imm"},
},
},
- { "Decode_hstvrp",
+ { "_hstvrp",
{20, 19, 18, 17, 16, 13},
- { {"000000", "Visit_fmov_d_floatdp1"},
- {"000010", "Visit_fneg_d_floatdp1"},
- {"000100", "Visit_fcvt_sd_floatdp1"},
- {"000110", "Visit_bfcvt_bs_floatdp1"},
- {"001000", "Visit_frintn_d_floatdp1"},
- {"001010", "Visit_frintm_d_floatdp1"},
- {"001100", "Visit_frinta_d_floatdp1"},
- {"001110", "Visit_frintx_d_floatdp1"},
- {"010000", "Visit_frint32z_d_floatdp1"},
- {"010010", "Visit_frint64z_d_floatdp1"},
+ { {"000000"_b, "fmov_d_floatdp1"},
+ {"000010"_b, "fneg_d_floatdp1"},
+ {"000100"_b, "fcvt_sd_floatdp1"},
+ {"000110"_b, "bfcvt_bs_floatdp1"},
+ {"001000"_b, "frintn_d_floatdp1"},
+ {"001010"_b, "frintm_d_floatdp1"},
+ {"001100"_b, "frinta_d_floatdp1"},
+ {"001110"_b, "frintx_d_floatdp1"},
+ {"010000"_b, "frint32z_d_floatdp1"},
+ {"010010"_b, "frint64z_d_floatdp1"},
},
},
- { "Decode_hsvgnt",
+ { "_hsvgnt",
{23, 22, 4, 3, 2, 1, 0},
- { {"0000001", "Visit_svc_ex_exception"},
- {"0000010", "Visit_hvc_ex_exception"},
- {"0000011", "Visit_smc_ex_exception"},
- {"0100000", "Visit_hlt_ex_exception"},
+ { {"0000001"_b, "svc_ex_exception"},
+ {"0000010"_b, "hvc_ex_exception"},
+ {"0000011"_b, "smc_ex_exception"},
+ {"0100000"_b, "hlt_ex_exception"},
},
},
- { "Decode_htgzzx",
+ { "_htgzzx",
{20, 18, 17, 16},
- { {"0000", "Decode_mqgtsq"},
+ { {"0000"_b, "_mqgtsq"},
},
},
- { "Decode_hthxvr",
+ { "_hthxvr",
{23, 22, 9},
- { {"010", "Visit_pfirst_p_p_p"},
+ { {"010"_b, "pfirst_p_p_p"},
},
},
- { "Decode_htmthz",
+ { "_htmthz",
{22, 20, 19, 18, 17, 16, 13, 12},
- { {"01111100", "Decode_msztzv"},
+ { {"01111100"_b, "_msztzv"},
},
},
- { "Decode_htnmls",
+ { "_htnmls",
{22, 13, 12},
- { {"000", "Visit_ldapr_32l_memop"},
+ { {"000"_b, "ldapr_32l_memop"},
},
},
- { "Decode_htplsj",
+ { "_htplsj",
{4},
- { {"0", "Visit_cmpeq_p_p_zz"},
- {"1", "Visit_cmpne_p_p_zz"},
+ { {"0"_b, "cmpeq_p_p_zz"},
+ {"1"_b, "cmpne_p_p_zz"},
},
},
- { "Decode_htppjj",
+ { "_htppjj",
{30, 23, 22},
- { {"000", "Visit_msub_64a_dp_3src"},
+ { {"000"_b, "msub_64a_dp_3src"},
},
},
- { "Decode_htqpks",
+ { "_htqpks",
{30, 20, 19, 18, 17, 16, 13},
- { {"000000x", "Visit_add_z_zi"},
- {"000001x", "Visit_sub_z_zi"},
- {"000011x", "Visit_subr_z_zi"},
- {"000100x", "Visit_sqadd_z_zi"},
- {"000101x", "Visit_uqadd_z_zi"},
- {"000110x", "Visit_sqsub_z_zi"},
- {"000111x", "Visit_uqsub_z_zi"},
- {"0010000", "Visit_smax_z_zi"},
- {"0010010", "Visit_umax_z_zi"},
- {"0010100", "Visit_smin_z_zi"},
- {"0010110", "Visit_umin_z_zi"},
- {"0100000", "Visit_mul_z_zi"},
- {"011000x", "Visit_dup_z_i"},
- {"0110010", "Visit_fdup_z_i"},
- {"1xxxxx0", "Visit_fnmad_z_p_zzz"},
- {"1xxxxx1", "Visit_fnmsb_z_p_zzz"},
+ { {"000000x"_b, "add_z_zi"},
+ {"000001x"_b, "sub_z_zi"},
+ {"000011x"_b, "subr_z_zi"},
+ {"000100x"_b, "sqadd_z_zi"},
+ {"000101x"_b, "uqadd_z_zi"},
+ {"000110x"_b, "sqsub_z_zi"},
+ {"000111x"_b, "uqsub_z_zi"},
+ {"0010000"_b, "smax_z_zi"},
+ {"0010010"_b, "umax_z_zi"},
+ {"0010100"_b, "smin_z_zi"},
+ {"0010110"_b, "umin_z_zi"},
+ {"0100000"_b, "mul_z_zi"},
+ {"011000x"_b, "dup_z_i"},
+ {"0110010"_b, "fdup_z_i"},
+ {"1xxxxx0"_b, "fnmad_z_p_zzz"},
+ {"1xxxxx1"_b, "fnmsb_z_p_zzz"},
},
},
- { "Decode_hvvyhl",
+ { "_hvvyhl",
{23, 22, 20, 19, 18, 17, 16},
- { {"0x00001", "Visit_frint32z_asimdmisc_r"},
- {"1111000", "Visit_fcmlt_asimdmiscfp16_fz"},
- {"1x00000", "Visit_fcmlt_asimdmisc_fz"},
+ { {"0x00001"_b, "frint32z_asimdmisc_r"},
+ {"1111000"_b, "fcmlt_asimdmiscfp16_fz"},
+ {"1x00000"_b, "fcmlt_asimdmisc_fz"},
},
},
- { "Decode_hvyjnk",
+ { "_hvyjnk",
{11},
- { {"0", "Visit_sqrdmulh_z_zzi_h"},
+ { {"0"_b, "sqrdmulh_z_zzi_h"},
},
},
- { "Decode_hxglyp",
+ { "_hxglyp",
{17},
- { {"0", "Visit_ld4_asisdlsep_r4_r"},
- {"1", "Visit_ld4_asisdlsep_i4_i"},
+ { {"0"_b, "ld4_asisdlsep_r4_r"},
+ {"1"_b, "ld4_asisdlsep_i4_i"},
},
},
- { "Decode_hxmjhn",
+ { "_hxmjhn",
{30, 23, 22, 19, 16},
- { {"10010", "Visit_aese_b_cryptoaes"},
- {"xxx00", "Visit_cls_asimdmisc_r"},
- {"xxx01", "Visit_sqxtn_asimdmisc_n"},
+ { {"10010"_b, "aese_b_cryptoaes"},
+ {"xxx00"_b, "cls_asimdmisc_r"},
+ {"xxx01"_b, "sqxtn_asimdmisc_n"},
},
},
- { "Decode_hxnmsl",
+ { "_hxnmsl",
{30, 23, 22, 20, 13},
- { {"00001", "Visit_ld2w_z_p_bi_contiguous"},
- {"000x0", "Visit_ld2w_z_p_br_contiguous"},
- {"00101", "Visit_ld4w_z_p_bi_contiguous"},
- {"001x0", "Visit_ld4w_z_p_br_contiguous"},
- {"01001", "Visit_ld2d_z_p_bi_contiguous"},
- {"010x0", "Visit_ld2d_z_p_br_contiguous"},
- {"01101", "Visit_ld4d_z_p_bi_contiguous"},
- {"011x0", "Visit_ld4d_z_p_br_contiguous"},
- {"10011", "Visit_st2w_z_p_bi_contiguous"},
- {"100x0", "Visit_st1w_z_p_bz_d_x32_scaled"},
- {"10111", "Visit_st4w_z_p_bi_contiguous"},
- {"101x0", "Visit_st1w_z_p_bz_s_x32_scaled"},
- {"10x01", "Visit_st1w_z_p_bi"},
- {"11011", "Visit_st2d_z_p_bi_contiguous"},
- {"110x0", "Visit_st1d_z_p_bz_d_x32_scaled"},
- {"11111", "Visit_st4d_z_p_bi_contiguous"},
- {"11x01", "Visit_st1d_z_p_bi"},
+ { {"00001"_b, "ld2w_z_p_bi_contiguous"},
+ {"000x0"_b, "ld2w_z_p_br_contiguous"},
+ {"00101"_b, "ld4w_z_p_bi_contiguous"},
+ {"001x0"_b, "ld4w_z_p_br_contiguous"},
+ {"01001"_b, "ld2d_z_p_bi_contiguous"},
+ {"010x0"_b, "ld2d_z_p_br_contiguous"},
+ {"01101"_b, "ld4d_z_p_bi_contiguous"},
+ {"011x0"_b, "ld4d_z_p_br_contiguous"},
+ {"10011"_b, "st2w_z_p_bi_contiguous"},
+ {"100x0"_b, "st1w_z_p_bz_d_x32_scaled"},
+ {"10111"_b, "st4w_z_p_bi_contiguous"},
+ {"101x0"_b, "st1w_z_p_bz_s_x32_scaled"},
+ {"10x01"_b, "st1w_z_p_bi"},
+ {"11011"_b, "st2d_z_p_bi_contiguous"},
+ {"110x0"_b, "st1d_z_p_bz_d_x32_scaled"},
+ {"11111"_b, "st4d_z_p_bi_contiguous"},
+ {"11x01"_b, "st1d_z_p_bi"},
},
},
- { "Decode_hxrtsq",
+ { "_hxrtsq",
{23, 22, 12},
- { {"000", "Decode_gxlvsg"},
- {"001", "Decode_kxhjtk"},
- {"010", "Decode_hyxhpl"},
- {"011", "Decode_kvgjzh"},
- {"110", "Decode_tpsylx"},
- {"111", "Decode_zhpxqz"},
+ { {"000"_b, "_gxlvsg"},
+ {"001"_b, "_kxhjtk"},
+ {"010"_b, "_hyxhpl"},
+ {"011"_b, "_kvgjzh"},
+ {"110"_b, "_tpsylx"},
+ {"111"_b, "_zhpxqz"},
},
},
- { "Decode_hxzlmm",
+ { "_hxzlmm",
{30, 23, 22},
- { {"000", "Visit_stxp_sp32_ldstexcl"},
- {"001", "Visit_ldxp_lp32_ldstexcl"},
- {"100", "Visit_stxp_sp64_ldstexcl"},
- {"101", "Visit_ldxp_lp64_ldstexcl"},
+ { {"000"_b, "stxp_sp32_ldstexcl"},
+ {"001"_b, "ldxp_lp32_ldstexcl"},
+ {"100"_b, "stxp_sp64_ldstexcl"},
+ {"101"_b, "ldxp_lp64_ldstexcl"},
},
},
- { "Decode_hykhmt",
+ { "_hykhmt",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_saddv_r_p_z"},
- {"00001", "Visit_uaddv_r_p_z"},
- {"01000", "Visit_smaxv_r_p_z"},
- {"01001", "Visit_umaxv_r_p_z"},
- {"01010", "Visit_sminv_r_p_z"},
- {"01011", "Visit_uminv_r_p_z"},
- {"1000x", "Visit_movprfx_z_p_z"},
- {"11000", "Visit_orv_r_p_z"},
- {"11001", "Visit_eorv_r_p_z"},
- {"11010", "Visit_andv_r_p_z"},
+ { {"00000"_b, "saddv_r_p_z"},
+ {"00001"_b, "uaddv_r_p_z"},
+ {"01000"_b, "smaxv_r_p_z"},
+ {"01001"_b, "umaxv_r_p_z"},
+ {"01010"_b, "sminv_r_p_z"},
+ {"01011"_b, "uminv_r_p_z"},
+ {"1000x"_b, "movprfx_z_p_z"},
+ {"11000"_b, "orv_r_p_z"},
+ {"11001"_b, "eorv_r_p_z"},
+ {"11010"_b, "andv_r_p_z"},
},
},
- { "Decode_hyxhpl",
+ { "_hyxhpl",
{13},
- { {"0", "Decode_yrrppk"},
- {"1", "Decode_pnxggm"},
+ { {"0"_b, "_yrrppk"},
+ {"1"_b, "_pnxggm"},
},
},
- { "Decode_hyymjs",
+ { "_hyymjs",
{18, 17, 12},
- { {"0x0", "Visit_ld2_asisdlsop_dx2_r2d"},
- {"100", "Visit_ld2_asisdlsop_dx2_r2d"},
- {"110", "Visit_ld2_asisdlsop_d2_i2d"},
+ { {"0x0"_b, "ld2_asisdlsop_dx2_r2d"},
+ {"100"_b, "ld2_asisdlsop_dx2_r2d"},
+ {"110"_b, "ld2_asisdlsop_d2_i2d"},
},
},
- { "Decode_hzkglv",
+ { "_hzkglv",
{30, 23, 22, 13},
- { {"0000", "Visit_ld1b_z_p_br_u8"},
- {"0001", "Visit_ldff1b_z_p_br_u8"},
- {"0010", "Visit_ld1b_z_p_br_u32"},
- {"0011", "Visit_ldff1b_z_p_br_u32"},
- {"0100", "Visit_ld1sw_z_p_br_s64"},
- {"0101", "Visit_ldff1sw_z_p_br_s64"},
- {"0110", "Visit_ld1h_z_p_br_u32"},
- {"0111", "Visit_ldff1h_z_p_br_u32"},
- {"1001", "Visit_stnt1b_z_p_br_contiguous"},
- {"1011", "Visit_st3b_z_p_br_contiguous"},
- {"10x0", "Visit_st1b_z_p_br"},
- {"1101", "Visit_stnt1h_z_p_br_contiguous"},
- {"1111", "Visit_st3h_z_p_br_contiguous"},
- {"11x0", "Visit_st1h_z_p_br"},
+ { {"0000"_b, "ld1b_z_p_br_u8"},
+ {"0001"_b, "ldff1b_z_p_br_u8"},
+ {"0010"_b, "ld1b_z_p_br_u32"},
+ {"0011"_b, "ldff1b_z_p_br_u32"},
+ {"0100"_b, "ld1sw_z_p_br_s64"},
+ {"0101"_b, "ldff1sw_z_p_br_s64"},
+ {"0110"_b, "ld1h_z_p_br_u32"},
+ {"0111"_b, "ldff1h_z_p_br_u32"},
+ {"1001"_b, "stnt1b_z_p_br_contiguous"},
+ {"1011"_b, "st3b_z_p_br_contiguous"},
+ {"10x0"_b, "st1b_z_p_br"},
+ {"1101"_b, "stnt1h_z_p_br_contiguous"},
+ {"1111"_b, "st3h_z_p_br_contiguous"},
+ {"11x0"_b, "st1h_z_p_br"},
},
},
- { "Decode_hzllgl",
+ { "_hzllgl",
{17},
- { {"0", "Visit_st1_asisdlse_r4_4v"},
+ { {"0"_b, "st1_asisdlse_r4_4v"},
},
},
- { "Decode_hzmlps",
+ { "_hzmlps",
{19},
- { {"0", "Decode_rpqgjl"},
- {"1", "Visit_sys_cr_systeminstrs"},
+ { {"0"_b, "_rpqgjl"},
+ {"1"_b, "sys_cr_systeminstrs"},
},
},
- { "Decode_hzxjsp",
+ { "_hzxjsp",
{23, 22, 20, 19, 16, 13, 10},
- { {"0000000", "Decode_shgkvq"},
- {"0000001", "Decode_vytxll"},
- {"0000010", "Decode_hqsvmh"},
- {"0000011", "Decode_gmvrxn"},
- {"0100000", "Decode_ygyxvx"},
- {"0100001", "Decode_tszvvk"},
- {"0100010", "Decode_tyjqvt"},
- {"0100011", "Decode_ylqnqt"},
- {"100xx00", "Visit_st2_asisdlsop_sx2_r2s"},
- {"100xx01", "Decode_hrktgs"},
- {"100xx10", "Visit_st4_asisdlsop_sx4_r4s"},
- {"100xx11", "Decode_mmrtvz"},
- {"1010x00", "Visit_st2_asisdlsop_sx2_r2s"},
- {"1010x01", "Decode_lmtnzv"},
- {"1010x10", "Visit_st4_asisdlsop_sx4_r4s"},
- {"1010x11", "Decode_qrykhm"},
- {"1011000", "Visit_st2_asisdlsop_sx2_r2s"},
- {"1011001", "Decode_nyssqn"},
- {"1011010", "Visit_st4_asisdlsop_sx4_r4s"},
- {"1011011", "Decode_kpqgsn"},
- {"1011100", "Decode_knpsmq"},
- {"1011101", "Decode_jzyzjh"},
- {"1011110", "Decode_vhhktl"},
- {"1011111", "Decode_yjxvkp"},
- {"110xx00", "Visit_ld2_asisdlsop_sx2_r2s"},
- {"110xx01", "Decode_zppjvk"},
- {"110xx10", "Visit_ld4_asisdlsop_sx4_r4s"},
- {"110xx11", "Decode_kqjmvy"},
- {"1110x00", "Visit_ld2_asisdlsop_sx2_r2s"},
- {"1110x01", "Decode_ptkrvg"},
- {"1110x10", "Visit_ld4_asisdlsop_sx4_r4s"},
- {"1110x11", "Decode_kjryvx"},
- {"1111000", "Visit_ld2_asisdlsop_sx2_r2s"},
- {"1111001", "Decode_mlvpxh"},
- {"1111010", "Visit_ld4_asisdlsop_sx4_r4s"},
- {"1111011", "Decode_xqjrgk"},
- {"1111100", "Decode_msgqps"},
- {"1111101", "Decode_hyymjs"},
- {"1111110", "Decode_qsnqpz"},
- {"1111111", "Decode_gzvgmh"},
+ { {"0000000"_b, "_shgkvq"},
+ {"0000001"_b, "_vytxll"},
+ {"0000010"_b, "_hqsvmh"},
+ {"0000011"_b, "_gmvrxn"},
+ {"0100000"_b, "_ygyxvx"},
+ {"0100001"_b, "_tszvvk"},
+ {"0100010"_b, "_tyjqvt"},
+ {"0100011"_b, "_ylqnqt"},
+ {"100xx00"_b, "st2_asisdlsop_sx2_r2s"},
+ {"100xx01"_b, "_hrktgs"},
+ {"100xx10"_b, "st4_asisdlsop_sx4_r4s"},
+ {"100xx11"_b, "_mmrtvz"},
+ {"1010x00"_b, "st2_asisdlsop_sx2_r2s"},
+ {"1010x01"_b, "_lmtnzv"},
+ {"1010x10"_b, "st4_asisdlsop_sx4_r4s"},
+ {"1010x11"_b, "_qrykhm"},
+ {"1011000"_b, "st2_asisdlsop_sx2_r2s"},
+ {"1011001"_b, "_nyssqn"},
+ {"1011010"_b, "st4_asisdlsop_sx4_r4s"},
+ {"1011011"_b, "_kpqgsn"},
+ {"1011100"_b, "_knpsmq"},
+ {"1011101"_b, "_jzyzjh"},
+ {"1011110"_b, "_vhhktl"},
+ {"1011111"_b, "_yjxvkp"},
+ {"110xx00"_b, "ld2_asisdlsop_sx2_r2s"},
+ {"110xx01"_b, "_zppjvk"},
+ {"110xx10"_b, "ld4_asisdlsop_sx4_r4s"},
+ {"110xx11"_b, "_kqjmvy"},
+ {"1110x00"_b, "ld2_asisdlsop_sx2_r2s"},
+ {"1110x01"_b, "_ptkrvg"},
+ {"1110x10"_b, "ld4_asisdlsop_sx4_r4s"},
+ {"1110x11"_b, "_kjryvx"},
+ {"1111000"_b, "ld2_asisdlsop_sx2_r2s"},
+ {"1111001"_b, "_mlvpxh"},
+ {"1111010"_b, "ld4_asisdlsop_sx4_r4s"},
+ {"1111011"_b, "_xqjrgk"},
+ {"1111100"_b, "_msgqps"},
+ {"1111101"_b, "_hyymjs"},
+ {"1111110"_b, "_qsnqpz"},
+ {"1111111"_b, "_gzvgmh"},
},
},
- { "Decode_jggvph",
+ { "_jggvph",
{30},
- { {"0", "Visit_bic_64_log_shift"},
- {"1", "Visit_eon_64_log_shift"},
+ { {"0"_b, "bic_64_log_shift"},
+ {"1"_b, "eon_64_log_shift"},
},
},
- { "Decode_jgmlpk",
+ { "_jgmlpk",
{4},
- { {"0", "Visit_match_p_p_zz"},
- {"1", "Visit_nmatch_p_p_zz"},
+ { {"0"_b, "match_p_p_zz"},
+ {"1"_b, "nmatch_p_p_zz"},
},
},
- { "Decode_jgyhrh",
+ { "_jgyhrh",
{4},
- { {"0", "Visit_cmplo_p_p_zi"},
- {"1", "Visit_cmpls_p_p_zi"},
+ { {"0"_b, "cmplo_p_p_zi"},
+ {"1"_b, "cmpls_p_p_zi"},
},
},
- { "Decode_jhkglp",
+ { "_jhkglp",
{30, 23, 22},
- { {"110", "Visit_xar_vvv2_crypto3_imm6"},
+ { {"110"_b, "xar_vvv2_crypto3_imm6"},
},
},
- { "Decode_jhllmn",
+ { "_jhllmn",
{4},
- { {"0", "Visit_cmpge_p_p_zz"},
- {"1", "Visit_cmpgt_p_p_zz"},
+ { {"0"_b, "cmpge_p_p_zz"},
+ {"1"_b, "cmpgt_p_p_zz"},
},
},
- { "Decode_jhqlkv",
+ { "_jhqlkv",
{30, 23, 22},
- { {"000", "Visit_stxr_sr32_ldstexcl"},
- {"001", "Visit_ldxr_lr32_ldstexcl"},
- {"010", "Visit_stllr_sl32_ldstexcl"},
- {"011", "Visit_ldlar_lr32_ldstexcl"},
- {"100", "Visit_stxr_sr64_ldstexcl"},
- {"101", "Visit_ldxr_lr64_ldstexcl"},
- {"110", "Visit_stllr_sl64_ldstexcl"},
- {"111", "Visit_ldlar_lr64_ldstexcl"},
+ { {"000"_b, "stxr_sr32_ldstexcl"},
+ {"001"_b, "ldxr_lr32_ldstexcl"},
+ {"010"_b, "stllr_sl32_ldstexcl"},
+ {"011"_b, "ldlar_lr32_ldstexcl"},
+ {"100"_b, "stxr_sr64_ldstexcl"},
+ {"101"_b, "ldxr_lr64_ldstexcl"},
+ {"110"_b, "stllr_sl64_ldstexcl"},
+ {"111"_b, "ldlar_lr64_ldstexcl"},
},
},
- { "Decode_jhytlg",
+ { "_jhytlg",
{30, 23, 22, 13, 11, 10},
- { {"000010", "Visit_str_b_ldst_regoff"},
- {"000110", "Visit_str_bl_ldst_regoff"},
- {"001010", "Visit_ldr_b_ldst_regoff"},
- {"001110", "Visit_ldr_bl_ldst_regoff"},
- {"010x10", "Visit_str_q_ldst_regoff"},
- {"011x10", "Visit_ldr_q_ldst_regoff"},
- {"100x10", "Visit_str_h_ldst_regoff"},
- {"101x10", "Visit_ldr_h_ldst_regoff"},
+ { {"000010"_b, "str_b_ldst_regoff"},
+ {"000110"_b, "str_bl_ldst_regoff"},
+ {"001010"_b, "ldr_b_ldst_regoff"},
+ {"001110"_b, "ldr_bl_ldst_regoff"},
+ {"010x10"_b, "str_q_ldst_regoff"},
+ {"011x10"_b, "ldr_q_ldst_regoff"},
+ {"100x10"_b, "str_h_ldst_regoff"},
+ {"101x10"_b, "ldr_h_ldst_regoff"},
},
},
- { "Decode_jkkqvy",
+ { "_jkkqvy",
{22, 20, 11},
- { {"100", "Visit_uqinch_z_zs"},
- {"101", "Visit_uqdech_z_zs"},
- {"110", "Visit_dech_z_zs"},
+ { {"100"_b, "uqinch_z_zs"},
+ {"101"_b, "uqdech_z_zs"},
+ {"110"_b, "dech_z_zs"},
},
},
- { "Decode_jkpsxk",
+ { "_jkpsxk",
{20},
- { {"0", "Decode_kyygzs"},
- {"1", "Visit_msr_sr_systemmove"},
+ { {"0"_b, "_kyygzs"},
+ {"1"_b, "msr_sr_systemmove"},
},
},
- { "Decode_jkqktg",
+ { "_jkqktg",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_sqneg_asimdmisc_r"},
+ { {"00000"_b, "sqneg_asimdmisc_r"},
},
},
- { "Decode_jkrlsg",
+ { "_jkrlsg",
{23, 22},
- { {"00", "Visit_fmsub_s_floatdp3"},
- {"01", "Visit_fmsub_d_floatdp3"},
- {"11", "Visit_fmsub_h_floatdp3"},
+ { {"00"_b, "fmsub_s_floatdp3"},
+ {"01"_b, "fmsub_d_floatdp3"},
+ {"11"_b, "fmsub_h_floatdp3"},
},
},
- { "Decode_jksztq",
+ { "_jksztq",
{22, 20, 19, 13, 12},
- { {"0x100", "Visit_sri_asisdshf_r"},
- {"0x101", "Visit_sli_asisdshf_r"},
- {"0x110", "Visit_sqshlu_asisdshf_r"},
- {"0x111", "Visit_uqshl_asisdshf_r"},
- {"10x00", "Visit_sri_asisdshf_r"},
- {"10x01", "Visit_sli_asisdshf_r"},
- {"10x10", "Visit_sqshlu_asisdshf_r"},
- {"10x11", "Visit_uqshl_asisdshf_r"},
- {"11100", "Visit_sri_asisdshf_r"},
- {"11101", "Visit_sli_asisdshf_r"},
- {"11110", "Visit_sqshlu_asisdshf_r"},
- {"11111", "Visit_uqshl_asisdshf_r"},
- {"x1000", "Visit_sri_asisdshf_r"},
- {"x1001", "Visit_sli_asisdshf_r"},
- {"x1010", "Visit_sqshlu_asisdshf_r"},
- {"x1011", "Visit_uqshl_asisdshf_r"},
+ { {"0x100"_b, "sri_asisdshf_r"},
+ {"0x101"_b, "sli_asisdshf_r"},
+ {"0x110"_b, "sqshlu_asisdshf_r"},
+ {"0x111"_b, "uqshl_asisdshf_r"},
+ {"10x00"_b, "sri_asisdshf_r"},
+ {"10x01"_b, "sli_asisdshf_r"},
+ {"10x10"_b, "sqshlu_asisdshf_r"},
+ {"10x11"_b, "uqshl_asisdshf_r"},
+ {"11100"_b, "sri_asisdshf_r"},
+ {"11101"_b, "sli_asisdshf_r"},
+ {"11110"_b, "sqshlu_asisdshf_r"},
+ {"11111"_b, "uqshl_asisdshf_r"},
+ {"x1000"_b, "sri_asisdshf_r"},
+ {"x1001"_b, "sli_asisdshf_r"},
+ {"x1010"_b, "sqshlu_asisdshf_r"},
+ {"x1011"_b, "uqshl_asisdshf_r"},
},
},
- { "Decode_jkxlnq",
+ { "_jkxlnq",
{30},
- { {"0", "Visit_bl_only_branch_imm"},
- {"1", "Decode_nhzyvv"},
+ { {"0"_b, "bl_only_branch_imm"},
+ {"1"_b, "_nhzyvv"},
},
},
- { "Decode_jlqjzr",
+ { "_jlqjzr",
{30, 23},
- { {"00", "Visit_adds_64s_addsub_imm"},
- {"10", "Visit_subs_64s_addsub_imm"},
+ { {"00"_b, "adds_64s_addsub_imm"},
+ {"10"_b, "subs_64s_addsub_imm"},
},
},
- { "Decode_jlqxvj",
+ { "_jlqxvj",
{23, 22},
- { {"01", "Decode_mplgqv"},
- {"10", "Visit_xar_vvv2_crypto3_imm6"},
- {"11", "Decode_ljhtkq"},
+ { {"01"_b, "_mplgqv"},
+ {"10"_b, "xar_vvv2_crypto3_imm6"},
+ {"11"_b, "_ljhtkq"},
},
},
- { "Decode_jlrrlt",
+ { "_jlrrlt",
{11, 10, 4},
- { {"000", "Visit_whilege_p_p_rr"},
- {"001", "Visit_whilegt_p_p_rr"},
- {"010", "Visit_whilelt_p_p_rr"},
- {"011", "Visit_whilele_p_p_rr"},
- {"100", "Visit_whilehs_p_p_rr"},
- {"101", "Visit_whilehi_p_p_rr"},
- {"110", "Visit_whilelo_p_p_rr"},
- {"111", "Visit_whilels_p_p_rr"},
+ { {"000"_b, "whilege_p_p_rr"},
+ {"001"_b, "whilegt_p_p_rr"},
+ {"010"_b, "whilelt_p_p_rr"},
+ {"011"_b, "whilele_p_p_rr"},
+ {"100"_b, "whilehs_p_p_rr"},
+ {"101"_b, "whilehi_p_p_rr"},
+ {"110"_b, "whilelo_p_p_rr"},
+ {"111"_b, "whilels_p_p_rr"},
},
},
- { "Decode_jlrvpl",
+ { "_jlrvpl",
{17},
- { {"0", "Visit_st2_asisdlse_r2"},
+ { {"0"_b, "st2_asisdlse_r2"},
},
},
- { "Decode_jmgkrl",
+ { "_jmgkrl",
{30},
- { {"0", "Visit_orn_32_log_shift"},
- {"1", "Visit_bics_32_log_shift"},
+ { {"0"_b, "orn_32_log_shift"},
+ {"1"_b, "bics_32_log_shift"},
},
},
- { "Decode_jmvgsp",
+ { "_jmvgsp",
{22, 20, 11},
- { {"100", "Visit_sqinch_z_zs"},
- {"101", "Visit_sqdech_z_zs"},
- {"110", "Visit_inch_z_zs"},
+ { {"100"_b, "sqinch_z_zs"},
+ {"101"_b, "sqdech_z_zs"},
+ {"110"_b, "inch_z_zs"},
},
},
- { "Decode_jmxstz",
+ { "_jmxstz",
{13, 12, 11, 10},
- { {"0000", "Visit_sqdecp_z_p_z"},
- {"0010", "Visit_sqdecp_r_p_r_sx"},
- {"0011", "Visit_sqdecp_r_p_r_x"},
+ { {"0000"_b, "sqdecp_z_p_z"},
+ {"0010"_b, "sqdecp_r_p_r_sx"},
+ {"0011"_b, "sqdecp_r_p_r_x"},
},
},
- { "Decode_jmyslr",
+ { "_jmyslr",
{17},
- { {"0", "Visit_ld1_asisdlsep_r4_r4"},
- {"1", "Visit_ld1_asisdlsep_i4_i4"},
+ { {"0"_b, "ld1_asisdlsep_r4_r4"},
+ {"1"_b, "ld1_asisdlsep_i4_i4"},
},
},
- { "Decode_jnjlsh",
+ { "_jnjlsh",
{12},
- { {"0", "Visit_st1_asisdlsop_dx1_r1d"},
+ { {"0"_b, "st1_asisdlsop_dx1_r1d"},
},
},
- { "Decode_jnmgrh",
+ { "_jnmgrh",
{30, 19, 18, 17, 16},
- { {"11000", "Visit_ins_asimdins_iv_v"},
- {"1x100", "Visit_ins_asimdins_iv_v"},
- {"1xx10", "Visit_ins_asimdins_iv_v"},
- {"1xxx1", "Visit_ins_asimdins_iv_v"},
+ { {"11000"_b, "ins_asimdins_iv_v"},
+ {"1x100"_b, "ins_asimdins_iv_v"},
+ {"1xx10"_b, "ins_asimdins_iv_v"},
+ {"1xxx1"_b, "ins_asimdins_iv_v"},
},
},
- { "Decode_jplmmr",
+ { "_jplmmr",
{23, 22, 20, 19, 16, 13, 12},
- { {"0111100", "Visit_fcvtas_asisdmiscfp16_r"},
- {"0111101", "Visit_scvtf_asisdmiscfp16_r"},
- {"0x00100", "Visit_fcvtas_asisdmisc_r"},
- {"0x00101", "Visit_scvtf_asisdmisc_r"},
- {"0x10000", "Visit_fmaxnmp_asisdpair_only_h"},
- {"0x10001", "Visit_faddp_asisdpair_only_h"},
- {"0x10011", "Visit_fmaxp_asisdpair_only_h"},
- {"1111000", "Visit_fcmgt_asisdmiscfp16_fz"},
- {"1111001", "Visit_fcmeq_asisdmiscfp16_fz"},
- {"1111010", "Visit_fcmlt_asisdmiscfp16_fz"},
- {"1111101", "Visit_frecpe_asisdmiscfp16_r"},
- {"1111111", "Visit_frecpx_asisdmiscfp16_r"},
- {"1x00000", "Visit_fcmgt_asisdmisc_fz"},
- {"1x00001", "Visit_fcmeq_asisdmisc_fz"},
- {"1x00010", "Visit_fcmlt_asisdmisc_fz"},
- {"1x00101", "Visit_frecpe_asisdmisc_r"},
- {"1x00111", "Visit_frecpx_asisdmisc_r"},
- {"1x10000", "Visit_fminnmp_asisdpair_only_h"},
- {"1x10011", "Visit_fminp_asisdpair_only_h"},
+ { {"0111100"_b, "fcvtas_asisdmiscfp16_r"},
+ {"0111101"_b, "scvtf_asisdmiscfp16_r"},
+ {"0x00100"_b, "fcvtas_asisdmisc_r"},
+ {"0x00101"_b, "scvtf_asisdmisc_r"},
+ {"0x10000"_b, "fmaxnmp_asisdpair_only_h"},
+ {"0x10001"_b, "faddp_asisdpair_only_h"},
+ {"0x10011"_b, "fmaxp_asisdpair_only_h"},
+ {"1111000"_b, "fcmgt_asisdmiscfp16_fz"},
+ {"1111001"_b, "fcmeq_asisdmiscfp16_fz"},
+ {"1111010"_b, "fcmlt_asisdmiscfp16_fz"},
+ {"1111101"_b, "frecpe_asisdmiscfp16_r"},
+ {"1111111"_b, "frecpx_asisdmiscfp16_r"},
+ {"1x00000"_b, "fcmgt_asisdmisc_fz"},
+ {"1x00001"_b, "fcmeq_asisdmisc_fz"},
+ {"1x00010"_b, "fcmlt_asisdmisc_fz"},
+ {"1x00101"_b, "frecpe_asisdmisc_r"},
+ {"1x00111"_b, "frecpx_asisdmisc_r"},
+ {"1x10000"_b, "fminnmp_asisdpair_only_h"},
+ {"1x10011"_b, "fminp_asisdpair_only_h"},
},
},
- { "Decode_jpvljz",
+ { "_jpvljz",
{23, 22},
- { {"01", "Visit_fcmeq_asimdsamefp16_only"},
+ { {"01"_b, "fcmeq_asimdsamefp16_only"},
},
},
- { "Decode_jpxgqh",
+ { "_jpxgqh",
{30, 23, 22},
- { {"000", "Visit_sbfm_32m_bitfield"},
- {"100", "Visit_ubfm_32m_bitfield"},
+ { {"000"_b, "sbfm_32m_bitfield"},
+ {"100"_b, "ubfm_32m_bitfield"},
},
},
- { "Decode_jqjnrv",
+ { "_jqjnrv",
{18, 17},
- { {"00", "Visit_st1_asisdlso_s1_1s"},
+ { {"00"_b, "st1_asisdlso_s1_1s"},
},
},
- { "Decode_jqnglz",
+ { "_jqnglz",
{23, 22, 20, 19, 11},
- { {"00010", "Visit_ucvtf_asisdshf_c"},
- {"001x0", "Visit_ucvtf_asisdshf_c"},
- {"01xx0", "Visit_ucvtf_asisdshf_c"},
+ { {"00010"_b, "ucvtf_asisdshf_c"},
+ {"001x0"_b, "ucvtf_asisdshf_c"},
+ {"01xx0"_b, "ucvtf_asisdshf_c"},
},
},
- { "Decode_jqnhrj",
+ { "_jqnhrj",
{12, 10},
- { {"00", "Decode_mzynlp"},
- {"01", "Decode_mvglql"},
- {"10", "Decode_tylqpt"},
- {"11", "Decode_lrjyhr"},
+ { {"00"_b, "_mzynlp"},
+ {"01"_b, "_mvglql"},
+ {"10"_b, "_tylqpt"},
+ {"11"_b, "_lrjyhr"},
},
},
- { "Decode_jqplxx",
+ { "_jqplxx",
{20, 19, 18, 17, 16, 13, 12},
- { {"1111100", "Decode_xpvpqq"},
+ { {"1111100"_b, "_xpvpqq"},
},
},
- { "Decode_jqtltz",
+ { "_jqtltz",
{13},
- { {"0", "Visit_mul_asimdelem_r"},
- {"1", "Visit_smull_asimdelem_l"},
+ { {"0"_b, "mul_asimdelem_r"},
+ {"1"_b, "smull_asimdelem_l"},
},
},
- { "Decode_jqxqql",
+ { "_jqxqql",
{22, 20, 11},
- { {"000", "Visit_uqincw_z_zs"},
- {"001", "Visit_uqdecw_z_zs"},
- {"010", "Visit_decw_z_zs"},
- {"100", "Visit_uqincd_z_zs"},
- {"101", "Visit_uqdecd_z_zs"},
- {"110", "Visit_decd_z_zs"},
+ { {"000"_b, "uqincw_z_zs"},
+ {"001"_b, "uqdecw_z_zs"},
+ {"010"_b, "decw_z_zs"},
+ {"100"_b, "uqincd_z_zs"},
+ {"101"_b, "uqdecd_z_zs"},
+ {"110"_b, "decd_z_zs"},
},
},
- { "Decode_jrgzxt",
+ { "_jrgzxt",
{18, 17},
- { {"00", "Visit_ld3_asisdlse_r3"},
+ { {"00"_b, "ld3_asisdlse_r3"},
},
},
- { "Decode_jrlynj",
+ { "_jrlynj",
{11, 10},
- { {"00", "Decode_gzqvnk"},
+ { {"00"_b, "_gzqvnk"},
},
},
- { "Decode_jrnlzs",
+ { "_jrnlzs",
{13, 12, 11},
- { {"000", "Visit_fminnmp_asimdsamefp16_only"},
- {"010", "Visit_fabd_asimdsamefp16_only"},
- {"100", "Visit_fcmgt_asimdsamefp16_only"},
- {"101", "Visit_facgt_asimdsamefp16_only"},
- {"110", "Visit_fminp_asimdsamefp16_only"},
+ { {"000"_b, "fminnmp_asimdsamefp16_only"},
+ {"010"_b, "fabd_asimdsamefp16_only"},
+ {"100"_b, "fcmgt_asimdsamefp16_only"},
+ {"101"_b, "facgt_asimdsamefp16_only"},
+ {"110"_b, "fminp_asimdsamefp16_only"},
},
},
- { "Decode_jrnxzh",
+ { "_jrnxzh",
{12},
- { {"0", "Visit_cmla_z_zzz"},
- {"1", "Visit_sqrdcmlah_z_zzz"},
+ { {"0"_b, "cmla_z_zzz"},
+ {"1"_b, "sqrdcmlah_z_zzz"},
},
},
- { "Decode_jrsptt",
+ { "_jrsptt",
{13, 12},
- { {"00", "Visit_sqadd_asisdsame_only"},
- {"10", "Visit_sqsub_asisdsame_only"},
- {"11", "Visit_cmge_asisdsame_only"},
+ { {"00"_b, "sqadd_asisdsame_only"},
+ {"10"_b, "sqsub_asisdsame_only"},
+ {"11"_b, "cmge_asisdsame_only"},
},
},
- { "Decode_jryylt",
+ { "_jryylt",
{30, 23, 22, 19, 18, 17, 16},
- { {"00000x1", "Visit_smov_asimdins_w_w"},
- {"0000x10", "Visit_smov_asimdins_w_w"},
- {"00010xx", "Visit_smov_asimdins_w_w"},
- {"0001110", "Visit_smov_asimdins_w_w"},
- {"000x10x", "Visit_smov_asimdins_w_w"},
- {"000x111", "Visit_smov_asimdins_w_w"},
- {"10000x1", "Visit_smov_asimdins_x_x"},
- {"1000x10", "Visit_smov_asimdins_x_x"},
- {"10010xx", "Visit_smov_asimdins_x_x"},
- {"1001110", "Visit_smov_asimdins_x_x"},
- {"100x10x", "Visit_smov_asimdins_x_x"},
- {"100x111", "Visit_smov_asimdins_x_x"},
+ { {"00000x1"_b, "smov_asimdins_w_w"},
+ {"0000x10"_b, "smov_asimdins_w_w"},
+ {"00010xx"_b, "smov_asimdins_w_w"},
+ {"0001110"_b, "smov_asimdins_w_w"},
+ {"000x10x"_b, "smov_asimdins_w_w"},
+ {"000x111"_b, "smov_asimdins_w_w"},
+ {"10000x1"_b, "smov_asimdins_x_x"},
+ {"1000x10"_b, "smov_asimdins_x_x"},
+ {"10010xx"_b, "smov_asimdins_x_x"},
+ {"1001110"_b, "smov_asimdins_x_x"},
+ {"100x10x"_b, "smov_asimdins_x_x"},
+ {"100x111"_b, "smov_asimdins_x_x"},
},
},
- { "Decode_jsygzs",
+ { "_jsygzs",
{30, 23, 22, 12, 11, 10},
- { {"0000xx", "Visit_add_64_addsub_ext"},
- {"000100", "Visit_add_64_addsub_ext"},
- {"1000xx", "Visit_sub_64_addsub_ext"},
- {"100100", "Visit_sub_64_addsub_ext"},
+ { {"0000xx"_b, "add_64_addsub_ext"},
+ {"000100"_b, "add_64_addsub_ext"},
+ {"1000xx"_b, "sub_64_addsub_ext"},
+ {"100100"_b, "sub_64_addsub_ext"},
},
},
- { "Decode_jtqlhs",
+ { "_jtqlhs",
{22},
- { {"0", "Visit_str_64_ldst_regoff"},
- {"1", "Visit_ldr_64_ldst_regoff"},
+ { {"0"_b, "str_64_ldst_regoff"},
+ {"1"_b, "ldr_64_ldst_regoff"},
},
},
- { "Decode_jvhnxl",
+ { "_jvhnxl",
{23},
- { {"0", "Visit_fcmge_asimdsame_only"},
- {"1", "Visit_fcmgt_asimdsame_only"},
+ { {"0"_b, "fcmge_asimdsame_only"},
+ {"1"_b, "fcmgt_asimdsame_only"},
},
},
- { "Decode_jvpqrp",
+ { "_jvpqrp",
{23, 22},
- { {"00", "Visit_fmla_asisdelem_rh_h"},
- {"1x", "Visit_fmla_asisdelem_r_sd"},
+ { {"00"_b, "fmla_asisdelem_rh_h"},
+ {"1x"_b, "fmla_asisdelem_r_sd"},
},
},
- { "Decode_jvvzjq",
+ { "_jvvzjq",
{23, 22},
- { {"00", "Visit_fcsel_s_floatsel"},
- {"01", "Visit_fcsel_d_floatsel"},
- {"11", "Visit_fcsel_h_floatsel"},
+ { {"00"_b, "fcsel_s_floatsel"},
+ {"01"_b, "fcsel_d_floatsel"},
+ {"11"_b, "fcsel_h_floatsel"},
},
},
- { "Decode_jxrlyh",
+ { "_jxrlyh",
{12},
- { {"0", "Decode_mtgksl"},
+ { {"0"_b, "_mtgksl"},
},
},
- { "Decode_jxszhy",
+ { "_jxszhy",
{23, 22, 11},
- { {"000", "Decode_rqhryp"},
+ { {"000"_b, "_rqhryp"},
},
},
- { "Decode_jxtgtx",
+ { "_jxtgtx",
{30, 23, 22},
- { {"000", "Visit_str_b_ldst_pos"},
- {"001", "Visit_ldr_b_ldst_pos"},
- {"010", "Visit_str_q_ldst_pos"},
- {"011", "Visit_ldr_q_ldst_pos"},
- {"100", "Visit_str_h_ldst_pos"},
- {"101", "Visit_ldr_h_ldst_pos"},
+ { {"000"_b, "str_b_ldst_pos"},
+ {"001"_b, "ldr_b_ldst_pos"},
+ {"010"_b, "str_q_ldst_pos"},
+ {"011"_b, "ldr_q_ldst_pos"},
+ {"100"_b, "str_h_ldst_pos"},
+ {"101"_b, "ldr_h_ldst_pos"},
},
},
- { "Decode_jxyskn",
+ { "_jxyskn",
{13, 12, 11, 10},
- { {"0000", "Visit_uqincp_z_p_z"},
- {"0010", "Visit_uqincp_r_p_r_uw"},
- {"0011", "Visit_uqincp_r_p_r_x"},
+ { {"0000"_b, "uqincp_z_p_z"},
+ {"0010"_b, "uqincp_r_p_r_uw"},
+ {"0011"_b, "uqincp_r_p_r_x"},
},
},
- { "Decode_jxzrxm",
+ { "_jxzrxm",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_usqadd_asisdmisc_r"},
+ { {"00000"_b, "usqadd_asisdmisc_r"},
},
},
- { "Decode_jymnkk",
+ { "_jymnkk",
{23, 22, 12, 11, 10},
- { {"01000", "Visit_bfdot_z_zzzi"},
- {"100x0", "Visit_fmlalb_z_zzzi_s"},
- {"100x1", "Visit_fmlalt_z_zzzi_s"},
- {"110x0", "Visit_bfmlalb_z_zzzi"},
- {"110x1", "Visit_bfmlalt_z_zzzi"},
+ { {"01000"_b, "bfdot_z_zzzi"},
+ {"100x0"_b, "fmlalb_z_zzzi_s"},
+ {"100x1"_b, "fmlalt_z_zzzi_s"},
+ {"110x0"_b, "bfmlalb_z_zzzi"},
+ {"110x1"_b, "bfmlalt_z_zzzi"},
},
},
- { "Decode_jyxszq",
+ { "_jyxszq",
{30, 4},
- { {"0x", "Visit_b_only_branch_imm"},
- {"10", "Visit_b_only_condbranch"},
+ { {"0x"_b, "b_only_branch_imm"},
+ {"10"_b, "b_only_condbranch"},
},
},
- { "Decode_jzjvtv",
+ { "_jzjvtv",
{19, 18, 17, 16, 4},
- { {"00000", "Visit_brkbs_p_p_p_z"},
+ { {"00000"_b, "brkbs_p_p_p_z"},
},
},
- { "Decode_jzkqhn",
+ { "_jzkqhn",
{23, 22, 12, 11, 10},
- { {"10000", "Visit_fmlslb_z_zzz"},
- {"10001", "Visit_fmlslt_z_zzz"},
+ { {"10000"_b, "fmlslb_z_zzz"},
+ {"10001"_b, "fmlslt_z_zzz"},
},
},
- { "Decode_jzyzjh",
+ { "_jzyzjh",
{18, 17, 12},
- { {"0x0", "Visit_st2_asisdlsop_dx2_r2d"},
- {"100", "Visit_st2_asisdlsop_dx2_r2d"},
- {"110", "Visit_st2_asisdlsop_d2_i2d"},
+ { {"0x0"_b, "st2_asisdlsop_dx2_r2d"},
+ {"100"_b, "st2_asisdlsop_dx2_r2d"},
+ {"110"_b, "st2_asisdlsop_d2_i2d"},
},
},
- { "Decode_kgmqkh",
+ { "_kgmqkh",
{30, 23, 22, 13},
- { {"0000", "Visit_ld1w_z_p_ai_s"},
- {"0001", "Visit_ldff1w_z_p_ai_s"},
- {"0010", "Visit_ld1rw_z_p_bi_u32"},
- {"0011", "Visit_ld1rw_z_p_bi_u64"},
- {"0110", "Visit_ld1rsb_z_p_bi_s16"},
- {"0111", "Visit_ld1rd_z_p_bi_u64"},
- {"1000", "Visit_ld1w_z_p_ai_d"},
- {"1001", "Visit_ldff1w_z_p_ai_d"},
- {"1010", "Visit_ld1w_z_p_bz_d_64_scaled"},
- {"1011", "Visit_ldff1w_z_p_bz_d_64_scaled"},
- {"1100", "Visit_ld1d_z_p_ai_d"},
- {"1101", "Visit_ldff1d_z_p_ai_d"},
- {"1110", "Visit_ld1d_z_p_bz_d_64_scaled"},
- {"1111", "Visit_ldff1d_z_p_bz_d_64_scaled"},
+ { {"0000"_b, "ld1w_z_p_ai_s"},
+ {"0001"_b, "ldff1w_z_p_ai_s"},
+ {"0010"_b, "ld1rw_z_p_bi_u32"},
+ {"0011"_b, "ld1rw_z_p_bi_u64"},
+ {"0110"_b, "ld1rsb_z_p_bi_s16"},
+ {"0111"_b, "ld1rd_z_p_bi_u64"},
+ {"1000"_b, "ld1w_z_p_ai_d"},
+ {"1001"_b, "ldff1w_z_p_ai_d"},
+ {"1010"_b, "ld1w_z_p_bz_d_64_scaled"},
+ {"1011"_b, "ldff1w_z_p_bz_d_64_scaled"},
+ {"1100"_b, "ld1d_z_p_ai_d"},
+ {"1101"_b, "ldff1d_z_p_ai_d"},
+ {"1110"_b, "ld1d_z_p_bz_d_64_scaled"},
+ {"1111"_b, "ldff1d_z_p_bz_d_64_scaled"},
},
},
- { "Decode_kgpgly",
+ { "_kgpgly",
{23, 22, 10},
- { {"100", "Visit_smlslb_z_zzzi_s"},
- {"101", "Visit_smlslt_z_zzzi_s"},
- {"110", "Visit_smlslb_z_zzzi_d"},
- {"111", "Visit_smlslt_z_zzzi_d"},
+ { {"100"_b, "smlslb_z_zzzi_s"},
+ {"101"_b, "smlslt_z_zzzi_s"},
+ {"110"_b, "smlslb_z_zzzi_d"},
+ {"111"_b, "smlslt_z_zzzi_d"},
},
},
- { "Decode_khjvqq",
+ { "_khjvqq",
{22, 11},
- { {"00", "Visit_sqrdmulh_z_zzi_s"},
- {"10", "Visit_sqrdmulh_z_zzi_d"},
+ { {"00"_b, "sqrdmulh_z_zzi_s"},
+ {"10"_b, "sqrdmulh_z_zzi_d"},
},
},
- { "Decode_kjghlk",
+ { "_kjghlk",
{23, 22, 20, 19, 13, 11},
- { {"0000x0", "Visit_orr_asimdimm_l_sl"},
- {"00x100", "Visit_ssra_asimdshf_r"},
- {"00x110", "Visit_srsra_asimdshf_r"},
- {"010x00", "Visit_ssra_asimdshf_r"},
- {"010x10", "Visit_srsra_asimdshf_r"},
- {"011100", "Visit_ssra_asimdshf_r"},
- {"011110", "Visit_srsra_asimdshf_r"},
- {"0x1000", "Visit_ssra_asimdshf_r"},
- {"0x1010", "Visit_srsra_asimdshf_r"},
+ { {"0000x0"_b, "orr_asimdimm_l_sl"},
+ {"00x100"_b, "ssra_asimdshf_r"},
+ {"00x110"_b, "srsra_asimdshf_r"},
+ {"010x00"_b, "ssra_asimdshf_r"},
+ {"010x10"_b, "srsra_asimdshf_r"},
+ {"011100"_b, "ssra_asimdshf_r"},
+ {"011110"_b, "srsra_asimdshf_r"},
+ {"0x1000"_b, "ssra_asimdshf_r"},
+ {"0x1010"_b, "srsra_asimdshf_r"},
},
},
- { "Decode_kjngjl",
+ { "_kjngjl",
{23, 22},
- { {"00", "Visit_tbx_asimdtbl_l1_1"},
+ { {"00"_b, "tbx_asimdtbl_l1_1"},
},
},
- { "Decode_kjpxvh",
+ { "_kjpxvh",
{20, 19, 18},
- { {"000", "Decode_yyrkmn"},
+ { {"000"_b, "_yyrkmn"},
},
},
- { "Decode_kjqynn",
+ { "_kjqynn",
{4},
- { {"0", "Visit_cmphs_p_p_zi"},
- {"1", "Visit_cmphi_p_p_zi"},
+ { {"0"_b, "cmphs_p_p_zi"},
+ {"1"_b, "cmphi_p_p_zi"},
},
},
- { "Decode_kjrxpx",
+ { "_kjrxpx",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_ucvtf_asimdmiscfp16_r"},
- {"0x00001", "Visit_ucvtf_asimdmisc_r"},
- {"1111000", "Visit_fcmle_asimdmiscfp16_fz"},
- {"1111001", "Visit_frsqrte_asimdmiscfp16_r"},
- {"1x00000", "Visit_fcmle_asimdmisc_fz"},
- {"1x00001", "Visit_frsqrte_asimdmisc_r"},
+ { {"0111001"_b, "ucvtf_asimdmiscfp16_r"},
+ {"0x00001"_b, "ucvtf_asimdmisc_r"},
+ {"1111000"_b, "fcmle_asimdmiscfp16_fz"},
+ {"1111001"_b, "frsqrte_asimdmiscfp16_r"},
+ {"1x00000"_b, "fcmle_asimdmisc_fz"},
+ {"1x00001"_b, "frsqrte_asimdmisc_r"},
},
},
- { "Decode_kjryvx",
+ { "_kjryvx",
{12},
- { {"0", "Visit_ld4_asisdlsop_dx4_r4d"},
+ { {"0"_b, "ld4_asisdlsop_dx4_r4d"},
},
},
- { "Decode_kjyphv",
+ { "_kjyphv",
{20, 19, 18, 17, 16},
- { {"10000", "Visit_fmaxp_asisdpair_only_sd"},
+ { {"10000"_b, "fmaxp_asisdpair_only_sd"},
},
},
- { "Decode_kkgpjl",
+ { "_kkgpjl",
{20, 19, 18, 17},
- { {"0000", "Decode_msqkyy"},
+ { {"0000"_b, "_msqkyy"},
},
},
- { "Decode_kkgzst",
+ { "_kkgzst",
{23, 22, 13, 12, 11, 10},
- { {"0001x0", "Visit_fmla_asimdelem_rh_h"},
- {"0x0001", "Visit_sshr_asimdshf_r"},
- {"0x0101", "Visit_ssra_asimdshf_r"},
- {"0x1001", "Visit_srshr_asimdshf_r"},
- {"0x1101", "Visit_srsra_asimdshf_r"},
- {"1000x0", "Visit_fmlal_asimdelem_lh"},
- {"1x01x0", "Visit_fmla_asimdelem_r_sd"},
- {"xx10x0", "Visit_smlal_asimdelem_l"},
- {"xx11x0", "Visit_sqdmlal_asimdelem_l"},
+ { {"0001x0"_b, "fmla_asimdelem_rh_h"},
+ {"0x0001"_b, "sshr_asimdshf_r"},
+ {"0x0101"_b, "ssra_asimdshf_r"},
+ {"0x1001"_b, "srshr_asimdshf_r"},
+ {"0x1101"_b, "srsra_asimdshf_r"},
+ {"1000x0"_b, "fmlal_asimdelem_lh"},
+ {"1x01x0"_b, "fmla_asimdelem_r_sd"},
+ {"xx10x0"_b, "smlal_asimdelem_l"},
+ {"xx11x0"_b, "sqdmlal_asimdelem_l"},
},
},
- { "Decode_kkmjyr",
+ { "_kkmjyr",
{0},
- { {"1", "Visit_blrabz_64_branch_reg"},
+ { {"1"_b, "blrabz_64_branch_reg"},
},
},
- { "Decode_kkmxxx",
+ { "_kkmxxx",
{30},
- { {"0", "Visit_bl_only_branch_imm"},
- {"1", "Decode_jqplxx"},
+ { {"0"_b, "bl_only_branch_imm"},
+ {"1"_b, "_jqplxx"},
},
},
- { "Decode_kknjng",
+ { "_kknjng",
{23, 22, 20, 19, 11},
- { {"00010", "Visit_ssra_asisdshf_r"},
- {"001x0", "Visit_ssra_asisdshf_r"},
- {"01xx0", "Visit_ssra_asisdshf_r"},
+ { {"00010"_b, "ssra_asisdshf_r"},
+ {"001x0"_b, "ssra_asisdshf_r"},
+ {"01xx0"_b, "ssra_asisdshf_r"},
},
},
- { "Decode_kktglv",
+ { "_kktglv",
{30, 13, 12},
- { {"000", "Decode_njvkjq"},
- {"001", "Decode_rpzykx"},
- {"010", "Decode_zzvxvh"},
- {"011", "Decode_yqxnzl"},
- {"100", "Decode_gxmnkl"},
- {"110", "Decode_lkxgjy"},
- {"111", "Decode_vjmklj"},
+ { {"000"_b, "_njvkjq"},
+ {"001"_b, "_rpzykx"},
+ {"010"_b, "_zzvxvh"},
+ {"011"_b, "_yqxnzl"},
+ {"100"_b, "_gxmnkl"},
+ {"110"_b, "_lkxgjy"},
+ {"111"_b, "_vjmklj"},
},
},
- { "Decode_kkvrzq",
+ { "_kkvrzq",
{23, 22, 9, 8, 7, 6, 5},
- { {"0000000", "Visit_pfalse_p"},
+ { {"0000000"_b, "pfalse_p"},
},
},
- { "Decode_klkgqk",
+ { "_klkgqk",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_fcvtms_asimdmiscfp16_r"},
- {"0x00001", "Visit_fcvtms_asimdmisc_r"},
- {"1111001", "Visit_fcvtzs_asimdmiscfp16_r"},
- {"1x00001", "Visit_fcvtzs_asimdmisc_r"},
- {"xx00000", "Visit_abs_asimdmisc_r"},
- {"xx10001", "Visit_addv_asimdall_only"},
+ { {"0111001"_b, "fcvtms_asimdmiscfp16_r"},
+ {"0x00001"_b, "fcvtms_asimdmisc_r"},
+ {"1111001"_b, "fcvtzs_asimdmiscfp16_r"},
+ {"1x00001"_b, "fcvtzs_asimdmisc_r"},
+ {"xx00000"_b, "abs_asimdmisc_r"},
+ {"xx10001"_b, "addv_asimdall_only"},
},
},
- { "Decode_klnhpj",
+ { "_klnhpj",
{9, 8, 7, 6, 5, 1, 0},
- { {"1111111", "Visit_eretab_64e_branch_reg"},
+ { {"1111111"_b, "eretab_64e_branch_reg"},
},
},
- { "Decode_klthpn",
+ { "_klthpn",
{30, 23, 22, 11, 10},
- { {"01000", "Visit_csel_64_condsel"},
- {"01001", "Visit_csinc_64_condsel"},
- {"11000", "Visit_csinv_64_condsel"},
- {"11001", "Visit_csneg_64_condsel"},
+ { {"01000"_b, "csel_64_condsel"},
+ {"01001"_b, "csinc_64_condsel"},
+ {"11000"_b, "csinv_64_condsel"},
+ {"11001"_b, "csneg_64_condsel"},
},
},
- { "Decode_kmhtqp",
+ { "_kmhtqp",
{30},
- { {"0", "Visit_bl_only_branch_imm"},
+ { {"0"_b, "bl_only_branch_imm"},
},
},
- { "Decode_kmkpnj",
+ { "_kmkpnj",
{17},
- { {"0", "Visit_ld3_asisdlso_h3_3h"},
+ { {"0"_b, "ld3_asisdlso_h3_3h"},
},
},
- { "Decode_knkjnz",
+ { "_knkjnz",
{30, 23, 22, 20, 13},
- { {"00001", "Visit_ld1sh_z_p_bi_s32"},
- {"00011", "Visit_ldnf1sh_z_p_bi_s32"},
- {"00101", "Visit_ld1w_z_p_bi_u64"},
- {"00111", "Visit_ldnf1w_z_p_bi_u64"},
- {"01001", "Visit_ld1sb_z_p_bi_s32"},
- {"01011", "Visit_ldnf1sb_z_p_bi_s32"},
- {"01101", "Visit_ld1d_z_p_bi_u64"},
- {"01111", "Visit_ldnf1d_z_p_bi_u64"},
- {"100x0", "Visit_st1w_z_p_bz_d_x32_scaled"},
- {"100x1", "Visit_st1w_z_p_bz_d_64_scaled"},
- {"101x0", "Visit_st1w_z_p_bz_s_x32_scaled"},
- {"101x1", "Visit_st1w_z_p_ai_s"},
- {"110x0", "Visit_st1d_z_p_bz_d_x32_scaled"},
- {"110x1", "Visit_st1d_z_p_bz_d_64_scaled"},
+ { {"00001"_b, "ld1sh_z_p_bi_s32"},
+ {"00011"_b, "ldnf1sh_z_p_bi_s32"},
+ {"00101"_b, "ld1w_z_p_bi_u64"},
+ {"00111"_b, "ldnf1w_z_p_bi_u64"},
+ {"01001"_b, "ld1sb_z_p_bi_s32"},
+ {"01011"_b, "ldnf1sb_z_p_bi_s32"},
+ {"01101"_b, "ld1d_z_p_bi_u64"},
+ {"01111"_b, "ldnf1d_z_p_bi_u64"},
+ {"100x0"_b, "st1w_z_p_bz_d_x32_scaled"},
+ {"100x1"_b, "st1w_z_p_bz_d_64_scaled"},
+ {"101x0"_b, "st1w_z_p_bz_s_x32_scaled"},
+ {"101x1"_b, "st1w_z_p_ai_s"},
+ {"110x0"_b, "st1d_z_p_bz_d_x32_scaled"},
+ {"110x1"_b, "st1d_z_p_bz_d_64_scaled"},
},
},
- { "Decode_knpsmq",
+ { "_knpsmq",
{18, 17},
- { {"0x", "Visit_st2_asisdlsop_sx2_r2s"},
- {"10", "Visit_st2_asisdlsop_sx2_r2s"},
- {"11", "Visit_st2_asisdlsop_s2_i2s"},
+ { {"0x"_b, "st2_asisdlsop_sx2_r2s"},
+ {"10"_b, "st2_asisdlsop_sx2_r2s"},
+ {"11"_b, "st2_asisdlsop_s2_i2s"},
},
},
- { "Decode_kpmvkn",
+ { "_kpmvkn",
{30, 23, 22, 11, 10},
- { {"00000", "Visit_stur_b_ldst_unscaled"},
- {"00001", "Visit_str_b_ldst_immpost"},
- {"00011", "Visit_str_b_ldst_immpre"},
- {"00100", "Visit_ldur_b_ldst_unscaled"},
- {"00101", "Visit_ldr_b_ldst_immpost"},
- {"00111", "Visit_ldr_b_ldst_immpre"},
- {"01000", "Visit_stur_q_ldst_unscaled"},
- {"01001", "Visit_str_q_ldst_immpost"},
- {"01011", "Visit_str_q_ldst_immpre"},
- {"01100", "Visit_ldur_q_ldst_unscaled"},
- {"01101", "Visit_ldr_q_ldst_immpost"},
- {"01111", "Visit_ldr_q_ldst_immpre"},
- {"10000", "Visit_stur_h_ldst_unscaled"},
- {"10001", "Visit_str_h_ldst_immpost"},
- {"10011", "Visit_str_h_ldst_immpre"},
- {"10100", "Visit_ldur_h_ldst_unscaled"},
- {"10101", "Visit_ldr_h_ldst_immpost"},
- {"10111", "Visit_ldr_h_ldst_immpre"},
+ { {"00000"_b, "stur_b_ldst_unscaled"},
+ {"00001"_b, "str_b_ldst_immpost"},
+ {"00011"_b, "str_b_ldst_immpre"},
+ {"00100"_b, "ldur_b_ldst_unscaled"},
+ {"00101"_b, "ldr_b_ldst_immpost"},
+ {"00111"_b, "ldr_b_ldst_immpre"},
+ {"01000"_b, "stur_q_ldst_unscaled"},
+ {"01001"_b, "str_q_ldst_immpost"},
+ {"01011"_b, "str_q_ldst_immpre"},
+ {"01100"_b, "ldur_q_ldst_unscaled"},
+ {"01101"_b, "ldr_q_ldst_immpost"},
+ {"01111"_b, "ldr_q_ldst_immpre"},
+ {"10000"_b, "stur_h_ldst_unscaled"},
+ {"10001"_b, "str_h_ldst_immpost"},
+ {"10011"_b, "str_h_ldst_immpre"},
+ {"10100"_b, "ldur_h_ldst_unscaled"},
+ {"10101"_b, "ldr_h_ldst_immpost"},
+ {"10111"_b, "ldr_h_ldst_immpre"},
},
},
- { "Decode_kpqgsn",
+ { "_kpqgsn",
{12},
- { {"0", "Visit_st4_asisdlsop_dx4_r4d"},
+ { {"0"_b, "st4_asisdlsop_dx4_r4d"},
},
},
- { "Decode_kpxtsp",
+ { "_kpxtsp",
{6, 5},
- { {"00", "Visit_cfinv_m_pstate"},
- {"01", "Visit_xaflag_m_pstate"},
- {"10", "Visit_axflag_m_pstate"},
+ { {"00"_b, "cfinv_m_pstate"},
+ {"01"_b, "xaflag_m_pstate"},
+ {"10"_b, "axflag_m_pstate"},
},
},
- { "Decode_kpyqyv",
+ { "_kpyqyv",
{12},
- { {"0", "Decode_vjxqhp"},
+ { {"0"_b, "_vjxqhp"},
},
},
- { "Decode_kqjmvy",
+ { "_kqjmvy",
{12},
- { {"0", "Visit_ld4_asisdlsop_dx4_r4d"},
+ { {"0"_b, "ld4_asisdlsop_dx4_r4d"},
},
},
- { "Decode_kqkhtz",
+ { "_kqkhtz",
{9, 8, 7, 6, 5},
- { {"11111", "Visit_autiza_64z_dp_1src"},
+ { {"11111"_b, "autiza_64z_dp_1src"},
},
},
- { "Decode_kqvljp",
+ { "_kqvljp",
{18, 17, 16},
- { {"000", "Visit_fabd_z_p_zz"},
- {"001", "Visit_fscale_z_p_zz"},
- {"010", "Visit_fmulx_z_p_zz"},
- {"100", "Visit_fdivr_z_p_zz"},
- {"101", "Visit_fdiv_z_p_zz"},
+ { {"000"_b, "fabd_z_p_zz"},
+ {"001"_b, "fscale_z_p_zz"},
+ {"010"_b, "fmulx_z_p_zz"},
+ {"100"_b, "fdivr_z_p_zz"},
+ {"101"_b, "fdiv_z_p_zz"},
},
},
- { "Decode_kqxhzx",
+ { "_kqxhzx",
{20, 19, 18, 16, 12, 11, 10},
- { {"0000xxx", "Decode_zmzxjm"},
- {"0010xxx", "Decode_tmshps"},
- {"0011xxx", "Decode_tsksxr"},
- {"0110100", "Decode_pnzphx"},
- {"0111100", "Decode_xpkkpn"},
- {"1000xxx", "Decode_psqpkp"},
- {"1001xxx", "Decode_phxkzh"},
- {"1100xxx", "Decode_vsvrgt"},
+ { {"0000xxx"_b, "_zmzxjm"},
+ {"0010xxx"_b, "_tmshps"},
+ {"0011xxx"_b, "_tsksxr"},
+ {"0110100"_b, "_pnzphx"},
+ {"0111100"_b, "_xpkkpn"},
+ {"1000xxx"_b, "_psqpkp"},
+ {"1001xxx"_b, "_phxkzh"},
+ {"1100xxx"_b, "_vsvrgt"},
},
},
- { "Decode_kqzmtr",
+ { "_kqzmtr",
{30, 23, 22, 20, 13},
- { {"00001", "Visit_ld1b_z_p_bi_u16"},
- {"00011", "Visit_ldnf1b_z_p_bi_u16"},
- {"00101", "Visit_ld1b_z_p_bi_u64"},
- {"00111", "Visit_ldnf1b_z_p_bi_u64"},
- {"01001", "Visit_ld1h_z_p_bi_u16"},
- {"01011", "Visit_ldnf1h_z_p_bi_u16"},
- {"01101", "Visit_ld1h_z_p_bi_u64"},
- {"01111", "Visit_ldnf1h_z_p_bi_u64"},
- {"101x1", "Visit_st1b_z_p_ai_s"},
- {"110x0", "Visit_st1h_z_p_bz_d_x32_scaled"},
- {"110x1", "Visit_st1h_z_p_bz_d_64_scaled"},
- {"111x0", "Visit_st1h_z_p_bz_s_x32_scaled"},
- {"111x1", "Visit_st1h_z_p_ai_s"},
+ { {"00001"_b, "ld1b_z_p_bi_u16"},
+ {"00011"_b, "ldnf1b_z_p_bi_u16"},
+ {"00101"_b, "ld1b_z_p_bi_u64"},
+ {"00111"_b, "ldnf1b_z_p_bi_u64"},
+ {"01001"_b, "ld1h_z_p_bi_u16"},
+ {"01011"_b, "ldnf1h_z_p_bi_u16"},
+ {"01101"_b, "ld1h_z_p_bi_u64"},
+ {"01111"_b, "ldnf1h_z_p_bi_u64"},
+ {"101x1"_b, "st1b_z_p_ai_s"},
+ {"110x0"_b, "st1h_z_p_bz_d_x32_scaled"},
+ {"110x1"_b, "st1h_z_p_bz_d_64_scaled"},
+ {"111x0"_b, "st1h_z_p_bz_s_x32_scaled"},
+ {"111x1"_b, "st1h_z_p_ai_s"},
},
},
- { "Decode_krhrrr",
+ { "_krhrrr",
{12, 10},
- { {"00", "Decode_xyzpvp"},
- {"01", "Decode_nlyntn"},
- {"10", "Decode_zhkjzg"},
- {"11", "Decode_zmpzkg"},
+ { {"00"_b, "_xyzpvp"},
+ {"01"_b, "_nlyntn"},
+ {"10"_b, "_zhkjzg"},
+ {"11"_b, "_zmpzkg"},
},
},
- { "Decode_krlpjl",
+ { "_krlpjl",
{23, 22, 20, 19, 17, 16},
- { {"000010", "Visit_scvtf_s64_float2fix"},
- {"000011", "Visit_ucvtf_s64_float2fix"},
- {"001100", "Visit_fcvtzs_64s_float2fix"},
- {"001101", "Visit_fcvtzu_64s_float2fix"},
- {"010010", "Visit_scvtf_d64_float2fix"},
- {"010011", "Visit_ucvtf_d64_float2fix"},
- {"011100", "Visit_fcvtzs_64d_float2fix"},
- {"011101", "Visit_fcvtzu_64d_float2fix"},
- {"110010", "Visit_scvtf_h64_float2fix"},
- {"110011", "Visit_ucvtf_h64_float2fix"},
- {"111100", "Visit_fcvtzs_64h_float2fix"},
- {"111101", "Visit_fcvtzu_64h_float2fix"},
+ { {"000010"_b, "scvtf_s64_float2fix"},
+ {"000011"_b, "ucvtf_s64_float2fix"},
+ {"001100"_b, "fcvtzs_64s_float2fix"},
+ {"001101"_b, "fcvtzu_64s_float2fix"},
+ {"010010"_b, "scvtf_d64_float2fix"},
+ {"010011"_b, "ucvtf_d64_float2fix"},
+ {"011100"_b, "fcvtzs_64d_float2fix"},
+ {"011101"_b, "fcvtzu_64d_float2fix"},
+ {"110010"_b, "scvtf_h64_float2fix"},
+ {"110011"_b, "ucvtf_h64_float2fix"},
+ {"111100"_b, "fcvtzs_64h_float2fix"},
+ {"111101"_b, "fcvtzu_64h_float2fix"},
},
},
- { "Decode_kstltt",
+ { "_kstltt",
{18, 17, 12},
- { {"0x0", "Visit_ld3_asisdlsop_dx3_r3d"},
- {"100", "Visit_ld3_asisdlsop_dx3_r3d"},
- {"110", "Visit_ld3_asisdlsop_d3_i3d"},
+ { {"0x0"_b, "ld3_asisdlsop_dx3_r3d"},
+ {"100"_b, "ld3_asisdlsop_dx3_r3d"},
+ {"110"_b, "ld3_asisdlsop_d3_i3d"},
},
},
- { "Decode_ksvxxm",
+ { "_ksvxxm",
{9, 8, 7, 6, 5},
- { {"11111", "Visit_pacizb_64z_dp_1src"},
+ { {"11111"_b, "pacizb_64z_dp_1src"},
},
},
- { "Decode_ktnjrx",
+ { "_ktnjrx",
{30, 23, 22, 13, 12, 11, 10},
- { {"000xxxx", "Visit_fnmadd_s_floatdp3"},
- {"001xxxx", "Visit_fnmadd_d_floatdp3"},
- {"011xxxx", "Visit_fnmadd_h_floatdp3"},
- {"10001x0", "Visit_fmls_asisdelem_rh_h"},
- {"10x0101", "Visit_shl_asisdshf_r"},
- {"10x1101", "Visit_sqshl_asisdshf_r"},
- {"11x01x0", "Visit_fmls_asisdelem_r_sd"},
- {"1xx11x0", "Visit_sqdmlsl_asisdelem_l"},
+ { {"000xxxx"_b, "fnmadd_s_floatdp3"},
+ {"001xxxx"_b, "fnmadd_d_floatdp3"},
+ {"011xxxx"_b, "fnmadd_h_floatdp3"},
+ {"10001x0"_b, "fmls_asisdelem_rh_h"},
+ {"10x0101"_b, "shl_asisdshf_r"},
+ {"10x1101"_b, "sqshl_asisdshf_r"},
+ {"11x01x0"_b, "fmls_asisdelem_r_sd"},
+ {"1xx11x0"_b, "sqdmlsl_asisdelem_l"},
},
},
- { "Decode_ktrkrp",
+ { "_ktrkrp",
{17},
- { {"0", "Visit_st3_asisdlso_h3_3h"},
+ { {"0"_b, "st3_asisdlso_h3_3h"},
},
},
- { "Decode_ktyppm",
+ { "_ktyppm",
{11, 10},
- { {"00", "Visit_asr_z_zw"},
- {"01", "Visit_lsr_z_zw"},
- {"11", "Visit_lsl_z_zw"},
+ { {"00"_b, "asr_z_zw"},
+ {"01"_b, "lsr_z_zw"},
+ {"11"_b, "lsl_z_zw"},
},
},
- { "Decode_kvgjzh",
+ { "_kvgjzh",
{9, 8, 7, 6, 5},
- { {"00000", "Visit_fmov_d_floatimm"},
+ { {"00000"_b, "fmov_d_floatimm"},
},
},
- { "Decode_kvmrng",
+ { "_kvmrng",
{23, 22},
- { {"00", "Visit_tbl_asimdtbl_l1_1"},
+ { {"00"_b, "tbl_asimdtbl_l1_1"},
},
},
- { "Decode_kvnqhn",
+ { "_kvnqhn",
{22, 20, 11},
- { {"000", "Visit_sqincw_r_rs_sx"},
- {"001", "Visit_sqdecw_r_rs_sx"},
- {"010", "Visit_sqincw_r_rs_x"},
- {"011", "Visit_sqdecw_r_rs_x"},
- {"100", "Visit_sqincd_r_rs_sx"},
- {"101", "Visit_sqdecd_r_rs_sx"},
- {"110", "Visit_sqincd_r_rs_x"},
- {"111", "Visit_sqdecd_r_rs_x"},
+ { {"000"_b, "sqincw_r_rs_sx"},
+ {"001"_b, "sqdecw_r_rs_sx"},
+ {"010"_b, "sqincw_r_rs_x"},
+ {"011"_b, "sqdecw_r_rs_x"},
+ {"100"_b, "sqincd_r_rs_sx"},
+ {"101"_b, "sqdecd_r_rs_sx"},
+ {"110"_b, "sqincd_r_rs_x"},
+ {"111"_b, "sqdecd_r_rs_x"},
},
},
- { "Decode_kvyysq",
+ { "_kvyysq",
{12, 9, 8, 7, 6, 5},
- { {"100000", "Decode_sjrqth"},
+ { {"100000"_b, "_sjrqth"},
},
},
- { "Decode_kxhjtk",
+ { "_kxhjtk",
{9, 8, 7, 6, 5},
- { {"00000", "Visit_fmov_s_floatimm"},
+ { {"00000"_b, "fmov_s_floatimm"},
},
},
- { "Decode_kxjgsz",
+ { "_kxjgsz",
{23, 22, 20, 19, 11},
- { {"00000", "Visit_movi_asimdimm_m_sm"},
+ { {"00000"_b, "movi_asimdimm_m_sm"},
},
},
- { "Decode_kxkyqr",
+ { "_kxkyqr",
{17},
- { {"0", "Visit_ld4_asisdlsop_hx4_r4h"},
- {"1", "Visit_ld4_asisdlsop_h4_i4h"},
+ { {"0"_b, "ld4_asisdlsop_hx4_r4h"},
+ {"1"_b, "ld4_asisdlsop_h4_i4h"},
},
},
- { "Decode_kxprqm",
+ { "_kxprqm",
{13, 12, 11, 10},
- { {"0000", "Visit_raddhn_asimddiff_n"},
- {"0001", "Visit_ushl_asimdsame_only"},
- {"0010", "Decode_mmknzp"},
- {"0011", "Visit_uqshl_asimdsame_only"},
- {"0100", "Visit_uabal_asimddiff_l"},
- {"0101", "Visit_urshl_asimdsame_only"},
- {"0110", "Decode_glgrjy"},
- {"0111", "Visit_uqrshl_asimdsame_only"},
- {"1000", "Visit_rsubhn_asimddiff_n"},
- {"1001", "Visit_umax_asimdsame_only"},
- {"1010", "Decode_pxlnhs"},
- {"1011", "Visit_umin_asimdsame_only"},
- {"1100", "Visit_uabdl_asimddiff_l"},
- {"1101", "Visit_uabd_asimdsame_only"},
- {"1110", "Decode_jkqktg"},
- {"1111", "Visit_uaba_asimdsame_only"},
+ { {"0000"_b, "raddhn_asimddiff_n"},
+ {"0001"_b, "ushl_asimdsame_only"},
+ {"0010"_b, "_mmknzp"},
+ {"0011"_b, "uqshl_asimdsame_only"},
+ {"0100"_b, "uabal_asimddiff_l"},
+ {"0101"_b, "urshl_asimdsame_only"},
+ {"0110"_b, "_glgrjy"},
+ {"0111"_b, "uqrshl_asimdsame_only"},
+ {"1000"_b, "rsubhn_asimddiff_n"},
+ {"1001"_b, "umax_asimdsame_only"},
+ {"1010"_b, "_pxlnhs"},
+ {"1011"_b, "umin_asimdsame_only"},
+ {"1100"_b, "uabdl_asimddiff_l"},
+ {"1101"_b, "uabd_asimdsame_only"},
+ {"1110"_b, "_jkqktg"},
+ {"1111"_b, "uaba_asimdsame_only"},
},
},
- { "Decode_kxsysq",
+ { "_kxsysq",
{30},
- { {"0", "Visit_tbnz_only_testbranch"},
+ { {"0"_b, "tbnz_only_testbranch"},
},
},
- { "Decode_kxvvkq",
+ { "_kxvvkq",
{30, 23, 13},
- { {"000", "Visit_ld1b_z_p_bz_s_x32_unscaled"},
- {"001", "Visit_ldff1b_z_p_bz_s_x32_unscaled"},
- {"010", "Visit_ld1h_z_p_bz_s_x32_unscaled"},
- {"011", "Visit_ldff1h_z_p_bz_s_x32_unscaled"},
- {"100", "Visit_ld1b_z_p_bz_d_x32_unscaled"},
- {"101", "Visit_ldff1b_z_p_bz_d_x32_unscaled"},
- {"110", "Visit_ld1h_z_p_bz_d_x32_unscaled"},
- {"111", "Visit_ldff1h_z_p_bz_d_x32_unscaled"},
+ { {"000"_b, "ld1b_z_p_bz_s_x32_unscaled"},
+ {"001"_b, "ldff1b_z_p_bz_s_x32_unscaled"},
+ {"010"_b, "ld1h_z_p_bz_s_x32_unscaled"},
+ {"011"_b, "ldff1h_z_p_bz_s_x32_unscaled"},
+ {"100"_b, "ld1b_z_p_bz_d_x32_unscaled"},
+ {"101"_b, "ldff1b_z_p_bz_d_x32_unscaled"},
+ {"110"_b, "ld1h_z_p_bz_d_x32_unscaled"},
+ {"111"_b, "ldff1h_z_p_bz_d_x32_unscaled"},
},
},
- { "Decode_kyjxrr",
+ { "_kyjxrr",
{30, 13},
- { {"00", "Decode_qtxpky"},
- {"01", "Decode_hnjrmp"},
- {"11", "Decode_vzjvtv"},
+ { {"00"_b, "_qtxpky"},
+ {"01"_b, "_hnjrmp"},
+ {"11"_b, "_vzjvtv"},
},
},
- { "Decode_kykymg",
+ { "_kykymg",
{30},
- { {"1", "Decode_rsyhtj"},
+ { {"1"_b, "_rsyhtj"},
},
},
- { "Decode_kypqpy",
+ { "_kypqpy",
{30, 23, 22, 13, 12, 11, 10},
- { {"1010000", "Visit_sm3partw1_vvv4_cryptosha512_3"},
- {"1010001", "Visit_sm3partw2_vvv4_cryptosha512_3"},
- {"1010010", "Visit_sm4ekey_vvv4_cryptosha512_3"},
+ { {"1010000"_b, "sm3partw1_vvv4_cryptosha512_3"},
+ {"1010001"_b, "sm3partw2_vvv4_cryptosha512_3"},
+ {"1010010"_b, "sm4ekey_vvv4_cryptosha512_3"},
},
},
- { "Decode_kyspnn",
+ { "_kyspnn",
{22},
- { {"0", "Visit_sqdmullb_z_zzi_s"},
- {"1", "Visit_sqdmullb_z_zzi_d"},
+ { {"0"_b, "sqdmullb_z_zzi_s"},
+ {"1"_b, "sqdmullb_z_zzi_d"},
},
},
- { "Decode_kyxqgg",
+ { "_kyxqgg",
{20, 19, 18, 17, 16, 13, 12},
- { {"0000000", "Visit_stgm_64bulk_ldsttags"},
+ { {"0000000"_b, "stgm_64bulk_ldsttags"},
},
},
- { "Decode_kyxrqg",
+ { "_kyxrqg",
{10},
- { {"0", "Visit_uabalb_z_zzz"},
- {"1", "Visit_uabalt_z_zzz"},
+ { {"0"_b, "uabalb_z_zzz"},
+ {"1"_b, "uabalt_z_zzz"},
},
},
- { "Decode_kyygzs",
+ { "_kyygzs",
{19},
- { {"0", "Decode_nnkyzr"},
- {"1", "Visit_sys_cr_systeminstrs"},
+ { {"0"_b, "_nnkyzr"},
+ {"1"_b, "sys_cr_systeminstrs"},
},
},
- { "Decode_kyyzks",
+ { "_kyyzks",
{13, 12},
- { {"00", "Visit_sdiv_32_dp_2src"},
- {"10", "Visit_rorv_32_dp_2src"},
+ { {"00"_b, "sdiv_32_dp_2src"},
+ {"10"_b, "rorv_32_dp_2src"},
},
},
- { "Decode_kzmvpk",
+ { "_kzmvpk",
{23, 22, 10},
- { {"100", "Visit_smlalb_z_zzzi_s"},
- {"101", "Visit_smlalt_z_zzzi_s"},
- {"110", "Visit_smlalb_z_zzzi_d"},
- {"111", "Visit_smlalt_z_zzzi_d"},
+ { {"100"_b, "smlalb_z_zzzi_s"},
+ {"101"_b, "smlalt_z_zzzi_s"},
+ {"110"_b, "smlalb_z_zzzi_d"},
+ {"111"_b, "smlalt_z_zzzi_d"},
},
},
- { "Decode_kzrklp",
+ { "_kzrklp",
{17},
- { {"0", "Visit_ld4_asisdlso_b4_4b"},
+ { {"0"_b, "ld4_asisdlso_b4_4b"},
},
},
- { "Decode_lgglzy",
+ { "_lgglzy",
{30, 23, 22, 19, 16},
- { {"10010", "Visit_aesimc_b_cryptoaes"},
- {"x0x01", "Visit_fcvtl_asimdmisc_l"},
- {"xxx00", "Visit_sqabs_asimdmisc_r"},
+ { {"10010"_b, "aesimc_b_cryptoaes"},
+ {"x0x01"_b, "fcvtl_asimdmisc_l"},
+ {"xxx00"_b, "sqabs_asimdmisc_r"},
},
},
- { "Decode_lhmlrj",
+ { "_lhmlrj",
{30, 23, 22, 20, 19},
- { {"0xxxx", "Visit_bl_only_branch_imm"},
- {"10001", "Visit_sysl_rc_systeminstrs"},
- {"1001x", "Visit_mrs_rs_systemmove"},
+ { {"0xxxx"_b, "bl_only_branch_imm"},
+ {"10001"_b, "sysl_rc_systeminstrs"},
+ {"1001x"_b, "mrs_rs_systemmove"},
},
},
- { "Decode_lhpgsn",
+ { "_lhpgsn",
{13, 12, 10},
- { {"000", "Visit_sqdmulh_asisdelem_r"},
- {"010", "Visit_sqrdmulh_asisdelem_r"},
- {"101", "Decode_mxkgnq"},
- {"111", "Decode_sgnknz"},
+ { {"000"_b, "sqdmulh_asisdelem_r"},
+ {"010"_b, "sqrdmulh_asisdelem_r"},
+ {"101"_b, "_mxkgnq"},
+ {"111"_b, "_sgnknz"},
},
},
- { "Decode_lhtyjq",
+ { "_lhtyjq",
{23, 22, 20, 19, 18, 16, 13},
- { {"0000000", "Decode_gskkxk"},
- {"0000001", "Decode_ktrkrp"},
- {"0100000", "Decode_nmtkjv"},
- {"0100001", "Decode_kmkpnj"},
- {"100xxx0", "Visit_st1_asisdlsop_hx1_r1h"},
- {"100xxx1", "Visit_st3_asisdlsop_hx3_r3h"},
- {"1010xx0", "Visit_st1_asisdlsop_hx1_r1h"},
- {"1010xx1", "Visit_st3_asisdlsop_hx3_r3h"},
- {"10110x0", "Visit_st1_asisdlsop_hx1_r1h"},
- {"10110x1", "Visit_st3_asisdlsop_hx3_r3h"},
- {"1011100", "Visit_st1_asisdlsop_hx1_r1h"},
- {"1011101", "Visit_st3_asisdlsop_hx3_r3h"},
- {"1011110", "Decode_mgmgqh"},
- {"1011111", "Decode_gzylzp"},
- {"110xxx0", "Visit_ld1_asisdlsop_hx1_r1h"},
- {"110xxx1", "Visit_ld3_asisdlsop_hx3_r3h"},
- {"1110xx0", "Visit_ld1_asisdlsop_hx1_r1h"},
- {"1110xx1", "Visit_ld3_asisdlsop_hx3_r3h"},
- {"11110x0", "Visit_ld1_asisdlsop_hx1_r1h"},
- {"11110x1", "Visit_ld3_asisdlsop_hx3_r3h"},
- {"1111100", "Visit_ld1_asisdlsop_hx1_r1h"},
- {"1111101", "Visit_ld3_asisdlsop_hx3_r3h"},
- {"1111110", "Decode_mrkkps"},
- {"1111111", "Decode_xygxsv"},
+ { {"0000000"_b, "_gskkxk"},
+ {"0000001"_b, "_ktrkrp"},
+ {"0100000"_b, "_nmtkjv"},
+ {"0100001"_b, "_kmkpnj"},
+ {"100xxx0"_b, "st1_asisdlsop_hx1_r1h"},
+ {"100xxx1"_b, "st3_asisdlsop_hx3_r3h"},
+ {"1010xx0"_b, "st1_asisdlsop_hx1_r1h"},
+ {"1010xx1"_b, "st3_asisdlsop_hx3_r3h"},
+ {"10110x0"_b, "st1_asisdlsop_hx1_r1h"},
+ {"10110x1"_b, "st3_asisdlsop_hx3_r3h"},
+ {"1011100"_b, "st1_asisdlsop_hx1_r1h"},
+ {"1011101"_b, "st3_asisdlsop_hx3_r3h"},
+ {"1011110"_b, "_mgmgqh"},
+ {"1011111"_b, "_gzylzp"},
+ {"110xxx0"_b, "ld1_asisdlsop_hx1_r1h"},
+ {"110xxx1"_b, "ld3_asisdlsop_hx3_r3h"},
+ {"1110xx0"_b, "ld1_asisdlsop_hx1_r1h"},
+ {"1110xx1"_b, "ld3_asisdlsop_hx3_r3h"},
+ {"11110x0"_b, "ld1_asisdlsop_hx1_r1h"},
+ {"11110x1"_b, "ld3_asisdlsop_hx3_r3h"},
+ {"1111100"_b, "ld1_asisdlsop_hx1_r1h"},
+ {"1111101"_b, "ld3_asisdlsop_hx3_r3h"},
+ {"1111110"_b, "_mrkkps"},
+ {"1111111"_b, "_xygxsv"},
},
},
- { "Decode_lhvtrp",
+ { "_lhvtrp",
{23, 22, 20, 19, 13, 11},
- { {"0000x0", "Visit_orr_asimdimm_l_hl"},
- {"00x100", "Visit_sqshrn_asimdshf_n"},
- {"00x101", "Visit_sqrshrn_asimdshf_n"},
- {"010x00", "Visit_sqshrn_asimdshf_n"},
- {"010x01", "Visit_sqrshrn_asimdshf_n"},
- {"011100", "Visit_sqshrn_asimdshf_n"},
- {"011101", "Visit_sqrshrn_asimdshf_n"},
- {"0x1000", "Visit_sqshrn_asimdshf_n"},
- {"0x1001", "Visit_sqrshrn_asimdshf_n"},
+ { {"0000x0"_b, "orr_asimdimm_l_hl"},
+ {"00x100"_b, "sqshrn_asimdshf_n"},
+ {"00x101"_b, "sqrshrn_asimdshf_n"},
+ {"010x00"_b, "sqshrn_asimdshf_n"},
+ {"010x01"_b, "sqrshrn_asimdshf_n"},
+ {"011100"_b, "sqshrn_asimdshf_n"},
+ {"011101"_b, "sqrshrn_asimdshf_n"},
+ {"0x1000"_b, "sqshrn_asimdshf_n"},
+ {"0x1001"_b, "sqrshrn_asimdshf_n"},
},
},
- { "Decode_ljhtkq",
+ { "_ljhtkq",
{20, 19, 18, 17, 16, 13, 12, 11},
- { {"00000000", "Decode_yvyxkx"},
+ { {"00000000"_b, "_yvyxkx"},
},
},
- { "Decode_ljljkv",
+ { "_ljljkv",
{30, 23, 22, 13, 12, 11, 10},
- { {"0001100", "Visit_and_z_zz"},
- {"0001110", "Visit_eor3_z_zzz"},
- {"0001111", "Visit_bsl_z_zzz"},
- {"0011100", "Visit_orr_z_zz"},
- {"0011110", "Visit_bcax_z_zzz"},
- {"0011111", "Visit_bsl1n_z_zzz"},
- {"0101100", "Visit_eor_z_zz"},
- {"0101111", "Visit_bsl2n_z_zzz"},
- {"0111100", "Visit_bic_z_zz"},
- {"0111111", "Visit_nbsl_z_zzz"},
- {"0xx0000", "Visit_add_z_zz"},
- {"0xx0001", "Visit_sub_z_zz"},
- {"0xx0100", "Visit_sqadd_z_zz"},
- {"0xx0101", "Visit_uqadd_z_zz"},
- {"0xx0110", "Visit_sqsub_z_zz"},
- {"0xx0111", "Visit_uqsub_z_zz"},
- {"0xx1101", "Visit_xar_z_zzi"},
- {"10x0010", "Visit_mla_z_zzzi_h"},
- {"10x0011", "Visit_mls_z_zzzi_h"},
- {"10x0100", "Visit_sqrdmlah_z_zzzi_h"},
- {"10x0101", "Visit_sqrdmlsh_z_zzzi_h"},
- {"1100000", "Visit_sdot_z_zzzi_s"},
- {"1100001", "Visit_udot_z_zzzi_s"},
- {"1100010", "Visit_mla_z_zzzi_s"},
- {"1100011", "Visit_mls_z_zzzi_s"},
- {"1100100", "Visit_sqrdmlah_z_zzzi_s"},
- {"1100101", "Visit_sqrdmlsh_z_zzzi_s"},
- {"1100110", "Visit_usdot_z_zzzi_s"},
- {"1100111", "Visit_sudot_z_zzzi_s"},
- {"11010x0", "Visit_sqdmlalb_z_zzzi_s"},
- {"11010x1", "Visit_sqdmlalt_z_zzzi_s"},
- {"11011x0", "Visit_sqdmlslb_z_zzzi_s"},
- {"11011x1", "Visit_sqdmlslt_z_zzzi_s"},
- {"1110000", "Visit_sdot_z_zzzi_d"},
- {"1110001", "Visit_udot_z_zzzi_d"},
- {"1110010", "Visit_mla_z_zzzi_d"},
- {"1110011", "Visit_mls_z_zzzi_d"},
- {"1110100", "Visit_sqrdmlah_z_zzzi_d"},
- {"1110101", "Visit_sqrdmlsh_z_zzzi_d"},
- {"11110x0", "Visit_sqdmlalb_z_zzzi_d"},
- {"11110x1", "Visit_sqdmlalt_z_zzzi_d"},
- {"11111x0", "Visit_sqdmlslb_z_zzzi_d"},
- {"11111x1", "Visit_sqdmlslt_z_zzzi_d"},
+ { {"0001100"_b, "and_z_zz"},
+ {"0001110"_b, "eor3_z_zzz"},
+ {"0001111"_b, "bsl_z_zzz"},
+ {"0011100"_b, "orr_z_zz"},
+ {"0011110"_b, "bcax_z_zzz"},
+ {"0011111"_b, "bsl1n_z_zzz"},
+ {"0101100"_b, "eor_z_zz"},
+ {"0101111"_b, "bsl2n_z_zzz"},
+ {"0111100"_b, "bic_z_zz"},
+ {"0111111"_b, "nbsl_z_zzz"},
+ {"0xx0000"_b, "add_z_zz"},
+ {"0xx0001"_b, "sub_z_zz"},
+ {"0xx0100"_b, "sqadd_z_zz"},
+ {"0xx0101"_b, "uqadd_z_zz"},
+ {"0xx0110"_b, "sqsub_z_zz"},
+ {"0xx0111"_b, "uqsub_z_zz"},
+ {"0xx1101"_b, "xar_z_zzi"},
+ {"10x0010"_b, "mla_z_zzzi_h"},
+ {"10x0011"_b, "mls_z_zzzi_h"},
+ {"10x0100"_b, "sqrdmlah_z_zzzi_h"},
+ {"10x0101"_b, "sqrdmlsh_z_zzzi_h"},
+ {"1100000"_b, "sdot_z_zzzi_s"},
+ {"1100001"_b, "udot_z_zzzi_s"},
+ {"1100010"_b, "mla_z_zzzi_s"},
+ {"1100011"_b, "mls_z_zzzi_s"},
+ {"1100100"_b, "sqrdmlah_z_zzzi_s"},
+ {"1100101"_b, "sqrdmlsh_z_zzzi_s"},
+ {"1100110"_b, "usdot_z_zzzi_s"},
+ {"1100111"_b, "sudot_z_zzzi_s"},
+ {"11010x0"_b, "sqdmlalb_z_zzzi_s"},
+ {"11010x1"_b, "sqdmlalt_z_zzzi_s"},
+ {"11011x0"_b, "sqdmlslb_z_zzzi_s"},
+ {"11011x1"_b, "sqdmlslt_z_zzzi_s"},
+ {"1110000"_b, "sdot_z_zzzi_d"},
+ {"1110001"_b, "udot_z_zzzi_d"},
+ {"1110010"_b, "mla_z_zzzi_d"},
+ {"1110011"_b, "mls_z_zzzi_d"},
+ {"1110100"_b, "sqrdmlah_z_zzzi_d"},
+ {"1110101"_b, "sqrdmlsh_z_zzzi_d"},
+ {"11110x0"_b, "sqdmlalb_z_zzzi_d"},
+ {"11110x1"_b, "sqdmlalt_z_zzzi_d"},
+ {"11111x0"_b, "sqdmlslb_z_zzzi_d"},
+ {"11111x1"_b, "sqdmlslt_z_zzzi_d"},
},
},
- { "Decode_ljxhnq",
+ { "_ljxhnq",
{12},
- { {"0", "Visit_ld1_asisdlsop_dx1_r1d"},
+ { {"0"_b, "ld1_asisdlsop_dx1_r1d"},
},
},
- { "Decode_lkttgy",
+ { "_lkttgy",
{10},
- { {"0", "Visit_saba_z_zzz"},
- {"1", "Visit_uaba_z_zzz"},
+ { {"0"_b, "saba_z_zzz"},
+ {"1"_b, "uaba_z_zzz"},
},
},
- { "Decode_lkvynm",
+ { "_lkvynm",
{22, 20, 19, 13, 12},
- { {"0x100", "Visit_ushr_asisdshf_r"},
- {"0x101", "Visit_usra_asisdshf_r"},
- {"0x110", "Visit_urshr_asisdshf_r"},
- {"0x111", "Visit_ursra_asisdshf_r"},
- {"10x00", "Visit_ushr_asisdshf_r"},
- {"10x01", "Visit_usra_asisdshf_r"},
- {"10x10", "Visit_urshr_asisdshf_r"},
- {"10x11", "Visit_ursra_asisdshf_r"},
- {"11100", "Visit_ushr_asisdshf_r"},
- {"11101", "Visit_usra_asisdshf_r"},
- {"11110", "Visit_urshr_asisdshf_r"},
- {"11111", "Visit_ursra_asisdshf_r"},
- {"x1000", "Visit_ushr_asisdshf_r"},
- {"x1001", "Visit_usra_asisdshf_r"},
- {"x1010", "Visit_urshr_asisdshf_r"},
- {"x1011", "Visit_ursra_asisdshf_r"},
+ { {"0x100"_b, "ushr_asisdshf_r"},
+ {"0x101"_b, "usra_asisdshf_r"},
+ {"0x110"_b, "urshr_asisdshf_r"},
+ {"0x111"_b, "ursra_asisdshf_r"},
+ {"10x00"_b, "ushr_asisdshf_r"},
+ {"10x01"_b, "usra_asisdshf_r"},
+ {"10x10"_b, "urshr_asisdshf_r"},
+ {"10x11"_b, "ursra_asisdshf_r"},
+ {"11100"_b, "ushr_asisdshf_r"},
+ {"11101"_b, "usra_asisdshf_r"},
+ {"11110"_b, "urshr_asisdshf_r"},
+ {"11111"_b, "ursra_asisdshf_r"},
+ {"x1000"_b, "ushr_asisdshf_r"},
+ {"x1001"_b, "usra_asisdshf_r"},
+ {"x1010"_b, "urshr_asisdshf_r"},
+ {"x1011"_b, "ursra_asisdshf_r"},
},
},
- { "Decode_lkxgjy",
+ { "_lkxgjy",
{23, 22},
- { {"10", "Visit_cmla_z_zzzi_h"},
- {"11", "Visit_cmla_z_zzzi_s"},
+ { {"10"_b, "cmla_z_zzzi_h"},
+ {"11"_b, "cmla_z_zzzi_s"},
},
},
- { "Decode_llnzlv",
+ { "_llnzlv",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_sqneg_asisdmisc_r"},
+ { {"00000"_b, "sqneg_asisdmisc_r"},
},
},
- { "Decode_llpsqq",
+ { "_llpsqq",
{13, 12, 10},
- { {"001", "Decode_zjjxjl"},
- {"100", "Visit_ptrues_p_s"},
- {"110", "Decode_njngkk"},
+ { {"001"_b, "_zjjxjl"},
+ {"100"_b, "ptrues_p_s"},
+ {"110"_b, "_njngkk"},
},
},
- { "Decode_llqjlh",
+ { "_llqjlh",
{10},
- { {"0", "Decode_lhtyjq"},
+ { {"0"_b, "_lhtyjq"},
},
},
- { "Decode_llvrrk",
+ { "_llvrrk",
{23, 18, 17, 16},
- { {"0000", "Visit_sqxtnb_z_zz"},
+ { {"0000"_b, "sqxtnb_z_zz"},
},
},
- { "Decode_llxlqz",
+ { "_llxlqz",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_cmge_asisdmisc_z"},
+ { {"00000"_b, "cmge_asisdmisc_z"},
},
},
- { "Decode_lmtnzv",
+ { "_lmtnzv",
{12},
- { {"0", "Visit_st2_asisdlsop_dx2_r2d"},
+ { {"0"_b, "st2_asisdlsop_dx2_r2d"},
},
},
- { "Decode_lmyxhr",
+ { "_lmyxhr",
{9, 4},
- { {"00", "Decode_gnqhsl"},
+ { {"00"_b, "_gnqhsl"},
},
},
- { "Decode_lnjpjs",
+ { "_lnjpjs",
{18, 17},
- { {"0x", "Visit_ld3_asisdlsop_sx3_r3s"},
- {"10", "Visit_ld3_asisdlsop_sx3_r3s"},
- {"11", "Visit_ld3_asisdlsop_s3_i3s"},
+ { {"0x"_b, "ld3_asisdlsop_sx3_r3s"},
+ {"10"_b, "ld3_asisdlsop_sx3_r3s"},
+ {"11"_b, "ld3_asisdlsop_s3_i3s"},
},
},
- { "Decode_lnkqjp",
+ { "_lnkqjp",
{18, 17, 12},
- { {"000", "Visit_ld3_asisdlso_d3_3d"},
+ { {"000"_b, "ld3_asisdlso_d3_3d"},
},
},
- { "Decode_lnnyzt",
+ { "_lnnyzt",
{23, 22},
- { {"01", "Visit_fmax_asimdsamefp16_only"},
- {"11", "Visit_fmin_asimdsamefp16_only"},
+ { {"01"_b, "fmax_asimdsamefp16_only"},
+ {"11"_b, "fmin_asimdsamefp16_only"},
},
},
- { "Decode_lnpvky",
+ { "_lnpvky",
{23, 22, 19, 13, 12},
- { {"00100", "Visit_sha1h_ss_cryptosha2"},
- {"00101", "Visit_sha1su1_vv_cryptosha2"},
- {"00110", "Visit_sha256su0_vv_cryptosha2"},
- {"xx011", "Visit_suqadd_asisdmisc_r"},
+ { {"00100"_b, "sha1h_ss_cryptosha2"},
+ {"00101"_b, "sha1su1_vv_cryptosha2"},
+ {"00110"_b, "sha256su0_vv_cryptosha2"},
+ {"xx011"_b, "suqadd_asisdmisc_r"},
},
},
- { "Decode_lpkqzl",
+ { "_lpkqzl",
{30, 23, 22, 12, 11, 10},
- { {"0000xx", "Visit_adds_64s_addsub_ext"},
- {"000100", "Visit_adds_64s_addsub_ext"},
- {"1000xx", "Visit_subs_64s_addsub_ext"},
- {"100100", "Visit_subs_64s_addsub_ext"},
+ { {"0000xx"_b, "adds_64s_addsub_ext"},
+ {"000100"_b, "adds_64s_addsub_ext"},
+ {"1000xx"_b, "subs_64s_addsub_ext"},
+ {"100100"_b, "subs_64s_addsub_ext"},
},
},
- { "Decode_lpslrz",
+ { "_lpslrz",
{4, 3, 2, 1, 0},
- { {"00000", "Visit_fcmp_s_floatcmp"},
- {"01000", "Visit_fcmp_sz_floatcmp"},
- {"10000", "Visit_fcmpe_s_floatcmp"},
- {"11000", "Visit_fcmpe_sz_floatcmp"},
+ { {"00000"_b, "fcmp_s_floatcmp"},
+ {"01000"_b, "fcmp_sz_floatcmp"},
+ {"10000"_b, "fcmpe_s_floatcmp"},
+ {"11000"_b, "fcmpe_sz_floatcmp"},
},
},
- { "Decode_lpsvyy",
+ { "_lpsvyy",
{30, 13},
- { {"00", "Decode_jlrrlt"},
- {"01", "Decode_jrlynj"},
- {"10", "Visit_fmla_z_p_zzz"},
- {"11", "Visit_fmls_z_p_zzz"},
+ { {"00"_b, "_jlrrlt"},
+ {"01"_b, "_jrlynj"},
+ {"10"_b, "fmla_z_p_zzz"},
+ {"11"_b, "fmls_z_p_zzz"},
},
},
- { "Decode_lpsxhz",
+ { "_lpsxhz",
{22, 20, 19, 18, 17, 16, 13, 12},
- { {"01111101", "Visit_ld64b_64l_memop"},
+ { {"01111101"_b, "ld64b_64l_memop"},
},
},
- { "Decode_lqmksm",
+ { "_lqmksm",
{30, 23, 22, 20, 13, 4},
- { {"00001x", "Visit_ld1row_z_p_bi_u32"},
- {"000x0x", "Visit_ld1row_z_p_br_contiguous"},
- {"01001x", "Visit_ld1rod_z_p_bi_u64"},
- {"010x0x", "Visit_ld1rod_z_p_br_contiguous"},
- {"110x00", "Visit_str_p_bi"},
+ { {"00001x"_b, "ld1row_z_p_bi_u32"},
+ {"000x0x"_b, "ld1row_z_p_br_contiguous"},
+ {"01001x"_b, "ld1rod_z_p_bi_u64"},
+ {"010x0x"_b, "ld1rod_z_p_br_contiguous"},
+ {"110x00"_b, "str_p_bi"},
},
},
- { "Decode_lqnvvj",
+ { "_lqnvvj",
{22, 13, 12},
- { {"000", "Visit_swp_32_memop"},
- {"100", "Visit_swpl_32_memop"},
+ { {"000"_b, "swp_32_memop"},
+ {"100"_b, "swpl_32_memop"},
},
},
- { "Decode_lrjyhr",
+ { "_lrjyhr",
{23, 22, 20, 19, 13, 11},
- { {"0000x0", "Visit_bic_asimdimm_l_hl"},
- {"00x100", "Visit_uqshrn_asimdshf_n"},
- {"00x101", "Visit_uqrshrn_asimdshf_n"},
- {"010x00", "Visit_uqshrn_asimdshf_n"},
- {"010x01", "Visit_uqrshrn_asimdshf_n"},
- {"011100", "Visit_uqshrn_asimdshf_n"},
- {"011101", "Visit_uqrshrn_asimdshf_n"},
- {"0x1000", "Visit_uqshrn_asimdshf_n"},
- {"0x1001", "Visit_uqrshrn_asimdshf_n"},
+ { {"0000x0"_b, "bic_asimdimm_l_hl"},
+ {"00x100"_b, "uqshrn_asimdshf_n"},
+ {"00x101"_b, "uqrshrn_asimdshf_n"},
+ {"010x00"_b, "uqshrn_asimdshf_n"},
+ {"010x01"_b, "uqrshrn_asimdshf_n"},
+ {"011100"_b, "uqshrn_asimdshf_n"},
+ {"011101"_b, "uqrshrn_asimdshf_n"},
+ {"0x1000"_b, "uqshrn_asimdshf_n"},
+ {"0x1001"_b, "uqrshrn_asimdshf_n"},
},
},
- { "Decode_lrntmz",
+ { "_lrntmz",
{13, 12, 11, 10},
- { {"0000", "Visit_saddlb_z_zz"},
- {"0001", "Visit_saddlt_z_zz"},
- {"0010", "Visit_uaddlb_z_zz"},
- {"0011", "Visit_uaddlt_z_zz"},
- {"0100", "Visit_ssublb_z_zz"},
- {"0101", "Visit_ssublt_z_zz"},
- {"0110", "Visit_usublb_z_zz"},
- {"0111", "Visit_usublt_z_zz"},
- {"1100", "Visit_sabdlb_z_zz"},
- {"1101", "Visit_sabdlt_z_zz"},
- {"1110", "Visit_uabdlb_z_zz"},
- {"1111", "Visit_uabdlt_z_zz"},
+ { {"0000"_b, "saddlb_z_zz"},
+ {"0001"_b, "saddlt_z_zz"},
+ {"0010"_b, "uaddlb_z_zz"},
+ {"0011"_b, "uaddlt_z_zz"},
+ {"0100"_b, "ssublb_z_zz"},
+ {"0101"_b, "ssublt_z_zz"},
+ {"0110"_b, "usublb_z_zz"},
+ {"0111"_b, "usublt_z_zz"},
+ {"1100"_b, "sabdlb_z_zz"},
+ {"1101"_b, "sabdlt_z_zz"},
+ {"1110"_b, "uabdlb_z_zz"},
+ {"1111"_b, "uabdlt_z_zz"},
},
},
- { "Decode_lrqkvp",
+ { "_lrqkvp",
{30, 23, 22, 13, 12, 11, 10},
- { {"0000000", "Visit_ldadd_32_memop"},
- {"0000100", "Visit_ldclr_32_memop"},
- {"0001000", "Visit_ldeor_32_memop"},
- {"0001100", "Visit_ldset_32_memop"},
- {"000xx10", "Visit_str_32_ldst_regoff"},
- {"0010000", "Visit_ldaddl_32_memop"},
- {"0010100", "Visit_ldclrl_32_memop"},
- {"0011000", "Visit_ldeorl_32_memop"},
- {"0011100", "Visit_ldsetl_32_memop"},
- {"001xx10", "Visit_ldr_32_ldst_regoff"},
- {"0100000", "Visit_ldadda_32_memop"},
- {"0100100", "Visit_ldclra_32_memop"},
- {"0101000", "Visit_ldeora_32_memop"},
- {"0101100", "Visit_ldseta_32_memop"},
- {"010xx10", "Visit_ldrsw_64_ldst_regoff"},
- {"0110000", "Visit_ldaddal_32_memop"},
- {"0110100", "Visit_ldclral_32_memop"},
- {"0111000", "Visit_ldeoral_32_memop"},
- {"0111100", "Visit_ldsetal_32_memop"},
- {"1000000", "Visit_ldadd_64_memop"},
- {"1000100", "Visit_ldclr_64_memop"},
- {"1001000", "Visit_ldeor_64_memop"},
- {"1001100", "Visit_ldset_64_memop"},
- {"100xx10", "Visit_str_64_ldst_regoff"},
- {"1010000", "Visit_ldaddl_64_memop"},
- {"1010100", "Visit_ldclrl_64_memop"},
- {"1011000", "Visit_ldeorl_64_memop"},
- {"1011100", "Visit_ldsetl_64_memop"},
- {"101xx10", "Visit_ldr_64_ldst_regoff"},
- {"10xxx01", "Visit_ldraa_64_ldst_pac"},
- {"10xxx11", "Visit_ldraa_64w_ldst_pac"},
- {"1100000", "Visit_ldadda_64_memop"},
- {"1100100", "Visit_ldclra_64_memop"},
- {"1101000", "Visit_ldeora_64_memop"},
- {"1101100", "Visit_ldseta_64_memop"},
- {"110xx10", "Visit_prfm_p_ldst_regoff"},
- {"1110000", "Visit_ldaddal_64_memop"},
- {"1110100", "Visit_ldclral_64_memop"},
- {"1111000", "Visit_ldeoral_64_memop"},
- {"1111100", "Visit_ldsetal_64_memop"},
- {"11xxx01", "Visit_ldrab_64_ldst_pac"},
- {"11xxx11", "Visit_ldrab_64w_ldst_pac"},
+ { {"0000000"_b, "ldadd_32_memop"},
+ {"0000100"_b, "ldclr_32_memop"},
+ {"0001000"_b, "ldeor_32_memop"},
+ {"0001100"_b, "ldset_32_memop"},
+ {"000xx10"_b, "str_32_ldst_regoff"},
+ {"0010000"_b, "ldaddl_32_memop"},
+ {"0010100"_b, "ldclrl_32_memop"},
+ {"0011000"_b, "ldeorl_32_memop"},
+ {"0011100"_b, "ldsetl_32_memop"},
+ {"001xx10"_b, "ldr_32_ldst_regoff"},
+ {"0100000"_b, "ldadda_32_memop"},
+ {"0100100"_b, "ldclra_32_memop"},
+ {"0101000"_b, "ldeora_32_memop"},
+ {"0101100"_b, "ldseta_32_memop"},
+ {"010xx10"_b, "ldrsw_64_ldst_regoff"},
+ {"0110000"_b, "ldaddal_32_memop"},
+ {"0110100"_b, "ldclral_32_memop"},
+ {"0111000"_b, "ldeoral_32_memop"},
+ {"0111100"_b, "ldsetal_32_memop"},
+ {"1000000"_b, "ldadd_64_memop"},
+ {"1000100"_b, "ldclr_64_memop"},
+ {"1001000"_b, "ldeor_64_memop"},
+ {"1001100"_b, "ldset_64_memop"},
+ {"100xx10"_b, "str_64_ldst_regoff"},
+ {"1010000"_b, "ldaddl_64_memop"},
+ {"1010100"_b, "ldclrl_64_memop"},
+ {"1011000"_b, "ldeorl_64_memop"},
+ {"1011100"_b, "ldsetl_64_memop"},
+ {"101xx10"_b, "ldr_64_ldst_regoff"},
+ {"10xxx01"_b, "ldraa_64_ldst_pac"},
+ {"10xxx11"_b, "ldraa_64w_ldst_pac"},
+ {"1100000"_b, "ldadda_64_memop"},
+ {"1100100"_b, "ldclra_64_memop"},
+ {"1101000"_b, "ldeora_64_memop"},
+ {"1101100"_b, "ldseta_64_memop"},
+ {"110xx10"_b, "prfm_p_ldst_regoff"},
+ {"1110000"_b, "ldaddal_64_memop"},
+ {"1110100"_b, "ldclral_64_memop"},
+ {"1111000"_b, "ldeoral_64_memop"},
+ {"1111100"_b, "ldsetal_64_memop"},
+ {"11xxx01"_b, "ldrab_64_ldst_pac"},
+ {"11xxx11"_b, "ldrab_64w_ldst_pac"},
},
},
- { "Decode_lspzrv",
+ { "_lspzrv",
{30, 23, 13},
- { {"000", "Visit_ld1sb_z_p_bz_s_x32_unscaled"},
- {"001", "Visit_ldff1sb_z_p_bz_s_x32_unscaled"},
- {"010", "Visit_ld1sh_z_p_bz_s_x32_unscaled"},
- {"011", "Visit_ldff1sh_z_p_bz_s_x32_unscaled"},
- {"100", "Visit_ld1sb_z_p_bz_d_x32_unscaled"},
- {"101", "Visit_ldff1sb_z_p_bz_d_x32_unscaled"},
- {"110", "Visit_ld1sh_z_p_bz_d_x32_unscaled"},
- {"111", "Visit_ldff1sh_z_p_bz_d_x32_unscaled"},
+ { {"000"_b, "ld1sb_z_p_bz_s_x32_unscaled"},
+ {"001"_b, "ldff1sb_z_p_bz_s_x32_unscaled"},
+ {"010"_b, "ld1sh_z_p_bz_s_x32_unscaled"},
+ {"011"_b, "ldff1sh_z_p_bz_s_x32_unscaled"},
+ {"100"_b, "ld1sb_z_p_bz_d_x32_unscaled"},
+ {"101"_b, "ldff1sb_z_p_bz_d_x32_unscaled"},
+ {"110"_b, "ld1sh_z_p_bz_d_x32_unscaled"},
+ {"111"_b, "ldff1sh_z_p_bz_d_x32_unscaled"},
},
},
- { "Decode_ltvrrg",
+ { "_ltvrrg",
{30},
- { {"0", "Visit_bl_only_branch_imm"},
- {"1", "Decode_htmthz"},
+ { {"0"_b, "bl_only_branch_imm"},
+ {"1"_b, "_htmthz"},
},
},
- { "Decode_lvshqt",
+ { "_lvshqt",
{23, 22},
- { {"00", "Decode_qtkpxg"},
+ { {"00"_b, "_qtkpxg"},
},
},
- { "Decode_lxgltj",
+ { "_lxgltj",
{30, 23, 22},
- { {"000", "Visit_stlxr_sr32_ldstexcl"},
- {"001", "Visit_ldaxr_lr32_ldstexcl"},
- {"010", "Visit_stlr_sl32_ldstexcl"},
- {"011", "Visit_ldar_lr32_ldstexcl"},
- {"100", "Visit_stlxr_sr64_ldstexcl"},
- {"101", "Visit_ldaxr_lr64_ldstexcl"},
- {"110", "Visit_stlr_sl64_ldstexcl"},
- {"111", "Visit_ldar_lr64_ldstexcl"},
+ { {"000"_b, "stlxr_sr32_ldstexcl"},
+ {"001"_b, "ldaxr_lr32_ldstexcl"},
+ {"010"_b, "stlr_sl32_ldstexcl"},
+ {"011"_b, "ldar_lr32_ldstexcl"},
+ {"100"_b, "stlxr_sr64_ldstexcl"},
+ {"101"_b, "ldaxr_lr64_ldstexcl"},
+ {"110"_b, "stlr_sl64_ldstexcl"},
+ {"111"_b, "ldar_lr64_ldstexcl"},
},
},
- { "Decode_lxhlkx",
+ { "_lxhlkx",
{12, 11, 10},
- { {"000", "Visit_ftmad_z_zzi"},
+ { {"000"_b, "ftmad_z_zzi"},
},
},
- { "Decode_lxmyjh",
+ { "_lxmyjh",
{30, 23, 11, 10},
- { {"0000", "Decode_lqnvvj"},
- {"0010", "Decode_tmthqm"},
- {"0100", "Decode_rxjrmn"},
- {"0110", "Decode_ypqgyp"},
- {"1000", "Decode_zpsymj"},
- {"1001", "Visit_ldraa_64_ldst_pac"},
- {"1010", "Decode_rsyzrs"},
- {"1011", "Visit_ldraa_64w_ldst_pac"},
- {"1100", "Decode_nrrmtx"},
- {"1101", "Visit_ldrab_64_ldst_pac"},
- {"1110", "Decode_tgqsyg"},
- {"1111", "Visit_ldrab_64w_ldst_pac"},
+ { {"0000"_b, "_lqnvvj"},
+ {"0010"_b, "_tmthqm"},
+ {"0100"_b, "_rxjrmn"},
+ {"0110"_b, "_ypqgyp"},
+ {"1000"_b, "_zpsymj"},
+ {"1001"_b, "ldraa_64_ldst_pac"},
+ {"1010"_b, "_rsyzrs"},
+ {"1011"_b, "ldraa_64w_ldst_pac"},
+ {"1100"_b, "_nrrmtx"},
+ {"1101"_b, "ldrab_64_ldst_pac"},
+ {"1110"_b, "_tgqsyg"},
+ {"1111"_b, "ldrab_64w_ldst_pac"},
},
},
- { "Decode_lxqynh",
+ { "_lxqynh",
{23, 22, 19, 18, 17, 16},
- { {"0000x1", "Visit_dup_asimdins_dr_r"},
- {"000x10", "Visit_dup_asimdins_dr_r"},
- {"0010xx", "Visit_dup_asimdins_dr_r"},
- {"001110", "Visit_dup_asimdins_dr_r"},
- {"00x10x", "Visit_dup_asimdins_dr_r"},
- {"00x111", "Visit_dup_asimdins_dr_r"},
- {"01xxxx", "Visit_fmla_asimdsamefp16_only"},
- {"11xxxx", "Visit_fmls_asimdsamefp16_only"},
+ { {"0000x1"_b, "dup_asimdins_dr_r"},
+ {"000x10"_b, "dup_asimdins_dr_r"},
+ {"0010xx"_b, "dup_asimdins_dr_r"},
+ {"001110"_b, "dup_asimdins_dr_r"},
+ {"00x10x"_b, "dup_asimdins_dr_r"},
+ {"00x111"_b, "dup_asimdins_dr_r"},
+ {"01xxxx"_b, "fmla_asimdsamefp16_only"},
+ {"11xxxx"_b, "fmls_asimdsamefp16_only"},
},
},
- { "Decode_lxvnxm",
+ { "_lxvnxm",
{23, 22, 12},
- { {"100", "Visit_fmlsl2_asimdelem_lh"},
- {"xx1", "Visit_sqrdmlah_asimdelem_r"},
+ { {"100"_b, "fmlsl2_asimdelem_lh"},
+ {"xx1"_b, "sqrdmlah_asimdelem_r"},
},
},
- { "Decode_lyghyg",
+ { "_lyghyg",
{20, 18, 17},
- { {"000", "Decode_hxmjhn"},
+ { {"000"_b, "_hxmjhn"},
},
},
- { "Decode_lylpyx",
+ { "_lylpyx",
{10},
- { {"0", "Visit_sabalb_z_zzz"},
- {"1", "Visit_sabalt_z_zzz"},
+ { {"0"_b, "sabalb_z_zzz"},
+ {"1"_b, "sabalt_z_zzz"},
},
},
- { "Decode_lynsgm",
+ { "_lynsgm",
{13},
- { {"0", "Decode_ttplgp"},
+ { {"0"_b, "_ttplgp"},
},
},
- { "Decode_lytkrx",
+ { "_lytkrx",
{12, 11, 10},
- { {"000", "Visit_dup_z_zi"},
- {"010", "Visit_tbl_z_zz_2"},
- {"011", "Visit_tbx_z_zz"},
- {"100", "Visit_tbl_z_zz_1"},
- {"110", "Decode_ylnsvy"},
+ { {"000"_b, "dup_z_zi"},
+ {"010"_b, "tbl_z_zz_2"},
+ {"011"_b, "tbx_z_zz"},
+ {"100"_b, "tbl_z_zz_1"},
+ {"110"_b, "_ylnsvy"},
},
},
- { "Decode_lyzxhr",
+ { "_lyzxhr",
{23, 22, 20, 19, 18, 17, 16, 13, 12, 11},
- { {"0011111001", "Decode_smplhv"},
+ { {"0011111001"_b, "_smplhv"},
},
},
- { "Decode_lzpykk",
+ { "_lzpykk",
{30, 23, 22},
- { {"000", "Visit_bfm_32m_bitfield"},
+ { {"000"_b, "bfm_32m_bitfield"},
},
},
- { "Decode_mgmgqh",
+ { "_mgmgqh",
{17},
- { {"0", "Visit_st1_asisdlsop_hx1_r1h"},
- {"1", "Visit_st1_asisdlsop_h1_i1h"},
+ { {"0"_b, "st1_asisdlsop_hx1_r1h"},
+ {"1"_b, "st1_asisdlsop_h1_i1h"},
},
},
- { "Decode_mgmkyq",
+ { "_mgmkyq",
{23},
- { {"0", "Visit_fmaxp_asimdsame_only"},
- {"1", "Visit_fminp_asimdsame_only"},
+ { {"0"_b, "fmaxp_asimdsame_only"},
+ {"1"_b, "fminp_asimdsame_only"},
},
},
- { "Decode_mgqvvn",
+ { "_mgqvvn",
{9, 8, 7, 6, 5},
- { {"11111", "Visit_pacdza_64z_dp_1src"},
+ { {"11111"_b, "pacdza_64z_dp_1src"},
},
},
- { "Decode_mgsvlj",
+ { "_mgsvlj",
{13, 12},
- { {"00", "Visit_udiv_32_dp_2src"},
- {"10", "Visit_asrv_32_dp_2src"},
+ { {"00"_b, "udiv_32_dp_2src"},
+ {"10"_b, "asrv_32_dp_2src"},
},
},
- { "Decode_mhrjvp",
+ { "_mhrjvp",
{30, 13},
- { {"00", "Decode_vxhgzz"},
- {"01", "Decode_lytkrx"},
- {"10", "Decode_rlyvpn"},
- {"11", "Decode_yvptvx"},
+ { {"00"_b, "_vxhgzz"},
+ {"01"_b, "_lytkrx"},
+ {"10"_b, "_rlyvpn"},
+ {"11"_b, "_yvptvx"},
},
},
- { "Decode_mjqvxq",
+ { "_mjqvxq",
{23, 22, 13, 12, 11, 10},
- { {"0001x0", "Visit_fmul_asimdelem_rh_h"},
- {"0x0001", "Visit_shrn_asimdshf_n"},
- {"0x0011", "Visit_rshrn_asimdshf_n"},
- {"0x0101", "Visit_sqshrn_asimdshf_n"},
- {"0x0111", "Visit_sqrshrn_asimdshf_n"},
- {"0x1001", "Visit_sshll_asimdshf_l"},
- {"1x01x0", "Visit_fmul_asimdelem_r_sd"},
- {"xx00x0", "Visit_mul_asimdelem_r"},
- {"xx10x0", "Visit_smull_asimdelem_l"},
- {"xx11x0", "Visit_sqdmull_asimdelem_l"},
+ { {"0001x0"_b, "fmul_asimdelem_rh_h"},
+ {"0x0001"_b, "shrn_asimdshf_n"},
+ {"0x0011"_b, "rshrn_asimdshf_n"},
+ {"0x0101"_b, "sqshrn_asimdshf_n"},
+ {"0x0111"_b, "sqrshrn_asimdshf_n"},
+ {"0x1001"_b, "sshll_asimdshf_l"},
+ {"1x01x0"_b, "fmul_asimdelem_r_sd"},
+ {"xx00x0"_b, "mul_asimdelem_r"},
+ {"xx10x0"_b, "smull_asimdelem_l"},
+ {"xx11x0"_b, "sqdmull_asimdelem_l"},
},
},
- { "Decode_mjxzks",
+ { "_mjxzks",
{4},
- { {"0", "Visit_ccmp_64_condcmp_reg"},
+ { {"0"_b, "ccmp_64_condcmp_reg"},
},
},
- { "Decode_mkgsly",
+ { "_mkgsly",
{19, 18, 17, 16, 4},
- { {"00000", "Visit_brkas_p_p_p_z"},
- {"10000", "Visit_brkns_p_p_pp"},
+ { {"00000"_b, "brkas_p_p_p_z"},
+ {"10000"_b, "brkns_p_p_pp"},
},
},
- { "Decode_mkklrm",
+ { "_mkklrm",
{18, 17},
- { {"00", "Visit_ld3_asisdlso_s3_3s"},
+ { {"00"_b, "ld3_asisdlso_s3_3s"},
},
},
- { "Decode_mkskxj",
+ { "_mkskxj",
{30, 23, 22, 13},
- { {"0000", "Visit_ld1sh_z_p_br_s32"},
- {"0001", "Visit_ldff1sh_z_p_br_s32"},
- {"0010", "Visit_ld1w_z_p_br_u64"},
- {"0011", "Visit_ldff1w_z_p_br_u64"},
- {"0100", "Visit_ld1sb_z_p_br_s32"},
- {"0101", "Visit_ldff1sb_z_p_br_s32"},
- {"0110", "Visit_ld1d_z_p_br_u64"},
- {"0111", "Visit_ldff1d_z_p_br_u64"},
- {"1001", "Visit_st2w_z_p_br_contiguous"},
- {"1011", "Visit_st4w_z_p_br_contiguous"},
- {"10x0", "Visit_st1w_z_p_br"},
- {"1100", "Visit_str_z_bi"},
- {"1101", "Visit_st2d_z_p_br_contiguous"},
- {"1110", "Visit_st1d_z_p_br"},
- {"1111", "Visit_st4d_z_p_br_contiguous"},
+ { {"0000"_b, "ld1sh_z_p_br_s32"},
+ {"0001"_b, "ldff1sh_z_p_br_s32"},
+ {"0010"_b, "ld1w_z_p_br_u64"},
+ {"0011"_b, "ldff1w_z_p_br_u64"},
+ {"0100"_b, "ld1sb_z_p_br_s32"},
+ {"0101"_b, "ldff1sb_z_p_br_s32"},
+ {"0110"_b, "ld1d_z_p_br_u64"},
+ {"0111"_b, "ldff1d_z_p_br_u64"},
+ {"1001"_b, "st2w_z_p_br_contiguous"},
+ {"1011"_b, "st4w_z_p_br_contiguous"},
+ {"10x0"_b, "st1w_z_p_br"},
+ {"1100"_b, "str_z_bi"},
+ {"1101"_b, "st2d_z_p_br_contiguous"},
+ {"1110"_b, "st1d_z_p_br"},
+ {"1111"_b, "st4d_z_p_br_contiguous"},
},
},
- { "Decode_mlnqrm",
+ { "_mlnqrm",
{30},
- { {"0", "Decode_nhzrqr"},
- {"1", "Decode_zpmkvt"},
+ { {"0"_b, "_nhzrqr"},
+ {"1"_b, "_zpmkvt"},
},
},
- { "Decode_mlvpxh",
+ { "_mlvpxh",
{12},
- { {"0", "Visit_ld2_asisdlsop_dx2_r2d"},
+ { {"0"_b, "ld2_asisdlsop_dx2_r2d"},
},
},
- { "Decode_mlxtxs",
+ { "_mlxtxs",
{10},
- { {"0", "Visit_ssra_z_zi"},
- {"1", "Visit_usra_z_zi"},
+ { {"0"_b, "ssra_z_zi"},
+ {"1"_b, "usra_z_zi"},
},
},
- { "Decode_mlyynz",
+ { "_mlyynz",
{12},
- { {"0", "Visit_st3_asisdlsop_dx3_r3d"},
+ { {"0"_b, "st3_asisdlsop_dx3_r3d"},
},
},
- { "Decode_mmhkmp",
+ { "_mmhkmp",
{18, 17},
- { {"0x", "Visit_ld1_asisdlsop_sx1_r1s"},
- {"10", "Visit_ld1_asisdlsop_sx1_r1s"},
- {"11", "Visit_ld1_asisdlsop_s1_i1s"},
+ { {"0x"_b, "ld1_asisdlsop_sx1_r1s"},
+ {"10"_b, "ld1_asisdlsop_sx1_r1s"},
+ {"11"_b, "ld1_asisdlsop_s1_i1s"},
},
},
- { "Decode_mmknzp",
+ { "_mmknzp",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_clz_asimdmisc_r"},
- {"00001", "Visit_uqxtn_asimdmisc_n"},
+ { {"00000"_b, "clz_asimdmisc_r"},
+ {"00001"_b, "uqxtn_asimdmisc_n"},
},
},
- { "Decode_mmmjkx",
+ { "_mmmjkx",
{20, 19, 18, 17, 16, 13, 12},
- { {"0000000", "Visit_rev_32_dp_1src"},
+ { {"0000000"_b, "rev_32_dp_1src"},
},
},
- { "Decode_mmrtvz",
+ { "_mmrtvz",
{12},
- { {"0", "Visit_st4_asisdlsop_dx4_r4d"},
+ { {"0"_b, "st4_asisdlsop_dx4_r4d"},
},
},
- { "Decode_mnmtql",
+ { "_mnmtql",
{10},
- { {"0", "Visit_srsra_z_zi"},
- {"1", "Visit_ursra_z_zi"},
+ { {"0"_b, "srsra_z_zi"},
+ {"1"_b, "ursra_z_zi"},
},
},
- { "Decode_mnxmst",
+ { "_mnxmst",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_fcvtns_asimdmiscfp16_r"},
- {"0x00001", "Visit_fcvtns_asimdmisc_r"},
- {"1111001", "Visit_fcvtps_asimdmiscfp16_r"},
- {"1x00001", "Visit_fcvtps_asimdmisc_r"},
- {"xx00000", "Visit_cmlt_asimdmisc_z"},
- {"xx10000", "Visit_smaxv_asimdall_only"},
- {"xx10001", "Visit_sminv_asimdall_only"},
+ { {"0111001"_b, "fcvtns_asimdmiscfp16_r"},
+ {"0x00001"_b, "fcvtns_asimdmisc_r"},
+ {"1111001"_b, "fcvtps_asimdmiscfp16_r"},
+ {"1x00001"_b, "fcvtps_asimdmisc_r"},
+ {"xx00000"_b, "cmlt_asimdmisc_z"},
+ {"xx10000"_b, "smaxv_asimdall_only"},
+ {"xx10001"_b, "sminv_asimdall_only"},
},
},
- { "Decode_mpgrgp",
+ { "_mpgrgp",
{30, 22, 13, 12, 11, 10},
- { {"000001", "Visit_rmif_only_rmif"},
- {"01xx00", "Visit_ccmn_64_condcmp_reg"},
- {"01xx10", "Visit_ccmn_64_condcmp_imm"},
- {"11xx00", "Visit_ccmp_64_condcmp_reg"},
- {"11xx10", "Visit_ccmp_64_condcmp_imm"},
+ { {"000001"_b, "rmif_only_rmif"},
+ {"01xx00"_b, "ccmn_64_condcmp_reg"},
+ {"01xx10"_b, "ccmn_64_condcmp_imm"},
+ {"11xx00"_b, "ccmp_64_condcmp_reg"},
+ {"11xx10"_b, "ccmp_64_condcmp_imm"},
},
},
- { "Decode_mplgqv",
+ { "_mplgqv",
{11, 10},
- { {"00", "Visit_sm3tt1a_vvv4_crypto3_imm2"},
- {"01", "Visit_sm3tt1b_vvv4_crypto3_imm2"},
- {"10", "Visit_sm3tt2a_vvv4_crypto3_imm2"},
- {"11", "Visit_sm3tt2b_vvv_crypto3_imm2"},
+ { {"00"_b, "sm3tt1a_vvv4_crypto3_imm2"},
+ {"01"_b, "sm3tt1b_vvv4_crypto3_imm2"},
+ {"10"_b, "sm3tt2a_vvv4_crypto3_imm2"},
+ {"11"_b, "sm3tt2b_vvv_crypto3_imm2"},
},
},
- { "Decode_mplskr",
+ { "_mplskr",
{13, 12},
- { {"00", "Visit_add_asisdsame_only"},
- {"11", "Visit_sqdmulh_asisdsame_only"},
+ { {"00"_b, "add_asisdsame_only"},
+ {"11"_b, "sqdmulh_asisdsame_only"},
},
},
- { "Decode_mpstrr",
+ { "_mpstrr",
{23, 22, 8, 7, 6, 5, 4, 3, 2, 1, 0},
- { {"00000000000", "Visit_setffr_f"},
+ { {"00000000000"_b, "setffr_f"},
},
},
- { "Decode_mpvsng",
+ { "_mpvsng",
{30},
- { {"0", "Decode_vvtnrv"},
- {"1", "Decode_yykhjv"},
+ { {"0"_b, "_vvtnrv"},
+ {"1"_b, "_yykhjv"},
},
},
- { "Decode_mpyhkm",
+ { "_mpyhkm",
{30, 23, 22, 13, 12, 11, 10},
- { {"000xxxx", "Visit_fnmsub_s_floatdp3"},
- {"001xxxx", "Visit_fnmsub_d_floatdp3"},
- {"011xxxx", "Visit_fnmsub_h_floatdp3"},
- {"10x1001", "Visit_scvtf_asisdshf_c"},
- {"10x1111", "Visit_fcvtzs_asisdshf_c"},
- {"1xx00x0", "Visit_sqdmulh_asisdelem_r"},
- {"1xx01x0", "Visit_sqrdmulh_asisdelem_r"},
+ { {"000xxxx"_b, "fnmsub_s_floatdp3"},
+ {"001xxxx"_b, "fnmsub_d_floatdp3"},
+ {"011xxxx"_b, "fnmsub_h_floatdp3"},
+ {"10x1001"_b, "scvtf_asisdshf_c"},
+ {"10x1111"_b, "fcvtzs_asisdshf_c"},
+ {"1xx00x0"_b, "sqdmulh_asisdelem_r"},
+ {"1xx01x0"_b, "sqrdmulh_asisdelem_r"},
},
},
- { "Decode_mpyklp",
+ { "_mpyklp",
{23, 22, 20, 19, 16, 13, 10},
- { {"0000000", "Decode_jqjnrv"},
- {"0000001", "Decode_yqmqzp"},
- {"0000010", "Decode_hgxqpp"},
- {"0000011", "Decode_rvzhhx"},
- {"0100000", "Decode_nnllqy"},
- {"0100001", "Decode_vhmsgj"},
- {"0100010", "Decode_mkklrm"},
- {"0100011", "Decode_lnkqjp"},
- {"100xx00", "Visit_st1_asisdlsop_sx1_r1s"},
- {"100xx01", "Decode_yxmkzr"},
- {"100xx10", "Visit_st3_asisdlsop_sx3_r3s"},
- {"100xx11", "Decode_mlyynz"},
- {"1010x00", "Visit_st1_asisdlsop_sx1_r1s"},
- {"1010x01", "Decode_jnjlsh"},
- {"1010x10", "Visit_st3_asisdlsop_sx3_r3s"},
- {"1010x11", "Decode_svrnxq"},
- {"1011000", "Visit_st1_asisdlsop_sx1_r1s"},
- {"1011001", "Decode_hjqtrt"},
- {"1011010", "Visit_st3_asisdlsop_sx3_r3s"},
- {"1011011", "Decode_vqlytp"},
- {"1011100", "Decode_qqpqnm"},
- {"1011101", "Decode_thvvzp"},
- {"1011110", "Decode_srglgl"},
- {"1011111", "Decode_qzrjss"},
- {"110xx00", "Visit_ld1_asisdlsop_sx1_r1s"},
- {"110xx01", "Decode_ljxhnq"},
- {"110xx10", "Visit_ld3_asisdlsop_sx3_r3s"},
- {"110xx11", "Decode_nkrqgn"},
- {"1110x00", "Visit_ld1_asisdlsop_sx1_r1s"},
- {"1110x01", "Decode_vmplgv"},
- {"1110x10", "Visit_ld3_asisdlsop_sx3_r3s"},
- {"1110x11", "Decode_gsttpm"},
- {"1111000", "Visit_ld1_asisdlsop_sx1_r1s"},
- {"1111001", "Decode_xmqvpl"},
- {"1111010", "Visit_ld3_asisdlsop_sx3_r3s"},
- {"1111011", "Decode_stqmps"},
- {"1111100", "Decode_mmhkmp"},
- {"1111101", "Decode_srvnql"},
- {"1111110", "Decode_lnjpjs"},
- {"1111111", "Decode_kstltt"},
+ { {"0000000"_b, "_jqjnrv"},
+ {"0000001"_b, "_yqmqzp"},
+ {"0000010"_b, "_hgxqpp"},
+ {"0000011"_b, "_rvzhhx"},
+ {"0100000"_b, "_nnllqy"},
+ {"0100001"_b, "_vhmsgj"},
+ {"0100010"_b, "_mkklrm"},
+ {"0100011"_b, "_lnkqjp"},
+ {"100xx00"_b, "st1_asisdlsop_sx1_r1s"},
+ {"100xx01"_b, "_yxmkzr"},
+ {"100xx10"_b, "st3_asisdlsop_sx3_r3s"},
+ {"100xx11"_b, "_mlyynz"},
+ {"1010x00"_b, "st1_asisdlsop_sx1_r1s"},
+ {"1010x01"_b, "_jnjlsh"},
+ {"1010x10"_b, "st3_asisdlsop_sx3_r3s"},
+ {"1010x11"_b, "_svrnxq"},
+ {"1011000"_b, "st1_asisdlsop_sx1_r1s"},
+ {"1011001"_b, "_hjqtrt"},
+ {"1011010"_b, "st3_asisdlsop_sx3_r3s"},
+ {"1011011"_b, "_vqlytp"},
+ {"1011100"_b, "_qqpqnm"},
+ {"1011101"_b, "_thvvzp"},
+ {"1011110"_b, "_srglgl"},
+ {"1011111"_b, "_qzrjss"},
+ {"110xx00"_b, "ld1_asisdlsop_sx1_r1s"},
+ {"110xx01"_b, "_ljxhnq"},
+ {"110xx10"_b, "ld3_asisdlsop_sx3_r3s"},
+ {"110xx11"_b, "_nkrqgn"},
+ {"1110x00"_b, "ld1_asisdlsop_sx1_r1s"},
+ {"1110x01"_b, "_vmplgv"},
+ {"1110x10"_b, "ld3_asisdlsop_sx3_r3s"},
+ {"1110x11"_b, "_gsttpm"},
+ {"1111000"_b, "ld1_asisdlsop_sx1_r1s"},
+ {"1111001"_b, "_xmqvpl"},
+ {"1111010"_b, "ld3_asisdlsop_sx3_r3s"},
+ {"1111011"_b, "_stqmps"},
+ {"1111100"_b, "_mmhkmp"},
+ {"1111101"_b, "_srvnql"},
+ {"1111110"_b, "_lnjpjs"},
+ {"1111111"_b, "_kstltt"},
},
},
- { "Decode_mpzqxm",
+ { "_mpzqxm",
{23, 22, 20, 19, 18, 16, 13},
- { {"0000000", "Decode_vpkhvh"},
- {"0000001", "Decode_gttglx"},
- {"0100000", "Decode_gsgzpg"},
- {"0100001", "Decode_ynqsgl"},
- {"100xxx0", "Visit_st2_asisdlsop_hx2_r2h"},
- {"100xxx1", "Visit_st4_asisdlsop_hx4_r4h"},
- {"1010xx0", "Visit_st2_asisdlsop_hx2_r2h"},
- {"1010xx1", "Visit_st4_asisdlsop_hx4_r4h"},
- {"10110x0", "Visit_st2_asisdlsop_hx2_r2h"},
- {"10110x1", "Visit_st4_asisdlsop_hx4_r4h"},
- {"1011100", "Visit_st2_asisdlsop_hx2_r2h"},
- {"1011101", "Visit_st4_asisdlsop_hx4_r4h"},
- {"1011110", "Decode_sjsltg"},
- {"1011111", "Decode_xrpmzt"},
- {"110xxx0", "Visit_ld2_asisdlsop_hx2_r2h"},
- {"110xxx1", "Visit_ld4_asisdlsop_hx4_r4h"},
- {"1110xx0", "Visit_ld2_asisdlsop_hx2_r2h"},
- {"1110xx1", "Visit_ld4_asisdlsop_hx4_r4h"},
- {"11110x0", "Visit_ld2_asisdlsop_hx2_r2h"},
- {"11110x1", "Visit_ld4_asisdlsop_hx4_r4h"},
- {"1111100", "Visit_ld2_asisdlsop_hx2_r2h"},
- {"1111101", "Visit_ld4_asisdlsop_hx4_r4h"},
- {"1111110", "Decode_gygnsz"},
- {"1111111", "Decode_kxkyqr"},
+ { {"0000000"_b, "_vpkhvh"},
+ {"0000001"_b, "_gttglx"},
+ {"0100000"_b, "_gsgzpg"},
+ {"0100001"_b, "_ynqsgl"},
+ {"100xxx0"_b, "st2_asisdlsop_hx2_r2h"},
+ {"100xxx1"_b, "st4_asisdlsop_hx4_r4h"},
+ {"1010xx0"_b, "st2_asisdlsop_hx2_r2h"},
+ {"1010xx1"_b, "st4_asisdlsop_hx4_r4h"},
+ {"10110x0"_b, "st2_asisdlsop_hx2_r2h"},
+ {"10110x1"_b, "st4_asisdlsop_hx4_r4h"},
+ {"1011100"_b, "st2_asisdlsop_hx2_r2h"},
+ {"1011101"_b, "st4_asisdlsop_hx4_r4h"},
+ {"1011110"_b, "_sjsltg"},
+ {"1011111"_b, "_xrpmzt"},
+ {"110xxx0"_b, "ld2_asisdlsop_hx2_r2h"},
+ {"110xxx1"_b, "ld4_asisdlsop_hx4_r4h"},
+ {"1110xx0"_b, "ld2_asisdlsop_hx2_r2h"},
+ {"1110xx1"_b, "ld4_asisdlsop_hx4_r4h"},
+ {"11110x0"_b, "ld2_asisdlsop_hx2_r2h"},
+ {"11110x1"_b, "ld4_asisdlsop_hx4_r4h"},
+ {"1111100"_b, "ld2_asisdlsop_hx2_r2h"},
+ {"1111101"_b, "ld4_asisdlsop_hx4_r4h"},
+ {"1111110"_b, "_gygnsz"},
+ {"1111111"_b, "_kxkyqr"},
},
},
- { "Decode_mqgtsq",
+ { "_mqgtsq",
{30, 23, 22, 19},
- { {"1001", "Visit_aesd_b_cryptoaes"},
- {"xxx0", "Visit_cnt_asimdmisc_r"},
+ { {"1001"_b, "aesd_b_cryptoaes"},
+ {"xxx0"_b, "cnt_asimdmisc_r"},
},
},
- { "Decode_mqkjxj",
+ { "_mqkjxj",
{30},
- { {"0", "Visit_bl_only_branch_imm"},
- {"1", "Decode_lyzxhr"},
+ { {"0"_b, "bl_only_branch_imm"},
+ {"1"_b, "_lyzxhr"},
},
},
- { "Decode_mqrzzk",
+ { "_mqrzzk",
{22, 20, 11},
- { {"000", "Visit_sqincw_z_zs"},
- {"001", "Visit_sqdecw_z_zs"},
- {"010", "Visit_incw_z_zs"},
- {"100", "Visit_sqincd_z_zs"},
- {"101", "Visit_sqdecd_z_zs"},
- {"110", "Visit_incd_z_zs"},
+ { {"000"_b, "sqincw_z_zs"},
+ {"001"_b, "sqdecw_z_zs"},
+ {"010"_b, "incw_z_zs"},
+ {"100"_b, "sqincd_z_zs"},
+ {"101"_b, "sqdecd_z_zs"},
+ {"110"_b, "incd_z_zs"},
},
},
- { "Decode_mrhtxt",
+ { "_mrhtxt",
{23, 22, 20, 9},
- { {"0000", "Visit_brkpb_p_p_pp"},
- {"0100", "Visit_brkpbs_p_p_pp"},
+ { {"0000"_b, "brkpb_p_p_pp"},
+ {"0100"_b, "brkpbs_p_p_pp"},
},
},
- { "Decode_mrkkps",
+ { "_mrkkps",
{17},
- { {"0", "Visit_ld1_asisdlsop_hx1_r1h"},
- {"1", "Visit_ld1_asisdlsop_h1_i1h"},
+ { {"0"_b, "ld1_asisdlsop_hx1_r1h"},
+ {"1"_b, "ld1_asisdlsop_h1_i1h"},
},
},
- { "Decode_mrmpgh",
+ { "_mrmpgh",
{30, 23, 22, 13, 12, 11, 10},
- { {"000xxxx", "Visit_stlxp_sp32_ldstexcl"},
- {"001xxxx", "Visit_ldaxp_lp32_ldstexcl"},
- {"0101111", "Visit_casl_c32_ldstexcl"},
- {"0111111", "Visit_casal_c32_ldstexcl"},
- {"100xxxx", "Visit_stlxp_sp64_ldstexcl"},
- {"101xxxx", "Visit_ldaxp_lp64_ldstexcl"},
- {"1101111", "Visit_casl_c64_ldstexcl"},
- {"1111111", "Visit_casal_c64_ldstexcl"},
+ { {"000xxxx"_b, "stlxp_sp32_ldstexcl"},
+ {"001xxxx"_b, "ldaxp_lp32_ldstexcl"},
+ {"0101111"_b, "casl_c32_ldstexcl"},
+ {"0111111"_b, "casal_c32_ldstexcl"},
+ {"100xxxx"_b, "stlxp_sp64_ldstexcl"},
+ {"101xxxx"_b, "ldaxp_lp64_ldstexcl"},
+ {"1101111"_b, "casl_c64_ldstexcl"},
+ {"1111111"_b, "casal_c64_ldstexcl"},
},
},
- { "Decode_mrqqlp",
+ { "_mrqqlp",
{30, 11, 10},
- { {"000", "Decode_gqykqv"},
- {"001", "Decode_xgvgmk"},
- {"010", "Decode_tjpjng"},
- {"011", "Decode_pjkylt"},
- {"101", "Decode_yrgnqz"},
- {"110", "Decode_hhymvj"},
- {"111", "Decode_xpmvjv"},
+ { {"000"_b, "_gqykqv"},
+ {"001"_b, "_xgvgmk"},
+ {"010"_b, "_tjpjng"},
+ {"011"_b, "_pjkylt"},
+ {"101"_b, "_yrgnqz"},
+ {"110"_b, "_hhymvj"},
+ {"111"_b, "_xpmvjv"},
},
},
- { "Decode_msgqps",
+ { "_msgqps",
{18, 17},
- { {"0x", "Visit_ld2_asisdlsop_sx2_r2s"},
- {"10", "Visit_ld2_asisdlsop_sx2_r2s"},
- {"11", "Visit_ld2_asisdlsop_s2_i2s"},
+ { {"0x"_b, "ld2_asisdlsop_sx2_r2s"},
+ {"10"_b, "ld2_asisdlsop_sx2_r2s"},
+ {"11"_b, "ld2_asisdlsop_s2_i2s"},
},
},
- { "Decode_msnsjp",
+ { "_msnsjp",
{23, 20, 19, 18, 17, 16},
- { {"000001", "Visit_fcvtxn_asisdmisc_n"},
+ { {"000001"_b, "fcvtxn_asisdmisc_n"},
},
},
- { "Decode_msqkyy",
+ { "_msqkyy",
{16, 13, 12},
- { {"000", "Visit_rbit_64_dp_1src"},
- {"001", "Visit_clz_64_dp_1src"},
- {"100", "Visit_pacia_64p_dp_1src"},
- {"101", "Visit_autia_64p_dp_1src"},
- {"110", "Decode_sqgxzn"},
- {"111", "Decode_kqkhtz"},
+ { {"000"_b, "rbit_64_dp_1src"},
+ {"001"_b, "clz_64_dp_1src"},
+ {"100"_b, "pacia_64p_dp_1src"},
+ {"101"_b, "autia_64p_dp_1src"},
+ {"110"_b, "_sqgxzn"},
+ {"111"_b, "_kqkhtz"},
},
},
- { "Decode_mstthg",
+ { "_mstthg",
{13, 12, 11, 10},
- { {"0000", "Visit_umull_asimddiff_l"},
- {"0001", "Decode_qptvrm"},
- {"0010", "Decode_qqzrhz"},
- {"0011", "Decode_yxhrpk"},
- {"0101", "Decode_vsqpzr"},
- {"0110", "Decode_kjrxpx"},
- {"0111", "Decode_qnvgmh"},
- {"1001", "Decode_jvhnxl"},
- {"1010", "Decode_zyzzhm"},
- {"1011", "Decode_slhpgp"},
- {"1101", "Decode_mgmkyq"},
- {"1110", "Decode_qvlytr"},
- {"1111", "Decode_qtmjkr"},
+ { {"0000"_b, "umull_asimddiff_l"},
+ {"0001"_b, "_qptvrm"},
+ {"0010"_b, "_qqzrhz"},
+ {"0011"_b, "_yxhrpk"},
+ {"0101"_b, "_vsqpzr"},
+ {"0110"_b, "_kjrxpx"},
+ {"0111"_b, "_qnvgmh"},
+ {"1001"_b, "_jvhnxl"},
+ {"1010"_b, "_zyzzhm"},
+ {"1011"_b, "_slhpgp"},
+ {"1101"_b, "_mgmkyq"},
+ {"1110"_b, "_qvlytr"},
+ {"1111"_b, "_qtmjkr"},
},
},
- { "Decode_msztzv",
+ { "_msztzv",
{23, 11, 10, 4, 3, 2, 1},
- { {"0000000", "Decode_vvprhx"},
- {"0101111", "Decode_nqysxy"},
- {"0111111", "Decode_kkmjyr"},
- {"1000000", "Decode_ypjyqh"},
+ { {"0000000"_b, "_vvprhx"},
+ {"0101111"_b, "_nqysxy"},
+ {"0111111"_b, "_kkmjyr"},
+ {"1000000"_b, "_ypjyqh"},
},
},
- { "Decode_mtgksl",
+ { "_mtgksl",
{23, 22, 20, 19, 18, 16, 13},
- { {"0000000", "Decode_vnrnmg"},
- {"0000001", "Decode_hzllgl"},
- {"0100000", "Decode_hrhzqy"},
- {"0100001", "Decode_qtjzhs"},
- {"100xxx0", "Visit_st4_asisdlsep_r4_r"},
- {"100xxx1", "Visit_st1_asisdlsep_r4_r4"},
- {"1010xx0", "Visit_st4_asisdlsep_r4_r"},
- {"1010xx1", "Visit_st1_asisdlsep_r4_r4"},
- {"10110x0", "Visit_st4_asisdlsep_r4_r"},
- {"10110x1", "Visit_st1_asisdlsep_r4_r4"},
- {"1011100", "Visit_st4_asisdlsep_r4_r"},
- {"1011101", "Visit_st1_asisdlsep_r4_r4"},
- {"1011110", "Decode_nzkhrj"},
- {"1011111", "Decode_gmjhll"},
- {"110xxx0", "Visit_ld4_asisdlsep_r4_r"},
- {"110xxx1", "Visit_ld1_asisdlsep_r4_r4"},
- {"1110xx0", "Visit_ld4_asisdlsep_r4_r"},
- {"1110xx1", "Visit_ld1_asisdlsep_r4_r4"},
- {"11110x0", "Visit_ld4_asisdlsep_r4_r"},
- {"11110x1", "Visit_ld1_asisdlsep_r4_r4"},
- {"1111100", "Visit_ld4_asisdlsep_r4_r"},
- {"1111101", "Visit_ld1_asisdlsep_r4_r4"},
- {"1111110", "Decode_hxglyp"},
- {"1111111", "Decode_jmyslr"},
+ { {"0000000"_b, "_vnrnmg"},
+ {"0000001"_b, "_hzllgl"},
+ {"0100000"_b, "_hrhzqy"},
+ {"0100001"_b, "_qtjzhs"},
+ {"100xxx0"_b, "st4_asisdlsep_r4_r"},
+ {"100xxx1"_b, "st1_asisdlsep_r4_r4"},
+ {"1010xx0"_b, "st4_asisdlsep_r4_r"},
+ {"1010xx1"_b, "st1_asisdlsep_r4_r4"},
+ {"10110x0"_b, "st4_asisdlsep_r4_r"},
+ {"10110x1"_b, "st1_asisdlsep_r4_r4"},
+ {"1011100"_b, "st4_asisdlsep_r4_r"},
+ {"1011101"_b, "st1_asisdlsep_r4_r4"},
+ {"1011110"_b, "_nzkhrj"},
+ {"1011111"_b, "_gmjhll"},
+ {"110xxx0"_b, "ld4_asisdlsep_r4_r"},
+ {"110xxx1"_b, "ld1_asisdlsep_r4_r4"},
+ {"1110xx0"_b, "ld4_asisdlsep_r4_r"},
+ {"1110xx1"_b, "ld1_asisdlsep_r4_r4"},
+ {"11110x0"_b, "ld4_asisdlsep_r4_r"},
+ {"11110x1"_b, "ld1_asisdlsep_r4_r4"},
+ {"1111100"_b, "ld4_asisdlsep_r4_r"},
+ {"1111101"_b, "ld1_asisdlsep_r4_r4"},
+ {"1111110"_b, "_hxglyp"},
+ {"1111111"_b, "_jmyslr"},
},
},
- { "Decode_mthzvm",
+ { "_mthzvm",
{30, 23, 13, 12, 11, 10},
- { {"100001", "Visit_ushr_asisdshf_r"},
- {"100101", "Visit_usra_asisdshf_r"},
- {"101001", "Visit_urshr_asisdshf_r"},
- {"101101", "Visit_ursra_asisdshf_r"},
+ { {"100001"_b, "ushr_asisdshf_r"},
+ {"100101"_b, "usra_asisdshf_r"},
+ {"101001"_b, "urshr_asisdshf_r"},
+ {"101101"_b, "ursra_asisdshf_r"},
},
},
- { "Decode_mtjrtt",
+ { "_mtjrtt",
{13, 12},
- { {"00", "Visit_subps_64s_dp_2src"},
+ { {"00"_b, "subps_64s_dp_2src"},
},
},
- { "Decode_mtlhnl",
+ { "_mtlhnl",
{23, 22, 20, 19, 13, 11},
- { {"0000x0", "Visit_movi_asimdimm_l_sl"},
- {"00x100", "Visit_sshr_asimdshf_r"},
- {"00x110", "Visit_srshr_asimdshf_r"},
- {"010x00", "Visit_sshr_asimdshf_r"},
- {"010x10", "Visit_srshr_asimdshf_r"},
- {"011100", "Visit_sshr_asimdshf_r"},
- {"011110", "Visit_srshr_asimdshf_r"},
- {"0x1000", "Visit_sshr_asimdshf_r"},
- {"0x1010", "Visit_srshr_asimdshf_r"},
+ { {"0000x0"_b, "movi_asimdimm_l_sl"},
+ {"00x100"_b, "sshr_asimdshf_r"},
+ {"00x110"_b, "srshr_asimdshf_r"},
+ {"010x00"_b, "sshr_asimdshf_r"},
+ {"010x10"_b, "srshr_asimdshf_r"},
+ {"011100"_b, "sshr_asimdshf_r"},
+ {"011110"_b, "srshr_asimdshf_r"},
+ {"0x1000"_b, "sshr_asimdshf_r"},
+ {"0x1010"_b, "srshr_asimdshf_r"},
},
},
- { "Decode_mtnpmr",
+ { "_mtnpmr",
{13, 12, 11, 10},
- { {"0000", "Visit_smull_asimddiff_l"},
- {"0001", "Decode_ypznsm"},
- {"0010", "Decode_sgztlj"},
- {"0011", "Decode_nsnyxt"},
- {"0100", "Visit_sqdmull_asimddiff_l"},
- {"0101", "Decode_plltlx"},
- {"0110", "Decode_qtystr"},
- {"0111", "Decode_gymljg"},
- {"1000", "Visit_pmull_asimddiff_l"},
- {"1001", "Decode_rpmrkq"},
- {"1010", "Decode_hvvyhl"},
- {"1011", "Decode_hlshjk"},
- {"1101", "Decode_gmvjgn"},
- {"1110", "Decode_rsyjqj"},
- {"1111", "Decode_yvlhjg"},
+ { {"0000"_b, "smull_asimddiff_l"},
+ {"0001"_b, "_ypznsm"},
+ {"0010"_b, "_sgztlj"},
+ {"0011"_b, "_nsnyxt"},
+ {"0100"_b, "sqdmull_asimddiff_l"},
+ {"0101"_b, "_plltlx"},
+ {"0110"_b, "_qtystr"},
+ {"0111"_b, "_gymljg"},
+ {"1000"_b, "pmull_asimddiff_l"},
+ {"1001"_b, "_rpmrkq"},
+ {"1010"_b, "_hvvyhl"},
+ {"1011"_b, "_hlshjk"},
+ {"1101"_b, "_gmvjgn"},
+ {"1110"_b, "_rsyjqj"},
+ {"1111"_b, "_yvlhjg"},
},
},
- { "Decode_mtzgpn",
+ { "_mtzgpn",
{30},
- { {"0", "Visit_cbz_32_compbranch"},
+ { {"0"_b, "cbz_32_compbranch"},
},
},
- { "Decode_mvglql",
+ { "_mvglql",
{23, 22, 20, 19, 13, 11},
- { {"0000x0", "Visit_mvni_asimdimm_l_hl"},
- {"00x100", "Visit_sqshrun_asimdshf_n"},
- {"00x101", "Visit_sqrshrun_asimdshf_n"},
- {"00x110", "Visit_ushll_asimdshf_l"},
- {"010x00", "Visit_sqshrun_asimdshf_n"},
- {"010x01", "Visit_sqrshrun_asimdshf_n"},
- {"010x10", "Visit_ushll_asimdshf_l"},
- {"011100", "Visit_sqshrun_asimdshf_n"},
- {"011101", "Visit_sqrshrun_asimdshf_n"},
- {"011110", "Visit_ushll_asimdshf_l"},
- {"0x1000", "Visit_sqshrun_asimdshf_n"},
- {"0x1001", "Visit_sqrshrun_asimdshf_n"},
- {"0x1010", "Visit_ushll_asimdshf_l"},
+ { {"0000x0"_b, "mvni_asimdimm_l_hl"},
+ {"00x100"_b, "sqshrun_asimdshf_n"},
+ {"00x101"_b, "sqrshrun_asimdshf_n"},
+ {"00x110"_b, "ushll_asimdshf_l"},
+ {"010x00"_b, "sqshrun_asimdshf_n"},
+ {"010x01"_b, "sqrshrun_asimdshf_n"},
+ {"010x10"_b, "ushll_asimdshf_l"},
+ {"011100"_b, "sqshrun_asimdshf_n"},
+ {"011101"_b, "sqrshrun_asimdshf_n"},
+ {"011110"_b, "ushll_asimdshf_l"},
+ {"0x1000"_b, "sqshrun_asimdshf_n"},
+ {"0x1001"_b, "sqrshrun_asimdshf_n"},
+ {"0x1010"_b, "ushll_asimdshf_l"},
},
},
- { "Decode_mvgsjr",
+ { "_mvgsjr",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_usqadd_asimdmisc_r"},
- {"00001", "Visit_shll_asimdmisc_s"},
- {"10000", "Visit_uaddlv_asimdall_only"},
+ { {"00000"_b, "usqadd_asimdmisc_r"},
+ {"00001"_b, "shll_asimdmisc_s"},
+ {"10000"_b, "uaddlv_asimdall_only"},
},
},
- { "Decode_mvzvpk",
+ { "_mvzvpk",
{30},
- { {"0", "Visit_orn_64_log_shift"},
- {"1", "Visit_bics_64_log_shift"},
+ { {"0"_b, "orn_64_log_shift"},
+ {"1"_b, "bics_64_log_shift"},
},
},
- { "Decode_mxgykv",
+ { "_mxgykv",
{19, 18, 17, 16},
- { {"0000", "Visit_cntp_r_p_p"},
- {"1000", "Decode_lynsgm"},
- {"1001", "Decode_jxyskn"},
- {"1010", "Decode_jmxstz"},
- {"1011", "Decode_yjzknm"},
- {"1100", "Decode_zmtkvx"},
- {"1101", "Decode_yhmlxk"},
+ { {"0000"_b, "cntp_r_p_p"},
+ {"1000"_b, "_lynsgm"},
+ {"1001"_b, "_jxyskn"},
+ {"1010"_b, "_jmxstz"},
+ {"1011"_b, "_yjzknm"},
+ {"1100"_b, "_zmtkvx"},
+ {"1101"_b, "_yhmlxk"},
},
},
- { "Decode_mxkgnq",
+ { "_mxkgnq",
{23, 22, 20, 19, 11},
- { {"00010", "Visit_scvtf_asisdshf_c"},
- {"001x0", "Visit_scvtf_asisdshf_c"},
- {"01xx0", "Visit_scvtf_asisdshf_c"},
+ { {"00010"_b, "scvtf_asisdshf_c"},
+ {"001x0"_b, "scvtf_asisdshf_c"},
+ {"01xx0"_b, "scvtf_asisdshf_c"},
},
},
- { "Decode_mxnzyr",
+ { "_mxnzyr",
{19, 16},
- { {"00", "Decode_nhxxmh"},
- {"10", "Decode_qgymsy"},
- {"11", "Decode_gjprmg"},
+ { {"00"_b, "_nhxxmh"},
+ {"10"_b, "_qgymsy"},
+ {"11"_b, "_gjprmg"},
},
},
- { "Decode_mxtskk",
+ { "_mxtskk",
{20, 19, 18, 17, 16, 13},
- { {"000000", "Visit_fmov_h_floatdp1"},
- {"000010", "Visit_fneg_h_floatdp1"},
- {"000100", "Visit_fcvt_sh_floatdp1"},
- {"001000", "Visit_frintn_h_floatdp1"},
- {"001010", "Visit_frintm_h_floatdp1"},
- {"001100", "Visit_frinta_h_floatdp1"},
- {"001110", "Visit_frintx_h_floatdp1"},
+ { {"000000"_b, "fmov_h_floatdp1"},
+ {"000010"_b, "fneg_h_floatdp1"},
+ {"000100"_b, "fcvt_sh_floatdp1"},
+ {"001000"_b, "frintn_h_floatdp1"},
+ {"001010"_b, "frintm_h_floatdp1"},
+ {"001100"_b, "frinta_h_floatdp1"},
+ {"001110"_b, "frintx_h_floatdp1"},
},
},
- { "Decode_mxvjxx",
+ { "_mxvjxx",
{20, 19, 18, 16},
- { {"0000", "Decode_nshjhk"},
+ { {"0000"_b, "_nshjhk"},
},
},
- { "Decode_myjqrl",
+ { "_myjqrl",
{22, 20, 19, 18, 17, 16},
- { {"111000", "Visit_fcmge_asisdmiscfp16_fz"},
- {"x00000", "Visit_fcmge_asisdmisc_fz"},
- {"x10000", "Visit_fminnmp_asisdpair_only_sd"},
+ { {"111000"_b, "fcmge_asisdmiscfp16_fz"},
+ {"x00000"_b, "fcmge_asisdmisc_fz"},
+ {"x10000"_b, "fminnmp_asisdpair_only_sd"},
},
},
- { "Decode_mykjss",
+ { "_mykjss",
{17},
- { {"0", "Visit_st2_asisdlsop_bx2_r2b"},
- {"1", "Visit_st2_asisdlsop_b2_i2b"},
+ { {"0"_b, "st2_asisdlsop_bx2_r2b"},
+ {"1"_b, "st2_asisdlsop_b2_i2b"},
},
},
- { "Decode_mylphg",
+ { "_mylphg",
{30, 13, 4},
- { {"000", "Visit_cmpge_p_p_zw"},
- {"001", "Visit_cmpgt_p_p_zw"},
- {"010", "Visit_cmplt_p_p_zw"},
- {"011", "Visit_cmple_p_p_zw"},
- {"1xx", "Visit_fcmla_z_p_zzz"},
+ { {"000"_b, "cmpge_p_p_zw"},
+ {"001"_b, "cmpgt_p_p_zw"},
+ {"010"_b, "cmplt_p_p_zw"},
+ {"011"_b, "cmple_p_p_zw"},
+ {"1xx"_b, "fcmla_z_p_zzz"},
},
},
- { "Decode_myrshl",
+ { "_myrshl",
{4},
- { {"0", "Visit_ccmn_32_condcmp_imm"},
+ { {"0"_b, "ccmn_32_condcmp_imm"},
},
},
- { "Decode_myxhpq",
+ { "_myxhpq",
{12},
- { {"0", "Visit_udot_asimdelem_d"},
- {"1", "Visit_sqrdmlsh_asimdelem_r"},
+ { {"0"_b, "udot_asimdelem_d"},
+ {"1"_b, "sqrdmlsh_asimdelem_r"},
},
},
- { "Decode_mzhsrq",
+ { "_mzhsrq",
{4},
- { {"0", "Visit_cmplt_p_p_zi"},
- {"1", "Visit_cmple_p_p_zi"},
+ { {"0"_b, "cmplt_p_p_zi"},
+ {"1"_b, "cmple_p_p_zi"},
},
},
- { "Decode_mzqzhq",
+ { "_mzqzhq",
{23, 22, 20, 19, 11},
- { {"00000", "Visit_mvni_asimdimm_m_sm"},
+ { {"00000"_b, "mvni_asimdimm_m_sm"},
},
},
- { "Decode_mzynlp",
+ { "_mzynlp",
{23, 22, 13},
- { {"100", "Visit_fmlal2_asimdelem_lh"},
- {"xx1", "Visit_umull_asimdelem_l"},
+ { {"100"_b, "fmlal2_asimdelem_lh"},
+ {"xx1"_b, "umull_asimdelem_l"},
},
},
- { "Decode_ngttyj",
+ { "_ngttyj",
{30, 23, 22, 13},
- { {"0000", "Visit_ld1b_z_p_br_u16"},
- {"0001", "Visit_ldff1b_z_p_br_u16"},
- {"0010", "Visit_ld1b_z_p_br_u64"},
- {"0011", "Visit_ldff1b_z_p_br_u64"},
- {"0100", "Visit_ld1h_z_p_br_u16"},
- {"0101", "Visit_ldff1h_z_p_br_u16"},
- {"0110", "Visit_ld1h_z_p_br_u64"},
- {"0111", "Visit_ldff1h_z_p_br_u64"},
- {"1001", "Visit_st2b_z_p_br_contiguous"},
- {"1011", "Visit_st4b_z_p_br_contiguous"},
- {"10x0", "Visit_st1b_z_p_br"},
- {"1101", "Visit_st2h_z_p_br_contiguous"},
- {"1111", "Visit_st4h_z_p_br_contiguous"},
- {"11x0", "Visit_st1h_z_p_br"},
+ { {"0000"_b, "ld1b_z_p_br_u16"},
+ {"0001"_b, "ldff1b_z_p_br_u16"},
+ {"0010"_b, "ld1b_z_p_br_u64"},
+ {"0011"_b, "ldff1b_z_p_br_u64"},
+ {"0100"_b, "ld1h_z_p_br_u16"},
+ {"0101"_b, "ldff1h_z_p_br_u16"},
+ {"0110"_b, "ld1h_z_p_br_u64"},
+ {"0111"_b, "ldff1h_z_p_br_u64"},
+ {"1001"_b, "st2b_z_p_br_contiguous"},
+ {"1011"_b, "st4b_z_p_br_contiguous"},
+ {"10x0"_b, "st1b_z_p_br"},
+ {"1101"_b, "st2h_z_p_br_contiguous"},
+ {"1111"_b, "st4h_z_p_br_contiguous"},
+ {"11x0"_b, "st1h_z_p_br"},
},
},
- { "Decode_ngxkmp",
+ { "_ngxkmp",
{18, 17},
- { {"0x", "Visit_st3_asisdlsep_r3_r"},
- {"10", "Visit_st3_asisdlsep_r3_r"},
- {"11", "Visit_st3_asisdlsep_i3_i"},
+ { {"0x"_b, "st3_asisdlsep_r3_r"},
+ {"10"_b, "st3_asisdlsep_r3_r"},
+ {"11"_b, "st3_asisdlsep_i3_i"},
},
},
- { "Decode_ngzyqj",
+ { "_ngzyqj",
{11, 10},
- { {"00", "Visit_asr_z_zi"},
- {"01", "Visit_lsr_z_zi"},
- {"11", "Visit_lsl_z_zi"},
+ { {"00"_b, "asr_z_zi"},
+ {"01"_b, "lsr_z_zi"},
+ {"11"_b, "lsl_z_zi"},
},
},
- { "Decode_nhhpqz",
+ { "_nhhpqz",
{23, 22, 13, 12},
- { {"0000", "Visit_fmul_s_floatdp2"},
- {"0001", "Visit_fdiv_s_floatdp2"},
- {"0010", "Visit_fadd_s_floatdp2"},
- {"0011", "Visit_fsub_s_floatdp2"},
- {"0100", "Visit_fmul_d_floatdp2"},
- {"0101", "Visit_fdiv_d_floatdp2"},
- {"0110", "Visit_fadd_d_floatdp2"},
- {"0111", "Visit_fsub_d_floatdp2"},
- {"1100", "Visit_fmul_h_floatdp2"},
- {"1101", "Visit_fdiv_h_floatdp2"},
- {"1110", "Visit_fadd_h_floatdp2"},
- {"1111", "Visit_fsub_h_floatdp2"},
+ { {"0000"_b, "fmul_s_floatdp2"},
+ {"0001"_b, "fdiv_s_floatdp2"},
+ {"0010"_b, "fadd_s_floatdp2"},
+ {"0011"_b, "fsub_s_floatdp2"},
+ {"0100"_b, "fmul_d_floatdp2"},
+ {"0101"_b, "fdiv_d_floatdp2"},
+ {"0110"_b, "fadd_d_floatdp2"},
+ {"0111"_b, "fsub_d_floatdp2"},
+ {"1100"_b, "fmul_h_floatdp2"},
+ {"1101"_b, "fdiv_h_floatdp2"},
+ {"1110"_b, "fadd_h_floatdp2"},
+ {"1111"_b, "fsub_h_floatdp2"},
},
},
- { "Decode_nhkstj",
+ { "_nhkstj",
{30, 23, 22},
- { {"00x", "Visit_add_64_addsub_shift"},
- {"010", "Visit_add_64_addsub_shift"},
- {"10x", "Visit_sub_64_addsub_shift"},
- {"110", "Visit_sub_64_addsub_shift"},
+ { {"00x"_b, "add_64_addsub_shift"},
+ {"010"_b, "add_64_addsub_shift"},
+ {"10x"_b, "sub_64_addsub_shift"},
+ {"110"_b, "sub_64_addsub_shift"},
},
},
- { "Decode_nhxxmh",
+ { "_nhxxmh",
{23, 22, 9, 3, 2, 1, 0},
- { {"0100000", "Visit_ptest_p_p"},
+ { {"0100000"_b, "ptest_p_p"},
},
},
- { "Decode_nhzrqr",
+ { "_nhzrqr",
{23, 22},
- { {"00", "Visit_fmadd_s_floatdp3"},
- {"01", "Visit_fmadd_d_floatdp3"},
- {"11", "Visit_fmadd_h_floatdp3"},
+ { {"00"_b, "fmadd_s_floatdp3"},
+ {"01"_b, "fmadd_d_floatdp3"},
+ {"11"_b, "fmadd_h_floatdp3"},
},
},
- { "Decode_nhzyvv",
+ { "_nhzyvv",
{23, 22, 4, 3, 2, 1, 0},
- { {"0000000", "Visit_brk_ex_exception"},
- {"0100000", "Visit_tcancel_ex_exception"},
- {"1000001", "Visit_dcps1_dc_exception"},
- {"1000010", "Visit_dcps2_dc_exception"},
- {"1000011", "Visit_dcps3_dc_exception"},
+ { {"0000000"_b, "brk_ex_exception"},
+ {"0100000"_b, "tcancel_ex_exception"},
+ {"1000001"_b, "dcps1_dc_exception"},
+ {"1000010"_b, "dcps2_dc_exception"},
+ {"1000011"_b, "dcps3_dc_exception"},
},
},
- { "Decode_njgmvx",
+ { "_njgmvx",
{18, 17},
- { {"00", "Decode_rzqzlq"},
+ { {"00"_b, "_rzqzlq"},
},
},
- { "Decode_njgxlz",
+ { "_njgxlz",
{30},
- { {"0", "Decode_txzxzs"},
- {"1", "Decode_vprkpq"},
+ { {"0"_b, "_txzxzs"},
+ {"1"_b, "_vprkpq"},
},
},
- { "Decode_njngkk",
+ { "_njngkk",
{23, 22, 9, 8, 7, 6, 5},
- { {"0000000", "Visit_rdffr_p_f"},
+ { {"0000000"_b, "rdffr_p_f"},
},
},
- { "Decode_njtngm",
+ { "_njtngm",
{13, 12, 10},
- { {"001", "Decode_qkzlkj"},
- {"010", "Decode_jvpqrp"},
- {"011", "Decode_kknjng"},
- {"101", "Decode_xmtlmj"},
- {"110", "Visit_sqdmlal_asisdelem_l"},
- {"111", "Decode_zgjpym"},
+ { {"001"_b, "_qkzlkj"},
+ {"010"_b, "_jvpqrp"},
+ {"011"_b, "_kknjng"},
+ {"101"_b, "_xmtlmj"},
+ {"110"_b, "sqdmlal_asisdelem_l"},
+ {"111"_b, "_zgjpym"},
},
},
- { "Decode_njvkjq",
+ { "_njvkjq",
{11, 10},
- { {"00", "Visit_index_z_ii"},
- {"01", "Visit_index_z_ri"},
- {"10", "Visit_index_z_ir"},
- {"11", "Visit_index_z_rr"},
+ { {"00"_b, "index_z_ii"},
+ {"01"_b, "index_z_ri"},
+ {"10"_b, "index_z_ir"},
+ {"11"_b, "index_z_rr"},
},
},
- { "Decode_njxtpv",
+ { "_njxtpv",
{30, 23, 22, 11, 10, 4},
- { {"001000", "Visit_ccmn_32_condcmp_reg"},
- {"001100", "Visit_ccmn_32_condcmp_imm"},
- {"101000", "Visit_ccmp_32_condcmp_reg"},
- {"101100", "Visit_ccmp_32_condcmp_imm"},
+ { {"001000"_b, "ccmn_32_condcmp_reg"},
+ {"001100"_b, "ccmn_32_condcmp_imm"},
+ {"101000"_b, "ccmp_32_condcmp_reg"},
+ {"101100"_b, "ccmp_32_condcmp_imm"},
},
},
- { "Decode_nkjgpq",
+ { "_nkjgpq",
{23, 20, 19, 18, 17, 16, 13},
- { {"0000000", "Visit_ld1r_asisdlso_r1"},
- {"0000001", "Visit_ld3r_asisdlso_r3"},
- {"10xxxx0", "Visit_ld1r_asisdlsop_rx1_r"},
- {"10xxxx1", "Visit_ld3r_asisdlsop_rx3_r"},
- {"110xxx0", "Visit_ld1r_asisdlsop_rx1_r"},
- {"110xxx1", "Visit_ld3r_asisdlsop_rx3_r"},
- {"1110xx0", "Visit_ld1r_asisdlsop_rx1_r"},
- {"1110xx1", "Visit_ld3r_asisdlsop_rx3_r"},
- {"11110x0", "Visit_ld1r_asisdlsop_rx1_r"},
- {"11110x1", "Visit_ld3r_asisdlsop_rx3_r"},
- {"1111100", "Visit_ld1r_asisdlsop_rx1_r"},
- {"1111101", "Visit_ld3r_asisdlsop_rx3_r"},
- {"1111110", "Visit_ld1r_asisdlsop_r1_i"},
- {"1111111", "Visit_ld3r_asisdlsop_r3_i"},
+ { {"0000000"_b, "ld1r_asisdlso_r1"},
+ {"0000001"_b, "ld3r_asisdlso_r3"},
+ {"10xxxx0"_b, "ld1r_asisdlsop_rx1_r"},
+ {"10xxxx1"_b, "ld3r_asisdlsop_rx3_r"},
+ {"110xxx0"_b, "ld1r_asisdlsop_rx1_r"},
+ {"110xxx1"_b, "ld3r_asisdlsop_rx3_r"},
+ {"1110xx0"_b, "ld1r_asisdlsop_rx1_r"},
+ {"1110xx1"_b, "ld3r_asisdlsop_rx3_r"},
+ {"11110x0"_b, "ld1r_asisdlsop_rx1_r"},
+ {"11110x1"_b, "ld3r_asisdlsop_rx3_r"},
+ {"1111100"_b, "ld1r_asisdlsop_rx1_r"},
+ {"1111101"_b, "ld3r_asisdlsop_rx3_r"},
+ {"1111110"_b, "ld1r_asisdlsop_r1_i"},
+ {"1111111"_b, "ld3r_asisdlsop_r3_i"},
},
},
- { "Decode_nkrqgn",
+ { "_nkrqgn",
{12},
- { {"0", "Visit_ld3_asisdlsop_dx3_r3d"},
+ { {"0"_b, "ld3_asisdlsop_dx3_r3d"},
},
},
- { "Decode_nkxhsy",
+ { "_nkxhsy",
{22, 20, 11},
- { {"000", "Visit_cntb_r_s"},
- {"010", "Visit_incb_r_rs"},
- {"100", "Visit_cnth_r_s"},
- {"110", "Visit_inch_r_rs"},
+ { {"000"_b, "cntb_r_s"},
+ {"010"_b, "incb_r_rs"},
+ {"100"_b, "cnth_r_s"},
+ {"110"_b, "inch_r_rs"},
},
},
- { "Decode_nlgqsk",
+ { "_nlgqsk",
{30, 23, 13, 12, 11, 10},
- { {"100001", "Visit_sri_asisdshf_r"},
- {"100101", "Visit_sli_asisdshf_r"},
- {"101001", "Visit_sqshlu_asisdshf_r"},
- {"101101", "Visit_uqshl_asisdshf_r"},
+ { {"100001"_b, "sri_asisdshf_r"},
+ {"100101"_b, "sli_asisdshf_r"},
+ {"101001"_b, "sqshlu_asisdshf_r"},
+ {"101101"_b, "uqshl_asisdshf_r"},
},
},
- { "Decode_nlkkyx",
+ { "_nlkkyx",
{23, 13, 12},
- { {"001", "Visit_fmulx_asisdsame_only"},
- {"011", "Visit_frecps_asisdsame_only"},
- {"111", "Visit_frsqrts_asisdsame_only"},
+ { {"001"_b, "fmulx_asisdsame_only"},
+ {"011"_b, "frecps_asisdsame_only"},
+ {"111"_b, "frsqrts_asisdsame_only"},
},
},
- { "Decode_nllnsg",
+ { "_nllnsg",
{30, 23, 22, 19, 16},
- { {"10010", "Visit_aesmc_b_cryptoaes"},
- {"x0x01", "Visit_fcvtn_asimdmisc_n"},
- {"x1001", "Visit_bfcvtn_asimdmisc_4s"},
- {"xxx00", "Visit_sadalp_asimdmisc_p"},
+ { {"10010"_b, "aesmc_b_cryptoaes"},
+ {"x0x01"_b, "fcvtn_asimdmisc_n"},
+ {"x1001"_b, "bfcvtn_asimdmisc_4s"},
+ {"xxx00"_b, "sadalp_asimdmisc_p"},
},
},
- { "Decode_nlpmvl",
+ { "_nlpmvl",
{30, 13},
- { {"00", "Visit_mad_z_p_zzz"},
- {"01", "Visit_msb_z_p_zzz"},
+ { {"00"_b, "mad_z_p_zzz"},
+ {"01"_b, "msb_z_p_zzz"},
},
},
- { "Decode_nlqglq",
+ { "_nlqglq",
{13, 10},
- { {"00", "Decode_lxvnxm"},
- {"01", "Decode_mzqzhq"},
- {"10", "Decode_myxhpq"},
- {"11", "Decode_pslllp"},
+ { {"00"_b, "_lxvnxm"},
+ {"01"_b, "_mzqzhq"},
+ {"10"_b, "_myxhpq"},
+ {"11"_b, "_pslllp"},
},
},
- { "Decode_nlyntn",
+ { "_nlyntn",
{23, 22, 20, 19, 11},
- { {"00000", "Visit_movi_asimdimm_l_sl"},
+ { {"00000"_b, "movi_asimdimm_l_sl"},
},
},
- { "Decode_nmkqzt",
+ { "_nmkqzt",
{20, 19, 18, 17},
- { {"0000", "Decode_nvqlyn"},
+ { {"0000"_b, "_nvqlyn"},
},
},
- { "Decode_nmtkjv",
+ { "_nmtkjv",
{17},
- { {"0", "Visit_ld1_asisdlso_h1_1h"},
+ { {"0"_b, "ld1_asisdlso_h1_1h"},
},
},
- { "Decode_nmzyvt",
+ { "_nmzyvt",
{30, 23, 22, 13, 12, 11, 10},
- { {"0000000", "Visit_ldsmaxb_32_memop"},
- {"0000100", "Visit_ldsminb_32_memop"},
- {"0000x10", "Visit_strb_32b_ldst_regoff"},
- {"0001000", "Visit_ldumaxb_32_memop"},
- {"0001100", "Visit_lduminb_32_memop"},
- {"0001x10", "Visit_strb_32bl_ldst_regoff"},
- {"0010000", "Visit_ldsmaxlb_32_memop"},
- {"0010100", "Visit_ldsminlb_32_memop"},
- {"0010x10", "Visit_ldrb_32b_ldst_regoff"},
- {"0011000", "Visit_ldumaxlb_32_memop"},
- {"0011100", "Visit_lduminlb_32_memop"},
- {"0011x10", "Visit_ldrb_32bl_ldst_regoff"},
- {"0100000", "Visit_ldsmaxab_32_memop"},
- {"0100100", "Visit_ldsminab_32_memop"},
- {"0100x10", "Visit_ldrsb_64b_ldst_regoff"},
- {"0101000", "Visit_ldumaxab_32_memop"},
- {"0101100", "Visit_lduminab_32_memop"},
- {"0101x10", "Visit_ldrsb_64bl_ldst_regoff"},
- {"0110000", "Visit_ldsmaxalb_32_memop"},
- {"0110100", "Visit_ldsminalb_32_memop"},
- {"0110x10", "Visit_ldrsb_32b_ldst_regoff"},
- {"0111000", "Visit_ldumaxalb_32_memop"},
- {"0111100", "Visit_lduminalb_32_memop"},
- {"0111x10", "Visit_ldrsb_32bl_ldst_regoff"},
- {"1000000", "Visit_ldsmaxh_32_memop"},
- {"1000100", "Visit_ldsminh_32_memop"},
- {"1001000", "Visit_ldumaxh_32_memop"},
- {"1001100", "Visit_lduminh_32_memop"},
- {"100xx10", "Visit_strh_32_ldst_regoff"},
- {"1010000", "Visit_ldsmaxlh_32_memop"},
- {"1010100", "Visit_ldsminlh_32_memop"},
- {"1011000", "Visit_ldumaxlh_32_memop"},
- {"1011100", "Visit_lduminlh_32_memop"},
- {"101xx10", "Visit_ldrh_32_ldst_regoff"},
- {"1100000", "Visit_ldsmaxah_32_memop"},
- {"1100100", "Visit_ldsminah_32_memop"},
- {"1101000", "Visit_ldumaxah_32_memop"},
- {"1101100", "Visit_lduminah_32_memop"},
- {"110xx10", "Visit_ldrsh_64_ldst_regoff"},
- {"1110000", "Visit_ldsmaxalh_32_memop"},
- {"1110100", "Visit_ldsminalh_32_memop"},
- {"1111000", "Visit_ldumaxalh_32_memop"},
- {"1111100", "Visit_lduminalh_32_memop"},
- {"111xx10", "Visit_ldrsh_32_ldst_regoff"},
+ { {"0000000"_b, "ldsmaxb_32_memop"},
+ {"0000100"_b, "ldsminb_32_memop"},
+ {"0000x10"_b, "strb_32b_ldst_regoff"},
+ {"0001000"_b, "ldumaxb_32_memop"},
+ {"0001100"_b, "lduminb_32_memop"},
+ {"0001x10"_b, "strb_32bl_ldst_regoff"},
+ {"0010000"_b, "ldsmaxlb_32_memop"},
+ {"0010100"_b, "ldsminlb_32_memop"},
+ {"0010x10"_b, "ldrb_32b_ldst_regoff"},
+ {"0011000"_b, "ldumaxlb_32_memop"},
+ {"0011100"_b, "lduminlb_32_memop"},
+ {"0011x10"_b, "ldrb_32bl_ldst_regoff"},
+ {"0100000"_b, "ldsmaxab_32_memop"},
+ {"0100100"_b, "ldsminab_32_memop"},
+ {"0100x10"_b, "ldrsb_64b_ldst_regoff"},
+ {"0101000"_b, "ldumaxab_32_memop"},
+ {"0101100"_b, "lduminab_32_memop"},
+ {"0101x10"_b, "ldrsb_64bl_ldst_regoff"},
+ {"0110000"_b, "ldsmaxalb_32_memop"},
+ {"0110100"_b, "ldsminalb_32_memop"},
+ {"0110x10"_b, "ldrsb_32b_ldst_regoff"},
+ {"0111000"_b, "ldumaxalb_32_memop"},
+ {"0111100"_b, "lduminalb_32_memop"},
+ {"0111x10"_b, "ldrsb_32bl_ldst_regoff"},
+ {"1000000"_b, "ldsmaxh_32_memop"},
+ {"1000100"_b, "ldsminh_32_memop"},
+ {"1001000"_b, "ldumaxh_32_memop"},
+ {"1001100"_b, "lduminh_32_memop"},
+ {"100xx10"_b, "strh_32_ldst_regoff"},
+ {"1010000"_b, "ldsmaxlh_32_memop"},
+ {"1010100"_b, "ldsminlh_32_memop"},
+ {"1011000"_b, "ldumaxlh_32_memop"},
+ {"1011100"_b, "lduminlh_32_memop"},
+ {"101xx10"_b, "ldrh_32_ldst_regoff"},
+ {"1100000"_b, "ldsmaxah_32_memop"},
+ {"1100100"_b, "ldsminah_32_memop"},
+ {"1101000"_b, "ldumaxah_32_memop"},
+ {"1101100"_b, "lduminah_32_memop"},
+ {"110xx10"_b, "ldrsh_64_ldst_regoff"},
+ {"1110000"_b, "ldsmaxalh_32_memop"},
+ {"1110100"_b, "ldsminalh_32_memop"},
+ {"1111000"_b, "ldumaxalh_32_memop"},
+ {"1111100"_b, "lduminalh_32_memop"},
+ {"111xx10"_b, "ldrsh_32_ldst_regoff"},
},
},
- { "Decode_nnhprs",
+ { "_nnhprs",
{1, 0},
- { {"00", "Visit_ret_64r_branch_reg"},
+ { {"00"_b, "ret_64r_branch_reg"},
},
},
- { "Decode_nnkxgr",
+ { "_nnkxgr",
{11, 10},
- { {"00", "Visit_ftssel_z_zz"},
- {"10", "Decode_yhlntp"},
- {"11", "Decode_rsqmgk"},
+ { {"00"_b, "ftssel_z_zz"},
+ {"10"_b, "_yhlntp"},
+ {"11"_b, "_rsqmgk"},
},
},
- { "Decode_nnkyzr",
+ { "_nnkyzr",
{18, 17, 16},
- { {"011", "Decode_yvgqjx"},
+ { {"011"_b, "_yvgqjx"},
},
},
- { "Decode_nnllqy",
+ { "_nnllqy",
{18, 17},
- { {"00", "Visit_ld1_asisdlso_s1_1s"},
+ { {"00"_b, "ld1_asisdlso_s1_1s"},
},
},
- { "Decode_nnlvqz",
+ { "_nnlvqz",
{9, 8, 7, 6, 5},
- { {"00000", "Visit_fmov_d_floatimm"},
+ { {"00000"_b, "fmov_d_floatimm"},
},
},
- { "Decode_nnzhgm",
+ { "_nnzhgm",
{19, 18, 17, 16, 4},
- { {"0000x", "Visit_brka_p_p_p"},
- {"10000", "Visit_brkn_p_p_pp"},
+ { {"0000x"_b, "brka_p_p_p"},
+ {"10000"_b, "brkn_p_p_pp"},
},
},
- { "Decode_nqgqjh",
+ { "_nqgqjh",
{30, 23, 22, 20, 19},
- { {"0xxxx", "Visit_bl_only_branch_imm"},
- {"10001", "Visit_sys_cr_systeminstrs"},
- {"1001x", "Visit_msr_sr_systemmove"},
+ { {"0xxxx"_b, "bl_only_branch_imm"},
+ {"10001"_b, "sys_cr_systeminstrs"},
+ {"1001x"_b, "msr_sr_systemmove"},
},
},
- { "Decode_nqkhrv",
+ { "_nqkhrv",
{30, 13},
- { {"10", "Visit_fnmla_z_p_zzz"},
- {"11", "Visit_fnmls_z_p_zzz"},
+ { {"10"_b, "fnmla_z_p_zzz"},
+ {"11"_b, "fnmls_z_p_zzz"},
},
},
- { "Decode_nqlgtn",
+ { "_nqlgtn",
{23, 20, 19, 18, 17, 16, 13},
- { {"0000000", "Visit_ld2r_asisdlso_r2"},
- {"0000001", "Visit_ld4r_asisdlso_r4"},
- {"10xxxx0", "Visit_ld2r_asisdlsop_rx2_r"},
- {"10xxxx1", "Visit_ld4r_asisdlsop_rx4_r"},
- {"110xxx0", "Visit_ld2r_asisdlsop_rx2_r"},
- {"110xxx1", "Visit_ld4r_asisdlsop_rx4_r"},
- {"1110xx0", "Visit_ld2r_asisdlsop_rx2_r"},
- {"1110xx1", "Visit_ld4r_asisdlsop_rx4_r"},
- {"11110x0", "Visit_ld2r_asisdlsop_rx2_r"},
- {"11110x1", "Visit_ld4r_asisdlsop_rx4_r"},
- {"1111100", "Visit_ld2r_asisdlsop_rx2_r"},
- {"1111101", "Visit_ld4r_asisdlsop_rx4_r"},
- {"1111110", "Visit_ld2r_asisdlsop_r2_i"},
- {"1111111", "Visit_ld4r_asisdlsop_r4_i"},
+ { {"0000000"_b, "ld2r_asisdlso_r2"},
+ {"0000001"_b, "ld4r_asisdlso_r4"},
+ {"10xxxx0"_b, "ld2r_asisdlsop_rx2_r"},
+ {"10xxxx1"_b, "ld4r_asisdlsop_rx4_r"},
+ {"110xxx0"_b, "ld2r_asisdlsop_rx2_r"},
+ {"110xxx1"_b, "ld4r_asisdlsop_rx4_r"},
+ {"1110xx0"_b, "ld2r_asisdlsop_rx2_r"},
+ {"1110xx1"_b, "ld4r_asisdlsop_rx4_r"},
+ {"11110x0"_b, "ld2r_asisdlsop_rx2_r"},
+ {"11110x1"_b, "ld4r_asisdlsop_rx4_r"},
+ {"1111100"_b, "ld2r_asisdlsop_rx2_r"},
+ {"1111101"_b, "ld4r_asisdlsop_rx4_r"},
+ {"1111110"_b, "ld2r_asisdlsop_r2_i"},
+ {"1111111"_b, "ld4r_asisdlsop_r4_i"},
},
},
- { "Decode_nqysxy",
+ { "_nqysxy",
{0},
- { {"1", "Visit_blraaz_64_branch_reg"},
+ { {"1"_b, "blraaz_64_branch_reg"},
},
},
- { "Decode_nrrmtx",
+ { "_nrrmtx",
{22, 13, 12},
- { {"000", "Visit_swpa_64_memop"},
- {"100", "Visit_swpal_64_memop"},
+ { {"000"_b, "swpa_64_memop"},
+ {"100"_b, "swpal_64_memop"},
},
},
- { "Decode_nrssjz",
+ { "_nrssjz",
{17},
- { {"0", "Visit_ld3_asisdlso_b3_3b"},
+ { {"0"_b, "ld3_asisdlso_b3_3b"},
},
},
- { "Decode_nshjhk",
+ { "_nshjhk",
{17, 9, 8, 7, 6, 5},
- { {"000000", "Visit_aesimc_z_z"},
- {"1xxxxx", "Visit_aesd_z_zz"},
+ { {"000000"_b, "aesimc_z_z"},
+ {"1xxxxx"_b, "aesd_z_zz"},
},
},
- { "Decode_nsjhhg",
+ { "_nsjhhg",
{30, 13},
- { {"00", "Decode_jhllmn"},
- {"01", "Decode_htplsj"},
- {"10", "Decode_rztvnl"},
- {"11", "Decode_vgtnjh"},
+ { {"00"_b, "_jhllmn"},
+ {"01"_b, "_htplsj"},
+ {"10"_b, "_rztvnl"},
+ {"11"_b, "_vgtnjh"},
},
},
- { "Decode_nsnyxt",
+ { "_nsnyxt",
{23},
- { {"0", "Visit_fmla_asimdsame_only"},
- {"1", "Visit_fmls_asimdsame_only"},
+ { {"0"_b, "fmla_asimdsame_only"},
+ {"1"_b, "fmls_asimdsame_only"},
},
},
- { "Decode_nssrnm",
+ { "_nssrnm",
{20, 18, 17, 16},
- { {"0000", "Decode_lnpvky"},
+ { {"0000"_b, "_lnpvky"},
},
},
- { "Decode_nszhhy",
+ { "_nszhhy",
{17},
- { {"0", "Visit_ld2_asisdlsep_r2_r"},
- {"1", "Visit_ld2_asisdlsep_i2_i"},
+ { {"0"_b, "ld2_asisdlsep_r2_r"},
+ {"1"_b, "ld2_asisdlsep_i2_i"},
},
},
- { "Decode_nthvqx",
+ { "_nthvqx",
{23, 22},
- { {"00", "Visit_eor_asimdsame_only"},
- {"01", "Visit_bsl_asimdsame_only"},
- {"10", "Visit_bit_asimdsame_only"},
- {"11", "Visit_bif_asimdsame_only"},
+ { {"00"_b, "eor_asimdsame_only"},
+ {"01"_b, "bsl_asimdsame_only"},
+ {"10"_b, "bit_asimdsame_only"},
+ {"11"_b, "bif_asimdsame_only"},
},
},
- { "Decode_ntjpsx",
+ { "_ntjpsx",
{22, 20, 11},
- { {"000", "Visit_uqincb_r_rs_uw"},
- {"001", "Visit_uqdecb_r_rs_uw"},
- {"010", "Visit_uqincb_r_rs_x"},
- {"011", "Visit_uqdecb_r_rs_x"},
- {"100", "Visit_uqinch_r_rs_uw"},
- {"101", "Visit_uqdech_r_rs_uw"},
- {"110", "Visit_uqinch_r_rs_x"},
- {"111", "Visit_uqdech_r_rs_x"},
+ { {"000"_b, "uqincb_r_rs_uw"},
+ {"001"_b, "uqdecb_r_rs_uw"},
+ {"010"_b, "uqincb_r_rs_x"},
+ {"011"_b, "uqdecb_r_rs_x"},
+ {"100"_b, "uqinch_r_rs_uw"},
+ {"101"_b, "uqdech_r_rs_uw"},
+ {"110"_b, "uqinch_r_rs_x"},
+ {"111"_b, "uqdech_r_rs_x"},
},
},
- { "Decode_ntkhsm",
+ { "_ntkhsm",
{13, 12},
- { {"00", "Visit_cmtst_asisdsame_only"},
+ { {"00"_b, "cmtst_asisdsame_only"},
},
},
- { "Decode_ntkqhk",
+ { "_ntkqhk",
{11, 10, 9, 8, 7, 6},
- { {"000000", "Visit_yield_hi_hints"},
- {"000001", "Visit_wfi_hi_hints"},
- {"000010", "Visit_sevl_hi_hints"},
- {"000011", "Visit_xpaclri_hi_hints"},
- {"001000", "Visit_psb_hc_hints"},
- {"0010x1", "Visit_hint_hm_hints"},
- {"001100", "Visit_paciasp_hi_hints"},
- {"001101", "Visit_pacibsp_hi_hints"},
- {"001110", "Visit_autiasp_hi_hints"},
- {"001111", "Visit_autibsp_hi_hints"},
- {"0x01xx", "Visit_hint_hm_hints"},
- {"0x1010", "Visit_hint_hm_hints"},
- {"10x0xx", "Visit_hint_hm_hints"},
- {"10x1xx", "Visit_hint_hm_hints"},
- {"1101xx", "Visit_hint_hm_hints"},
- {"111010", "Visit_hint_hm_hints"},
- {"x100xx", "Visit_hint_hm_hints"},
- {"x1100x", "Visit_hint_hm_hints"},
- {"x11011", "Visit_hint_hm_hints"},
- {"x111xx", "Visit_hint_hm_hints"},
+ { {"000000"_b, "yield_hi_hints"},
+ {"000001"_b, "wfi_hi_hints"},
+ {"000010"_b, "sevl_hi_hints"},
+ {"000011"_b, "xpaclri_hi_hints"},
+ {"001000"_b, "psb_hc_hints"},
+ {"0010x1"_b, "hint_hm_hints"},
+ {"001100"_b, "paciasp_hi_hints"},
+ {"001101"_b, "pacibsp_hi_hints"},
+ {"001110"_b, "autiasp_hi_hints"},
+ {"001111"_b, "autibsp_hi_hints"},
+ {"0x01xx"_b, "hint_hm_hints"},
+ {"0x1010"_b, "hint_hm_hints"},
+ {"10x0xx"_b, "hint_hm_hints"},
+ {"10x1xx"_b, "hint_hm_hints"},
+ {"1101xx"_b, "hint_hm_hints"},
+ {"111010"_b, "hint_hm_hints"},
+ {"x100xx"_b, "hint_hm_hints"},
+ {"x1100x"_b, "hint_hm_hints"},
+ {"x11011"_b, "hint_hm_hints"},
+ {"x111xx"_b, "hint_hm_hints"},
},
},
- { "Decode_nvkthr",
+ { "_nvkthr",
{30, 13},
- { {"00", "Decode_kjqynn"},
- {"01", "Decode_jgyhrh"},
- {"10", "Decode_jymnkk"},
- {"11", "Decode_pqjjsh"},
+ { {"00"_b, "_kjqynn"},
+ {"01"_b, "_jgyhrh"},
+ {"10"_b, "_jymnkk"},
+ {"11"_b, "_pqjjsh"},
},
},
- { "Decode_nvqlyn",
+ { "_nvqlyn",
{16, 13, 12},
- { {"000", "Visit_rev_64_dp_1src"},
- {"100", "Visit_pacdb_64p_dp_1src"},
- {"101", "Visit_autdb_64p_dp_1src"},
- {"110", "Decode_hhnjjk"},
- {"111", "Decode_yvnjkr"},
+ { {"000"_b, "rev_64_dp_1src"},
+ {"100"_b, "pacdb_64p_dp_1src"},
+ {"101"_b, "autdb_64p_dp_1src"},
+ {"110"_b, "_hhnjjk"},
+ {"111"_b, "_yvnjkr"},
},
},
- { "Decode_nvthzh",
+ { "_nvthzh",
{20, 19, 18, 17, 16, 13, 12, 9, 8, 7, 6, 5},
- { {"000010011111", "Visit_xpacd_64z_dp_1src"},
+ { {"000010011111"_b, "xpacd_64z_dp_1src"},
},
},
- { "Decode_nvyxmh",
+ { "_nvyxmh",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_add_z_p_zz"},
- {"00001", "Visit_sub_z_p_zz"},
- {"00011", "Visit_subr_z_p_zz"},
- {"01000", "Visit_smax_z_p_zz"},
- {"01001", "Visit_umax_z_p_zz"},
- {"01010", "Visit_smin_z_p_zz"},
- {"01011", "Visit_umin_z_p_zz"},
- {"01100", "Visit_sabd_z_p_zz"},
- {"01101", "Visit_uabd_z_p_zz"},
- {"10000", "Visit_mul_z_p_zz"},
- {"10010", "Visit_smulh_z_p_zz"},
- {"10011", "Visit_umulh_z_p_zz"},
- {"10100", "Visit_sdiv_z_p_zz"},
- {"10101", "Visit_udiv_z_p_zz"},
- {"10110", "Visit_sdivr_z_p_zz"},
- {"10111", "Visit_udivr_z_p_zz"},
- {"11000", "Visit_orr_z_p_zz"},
- {"11001", "Visit_eor_z_p_zz"},
- {"11010", "Visit_and_z_p_zz"},
- {"11011", "Visit_bic_z_p_zz"},
+ { {"00000"_b, "add_z_p_zz"},
+ {"00001"_b, "sub_z_p_zz"},
+ {"00011"_b, "subr_z_p_zz"},
+ {"01000"_b, "smax_z_p_zz"},
+ {"01001"_b, "umax_z_p_zz"},
+ {"01010"_b, "smin_z_p_zz"},
+ {"01011"_b, "umin_z_p_zz"},
+ {"01100"_b, "sabd_z_p_zz"},
+ {"01101"_b, "uabd_z_p_zz"},
+ {"10000"_b, "mul_z_p_zz"},
+ {"10010"_b, "smulh_z_p_zz"},
+ {"10011"_b, "umulh_z_p_zz"},
+ {"10100"_b, "sdiv_z_p_zz"},
+ {"10101"_b, "udiv_z_p_zz"},
+ {"10110"_b, "sdivr_z_p_zz"},
+ {"10111"_b, "udivr_z_p_zz"},
+ {"11000"_b, "orr_z_p_zz"},
+ {"11001"_b, "eor_z_p_zz"},
+ {"11010"_b, "and_z_p_zz"},
+ {"11011"_b, "bic_z_p_zz"},
},
},
- { "Decode_nxjgmm",
+ { "_nxjgmm",
{17},
- { {"0", "Visit_st3_asisdlsop_bx3_r3b"},
- {"1", "Visit_st3_asisdlsop_b3_i3b"},
+ { {"0"_b, "st3_asisdlsop_bx3_r3b"},
+ {"1"_b, "st3_asisdlsop_b3_i3b"},
},
},
- { "Decode_nxjkqs",
+ { "_nxjkqs",
{23, 22, 12, 11, 10},
- { {"0x000", "Visit_fmla_z_zzzi_h"},
- {"0x001", "Visit_fmls_z_zzzi_h"},
- {"10000", "Visit_fmla_z_zzzi_s"},
- {"10001", "Visit_fmls_z_zzzi_s"},
- {"101xx", "Visit_fcmla_z_zzzi_h"},
- {"11000", "Visit_fmla_z_zzzi_d"},
- {"11001", "Visit_fmls_z_zzzi_d"},
- {"111xx", "Visit_fcmla_z_zzzi_s"},
+ { {"0x000"_b, "fmla_z_zzzi_h"},
+ {"0x001"_b, "fmls_z_zzzi_h"},
+ {"10000"_b, "fmla_z_zzzi_s"},
+ {"10001"_b, "fmls_z_zzzi_s"},
+ {"101xx"_b, "fcmla_z_zzzi_h"},
+ {"11000"_b, "fmla_z_zzzi_d"},
+ {"11001"_b, "fmls_z_zzzi_d"},
+ {"111xx"_b, "fcmla_z_zzzi_s"},
},
},
- { "Decode_nxmjvy",
+ { "_nxmjvy",
{30, 23, 11, 10},
- { {"1001", "Decode_jksztq"},
+ { {"1001"_b, "_jksztq"},
},
},
- { "Decode_nxqygl",
+ { "_nxqygl",
{13},
- { {"0", "Visit_mla_asimdelem_r"},
- {"1", "Visit_umlal_asimdelem_l"},
+ { {"0"_b, "mla_asimdelem_r"},
+ {"1"_b, "umlal_asimdelem_l"},
},
},
- { "Decode_nxyhyv",
+ { "_nxyhyv",
{30, 11, 10},
- { {"000", "Decode_kvyysq"},
- {"001", "Decode_rvjzgt"},
- {"010", "Decode_vjlnqj"},
- {"011", "Decode_jvvzjq"},
- {"100", "Decode_tzzhsk"},
- {"101", "Decode_mplskr"},
- {"110", "Decode_njgmvx"},
- {"111", "Decode_ntkhsm"},
+ { {"000"_b, "_kvyysq"},
+ {"001"_b, "_rvjzgt"},
+ {"010"_b, "_vjlnqj"},
+ {"011"_b, "_jvvzjq"},
+ {"100"_b, "_tzzhsk"},
+ {"101"_b, "_mplskr"},
+ {"110"_b, "_njgmvx"},
+ {"111"_b, "_ntkhsm"},
},
},
- { "Decode_nykvly",
+ { "_nykvly",
{16, 13, 12},
- { {"000", "Visit_rev32_64_dp_1src"},
- {"100", "Visit_pacda_64p_dp_1src"},
- {"101", "Visit_autda_64p_dp_1src"},
- {"110", "Decode_mgqvvn"},
- {"111", "Decode_xvlnmy"},
+ { {"000"_b, "rev32_64_dp_1src"},
+ {"100"_b, "pacda_64p_dp_1src"},
+ {"101"_b, "autda_64p_dp_1src"},
+ {"110"_b, "_mgqvvn"},
+ {"111"_b, "_xvlnmy"},
},
},
- { "Decode_nyssqn",
+ { "_nyssqn",
{12},
- { {"0", "Visit_st2_asisdlsop_dx2_r2d"},
+ { {"0"_b, "st2_asisdlsop_dx2_r2d"},
},
},
- { "Decode_nyxxks",
+ { "_nyxxks",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_suqadd_asimdmisc_r"},
- {"10000", "Visit_saddlv_asimdall_only"},
+ { {"00000"_b, "suqadd_asimdmisc_r"},
+ {"10000"_b, "saddlv_asimdall_only"},
},
},
- { "Decode_nzkhrj",
+ { "_nzkhrj",
{17},
- { {"0", "Visit_st4_asisdlsep_r4_r"},
- {"1", "Visit_st4_asisdlsep_i4_i"},
+ { {"0"_b, "st4_asisdlsep_r4_r"},
+ {"1"_b, "st4_asisdlsep_i4_i"},
},
},
- { "Decode_nzqkky",
+ { "_nzqkky",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_rev32_asimdmisc_r"},
+ { {"00000"_b, "rev32_asimdmisc_r"},
},
},
- { "Decode_pgjjsz",
+ { "_pgjjsz",
{30, 13, 12, 11, 10},
- { {"00000", "Decode_lmyxhr"},
- {"00001", "Decode_tmhlvh"},
- {"00010", "Decode_qvtxpr"},
- {"00011", "Decode_ymkthj"},
- {"00100", "Decode_rhmxyp"},
- {"00101", "Decode_zryvjk"},
- {"01000", "Visit_zip1_z_zz"},
- {"01001", "Visit_zip2_z_zz"},
- {"01010", "Visit_uzp1_z_zz"},
- {"01011", "Visit_uzp2_z_zz"},
- {"01100", "Visit_trn1_z_zz"},
- {"01101", "Visit_trn2_z_zz"},
- {"10000", "Decode_llvrrk"},
- {"10001", "Decode_qyjvqr"},
- {"10010", "Decode_tmtnkq"},
- {"10011", "Decode_gpxltv"},
- {"10100", "Decode_pnlnzt"},
- {"10101", "Decode_pygvrr"},
- {"11000", "Visit_addhnb_z_zz"},
- {"11001", "Visit_addhnt_z_zz"},
- {"11010", "Visit_raddhnb_z_zz"},
- {"11011", "Visit_raddhnt_z_zz"},
- {"11100", "Visit_subhnb_z_zz"},
- {"11101", "Visit_subhnt_z_zz"},
- {"11110", "Visit_rsubhnb_z_zz"},
- {"11111", "Visit_rsubhnt_z_zz"},
+ { {"00000"_b, "_lmyxhr"},
+ {"00001"_b, "_tmhlvh"},
+ {"00010"_b, "_qvtxpr"},
+ {"00011"_b, "_ymkthj"},
+ {"00100"_b, "_rhmxyp"},
+ {"00101"_b, "_zryvjk"},
+ {"01000"_b, "zip1_z_zz"},
+ {"01001"_b, "zip2_z_zz"},
+ {"01010"_b, "uzp1_z_zz"},
+ {"01011"_b, "uzp2_z_zz"},
+ {"01100"_b, "trn1_z_zz"},
+ {"01101"_b, "trn2_z_zz"},
+ {"10000"_b, "_llvrrk"},
+ {"10001"_b, "_qyjvqr"},
+ {"10010"_b, "_tmtnkq"},
+ {"10011"_b, "_gpxltv"},
+ {"10100"_b, "_pnlnzt"},
+ {"10101"_b, "_pygvrr"},
+ {"11000"_b, "addhnb_z_zz"},
+ {"11001"_b, "addhnt_z_zz"},
+ {"11010"_b, "raddhnb_z_zz"},
+ {"11011"_b, "raddhnt_z_zz"},
+ {"11100"_b, "subhnb_z_zz"},
+ {"11101"_b, "subhnt_z_zz"},
+ {"11110"_b, "rsubhnb_z_zz"},
+ {"11111"_b, "rsubhnt_z_zz"},
},
},
- { "Decode_phthqj",
+ { "_phthqj",
{30, 13},
- { {"00", "Decode_sntyqy"},
- {"01", "Decode_xhlhmh"},
- {"10", "Decode_rtrlts"},
- {"11", "Decode_jzkqhn"},
+ { {"00"_b, "_sntyqy"},
+ {"01"_b, "_xhlhmh"},
+ {"10"_b, "_rtrlts"},
+ {"11"_b, "_jzkqhn"},
},
},
- { "Decode_phtnny",
+ { "_phtnny",
{18, 17},
- { {"0x", "Visit_ld1_asisdlsep_r3_r3"},
- {"10", "Visit_ld1_asisdlsep_r3_r3"},
- {"11", "Visit_ld1_asisdlsep_i3_i3"},
+ { {"0x"_b, "ld1_asisdlsep_r3_r3"},
+ {"10"_b, "ld1_asisdlsep_r3_r3"},
+ {"11"_b, "ld1_asisdlsep_i3_i3"},
},
},
- { "Decode_phvnqh",
+ { "_phvnqh",
{30},
- { {"0", "Visit_bic_32_log_shift"},
- {"1", "Visit_eon_32_log_shift"},
+ { {"0"_b, "bic_32_log_shift"},
+ {"1"_b, "eon_32_log_shift"},
},
},
- { "Decode_phxkzh",
+ { "_phxkzh",
{17, 4},
- { {"00", "Visit_fcmlt_p_p_z0"},
- {"01", "Visit_fcmle_p_p_z0"},
- {"10", "Visit_fcmne_p_p_z0"},
+ { {"00"_b, "fcmlt_p_p_z0"},
+ {"01"_b, "fcmle_p_p_z0"},
+ {"10"_b, "fcmne_p_p_z0"},
},
},
- { "Decode_pjgkjs",
+ { "_pjgkjs",
{18, 17},
- { {"00", "Decode_mxnzyr"},
+ { {"00"_b, "_mxnzyr"},
},
},
- { "Decode_pjkylt",
+ { "_pjkylt",
{23, 22},
- { {"00", "Visit_fcsel_s_floatsel"},
- {"01", "Visit_fcsel_d_floatsel"},
- {"11", "Visit_fcsel_h_floatsel"},
+ { {"00"_b, "fcsel_s_floatsel"},
+ {"01"_b, "fcsel_d_floatsel"},
+ {"11"_b, "fcsel_h_floatsel"},
},
},
- { "Decode_plktrh",
+ { "_plktrh",
{30, 23},
- { {"00", "Visit_adds_32s_addsub_imm"},
- {"10", "Visit_subs_32s_addsub_imm"},
+ { {"00"_b, "adds_32s_addsub_imm"},
+ {"10"_b, "subs_32s_addsub_imm"},
},
},
- { "Decode_plltlx",
+ { "_plltlx",
{23},
- { {"0", "Visit_fadd_asimdsame_only"},
- {"1", "Visit_fsub_asimdsame_only"},
+ { {"0"_b, "fadd_asimdsame_only"},
+ {"1"_b, "fsub_asimdsame_only"},
},
},
- { "Decode_pmkxlj",
+ { "_pmkxlj",
{17},
- { {"0", "Visit_st1_asisdlse_r2_2v"},
+ { {"0"_b, "st1_asisdlse_r2_2v"},
},
},
- { "Decode_pmrngh",
+ { "_pmrngh",
{30},
- { {"0", "Visit_bl_only_branch_imm"},
- {"1", "Decode_snkqvp"},
+ { {"0"_b, "bl_only_branch_imm"},
+ {"1"_b, "_snkqvp"},
},
},
- { "Decode_pnlnzt",
+ { "_pnlnzt",
{23, 18, 17, 16},
- { {"0000", "Visit_sqxtunb_z_zz"},
+ { {"0000"_b, "sqxtunb_z_zz"},
},
},
- { "Decode_pnqxjg",
+ { "_pnqxjg",
{4},
- { {"0", "Visit_ccmn_32_condcmp_reg"},
+ { {"0"_b, "ccmn_32_condcmp_reg"},
},
},
- { "Decode_pnxggm",
+ { "_pnxggm",
{4, 3, 2, 1, 0},
- { {"00000", "Visit_fcmp_d_floatcmp"},
- {"01000", "Visit_fcmp_dz_floatcmp"},
- {"10000", "Visit_fcmpe_d_floatcmp"},
- {"11000", "Visit_fcmpe_dz_floatcmp"},
+ { {"00000"_b, "fcmp_d_floatcmp"},
+ {"01000"_b, "fcmp_dz_floatcmp"},
+ {"10000"_b, "fcmpe_d_floatcmp"},
+ {"11000"_b, "fcmpe_dz_floatcmp"},
},
},
- { "Decode_pnxgrg",
+ { "_pnxgrg",
{30, 23, 22},
- { {"000", "Visit_madd_32a_dp_3src"},
+ { {"000"_b, "madd_32a_dp_3src"},
},
},
- { "Decode_pnzphx",
+ { "_pnzphx",
{17},
- { {"1", "Visit_frecpe_z_z"},
+ { {"1"_b, "frecpe_z_z"},
},
},
- { "Decode_pphhym",
+ { "_pphhym",
{30, 23, 22},
- { {"00x", "Visit_add_32_addsub_shift"},
- {"010", "Visit_add_32_addsub_shift"},
- {"10x", "Visit_sub_32_addsub_shift"},
- {"110", "Visit_sub_32_addsub_shift"},
+ { {"00x"_b, "add_32_addsub_shift"},
+ {"010"_b, "add_32_addsub_shift"},
+ {"10x"_b, "sub_32_addsub_shift"},
+ {"110"_b, "sub_32_addsub_shift"},
},
},
- { "Decode_ppllxt",
+ { "_ppllxt",
{18, 17},
- { {"00", "Visit_ld1_asisdlse_r3_3v"},
+ { {"00"_b, "ld1_asisdlse_r3_3v"},
},
},
- { "Decode_ppnssm",
+ { "_ppnssm",
{30, 13, 12},
- { {"000", "Decode_ktyppm"},
- {"001", "Decode_ngzyqj"},
- {"010", "Decode_yxnslx"},
- {"011", "Decode_nnkxgr"},
- {"100", "Decode_kzmvpk"},
- {"101", "Decode_thrxph"},
- {"110", "Decode_kgpgly"},
- {"111", "Decode_yppszx"},
+ { {"000"_b, "_ktyppm"},
+ {"001"_b, "_ngzyqj"},
+ {"010"_b, "_yxnslx"},
+ {"011"_b, "_nnkxgr"},
+ {"100"_b, "_kzmvpk"},
+ {"101"_b, "_thrxph"},
+ {"110"_b, "_kgpgly"},
+ {"111"_b, "_yppszx"},
},
},
- { "Decode_pppsmg",
+ { "_pppsmg",
{30},
- { {"0", "Decode_xyhmgh"},
- {"1", "Decode_rlrjxp"},
+ { {"0"_b, "_xyhmgh"},
+ {"1"_b, "_rlrjxp"},
},
},
- { "Decode_ppqkym",
+ { "_ppqkym",
{30, 23, 22, 11, 10},
- { {"10001", "Visit_stg_64spost_ldsttags"},
- {"10010", "Visit_stg_64soffset_ldsttags"},
- {"10011", "Visit_stg_64spre_ldsttags"},
- {"10100", "Visit_ldg_64loffset_ldsttags"},
- {"10101", "Visit_stzg_64spost_ldsttags"},
- {"10110", "Visit_stzg_64soffset_ldsttags"},
- {"10111", "Visit_stzg_64spre_ldsttags"},
- {"11001", "Visit_st2g_64spost_ldsttags"},
- {"11010", "Visit_st2g_64soffset_ldsttags"},
- {"11011", "Visit_st2g_64spre_ldsttags"},
- {"11101", "Visit_stz2g_64spost_ldsttags"},
- {"11110", "Visit_stz2g_64soffset_ldsttags"},
- {"11111", "Visit_stz2g_64spre_ldsttags"},
+ { {"10001"_b, "stg_64spost_ldsttags"},
+ {"10010"_b, "stg_64soffset_ldsttags"},
+ {"10011"_b, "stg_64spre_ldsttags"},
+ {"10100"_b, "ldg_64loffset_ldsttags"},
+ {"10101"_b, "stzg_64spost_ldsttags"},
+ {"10110"_b, "stzg_64soffset_ldsttags"},
+ {"10111"_b, "stzg_64spre_ldsttags"},
+ {"11001"_b, "st2g_64spost_ldsttags"},
+ {"11010"_b, "st2g_64soffset_ldsttags"},
+ {"11011"_b, "st2g_64spre_ldsttags"},
+ {"11101"_b, "stz2g_64spost_ldsttags"},
+ {"11110"_b, "stz2g_64soffset_ldsttags"},
+ {"11111"_b, "stz2g_64spre_ldsttags"},
},
},
- { "Decode_pqjjsh",
+ { "_pqjjsh",
{23, 22, 12, 10},
- { {"1000", "Visit_fmlslb_z_zzzi_s"},
- {"1001", "Visit_fmlslt_z_zzzi_s"},
+ { {"1000"_b, "fmlslb_z_zzzi_s"},
+ {"1001"_b, "fmlslt_z_zzzi_s"},
},
},
- { "Decode_pqpzkt",
+ { "_pqpzkt",
{11, 10, 9, 8, 7, 6},
- { {"000000", "Visit_nop_hi_hints"},
- {"000001", "Visit_wfe_hi_hints"},
- {"000010", "Visit_sev_hi_hints"},
- {"000011", "Visit_dgh_hi_hints"},
- {"000100", "Visit_pacia1716_hi_hints"},
- {"000101", "Visit_pacib1716_hi_hints"},
- {"000110", "Visit_autia1716_hi_hints"},
- {"000111", "Visit_autib1716_hi_hints"},
- {"001000", "Visit_esb_hi_hints"},
- {"001001", "Visit_tsb_hc_hints"},
- {"001010", "Visit_csdb_hi_hints"},
- {"001100", "Visit_paciaz_hi_hints"},
- {"001101", "Visit_pacibz_hi_hints"},
- {"001110", "Visit_autiaz_hi_hints"},
- {"001111", "Visit_autibz_hi_hints"},
- {"0100xx", "Visit_bti_hb_hints"},
- {"0x1011", "Visit_hint_hm_hints"},
- {"10x0xx", "Visit_hint_hm_hints"},
- {"10x1xx", "Visit_hint_hm_hints"},
- {"1100xx", "Visit_hint_hm_hints"},
- {"111011", "Visit_hint_hm_hints"},
- {"x1100x", "Visit_hint_hm_hints"},
- {"x11010", "Visit_hint_hm_hints"},
- {"x1x1xx", "Visit_hint_hm_hints"},
+ { {"000000"_b, "nop_hi_hints"},
+ {"000001"_b, "wfe_hi_hints"},
+ {"000010"_b, "sev_hi_hints"},
+ {"000011"_b, "dgh_hi_hints"},
+ {"000100"_b, "pacia1716_hi_hints"},
+ {"000101"_b, "pacib1716_hi_hints"},
+ {"000110"_b, "autia1716_hi_hints"},
+ {"000111"_b, "autib1716_hi_hints"},
+ {"001000"_b, "esb_hi_hints"},
+ {"001001"_b, "tsb_hc_hints"},
+ {"001010"_b, "csdb_hi_hints"},
+ {"001100"_b, "paciaz_hi_hints"},
+ {"001101"_b, "pacibz_hi_hints"},
+ {"001110"_b, "autiaz_hi_hints"},
+ {"001111"_b, "autibz_hi_hints"},
+ {"0100xx"_b, "bti_hb_hints"},
+ {"0x1011"_b, "hint_hm_hints"},
+ {"10x0xx"_b, "hint_hm_hints"},
+ {"10x1xx"_b, "hint_hm_hints"},
+ {"1100xx"_b, "hint_hm_hints"},
+ {"111011"_b, "hint_hm_hints"},
+ {"x1100x"_b, "hint_hm_hints"},
+ {"x11010"_b, "hint_hm_hints"},
+ {"x1x1xx"_b, "hint_hm_hints"},
},
},
- { "Decode_pqtjgx",
+ { "_pqtjgx",
{23, 22, 13, 12, 11, 10},
- { {"01x1x0", "Visit_fcmla_asimdelem_c_h"},
- {"0x0001", "Visit_sri_asimdshf_r"},
- {"0x0101", "Visit_sli_asimdshf_r"},
- {"0x1001", "Visit_sqshlu_asimdshf_r"},
- {"0x1101", "Visit_uqshl_asimdshf_r"},
- {"10x1x0", "Visit_fcmla_asimdelem_c_s"},
- {"xx00x0", "Visit_mls_asimdelem_r"},
- {"xx10x0", "Visit_umlsl_asimdelem_l"},
+ { {"01x1x0"_b, "fcmla_asimdelem_c_h"},
+ {"0x0001"_b, "sri_asimdshf_r"},
+ {"0x0101"_b, "sli_asimdshf_r"},
+ {"0x1001"_b, "sqshlu_asimdshf_r"},
+ {"0x1101"_b, "uqshl_asimdshf_r"},
+ {"10x1x0"_b, "fcmla_asimdelem_c_s"},
+ {"xx00x0"_b, "mls_asimdelem_r"},
+ {"xx10x0"_b, "umlsl_asimdelem_l"},
},
},
- { "Decode_prkmty",
+ { "_prkmty",
{23, 22, 9},
- { {"000", "Visit_brkpa_p_p_pp"},
- {"010", "Visit_brkpas_p_p_pp"},
+ { {"000"_b, "brkpa_p_p_pp"},
+ {"010"_b, "brkpas_p_p_pp"},
},
},
- { "Decode_pslllp",
+ { "_pslllp",
{30, 23, 22, 20, 19, 12, 11},
- { {"0000000", "Visit_movi_asimdimm_d_ds"},
- {"1000000", "Visit_movi_asimdimm_d2_d"},
- {"1000010", "Visit_fmov_asimdimm_d2_d"},
- {"x00x100", "Visit_ucvtf_asimdshf_c"},
- {"x00x111", "Visit_fcvtzu_asimdshf_c"},
- {"x010x00", "Visit_ucvtf_asimdshf_c"},
- {"x010x11", "Visit_fcvtzu_asimdshf_c"},
- {"x011100", "Visit_ucvtf_asimdshf_c"},
- {"x011111", "Visit_fcvtzu_asimdshf_c"},
- {"x0x1000", "Visit_ucvtf_asimdshf_c"},
- {"x0x1011", "Visit_fcvtzu_asimdshf_c"},
+ { {"0000000"_b, "movi_asimdimm_d_ds"},
+ {"1000000"_b, "movi_asimdimm_d2_d"},
+ {"1000010"_b, "fmov_asimdimm_d2_d"},
+ {"x00x100"_b, "ucvtf_asimdshf_c"},
+ {"x00x111"_b, "fcvtzu_asimdshf_c"},
+ {"x010x00"_b, "ucvtf_asimdshf_c"},
+ {"x010x11"_b, "fcvtzu_asimdshf_c"},
+ {"x011100"_b, "ucvtf_asimdshf_c"},
+ {"x011111"_b, "fcvtzu_asimdshf_c"},
+ {"x0x1000"_b, "ucvtf_asimdshf_c"},
+ {"x0x1011"_b, "fcvtzu_asimdshf_c"},
},
},
- { "Decode_psqpkp",
+ { "_psqpkp",
{17, 4},
- { {"00", "Visit_fcmge_p_p_z0"},
- {"01", "Visit_fcmgt_p_p_z0"},
- {"10", "Visit_fcmeq_p_p_z0"},
+ { {"00"_b, "fcmge_p_p_z0"},
+ {"01"_b, "fcmgt_p_p_z0"},
+ {"10"_b, "fcmeq_p_p_z0"},
},
},
- { "Decode_ptjyqx",
+ { "_ptjyqx",
{13},
- { {"0", "Visit_fcmuo_p_p_zz"},
+ { {"0"_b, "fcmuo_p_p_zz"},
},
},
- { "Decode_ptkrvg",
+ { "_ptkrvg",
{12},
- { {"0", "Visit_ld2_asisdlsop_dx2_r2d"},
+ { {"0"_b, "ld2_asisdlsop_dx2_r2d"},
},
},
- { "Decode_ptsjnr",
+ { "_ptsjnr",
{30, 20, 19, 18, 17, 16, 13},
- { {"0000000", "Visit_asr_z_p_zi"},
- {"0000010", "Visit_lsr_z_p_zi"},
- {"0000110", "Visit_lsl_z_p_zi"},
- {"0001000", "Visit_asrd_z_p_zi"},
- {"0001100", "Visit_sqshl_z_p_zi"},
- {"0001110", "Visit_uqshl_z_p_zi"},
- {"0011000", "Visit_srshr_z_p_zi"},
- {"0011010", "Visit_urshr_z_p_zi"},
- {"0011110", "Visit_sqshlu_z_p_zi"},
- {"0100000", "Visit_asr_z_p_zz"},
- {"0100001", "Visit_sxtb_z_p_z"},
- {"0100010", "Visit_lsr_z_p_zz"},
- {"0100011", "Visit_uxtb_z_p_z"},
- {"0100101", "Visit_sxth_z_p_z"},
- {"0100110", "Visit_lsl_z_p_zz"},
- {"0100111", "Visit_uxth_z_p_z"},
- {"0101000", "Visit_asrr_z_p_zz"},
- {"0101001", "Visit_sxtw_z_p_z"},
- {"0101010", "Visit_lsrr_z_p_zz"},
- {"0101011", "Visit_uxtw_z_p_z"},
- {"0101101", "Visit_abs_z_p_z"},
- {"0101110", "Visit_lslr_z_p_zz"},
- {"0101111", "Visit_neg_z_p_z"},
- {"0110000", "Visit_asr_z_p_zw"},
- {"0110001", "Visit_cls_z_p_z"},
- {"0110010", "Visit_lsr_z_p_zw"},
- {"0110011", "Visit_clz_z_p_z"},
- {"0110101", "Visit_cnt_z_p_z"},
- {"0110110", "Visit_lsl_z_p_zw"},
- {"0110111", "Visit_cnot_z_p_z"},
- {"0111001", "Visit_fabs_z_p_z"},
- {"0111011", "Visit_fneg_z_p_z"},
- {"0111101", "Visit_not_z_p_z"},
- {"1000001", "Visit_urecpe_z_p_z"},
- {"1000011", "Visit_ursqrte_z_p_z"},
- {"1000100", "Visit_srshl_z_p_zz"},
- {"1000110", "Visit_urshl_z_p_zz"},
- {"1001001", "Visit_sadalp_z_p_z"},
- {"1001011", "Visit_uadalp_z_p_z"},
- {"1001100", "Visit_srshlr_z_p_zz"},
- {"1001110", "Visit_urshlr_z_p_zz"},
- {"1010000", "Visit_sqshl_z_p_zz"},
- {"1010001", "Visit_sqabs_z_p_z"},
- {"1010010", "Visit_uqshl_z_p_zz"},
- {"1010011", "Visit_sqneg_z_p_z"},
- {"1010100", "Visit_sqrshl_z_p_zz"},
- {"1010110", "Visit_uqrshl_z_p_zz"},
- {"1011000", "Visit_sqshlr_z_p_zz"},
- {"1011010", "Visit_uqshlr_z_p_zz"},
- {"1011100", "Visit_sqrshlr_z_p_zz"},
- {"1011110", "Visit_uqrshlr_z_p_zz"},
- {"1100000", "Visit_shadd_z_p_zz"},
- {"1100010", "Visit_uhadd_z_p_zz"},
- {"1100011", "Visit_addp_z_p_zz"},
- {"1100100", "Visit_shsub_z_p_zz"},
- {"1100110", "Visit_uhsub_z_p_zz"},
- {"1101000", "Visit_srhadd_z_p_zz"},
- {"1101001", "Visit_smaxp_z_p_zz"},
- {"1101010", "Visit_urhadd_z_p_zz"},
- {"1101011", "Visit_umaxp_z_p_zz"},
- {"1101100", "Visit_shsubr_z_p_zz"},
- {"1101101", "Visit_sminp_z_p_zz"},
- {"1101110", "Visit_uhsubr_z_p_zz"},
- {"1101111", "Visit_uminp_z_p_zz"},
- {"1110000", "Visit_sqadd_z_p_zz"},
- {"1110010", "Visit_uqadd_z_p_zz"},
- {"1110100", "Visit_sqsub_z_p_zz"},
- {"1110110", "Visit_uqsub_z_p_zz"},
- {"1111000", "Visit_suqadd_z_p_zz"},
- {"1111010", "Visit_usqadd_z_p_zz"},
- {"1111100", "Visit_sqsubr_z_p_zz"},
- {"1111110", "Visit_uqsubr_z_p_zz"},
+ { {"0000000"_b, "asr_z_p_zi"},
+ {"0000010"_b, "lsr_z_p_zi"},
+ {"0000110"_b, "lsl_z_p_zi"},
+ {"0001000"_b, "asrd_z_p_zi"},
+ {"0001100"_b, "sqshl_z_p_zi"},
+ {"0001110"_b, "uqshl_z_p_zi"},
+ {"0011000"_b, "srshr_z_p_zi"},
+ {"0011010"_b, "urshr_z_p_zi"},
+ {"0011110"_b, "sqshlu_z_p_zi"},
+ {"0100000"_b, "asr_z_p_zz"},
+ {"0100001"_b, "sxtb_z_p_z"},
+ {"0100010"_b, "lsr_z_p_zz"},
+ {"0100011"_b, "uxtb_z_p_z"},
+ {"0100101"_b, "sxth_z_p_z"},
+ {"0100110"_b, "lsl_z_p_zz"},
+ {"0100111"_b, "uxth_z_p_z"},
+ {"0101000"_b, "asrr_z_p_zz"},
+ {"0101001"_b, "sxtw_z_p_z"},
+ {"0101010"_b, "lsrr_z_p_zz"},
+ {"0101011"_b, "uxtw_z_p_z"},
+ {"0101101"_b, "abs_z_p_z"},
+ {"0101110"_b, "lslr_z_p_zz"},
+ {"0101111"_b, "neg_z_p_z"},
+ {"0110000"_b, "asr_z_p_zw"},
+ {"0110001"_b, "cls_z_p_z"},
+ {"0110010"_b, "lsr_z_p_zw"},
+ {"0110011"_b, "clz_z_p_z"},
+ {"0110101"_b, "cnt_z_p_z"},
+ {"0110110"_b, "lsl_z_p_zw"},
+ {"0110111"_b, "cnot_z_p_z"},
+ {"0111001"_b, "fabs_z_p_z"},
+ {"0111011"_b, "fneg_z_p_z"},
+ {"0111101"_b, "not_z_p_z"},
+ {"1000001"_b, "urecpe_z_p_z"},
+ {"1000011"_b, "ursqrte_z_p_z"},
+ {"1000100"_b, "srshl_z_p_zz"},
+ {"1000110"_b, "urshl_z_p_zz"},
+ {"1001001"_b, "sadalp_z_p_z"},
+ {"1001011"_b, "uadalp_z_p_z"},
+ {"1001100"_b, "srshlr_z_p_zz"},
+ {"1001110"_b, "urshlr_z_p_zz"},
+ {"1010000"_b, "sqshl_z_p_zz"},
+ {"1010001"_b, "sqabs_z_p_z"},
+ {"1010010"_b, "uqshl_z_p_zz"},
+ {"1010011"_b, "sqneg_z_p_z"},
+ {"1010100"_b, "sqrshl_z_p_zz"},
+ {"1010110"_b, "uqrshl_z_p_zz"},
+ {"1011000"_b, "sqshlr_z_p_zz"},
+ {"1011010"_b, "uqshlr_z_p_zz"},
+ {"1011100"_b, "sqrshlr_z_p_zz"},
+ {"1011110"_b, "uqrshlr_z_p_zz"},
+ {"1100000"_b, "shadd_z_p_zz"},
+ {"1100010"_b, "uhadd_z_p_zz"},
+ {"1100011"_b, "addp_z_p_zz"},
+ {"1100100"_b, "shsub_z_p_zz"},
+ {"1100110"_b, "uhsub_z_p_zz"},
+ {"1101000"_b, "srhadd_z_p_zz"},
+ {"1101001"_b, "smaxp_z_p_zz"},
+ {"1101010"_b, "urhadd_z_p_zz"},
+ {"1101011"_b, "umaxp_z_p_zz"},
+ {"1101100"_b, "shsubr_z_p_zz"},
+ {"1101101"_b, "sminp_z_p_zz"},
+ {"1101110"_b, "uhsubr_z_p_zz"},
+ {"1101111"_b, "uminp_z_p_zz"},
+ {"1110000"_b, "sqadd_z_p_zz"},
+ {"1110010"_b, "uqadd_z_p_zz"},
+ {"1110100"_b, "sqsub_z_p_zz"},
+ {"1110110"_b, "uqsub_z_p_zz"},
+ {"1111000"_b, "suqadd_z_p_zz"},
+ {"1111010"_b, "usqadd_z_p_zz"},
+ {"1111100"_b, "sqsubr_z_p_zz"},
+ {"1111110"_b, "uqsubr_z_p_zz"},
},
},
- { "Decode_ptslzg",
+ { "_ptslzg",
{30, 23, 22, 13, 4},
- { {"01000", "Visit_ldr_p_bi"},
- {"01100", "Visit_prfb_i_p_bi_s"},
- {"01110", "Visit_prfh_i_p_bi_s"},
- {"10x0x", "Visit_ld1sw_z_p_bz_d_x32_scaled"},
- {"10x1x", "Visit_ldff1sw_z_p_bz_d_x32_scaled"},
+ { {"01000"_b, "ldr_p_bi"},
+ {"01100"_b, "prfb_i_p_bi_s"},
+ {"01110"_b, "prfh_i_p_bi_s"},
+ {"10x0x"_b, "ld1sw_z_p_bz_d_x32_scaled"},
+ {"10x1x"_b, "ldff1sw_z_p_bz_d_x32_scaled"},
},
},
- { "Decode_pvkmmv",
+ { "_pvkmmv",
{30, 23, 22, 13, 12, 11, 10},
- { {"0000000", "Visit_ldsmax_32_memop"},
- {"0000100", "Visit_ldsmin_32_memop"},
- {"0001000", "Visit_ldumax_32_memop"},
- {"0001100", "Visit_ldumin_32_memop"},
- {"000xx10", "Visit_str_32_ldst_regoff"},
- {"0010000", "Visit_ldsmaxl_32_memop"},
- {"0010100", "Visit_ldsminl_32_memop"},
- {"0011000", "Visit_ldumaxl_32_memop"},
- {"0011100", "Visit_lduminl_32_memop"},
- {"001xx10", "Visit_ldr_32_ldst_regoff"},
- {"0100000", "Visit_ldsmaxa_32_memop"},
- {"0100100", "Visit_ldsmina_32_memop"},
- {"0101000", "Visit_ldumaxa_32_memop"},
- {"0101100", "Visit_ldumina_32_memop"},
- {"010xx10", "Visit_ldrsw_64_ldst_regoff"},
- {"0110000", "Visit_ldsmaxal_32_memop"},
- {"0110100", "Visit_ldsminal_32_memop"},
- {"0111000", "Visit_ldumaxal_32_memop"},
- {"0111100", "Visit_lduminal_32_memop"},
- {"1000000", "Visit_ldsmax_64_memop"},
- {"1000100", "Visit_ldsmin_64_memop"},
- {"1001000", "Visit_ldumax_64_memop"},
- {"1001100", "Visit_ldumin_64_memop"},
- {"100xx10", "Visit_str_64_ldst_regoff"},
- {"1010000", "Visit_ldsmaxl_64_memop"},
- {"1010100", "Visit_ldsminl_64_memop"},
- {"1011000", "Visit_ldumaxl_64_memop"},
- {"1011100", "Visit_lduminl_64_memop"},
- {"101xx10", "Visit_ldr_64_ldst_regoff"},
- {"10xxx01", "Visit_ldraa_64_ldst_pac"},
- {"10xxx11", "Visit_ldraa_64w_ldst_pac"},
- {"1100000", "Visit_ldsmaxa_64_memop"},
- {"1100100", "Visit_ldsmina_64_memop"},
- {"1101000", "Visit_ldumaxa_64_memop"},
- {"1101100", "Visit_ldumina_64_memop"},
- {"110xx10", "Visit_prfm_p_ldst_regoff"},
- {"1110000", "Visit_ldsmaxal_64_memop"},
- {"1110100", "Visit_ldsminal_64_memop"},
- {"1111000", "Visit_ldumaxal_64_memop"},
- {"1111100", "Visit_lduminal_64_memop"},
- {"11xxx01", "Visit_ldrab_64_ldst_pac"},
- {"11xxx11", "Visit_ldrab_64w_ldst_pac"},
+ { {"0000000"_b, "ldsmax_32_memop"},
+ {"0000100"_b, "ldsmin_32_memop"},
+ {"0001000"_b, "ldumax_32_memop"},
+ {"0001100"_b, "ldumin_32_memop"},
+ {"000xx10"_b, "str_32_ldst_regoff"},
+ {"0010000"_b, "ldsmaxl_32_memop"},
+ {"0010100"_b, "ldsminl_32_memop"},
+ {"0011000"_b, "ldumaxl_32_memop"},
+ {"0011100"_b, "lduminl_32_memop"},
+ {"001xx10"_b, "ldr_32_ldst_regoff"},
+ {"0100000"_b, "ldsmaxa_32_memop"},
+ {"0100100"_b, "ldsmina_32_memop"},
+ {"0101000"_b, "ldumaxa_32_memop"},
+ {"0101100"_b, "ldumina_32_memop"},
+ {"010xx10"_b, "ldrsw_64_ldst_regoff"},
+ {"0110000"_b, "ldsmaxal_32_memop"},
+ {"0110100"_b, "ldsminal_32_memop"},
+ {"0111000"_b, "ldumaxal_32_memop"},
+ {"0111100"_b, "lduminal_32_memop"},
+ {"1000000"_b, "ldsmax_64_memop"},
+ {"1000100"_b, "ldsmin_64_memop"},
+ {"1001000"_b, "ldumax_64_memop"},
+ {"1001100"_b, "ldumin_64_memop"},
+ {"100xx10"_b, "str_64_ldst_regoff"},
+ {"1010000"_b, "ldsmaxl_64_memop"},
+ {"1010100"_b, "ldsminl_64_memop"},
+ {"1011000"_b, "ldumaxl_64_memop"},
+ {"1011100"_b, "lduminl_64_memop"},
+ {"101xx10"_b, "ldr_64_ldst_regoff"},
+ {"10xxx01"_b, "ldraa_64_ldst_pac"},
+ {"10xxx11"_b, "ldraa_64w_ldst_pac"},
+ {"1100000"_b, "ldsmaxa_64_memop"},
+ {"1100100"_b, "ldsmina_64_memop"},
+ {"1101000"_b, "ldumaxa_64_memop"},
+ {"1101100"_b, "ldumina_64_memop"},
+ {"110xx10"_b, "prfm_p_ldst_regoff"},
+ {"1110000"_b, "ldsmaxal_64_memop"},
+ {"1110100"_b, "ldsminal_64_memop"},
+ {"1111000"_b, "ldumaxal_64_memop"},
+ {"1111100"_b, "lduminal_64_memop"},
+ {"11xxx01"_b, "ldrab_64_ldst_pac"},
+ {"11xxx11"_b, "ldrab_64w_ldst_pac"},
},
},
- { "Decode_pvrylp",
+ { "_pvrylp",
{13, 12},
- { {"00", "Visit_sbc_64_addsub_carry"},
+ { {"00"_b, "sbc_64_addsub_carry"},
},
},
- { "Decode_pxgztg",
+ { "_pxgztg",
{23, 22, 20, 19, 13, 11},
- { {"0000x0", "Visit_bic_asimdimm_l_sl"},
- {"00x100", "Visit_sli_asimdshf_r"},
- {"00x110", "Visit_uqshl_asimdshf_r"},
- {"010x00", "Visit_sli_asimdshf_r"},
- {"010x10", "Visit_uqshl_asimdshf_r"},
- {"011100", "Visit_sli_asimdshf_r"},
- {"011110", "Visit_uqshl_asimdshf_r"},
- {"0x1000", "Visit_sli_asimdshf_r"},
- {"0x1010", "Visit_uqshl_asimdshf_r"},
+ { {"0000x0"_b, "bic_asimdimm_l_sl"},
+ {"00x100"_b, "sli_asimdshf_r"},
+ {"00x110"_b, "uqshl_asimdshf_r"},
+ {"010x00"_b, "sli_asimdshf_r"},
+ {"010x10"_b, "uqshl_asimdshf_r"},
+ {"011100"_b, "sli_asimdshf_r"},
+ {"011110"_b, "uqshl_asimdshf_r"},
+ {"0x1000"_b, "sli_asimdshf_r"},
+ {"0x1010"_b, "uqshl_asimdshf_r"},
},
},
- { "Decode_pxkqxn",
+ { "_pxkqxn",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_cmle_asisdmisc_z"},
+ { {"00000"_b, "cmle_asisdmisc_z"},
},
},
- { "Decode_pxlnhs",
+ { "_pxlnhs",
{23, 20, 19, 18, 17, 16},
- { {"000001", "Visit_fcvtxn_asimdmisc_n"},
- {"x00000", "Visit_uadalp_asimdmisc_p"},
+ { {"000001"_b, "fcvtxn_asimdmisc_n"},
+ {"x00000"_b, "uadalp_asimdmisc_p"},
},
},
- { "Decode_pxnnrz",
+ { "_pxnnrz",
{20, 19, 18, 17, 16, 13, 12, 3, 2, 1, 0},
- { {"00000001101", "Visit_setf16_only_setf"},
+ { {"00000001101"_b, "setf16_only_setf"},
},
},
- { "Decode_pxtsvn",
+ { "_pxtsvn",
{20, 19, 18, 17, 16},
- { {"10000", "Visit_fminp_asisdpair_only_sd"},
+ { {"10000"_b, "fminp_asisdpair_only_sd"},
},
},
- { "Decode_pxyrpm",
+ { "_pxyrpm",
{22, 11},
- { {"00", "Visit_sqdmulh_z_zzi_s"},
- {"01", "Visit_mul_z_zzi_s"},
- {"10", "Visit_sqdmulh_z_zzi_d"},
- {"11", "Visit_mul_z_zzi_d"},
+ { {"00"_b, "sqdmulh_z_zzi_s"},
+ {"01"_b, "mul_z_zzi_s"},
+ {"10"_b, "sqdmulh_z_zzi_d"},
+ {"11"_b, "mul_z_zzi_d"},
},
},
- { "Decode_pxzkjy",
+ { "_pxzkjy",
{30},
- { {"1", "Decode_yplktv"},
+ { {"1"_b, "_yplktv"},
},
},
- { "Decode_pygvrr",
+ { "_pygvrr",
{23, 18, 17, 16},
- { {"0000", "Visit_sqxtunt_z_zz"},
+ { {"0000"_b, "sqxtunt_z_zz"},
},
},
- { "Decode_qghmks",
+ { "_qghmks",
{13, 12},
- { {"00", "Visit_subp_64s_dp_2src"},
- {"01", "Visit_irg_64i_dp_2src"},
- {"10", "Visit_lslv_64_dp_2src"},
- {"11", "Visit_pacga_64p_dp_2src"},
+ { {"00"_b, "subp_64s_dp_2src"},
+ {"01"_b, "irg_64i_dp_2src"},
+ {"10"_b, "lslv_64_dp_2src"},
+ {"11"_b, "pacga_64p_dp_2src"},
},
},
- { "Decode_qgmngg",
+ { "_qgmngg",
{30, 23},
- { {"00", "Visit_orr_64_log_imm"},
- {"10", "Visit_ands_64s_log_imm"},
- {"11", "Visit_movk_64_movewide"},
+ { {"00"_b, "orr_64_log_imm"},
+ {"10"_b, "ands_64s_log_imm"},
+ {"11"_b, "movk_64_movewide"},
},
},
- { "Decode_qgryzh",
+ { "_qgryzh",
{18, 17},
- { {"0x", "Visit_st1_asisdlsep_r3_r3"},
- {"10", "Visit_st1_asisdlsep_r3_r3"},
- {"11", "Visit_st1_asisdlsep_i3_i3"},
+ { {"0x"_b, "st1_asisdlsep_r3_r3"},
+ {"10"_b, "st1_asisdlsep_r3_r3"},
+ {"11"_b, "st1_asisdlsep_i3_i3"},
},
},
- { "Decode_qgymsy",
+ { "_qgymsy",
{11},
- { {"0", "Decode_hmsgpj"},
+ { {"0"_b, "_hmsgpj"},
},
},
- { "Decode_qhgtvk",
+ { "_qhgtvk",
{30, 23, 22},
- { {"00x", "Visit_adds_32_addsub_shift"},
- {"010", "Visit_adds_32_addsub_shift"},
- {"10x", "Visit_subs_32_addsub_shift"},
- {"110", "Visit_subs_32_addsub_shift"},
+ { {"00x"_b, "adds_32_addsub_shift"},
+ {"010"_b, "adds_32_addsub_shift"},
+ {"10x"_b, "subs_32_addsub_shift"},
+ {"110"_b, "subs_32_addsub_shift"},
},
},
- { "Decode_qhsplz",
+ { "_qhsplz",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_frintn_asimdmiscfp16_r"},
- {"0x00001", "Visit_frintn_asimdmisc_r"},
- {"1111001", "Visit_frintp_asimdmiscfp16_r"},
- {"1x00001", "Visit_frintp_asimdmisc_r"},
- {"xx00000", "Visit_cmgt_asimdmisc_z"},
+ { {"0111001"_b, "frintn_asimdmiscfp16_r"},
+ {"0x00001"_b, "frintn_asimdmisc_r"},
+ {"1111001"_b, "frintp_asimdmiscfp16_r"},
+ {"1x00001"_b, "frintp_asimdmisc_r"},
+ {"xx00000"_b, "cmgt_asimdmisc_z"},
},
},
- { "Decode_qhtqrj",
+ { "_qhtqrj",
{30, 23, 22},
- { {"000", "Visit_stnp_s_ldstnapair_offs"},
- {"001", "Visit_ldnp_s_ldstnapair_offs"},
- {"010", "Visit_stp_s_ldstpair_post"},
- {"011", "Visit_ldp_s_ldstpair_post"},
- {"100", "Visit_stnp_d_ldstnapair_offs"},
- {"101", "Visit_ldnp_d_ldstnapair_offs"},
- {"110", "Visit_stp_d_ldstpair_post"},
- {"111", "Visit_ldp_d_ldstpair_post"},
+ { {"000"_b, "stnp_s_ldstnapair_offs"},
+ {"001"_b, "ldnp_s_ldstnapair_offs"},
+ {"010"_b, "stp_s_ldstpair_post"},
+ {"011"_b, "ldp_s_ldstpair_post"},
+ {"100"_b, "stnp_d_ldstnapair_offs"},
+ {"101"_b, "ldnp_d_ldstnapair_offs"},
+ {"110"_b, "stp_d_ldstpair_post"},
+ {"111"_b, "ldp_d_ldstpair_post"},
},
},
- { "Decode_qhtrnn",
+ { "_qhtrnn",
{30, 23, 22, 11, 10},
- { {"00000", "Visit_stur_32_ldst_unscaled"},
- {"00001", "Visit_str_32_ldst_immpost"},
- {"00010", "Visit_sttr_32_ldst_unpriv"},
- {"00011", "Visit_str_32_ldst_immpre"},
- {"00100", "Visit_ldur_32_ldst_unscaled"},
- {"00101", "Visit_ldr_32_ldst_immpost"},
- {"00110", "Visit_ldtr_32_ldst_unpriv"},
- {"00111", "Visit_ldr_32_ldst_immpre"},
- {"01000", "Visit_ldursw_64_ldst_unscaled"},
- {"01001", "Visit_ldrsw_64_ldst_immpost"},
- {"01010", "Visit_ldtrsw_64_ldst_unpriv"},
- {"01011", "Visit_ldrsw_64_ldst_immpre"},
- {"10000", "Visit_stur_64_ldst_unscaled"},
- {"10001", "Visit_str_64_ldst_immpost"},
- {"10010", "Visit_sttr_64_ldst_unpriv"},
- {"10011", "Visit_str_64_ldst_immpre"},
- {"10100", "Visit_ldur_64_ldst_unscaled"},
- {"10101", "Visit_ldr_64_ldst_immpost"},
- {"10110", "Visit_ldtr_64_ldst_unpriv"},
- {"10111", "Visit_ldr_64_ldst_immpre"},
- {"11000", "Visit_prfum_p_ldst_unscaled"},
+ { {"00000"_b, "stur_32_ldst_unscaled"},
+ {"00001"_b, "str_32_ldst_immpost"},
+ {"00010"_b, "sttr_32_ldst_unpriv"},
+ {"00011"_b, "str_32_ldst_immpre"},
+ {"00100"_b, "ldur_32_ldst_unscaled"},
+ {"00101"_b, "ldr_32_ldst_immpost"},
+ {"00110"_b, "ldtr_32_ldst_unpriv"},
+ {"00111"_b, "ldr_32_ldst_immpre"},
+ {"01000"_b, "ldursw_64_ldst_unscaled"},
+ {"01001"_b, "ldrsw_64_ldst_immpost"},
+ {"01010"_b, "ldtrsw_64_ldst_unpriv"},
+ {"01011"_b, "ldrsw_64_ldst_immpre"},
+ {"10000"_b, "stur_64_ldst_unscaled"},
+ {"10001"_b, "str_64_ldst_immpost"},
+ {"10010"_b, "sttr_64_ldst_unpriv"},
+ {"10011"_b, "str_64_ldst_immpre"},
+ {"10100"_b, "ldur_64_ldst_unscaled"},
+ {"10101"_b, "ldr_64_ldst_immpost"},
+ {"10110"_b, "ldtr_64_ldst_unpriv"},
+ {"10111"_b, "ldr_64_ldst_immpre"},
+ {"11000"_b, "prfum_p_ldst_unscaled"},
},
},
- { "Decode_qhxzxl",
+ { "_qhxzxl",
{17},
- { {"0", "Visit_ld1_asisdlse_r2_2v"},
+ { {"0"_b, "ld1_asisdlse_r2_2v"},
},
},
- { "Decode_qjyvln",
+ { "_qjyvln",
{20, 19, 18, 17, 16, 13, 12, 9, 8, 7, 6, 5},
- { {"000010011111", "Visit_xpaci_64z_dp_1src"},
+ { {"000010011111"_b, "xpaci_64z_dp_1src"},
},
},
- { "Decode_qkyjhg",
+ { "_qkyjhg",
{30},
- { {"0", "Visit_ldr_32_loadlit"},
- {"1", "Visit_ldr_64_loadlit"},
+ { {"0"_b, "ldr_32_loadlit"},
+ {"1"_b, "ldr_64_loadlit"},
},
},
- { "Decode_qkzlkj",
+ { "_qkzlkj",
{23, 22, 20, 19, 11},
- { {"00010", "Visit_sshr_asisdshf_r"},
- {"001x0", "Visit_sshr_asisdshf_r"},
- {"01xx0", "Visit_sshr_asisdshf_r"},
+ { {"00010"_b, "sshr_asisdshf_r"},
+ {"001x0"_b, "sshr_asisdshf_r"},
+ {"01xx0"_b, "sshr_asisdshf_r"},
},
},
- { "Decode_qljhnp",
+ { "_qljhnp",
{22},
- { {"0", "Visit_sqdmullt_z_zzi_s"},
- {"1", "Visit_sqdmullt_z_zzi_d"},
+ { {"0"_b, "sqdmullt_z_zzi_s"},
+ {"1"_b, "sqdmullt_z_zzi_d"},
},
},
- { "Decode_qlqhzg",
+ { "_qlqhzg",
{20},
- { {"0", "Decode_hzmlps"},
- {"1", "Visit_msr_sr_systemmove"},
+ { {"0"_b, "_hzmlps"},
+ {"1"_b, "msr_sr_systemmove"},
},
},
- { "Decode_qlxksl",
+ { "_qlxksl",
{30},
- { {"0", "Decode_hrxyts"},
- {"1", "Decode_tytvjk"},
+ { {"0"_b, "_hrxyts"},
+ {"1"_b, "_tytvjk"},
},
},
- { "Decode_qmgtyq",
+ { "_qmgtyq",
{17},
- { {"0", "Visit_ld2_asisdlse_r2"},
+ { {"0"_b, "ld2_asisdlse_r2"},
},
},
- { "Decode_qmjqhq",
+ { "_qmjqhq",
{9, 8, 7, 6, 5},
- { {"00000", "Visit_fmov_h_floatimm"},
+ { {"00000"_b, "fmov_h_floatimm"},
},
},
- { "Decode_qmqmpj",
+ { "_qmqmpj",
{12, 10},
- { {"00", "Decode_nxqygl"},
- {"01", "Decode_skglrt"},
- {"10", "Decode_sjlpxn"},
- {"11", "Decode_qzxvsk"},
+ { {"00"_b, "_nxqygl"},
+ {"01"_b, "_skglrt"},
+ {"10"_b, "_sjlpxn"},
+ {"11"_b, "_qzxvsk"},
},
},
- { "Decode_qmrgkn",
+ { "_qmrgkn",
{30},
- { {"0", "Visit_bl_only_branch_imm"},
- {"1", "Decode_hsvgnt"},
+ { {"0"_b, "bl_only_branch_imm"},
+ {"1"_b, "_hsvgnt"},
},
},
- { "Decode_qmzqsy",
+ { "_qmzqsy",
{20, 19, 18, 17},
- { {"0000", "Decode_nykvly"},
+ { {"0000"_b, "_nykvly"},
},
},
- { "Decode_qnprqt",
+ { "_qnprqt",
{4},
- { {"0", "Visit_eor_p_p_pp_z"},
- {"1", "Visit_sel_p_p_pp"},
+ { {"0"_b, "eor_p_p_pp_z"},
+ {"1"_b, "sel_p_p_pp"},
},
},
- { "Decode_qnsxkj",
+ { "_qnsxkj",
{20, 19, 18, 17, 16, 13},
- { {"000000", "Visit_fabs_d_floatdp1"},
- {"000010", "Visit_fsqrt_d_floatdp1"},
- {"000110", "Visit_fcvt_hd_floatdp1"},
- {"001000", "Visit_frintp_d_floatdp1"},
- {"001010", "Visit_frintz_d_floatdp1"},
- {"001110", "Visit_frinti_d_floatdp1"},
- {"010000", "Visit_frint32x_d_floatdp1"},
- {"010010", "Visit_frint64x_d_floatdp1"},
+ { {"000000"_b, "fabs_d_floatdp1"},
+ {"000010"_b, "fsqrt_d_floatdp1"},
+ {"000110"_b, "fcvt_hd_floatdp1"},
+ {"001000"_b, "frintp_d_floatdp1"},
+ {"001010"_b, "frintz_d_floatdp1"},
+ {"001110"_b, "frinti_d_floatdp1"},
+ {"010000"_b, "frint32x_d_floatdp1"},
+ {"010010"_b, "frint64x_d_floatdp1"},
},
},
- { "Decode_qntssm",
+ { "_qntssm",
{30, 11, 10},
- { {"000", "Decode_hxrtsq"},
- {"001", "Decode_ygxhyg"},
- {"010", "Decode_nhhpqz"},
- {"011", "Decode_vjymzn"},
- {"101", "Decode_gszxkp"},
- {"110", "Decode_nssrnm"},
- {"111", "Decode_jrsptt"},
+ { {"000"_b, "_hxrtsq"},
+ {"001"_b, "_ygxhyg"},
+ {"010"_b, "_nhhpqz"},
+ {"011"_b, "_vjymzn"},
+ {"101"_b, "_gszxkp"},
+ {"110"_b, "_nssrnm"},
+ {"111"_b, "_jrsptt"},
},
},
- { "Decode_qntygx",
+ { "_qntygx",
{13, 12, 11, 10},
- { {"0000", "Visit_uaddl_asimddiff_l"},
- {"0001", "Visit_uhadd_asimdsame_only"},
- {"0010", "Decode_nzqkky"},
- {"0011", "Visit_uqadd_asimdsame_only"},
- {"0100", "Visit_uaddw_asimddiff_w"},
- {"0101", "Visit_urhadd_asimdsame_only"},
- {"0111", "Decode_nthvqx"},
- {"1000", "Visit_usubl_asimddiff_l"},
- {"1001", "Visit_uhsub_asimdsame_only"},
- {"1010", "Decode_srmhlk"},
- {"1011", "Visit_uqsub_asimdsame_only"},
- {"1100", "Visit_usubw_asimddiff_w"},
- {"1101", "Visit_cmhi_asimdsame_only"},
- {"1110", "Decode_mvgsjr"},
- {"1111", "Visit_cmhs_asimdsame_only"},
+ { {"0000"_b, "uaddl_asimddiff_l"},
+ {"0001"_b, "uhadd_asimdsame_only"},
+ {"0010"_b, "_nzqkky"},
+ {"0011"_b, "uqadd_asimdsame_only"},
+ {"0100"_b, "uaddw_asimddiff_w"},
+ {"0101"_b, "urhadd_asimdsame_only"},
+ {"0111"_b, "_nthvqx"},
+ {"1000"_b, "usubl_asimddiff_l"},
+ {"1001"_b, "uhsub_asimdsame_only"},
+ {"1010"_b, "_srmhlk"},
+ {"1011"_b, "uqsub_asimdsame_only"},
+ {"1100"_b, "usubw_asimddiff_w"},
+ {"1101"_b, "cmhi_asimdsame_only"},
+ {"1110"_b, "_mvgsjr"},
+ {"1111"_b, "cmhs_asimdsame_only"},
},
},
- { "Decode_qnvgmh",
+ { "_qnvgmh",
{23},
- { {"0", "Visit_fmul_asimdsame_only"},
+ { {"0"_b, "fmul_asimdsame_only"},
},
},
- { "Decode_qptvrm",
+ { "_qptvrm",
{23},
- { {"0", "Visit_fmaxnmp_asimdsame_only"},
- {"1", "Visit_fminnmp_asimdsame_only"},
+ { {"0"_b, "fmaxnmp_asimdsame_only"},
+ {"1"_b, "fminnmp_asimdsame_only"},
},
},
- { "Decode_qpvgnh",
+ { "_qpvgnh",
{30, 23, 22, 20, 13},
- { {"00001", "Visit_ld2b_z_p_bi_contiguous"},
- {"000x0", "Visit_ld2b_z_p_br_contiguous"},
- {"00101", "Visit_ld4b_z_p_bi_contiguous"},
- {"001x0", "Visit_ld4b_z_p_br_contiguous"},
- {"01001", "Visit_ld2h_z_p_bi_contiguous"},
- {"010x0", "Visit_ld2h_z_p_br_contiguous"},
- {"01101", "Visit_ld4h_z_p_bi_contiguous"},
- {"011x0", "Visit_ld4h_z_p_br_contiguous"},
- {"10011", "Visit_st2b_z_p_bi_contiguous"},
- {"10111", "Visit_st4b_z_p_bi_contiguous"},
- {"10x01", "Visit_st1b_z_p_bi"},
- {"11011", "Visit_st2h_z_p_bi_contiguous"},
- {"110x0", "Visit_st1h_z_p_bz_d_x32_scaled"},
- {"11111", "Visit_st4h_z_p_bi_contiguous"},
- {"111x0", "Visit_st1h_z_p_bz_s_x32_scaled"},
- {"11x01", "Visit_st1h_z_p_bi"},
+ { {"00001"_b, "ld2b_z_p_bi_contiguous"},
+ {"000x0"_b, "ld2b_z_p_br_contiguous"},
+ {"00101"_b, "ld4b_z_p_bi_contiguous"},
+ {"001x0"_b, "ld4b_z_p_br_contiguous"},
+ {"01001"_b, "ld2h_z_p_bi_contiguous"},
+ {"010x0"_b, "ld2h_z_p_br_contiguous"},
+ {"01101"_b, "ld4h_z_p_bi_contiguous"},
+ {"011x0"_b, "ld4h_z_p_br_contiguous"},
+ {"10011"_b, "st2b_z_p_bi_contiguous"},
+ {"10111"_b, "st4b_z_p_bi_contiguous"},
+ {"10x01"_b, "st1b_z_p_bi"},
+ {"11011"_b, "st2h_z_p_bi_contiguous"},
+ {"110x0"_b, "st1h_z_p_bz_d_x32_scaled"},
+ {"11111"_b, "st4h_z_p_bi_contiguous"},
+ {"111x0"_b, "st1h_z_p_bz_s_x32_scaled"},
+ {"11x01"_b, "st1h_z_p_bi"},
},
},
- { "Decode_qpzynz",
+ { "_qpzynz",
{23, 22},
- { {"00", "Decode_jkpsxk"},
+ { {"00"_b, "_jkpsxk"},
},
},
- { "Decode_qqpkkm",
+ { "_qqpkkm",
{9, 8, 7, 6, 5, 1, 0},
- { {"1111111", "Visit_eretaa_64e_branch_reg"},
+ { {"1111111"_b, "eretaa_64e_branch_reg"},
},
},
- { "Decode_qqpqnm",
+ { "_qqpqnm",
{18, 17},
- { {"0x", "Visit_st1_asisdlsop_sx1_r1s"},
- {"10", "Visit_st1_asisdlsop_sx1_r1s"},
- {"11", "Visit_st1_asisdlsop_s1_i1s"},
+ { {"0x"_b, "st1_asisdlsop_sx1_r1s"},
+ {"10"_b, "st1_asisdlsop_sx1_r1s"},
+ {"11"_b, "st1_asisdlsop_s1_i1s"},
},
},
- { "Decode_qqsmlt",
+ { "_qqsmlt",
{4},
- { {"0", "Visit_ccmp_32_condcmp_imm"},
+ { {"0"_b, "ccmp_32_condcmp_imm"},
},
},
- { "Decode_qqtpln",
+ { "_qqtpln",
{17},
- { {"0", "Visit_ld1_asisdlsop_bx1_r1b"},
- {"1", "Visit_ld1_asisdlsop_b1_i1b"},
+ { {"0"_b, "ld1_asisdlsop_bx1_r1b"},
+ {"1"_b, "ld1_asisdlsop_b1_i1b"},
},
},
- { "Decode_qqyryl",
+ { "_qqyryl",
{30, 23, 22, 13, 4},
- { {"00x0x", "Visit_ld1w_z_p_bz_s_x32_unscaled"},
- {"00x1x", "Visit_ldff1w_z_p_bz_s_x32_unscaled"},
- {"0100x", "Visit_ldr_z_bi"},
- {"01100", "Visit_prfw_i_p_bi_s"},
- {"01110", "Visit_prfd_i_p_bi_s"},
- {"10x0x", "Visit_ld1w_z_p_bz_d_x32_unscaled"},
- {"10x1x", "Visit_ldff1w_z_p_bz_d_x32_unscaled"},
- {"11x0x", "Visit_ld1d_z_p_bz_d_x32_unscaled"},
- {"11x1x", "Visit_ldff1d_z_p_bz_d_x32_unscaled"},
+ { {"00x0x"_b, "ld1w_z_p_bz_s_x32_unscaled"},
+ {"00x1x"_b, "ldff1w_z_p_bz_s_x32_unscaled"},
+ {"0100x"_b, "ldr_z_bi"},
+ {"01100"_b, "prfw_i_p_bi_s"},
+ {"01110"_b, "prfd_i_p_bi_s"},
+ {"10x0x"_b, "ld1w_z_p_bz_d_x32_unscaled"},
+ {"10x1x"_b, "ldff1w_z_p_bz_d_x32_unscaled"},
+ {"11x0x"_b, "ld1d_z_p_bz_d_x32_unscaled"},
+ {"11x1x"_b, "ldff1d_z_p_bz_d_x32_unscaled"},
},
},
- { "Decode_qqzrhz",
+ { "_qqzrhz",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_fcvtau_asimdmiscfp16_r"},
- {"0x00001", "Visit_fcvtau_asimdmisc_r"},
- {"0x10000", "Visit_fmaxnmv_asimdall_only_sd"},
- {"1111000", "Visit_fcmge_asimdmiscfp16_fz"},
- {"1x00000", "Visit_fcmge_asimdmisc_fz"},
- {"1x00001", "Visit_ursqrte_asimdmisc_r"},
- {"1x10000", "Visit_fminnmv_asimdall_only_sd"},
+ { {"0111001"_b, "fcvtau_asimdmiscfp16_r"},
+ {"0x00001"_b, "fcvtau_asimdmisc_r"},
+ {"0x10000"_b, "fmaxnmv_asimdall_only_sd"},
+ {"1111000"_b, "fcmge_asimdmiscfp16_fz"},
+ {"1x00000"_b, "fcmge_asimdmisc_fz"},
+ {"1x00001"_b, "ursqrte_asimdmisc_r"},
+ {"1x10000"_b, "fminnmv_asimdall_only_sd"},
},
},
- { "Decode_qrygny",
+ { "_qrygny",
{30, 23, 22, 20, 13},
- { {"00001", "Visit_ld1b_z_p_bi_u8"},
- {"00011", "Visit_ldnf1b_z_p_bi_u8"},
- {"00101", "Visit_ld1b_z_p_bi_u32"},
- {"00111", "Visit_ldnf1b_z_p_bi_u32"},
- {"01001", "Visit_ld1sw_z_p_bi_s64"},
- {"01011", "Visit_ldnf1sw_z_p_bi_s64"},
- {"01101", "Visit_ld1h_z_p_bi_u32"},
- {"01111", "Visit_ldnf1h_z_p_bi_u32"},
- {"100x0", "Visit_st1b_z_p_bz_d_x32_unscaled"},
- {"100x1", "Visit_st1b_z_p_bz_d_64_unscaled"},
- {"101x0", "Visit_st1b_z_p_bz_s_x32_unscaled"},
- {"101x1", "Visit_st1b_z_p_ai_d"},
- {"110x0", "Visit_st1h_z_p_bz_d_x32_unscaled"},
- {"110x1", "Visit_st1h_z_p_bz_d_64_unscaled"},
- {"111x0", "Visit_st1h_z_p_bz_s_x32_unscaled"},
- {"111x1", "Visit_st1h_z_p_ai_d"},
+ { {"00001"_b, "ld1b_z_p_bi_u8"},
+ {"00011"_b, "ldnf1b_z_p_bi_u8"},
+ {"00101"_b, "ld1b_z_p_bi_u32"},
+ {"00111"_b, "ldnf1b_z_p_bi_u32"},
+ {"01001"_b, "ld1sw_z_p_bi_s64"},
+ {"01011"_b, "ldnf1sw_z_p_bi_s64"},
+ {"01101"_b, "ld1h_z_p_bi_u32"},
+ {"01111"_b, "ldnf1h_z_p_bi_u32"},
+ {"100x0"_b, "st1b_z_p_bz_d_x32_unscaled"},
+ {"100x1"_b, "st1b_z_p_bz_d_64_unscaled"},
+ {"101x0"_b, "st1b_z_p_bz_s_x32_unscaled"},
+ {"101x1"_b, "st1b_z_p_ai_d"},
+ {"110x0"_b, "st1h_z_p_bz_d_x32_unscaled"},
+ {"110x1"_b, "st1h_z_p_bz_d_64_unscaled"},
+ {"111x0"_b, "st1h_z_p_bz_s_x32_unscaled"},
+ {"111x1"_b, "st1h_z_p_ai_d"},
},
},
- { "Decode_qrykhm",
+ { "_qrykhm",
{12},
- { {"0", "Visit_st4_asisdlsop_dx4_r4d"},
+ { {"0"_b, "st4_asisdlsop_dx4_r4d"},
},
},
- { "Decode_qsnqpz",
+ { "_qsnqpz",
{18, 17},
- { {"0x", "Visit_ld4_asisdlsop_sx4_r4s"},
- {"10", "Visit_ld4_asisdlsop_sx4_r4s"},
- {"11", "Visit_ld4_asisdlsop_s4_i4s"},
+ { {"0x"_b, "ld4_asisdlsop_sx4_r4s"},
+ {"10"_b, "ld4_asisdlsop_sx4_r4s"},
+ {"11"_b, "ld4_asisdlsop_s4_i4s"},
},
},
- { "Decode_qsqqxg",
+ { "_qsqqxg",
{30, 23, 22, 13, 12, 11, 10},
- { {"1010000", "Visit_sha512h_qqv_cryptosha512_3"},
- {"1010001", "Visit_sha512h2_qqv_cryptosha512_3"},
- {"1010010", "Visit_sha512su1_vvv2_cryptosha512_3"},
- {"1010011", "Visit_rax1_vvv2_cryptosha512_3"},
+ { {"1010000"_b, "sha512h_qqv_cryptosha512_3"},
+ {"1010001"_b, "sha512h2_qqv_cryptosha512_3"},
+ {"1010010"_b, "sha512su1_vvv2_cryptosha512_3"},
+ {"1010011"_b, "rax1_vvv2_cryptosha512_3"},
},
},
- { "Decode_qsrlql",
+ { "_qsrlql",
{30, 23, 22, 13, 12, 11, 10},
- { {"010xx00", "Visit_csel_32_condsel"},
- {"010xx01", "Visit_csinc_32_condsel"},
- {"0110000", "Visit_crc32b_32c_dp_2src"},
- {"0110001", "Visit_crc32h_32c_dp_2src"},
- {"0110010", "Visit_crc32w_32c_dp_2src"},
- {"0110100", "Visit_crc32cb_32c_dp_2src"},
- {"0110101", "Visit_crc32ch_32c_dp_2src"},
- {"0110110", "Visit_crc32cw_32c_dp_2src"},
- {"110xx00", "Visit_csinv_32_condsel"},
- {"110xx01", "Visit_csneg_32_condsel"},
+ { {"010xx00"_b, "csel_32_condsel"},
+ {"010xx01"_b, "csinc_32_condsel"},
+ {"0110000"_b, "crc32b_32c_dp_2src"},
+ {"0110001"_b, "crc32h_32c_dp_2src"},
+ {"0110010"_b, "crc32w_32c_dp_2src"},
+ {"0110100"_b, "crc32cb_32c_dp_2src"},
+ {"0110101"_b, "crc32ch_32c_dp_2src"},
+ {"0110110"_b, "crc32cw_32c_dp_2src"},
+ {"110xx00"_b, "csinv_32_condsel"},
+ {"110xx01"_b, "csneg_32_condsel"},
},
},
- { "Decode_qsrtzz",
+ { "_qsrtzz",
{30},
- { {"0", "Visit_bl_only_branch_imm"},
- {"1", "Decode_lvshqt"},
+ { {"0"_b, "bl_only_branch_imm"},
+ {"1"_b, "_lvshqt"},
},
},
- { "Decode_qssyls",
+ { "_qssyls",
{20, 19, 18, 17, 16, 13, 12},
- { {"0000000", "Visit_stzgm_64bulk_ldsttags"},
+ { {"0000000"_b, "stzgm_64bulk_ldsttags"},
},
},
- { "Decode_qsxpyq",
+ { "_qsxpyq",
{20, 19, 18, 17, 16, 13, 12, 4, 3, 2, 1, 0},
- { {"000000001101", "Visit_setf8_only_setf"},
+ { {"000000001101"_b, "setf8_only_setf"},
},
},
- { "Decode_qsygjs",
+ { "_qsygjs",
{30, 23, 22, 12, 11, 10},
- { {"0000xx", "Visit_add_32_addsub_ext"},
- {"000100", "Visit_add_32_addsub_ext"},
- {"1000xx", "Visit_sub_32_addsub_ext"},
- {"100100", "Visit_sub_32_addsub_ext"},
+ { {"0000xx"_b, "add_32_addsub_ext"},
+ {"000100"_b, "add_32_addsub_ext"},
+ {"1000xx"_b, "sub_32_addsub_ext"},
+ {"100100"_b, "sub_32_addsub_ext"},
},
},
- { "Decode_qtgvhn",
+ { "_qtgvhn",
{17},
- { {"0", "Visit_ld4_asisdlsop_bx4_r4b"},
- {"1", "Visit_ld4_asisdlsop_b4_i4b"},
+ { {"0"_b, "ld4_asisdlsop_bx4_r4b"},
+ {"1"_b, "ld4_asisdlsop_b4_i4b"},
},
},
- { "Decode_qtjzhs",
+ { "_qtjzhs",
{17},
- { {"0", "Visit_ld1_asisdlse_r4_4v"},
+ { {"0"_b, "ld1_asisdlse_r4_4v"},
},
},
- { "Decode_qtknlp",
+ { "_qtknlp",
{30, 11, 10},
- { {"000", "Decode_skpjrp"},
- {"001", "Decode_sjnqvx"},
- {"011", "Decode_rgnxpp"},
- {"100", "Decode_rtlzxv"},
- {"101", "Decode_zvlxrl"},
- {"110", "Decode_ynnrny"},
- {"111", "Decode_nlkkyx"},
+ { {"000"_b, "_skpjrp"},
+ {"001"_b, "_sjnqvx"},
+ {"011"_b, "_rgnxpp"},
+ {"100"_b, "_rtlzxv"},
+ {"101"_b, "_zvlxrl"},
+ {"110"_b, "_ynnrny"},
+ {"111"_b, "_nlkkyx"},
},
},
- { "Decode_qtkpxg",
+ { "_qtkpxg",
{20},
- { {"0", "Decode_srggzy"},
- {"1", "Visit_mrs_rs_systemmove"},
+ { {"0"_b, "_srggzy"},
+ {"1"_b, "mrs_rs_systemmove"},
},
},
- { "Decode_qtmjkr",
+ { "_qtmjkr",
{23},
- { {"0", "Visit_fdiv_asimdsame_only"},
+ { {"0"_b, "fdiv_asimdsame_only"},
},
},
- { "Decode_qtxpky",
+ { "_qtxpky",
{4},
- { {"0", "Visit_cmphs_p_p_zi"},
- {"1", "Visit_cmphi_p_p_zi"},
+ { {"0"_b, "cmphs_p_p_zi"},
+ {"1"_b, "cmphi_p_p_zi"},
},
},
- { "Decode_qtxypt",
+ { "_qtxypt",
{9, 8, 7, 6, 5, 1, 0},
- { {"1111111", "Visit_retab_64e_branch_reg"},
+ { {"1111111"_b, "retab_64e_branch_reg"},
},
},
- { "Decode_qtystr",
+ { "_qtystr",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_scvtf_asimdmiscfp16_r"},
- {"0x00001", "Visit_scvtf_asimdmisc_r"},
- {"1111000", "Visit_fcmeq_asimdmiscfp16_fz"},
- {"1111001", "Visit_frecpe_asimdmiscfp16_r"},
- {"1x00000", "Visit_fcmeq_asimdmisc_fz"},
- {"1x00001", "Visit_frecpe_asimdmisc_r"},
+ { {"0111001"_b, "scvtf_asimdmiscfp16_r"},
+ {"0x00001"_b, "scvtf_asimdmisc_r"},
+ {"1111000"_b, "fcmeq_asimdmiscfp16_fz"},
+ {"1111001"_b, "frecpe_asimdmiscfp16_r"},
+ {"1x00000"_b, "fcmeq_asimdmisc_fz"},
+ {"1x00001"_b, "frecpe_asimdmisc_r"},
},
},
- { "Decode_qvlnll",
+ { "_qvlnll",
{22, 20, 11},
- { {"010", "Visit_decw_r_rs"},
- {"110", "Visit_decd_r_rs"},
+ { {"010"_b, "decw_r_rs"},
+ {"110"_b, "decd_r_rs"},
},
},
- { "Decode_qvlytr",
+ { "_qvlytr",
{23, 22, 20, 19, 18, 17, 16},
- { {"0x00001", "Visit_frint64x_asimdmisc_r"},
- {"0x10000", "Visit_fmaxv_asimdall_only_sd"},
- {"1111000", "Visit_fneg_asimdmiscfp16_r"},
- {"1111001", "Visit_fsqrt_asimdmiscfp16_r"},
- {"1x00000", "Visit_fneg_asimdmisc_r"},
- {"1x00001", "Visit_fsqrt_asimdmisc_r"},
- {"1x10000", "Visit_fminv_asimdall_only_sd"},
+ { {"0x00001"_b, "frint64x_asimdmisc_r"},
+ {"0x10000"_b, "fmaxv_asimdall_only_sd"},
+ {"1111000"_b, "fneg_asimdmiscfp16_r"},
+ {"1111001"_b, "fsqrt_asimdmiscfp16_r"},
+ {"1x00000"_b, "fneg_asimdmisc_r"},
+ {"1x00001"_b, "fsqrt_asimdmisc_r"},
+ {"1x10000"_b, "fminv_asimdall_only_sd"},
},
},
- { "Decode_qvsypn",
+ { "_qvsypn",
{30, 23, 22, 20, 13},
- { {"00001", "Visit_ldnt1w_z_p_bi_contiguous"},
- {"000x0", "Visit_ldnt1w_z_p_br_contiguous"},
- {"00101", "Visit_ld3w_z_p_bi_contiguous"},
- {"001x0", "Visit_ld3w_z_p_br_contiguous"},
- {"01001", "Visit_ldnt1d_z_p_bi_contiguous"},
- {"010x0", "Visit_ldnt1d_z_p_br_contiguous"},
- {"01101", "Visit_ld3d_z_p_bi_contiguous"},
- {"011x0", "Visit_ld3d_z_p_br_contiguous"},
- {"10011", "Visit_stnt1w_z_p_bi_contiguous"},
- {"100x0", "Visit_st1w_z_p_bz_d_x32_unscaled"},
- {"10111", "Visit_st3w_z_p_bi_contiguous"},
- {"101x0", "Visit_st1w_z_p_bz_s_x32_unscaled"},
- {"10x01", "Visit_st1w_z_p_bi"},
- {"11011", "Visit_stnt1d_z_p_bi_contiguous"},
- {"110x0", "Visit_st1d_z_p_bz_d_x32_unscaled"},
- {"11111", "Visit_st3d_z_p_bi_contiguous"},
- {"11x01", "Visit_st1d_z_p_bi"},
+ { {"00001"_b, "ldnt1w_z_p_bi_contiguous"},
+ {"000x0"_b, "ldnt1w_z_p_br_contiguous"},
+ {"00101"_b, "ld3w_z_p_bi_contiguous"},
+ {"001x0"_b, "ld3w_z_p_br_contiguous"},
+ {"01001"_b, "ldnt1d_z_p_bi_contiguous"},
+ {"010x0"_b, "ldnt1d_z_p_br_contiguous"},
+ {"01101"_b, "ld3d_z_p_bi_contiguous"},
+ {"011x0"_b, "ld3d_z_p_br_contiguous"},
+ {"10011"_b, "stnt1w_z_p_bi_contiguous"},
+ {"100x0"_b, "st1w_z_p_bz_d_x32_unscaled"},
+ {"10111"_b, "st3w_z_p_bi_contiguous"},
+ {"101x0"_b, "st1w_z_p_bz_s_x32_unscaled"},
+ {"10x01"_b, "st1w_z_p_bi"},
+ {"11011"_b, "stnt1d_z_p_bi_contiguous"},
+ {"110x0"_b, "st1d_z_p_bz_d_x32_unscaled"},
+ {"11111"_b, "st3d_z_p_bi_contiguous"},
+ {"11x01"_b, "st1d_z_p_bi"},
},
},
- { "Decode_qvtxpr",
+ { "_qvtxpr",
{20, 9, 4},
- { {"000", "Visit_uzp1_p_pp"},
+ { {"000"_b, "uzp1_p_pp"},
},
},
- { "Decode_qxrzgv",
+ { "_qxrzgv",
{17},
- { {"0", "Visit_ld1_asisdlsep_r2_r2"},
- {"1", "Visit_ld1_asisdlsep_i2_i2"},
+ { {"0"_b, "ld1_asisdlsep_r2_r2"},
+ {"1"_b, "ld1_asisdlsep_i2_i2"},
},
},
- { "Decode_qxtvzy",
+ { "_qxtvzy",
{13, 12, 11, 10},
- { {"0000", "Visit_umlal_asimddiff_l"},
- {"0001", "Visit_sub_asimdsame_only"},
- {"0010", "Decode_gznnvh"},
- {"0011", "Visit_cmeq_asimdsame_only"},
- {"0101", "Visit_mls_asimdsame_only"},
- {"0110", "Decode_vsqlkr"},
- {"0111", "Visit_pmul_asimdsame_only"},
- {"1000", "Visit_umlsl_asimddiff_l"},
- {"1001", "Visit_umaxp_asimdsame_only"},
- {"1010", "Decode_gggyqx"},
- {"1011", "Visit_uminp_asimdsame_only"},
- {"1101", "Visit_sqrdmulh_asimdsame_only"},
- {"1110", "Decode_slnkst"},
+ { {"0000"_b, "umlal_asimddiff_l"},
+ {"0001"_b, "sub_asimdsame_only"},
+ {"0010"_b, "_gznnvh"},
+ {"0011"_b, "cmeq_asimdsame_only"},
+ {"0101"_b, "mls_asimdsame_only"},
+ {"0110"_b, "_vsqlkr"},
+ {"0111"_b, "pmul_asimdsame_only"},
+ {"1000"_b, "umlsl_asimddiff_l"},
+ {"1001"_b, "umaxp_asimdsame_only"},
+ {"1010"_b, "_gggyqx"},
+ {"1011"_b, "uminp_asimdsame_only"},
+ {"1101"_b, "sqrdmulh_asimdsame_only"},
+ {"1110"_b, "_slnkst"},
},
},
- { "Decode_qyjvqr",
+ { "_qyjvqr",
{23, 18, 17, 16},
- { {"0000", "Visit_sqxtnt_z_zz"},
+ { {"0000"_b, "sqxtnt_z_zz"},
},
},
- { "Decode_qytrjj",
+ { "_qytrjj",
{30, 23, 22},
- { {"100", "Visit_bcax_vvv16_crypto4"},
+ { {"100"_b, "bcax_vvv16_crypto4"},
},
},
- { "Decode_qzjnpr",
+ { "_qzjnpr",
{30, 23, 22, 20, 19, 18, 17, 16},
- { {"00000000", "Visit_udf_only_perm_undef"},
+ { {"00000000"_b, "udf_only_perm_undef"},
},
},
- { "Decode_qzrjss",
+ { "_qzrjss",
{18, 17, 12},
- { {"0x0", "Visit_st3_asisdlsop_dx3_r3d"},
- {"100", "Visit_st3_asisdlsop_dx3_r3d"},
- {"110", "Visit_st3_asisdlsop_d3_i3d"},
+ { {"0x0"_b, "st3_asisdlsop_dx3_r3d"},
+ {"100"_b, "st3_asisdlsop_dx3_r3d"},
+ {"110"_b, "st3_asisdlsop_d3_i3d"},
},
},
- { "Decode_qzsthq",
+ { "_qzsthq",
{30, 23, 22},
- { {"000", "Visit_strb_32_ldst_pos"},
- {"001", "Visit_ldrb_32_ldst_pos"},
- {"010", "Visit_ldrsb_64_ldst_pos"},
- {"011", "Visit_ldrsb_32_ldst_pos"},
- {"100", "Visit_strh_32_ldst_pos"},
- {"101", "Visit_ldrh_32_ldst_pos"},
- {"110", "Visit_ldrsh_64_ldst_pos"},
- {"111", "Visit_ldrsh_32_ldst_pos"},
+ { {"000"_b, "strb_32_ldst_pos"},
+ {"001"_b, "ldrb_32_ldst_pos"},
+ {"010"_b, "ldrsb_64_ldst_pos"},
+ {"011"_b, "ldrsb_32_ldst_pos"},
+ {"100"_b, "strh_32_ldst_pos"},
+ {"101"_b, "ldrh_32_ldst_pos"},
+ {"110"_b, "ldrsh_64_ldst_pos"},
+ {"111"_b, "ldrsh_32_ldst_pos"},
},
},
- { "Decode_qzxvsk",
+ { "_qzxvsk",
{23, 22, 20, 19, 13, 11},
- { {"0000x0", "Visit_bic_asimdimm_l_sl"},
- {"00x100", "Visit_usra_asimdshf_r"},
- {"00x110", "Visit_ursra_asimdshf_r"},
- {"010x00", "Visit_usra_asimdshf_r"},
- {"010x10", "Visit_ursra_asimdshf_r"},
- {"011100", "Visit_usra_asimdshf_r"},
- {"011110", "Visit_ursra_asimdshf_r"},
- {"0x1000", "Visit_usra_asimdshf_r"},
- {"0x1010", "Visit_ursra_asimdshf_r"},
+ { {"0000x0"_b, "bic_asimdimm_l_sl"},
+ {"00x100"_b, "usra_asimdshf_r"},
+ {"00x110"_b, "ursra_asimdshf_r"},
+ {"010x00"_b, "usra_asimdshf_r"},
+ {"010x10"_b, "ursra_asimdshf_r"},
+ {"011100"_b, "usra_asimdshf_r"},
+ {"011110"_b, "ursra_asimdshf_r"},
+ {"0x1000"_b, "usra_asimdshf_r"},
+ {"0x1010"_b, "ursra_asimdshf_r"},
},
},
- { "Decode_qzzlhq",
+ { "_qzzlhq",
{30, 23, 22},
- { {"000", "Visit_and_32_log_imm"},
- {"010", "Visit_movn_32_movewide"},
- {"100", "Visit_eor_32_log_imm"},
- {"110", "Visit_movz_32_movewide"},
+ { {"000"_b, "and_32_log_imm"},
+ {"010"_b, "movn_32_movewide"},
+ {"100"_b, "eor_32_log_imm"},
+ {"110"_b, "movz_32_movewide"},
},
},
- { "Decode_qzzlpv",
+ { "_qzzlpv",
{13, 12},
- { {"01", "Visit_gmi_64g_dp_2src"},
- {"10", "Visit_lsrv_64_dp_2src"},
+ { {"01"_b, "gmi_64g_dp_2src"},
+ {"10"_b, "lsrv_64_dp_2src"},
},
},
- { "Decode_rgjqzs",
+ { "_rgjqzs",
{30, 23, 22},
- { {"001", "Visit_sbfm_64m_bitfield"},
- {"101", "Visit_ubfm_64m_bitfield"},
+ { {"001"_b, "sbfm_64m_bitfield"},
+ {"101"_b, "ubfm_64m_bitfield"},
},
},
- { "Decode_rgnxpp",
+ { "_rgnxpp",
{23, 22},
- { {"00", "Visit_fcsel_s_floatsel"},
- {"01", "Visit_fcsel_d_floatsel"},
- {"11", "Visit_fcsel_h_floatsel"},
+ { {"00"_b, "fcsel_s_floatsel"},
+ {"01"_b, "fcsel_d_floatsel"},
+ {"11"_b, "fcsel_h_floatsel"},
},
},
- { "Decode_rgztzl",
+ { "_rgztzl",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_saddlp_asimdmisc_p"},
- {"00001", "Visit_xtn_asimdmisc_n"},
+ { {"00000"_b, "saddlp_asimdmisc_p"},
+ {"00001"_b, "xtn_asimdmisc_n"},
},
},
- { "Decode_rhhrhg",
+ { "_rhhrhg",
{30, 13, 4},
- { {"000", "Visit_cmphs_p_p_zw"},
- {"001", "Visit_cmphi_p_p_zw"},
- {"010", "Visit_cmplo_p_p_zw"},
- {"011", "Visit_cmpls_p_p_zw"},
+ { {"000"_b, "cmphs_p_p_zw"},
+ {"001"_b, "cmphi_p_p_zw"},
+ {"010"_b, "cmplo_p_p_zw"},
+ {"011"_b, "cmpls_p_p_zw"},
},
},
- { "Decode_rhmxyp",
+ { "_rhmxyp",
{20, 9, 4},
- { {"000", "Visit_trn1_p_pp"},
+ { {"000"_b, "trn1_p_pp"},
},
},
- { "Decode_rhpmjz",
+ { "_rhpmjz",
{12, 11},
- { {"00", "Visit_incp_z_p_z"},
- {"01", "Visit_incp_r_p_r"},
- {"10", "Decode_mpstrr"},
+ { {"00"_b, "incp_z_p_z"},
+ {"01"_b, "incp_r_p_r"},
+ {"10"_b, "_mpstrr"},
},
},
- { "Decode_rhttgj",
+ { "_rhttgj",
{12, 10},
- { {"00", "Decode_xxpzrl"},
- {"01", "Decode_vlzrlm"},
- {"10", "Decode_vxylhh"},
- {"11", "Decode_pxgztg"},
+ { {"00"_b, "_xxpzrl"},
+ {"01"_b, "_vlzrlm"},
+ {"10"_b, "_vxylhh"},
+ {"11"_b, "_pxgztg"},
},
},
- { "Decode_rhvksm",
+ { "_rhvksm",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_fcvtnu_asisdmiscfp16_r"},
- {"0x00001", "Visit_fcvtnu_asisdmisc_r"},
- {"1111001", "Visit_fcvtpu_asisdmiscfp16_r"},
- {"1x00001", "Visit_fcvtpu_asisdmisc_r"},
+ { {"0111001"_b, "fcvtnu_asisdmiscfp16_r"},
+ {"0x00001"_b, "fcvtnu_asisdmisc_r"},
+ {"1111001"_b, "fcvtpu_asisdmiscfp16_r"},
+ {"1x00001"_b, "fcvtpu_asisdmisc_r"},
},
},
- { "Decode_rhzhyz",
+ { "_rhzhyz",
{13, 12, 4},
- { {"000", "Visit_rmif_only_rmif"},
+ { {"000"_b, "rmif_only_rmif"},
},
},
- { "Decode_rjmyyl",
+ { "_rjmyyl",
{20, 19, 18, 17, 16, 13},
- { {"000000", "Visit_fmov_s_floatdp1"},
- {"000010", "Visit_fneg_s_floatdp1"},
- {"001000", "Visit_frintn_s_floatdp1"},
- {"001010", "Visit_frintm_s_floatdp1"},
- {"001100", "Visit_frinta_s_floatdp1"},
- {"001110", "Visit_frintx_s_floatdp1"},
- {"010000", "Visit_frint32z_s_floatdp1"},
- {"010010", "Visit_frint64z_s_floatdp1"},
+ { {"000000"_b, "fmov_s_floatdp1"},
+ {"000010"_b, "fneg_s_floatdp1"},
+ {"001000"_b, "frintn_s_floatdp1"},
+ {"001010"_b, "frintm_s_floatdp1"},
+ {"001100"_b, "frinta_s_floatdp1"},
+ {"001110"_b, "frintx_s_floatdp1"},
+ {"010000"_b, "frint32z_s_floatdp1"},
+ {"010010"_b, "frint64z_s_floatdp1"},
},
},
- { "Decode_rjyrnt",
+ { "_rjyrnt",
{4},
- { {"0", "Visit_cmpge_p_p_zi"},
- {"1", "Visit_cmpgt_p_p_zi"},
+ { {"0"_b, "cmpge_p_p_zi"},
+ {"1"_b, "cmpgt_p_p_zi"},
},
},
- { "Decode_rjysnh",
+ { "_rjysnh",
{18, 17, 16, 9, 8, 7, 6},
- { {"0000000", "Visit_fadd_z_p_zs"},
- {"0010000", "Visit_fsub_z_p_zs"},
- {"0100000", "Visit_fmul_z_p_zs"},
- {"0110000", "Visit_fsubr_z_p_zs"},
- {"1000000", "Visit_fmaxnm_z_p_zs"},
- {"1010000", "Visit_fminnm_z_p_zs"},
- {"1100000", "Visit_fmax_z_p_zs"},
- {"1110000", "Visit_fmin_z_p_zs"},
+ { {"0000000"_b, "fadd_z_p_zs"},
+ {"0010000"_b, "fsub_z_p_zs"},
+ {"0100000"_b, "fmul_z_p_zs"},
+ {"0110000"_b, "fsubr_z_p_zs"},
+ {"1000000"_b, "fmaxnm_z_p_zs"},
+ {"1010000"_b, "fminnm_z_p_zs"},
+ {"1100000"_b, "fmax_z_p_zs"},
+ {"1110000"_b, "fmin_z_p_zs"},
},
},
- { "Decode_rkqtvs",
+ { "_rkqtvs",
{23, 22, 13},
- { {"100", "Visit_fmlal_asimdelem_lh"},
- {"xx1", "Visit_smlal_asimdelem_l"},
+ { {"100"_b, "fmlal_asimdelem_lh"},
+ {"xx1"_b, "smlal_asimdelem_l"},
},
},
- { "Decode_rkrltp",
+ { "_rkrltp",
{17},
- { {"0", "Visit_st3_asisdlso_b3_3b"},
+ { {"0"_b, "st3_asisdlso_b3_3b"},
},
},
- { "Decode_rksxpn",
+ { "_rksxpn",
{30, 23, 22, 11, 10},
- { {"00010", "Visit_str_b_ldst_regoff"},
- {"00110", "Visit_ldr_b_ldst_regoff"},
- {"01010", "Visit_str_q_ldst_regoff"},
- {"01110", "Visit_ldr_q_ldst_regoff"},
- {"10010", "Visit_str_h_ldst_regoff"},
- {"10110", "Visit_ldr_h_ldst_regoff"},
+ { {"00010"_b, "str_b_ldst_regoff"},
+ {"00110"_b, "ldr_b_ldst_regoff"},
+ {"01010"_b, "str_q_ldst_regoff"},
+ {"01110"_b, "ldr_q_ldst_regoff"},
+ {"10010"_b, "str_h_ldst_regoff"},
+ {"10110"_b, "ldr_h_ldst_regoff"},
},
},
- { "Decode_rkvyqk",
+ { "_rkvyqk",
{23, 22, 20, 19, 13, 11},
- { {"0000x0", "Visit_movi_asimdimm_l_hl"},
- {"00x100", "Visit_shrn_asimdshf_n"},
- {"00x101", "Visit_rshrn_asimdshf_n"},
- {"00x110", "Visit_sshll_asimdshf_l"},
- {"010x00", "Visit_shrn_asimdshf_n"},
- {"010x01", "Visit_rshrn_asimdshf_n"},
- {"010x10", "Visit_sshll_asimdshf_l"},
- {"011100", "Visit_shrn_asimdshf_n"},
- {"011101", "Visit_rshrn_asimdshf_n"},
- {"011110", "Visit_sshll_asimdshf_l"},
- {"0x1000", "Visit_shrn_asimdshf_n"},
- {"0x1001", "Visit_rshrn_asimdshf_n"},
- {"0x1010", "Visit_sshll_asimdshf_l"},
+ { {"0000x0"_b, "movi_asimdimm_l_hl"},
+ {"00x100"_b, "shrn_asimdshf_n"},
+ {"00x101"_b, "rshrn_asimdshf_n"},
+ {"00x110"_b, "sshll_asimdshf_l"},
+ {"010x00"_b, "shrn_asimdshf_n"},
+ {"010x01"_b, "rshrn_asimdshf_n"},
+ {"010x10"_b, "sshll_asimdshf_l"},
+ {"011100"_b, "shrn_asimdshf_n"},
+ {"011101"_b, "rshrn_asimdshf_n"},
+ {"011110"_b, "sshll_asimdshf_l"},
+ {"0x1000"_b, "shrn_asimdshf_n"},
+ {"0x1001"_b, "rshrn_asimdshf_n"},
+ {"0x1010"_b, "sshll_asimdshf_l"},
},
},
- { "Decode_rlrjxp",
+ { "_rlrjxp",
{13, 4},
- { {"00", "Visit_fcmge_p_p_zz"},
- {"01", "Visit_fcmgt_p_p_zz"},
- {"10", "Visit_fcmeq_p_p_zz"},
- {"11", "Visit_fcmne_p_p_zz"},
+ { {"00"_b, "fcmge_p_p_zz"},
+ {"01"_b, "fcmgt_p_p_zz"},
+ {"10"_b, "fcmeq_p_p_zz"},
+ {"11"_b, "fcmne_p_p_zz"},
},
},
- { "Decode_rlyvpn",
+ { "_rlyvpn",
{23, 12, 11, 10},
- { {"0000", "Visit_sqshrunb_z_zi"},
- {"0001", "Visit_sqshrunt_z_zi"},
- {"0010", "Visit_sqrshrunb_z_zi"},
- {"0011", "Visit_sqrshrunt_z_zi"},
- {"0100", "Visit_shrnb_z_zi"},
- {"0101", "Visit_shrnt_z_zi"},
- {"0110", "Visit_rshrnb_z_zi"},
- {"0111", "Visit_rshrnt_z_zi"},
+ { {"0000"_b, "sqshrunb_z_zi"},
+ {"0001"_b, "sqshrunt_z_zi"},
+ {"0010"_b, "sqrshrunb_z_zi"},
+ {"0011"_b, "sqrshrunt_z_zi"},
+ {"0100"_b, "shrnb_z_zi"},
+ {"0101"_b, "shrnt_z_zi"},
+ {"0110"_b, "rshrnb_z_zi"},
+ {"0111"_b, "rshrnt_z_zi"},
},
},
- { "Decode_rmltms",
+ { "_rmltms",
{9, 8, 7, 6, 5, 1, 0},
- { {"1111100", "Visit_eret_64e_branch_reg"},
+ { {"1111100"_b, "eret_64e_branch_reg"},
},
},
- { "Decode_rmmmjj",
+ { "_rmmmjj",
{30, 23, 22},
- { {"000", "Visit_smaddl_64wa_dp_3src"},
- {"010", "Visit_umaddl_64wa_dp_3src"},
+ { {"000"_b, "smaddl_64wa_dp_3src"},
+ {"010"_b, "umaddl_64wa_dp_3src"},
},
},
- { "Decode_rmxjsn",
+ { "_rmxjsn",
{30},
- { {"0", "Visit_orr_64_log_shift"},
- {"1", "Visit_ands_64_log_shift"},
+ { {"0"_b, "orr_64_log_shift"},
+ {"1"_b, "ands_64_log_shift"},
},
},
- { "Decode_rnktts",
+ { "_rnktts",
{23, 22},
- { {"00", "Visit_and_asimdsame_only"},
- {"01", "Visit_bic_asimdsame_only"},
- {"10", "Visit_orr_asimdsame_only"},
- {"11", "Visit_orn_asimdsame_only"},
+ { {"00"_b, "and_asimdsame_only"},
+ {"01"_b, "bic_asimdsame_only"},
+ {"10"_b, "orr_asimdsame_only"},
+ {"11"_b, "orn_asimdsame_only"},
},
},
- { "Decode_rnqtmt",
+ { "_rnqtmt",
{30},
- { {"0", "Decode_zyjjgs"},
- {"1", "Decode_lrntmz"},
+ { {"0"_b, "_zyjjgs"},
+ {"1"_b, "_lrntmz"},
},
},
- { "Decode_rnrzsj",
+ { "_rnrzsj",
{20, 18, 17},
- { {"000", "Decode_lgglzy"},
+ { {"000"_b, "_lgglzy"},
},
},
- { "Decode_rnypvh",
+ { "_rnypvh",
{17},
- { {"0", "Visit_st1_asisdlsop_bx1_r1b"},
- {"1", "Visit_st1_asisdlsop_b1_i1b"},
+ { {"0"_b, "st1_asisdlsop_bx1_r1b"},
+ {"1"_b, "st1_asisdlsop_b1_i1b"},
},
},
- { "Decode_rpmrkq",
+ { "_rpmrkq",
{23},
- { {"0", "Visit_fcmeq_asimdsame_only"},
+ { {"0"_b, "fcmeq_asimdsame_only"},
},
},
- { "Decode_rpqgjl",
+ { "_rpqgjl",
{18, 17, 16, 13, 12, 7, 4, 3, 2, 1, 0},
- { {"00000011111", "Decode_kpxtsp"},
+ { {"00000011111"_b, "_kpxtsp"},
},
},
- { "Decode_rpzykx",
+ { "_rpzykx",
{11},
- { {"0", "Decode_svvyrz"},
+ { {"0"_b, "_svvyrz"},
},
},
- { "Decode_rqhryp",
+ { "_rqhryp",
{12, 10},
- { {"00", "Decode_kjpxvh"},
- {"01", "Decode_mxvjxx"},
- {"10", "Visit_sm4ekey_z_zz"},
- {"11", "Visit_rax1_z_zz"},
+ { {"00"_b, "_kjpxvh"},
+ {"01"_b, "_mxvjxx"},
+ {"10"_b, "sm4ekey_z_zz"},
+ {"11"_b, "rax1_z_zz"},
},
},
- { "Decode_rshyht",
+ { "_rshyht",
{13},
- { {"0", "Visit_facge_p_p_zz"},
- {"1", "Visit_facgt_p_p_zz"},
+ { {"0"_b, "facge_p_p_zz"},
+ {"1"_b, "facgt_p_p_zz"},
},
},
- { "Decode_rsqmgk",
+ { "_rsqmgk",
{23, 22, 20, 19, 18, 17, 16},
- { {"0000000", "Visit_movprfx_z_z"},
+ { {"0000000"_b, "movprfx_z_z"},
},
},
- { "Decode_rsyhtj",
+ { "_rsyhtj",
{13, 12, 11, 10},
- { {"0001", "Visit_ushl_asisdsame_only"},
- {"0010", "Decode_gxnlxg"},
- {"0011", "Visit_uqshl_asisdsame_only"},
- {"0101", "Visit_urshl_asisdsame_only"},
- {"0111", "Visit_uqrshl_asisdsame_only"},
- {"1010", "Decode_msnsjp"},
- {"1110", "Decode_llnzlv"},
+ { {"0001"_b, "ushl_asisdsame_only"},
+ {"0010"_b, "_gxnlxg"},
+ {"0011"_b, "uqshl_asisdsame_only"},
+ {"0101"_b, "urshl_asisdsame_only"},
+ {"0111"_b, "uqrshl_asisdsame_only"},
+ {"1010"_b, "_msnsjp"},
+ {"1110"_b, "_llnzlv"},
},
},
- { "Decode_rsyjqj",
+ { "_rsyjqj",
{23, 22, 20, 19, 18, 17, 16},
- { {"0010000", "Visit_fmaxv_asimdall_only_h"},
- {"0x00001", "Visit_frint64z_asimdmisc_r"},
- {"1010000", "Visit_fminv_asimdall_only_h"},
- {"1111000", "Visit_fabs_asimdmiscfp16_r"},
- {"1x00000", "Visit_fabs_asimdmisc_r"},
+ { {"0010000"_b, "fmaxv_asimdall_only_h"},
+ {"0x00001"_b, "frint64z_asimdmisc_r"},
+ {"1010000"_b, "fminv_asimdall_only_h"},
+ {"1111000"_b, "fabs_asimdmiscfp16_r"},
+ {"1x00000"_b, "fabs_asimdmisc_r"},
},
},
- { "Decode_rsyzrs",
+ { "_rsyzrs",
{22},
- { {"0", "Visit_str_64_ldst_regoff"},
- {"1", "Visit_ldr_64_ldst_regoff"},
+ { {"0"_b, "str_64_ldst_regoff"},
+ {"1"_b, "ldr_64_ldst_regoff"},
},
},
- { "Decode_rtgkkg",
+ { "_rtgkkg",
{30, 23, 22, 13, 12, 11, 10},
- { {"1101001", "Visit_smmla_asimdsame2_g"},
- {"1101011", "Visit_usmmla_asimdsame2_g"},
- {"x100111", "Visit_usdot_asimdsame2_d"},
- {"xxx0101", "Visit_sdot_asimdsame2_d"},
+ { {"1101001"_b, "smmla_asimdsame2_g"},
+ {"1101011"_b, "usmmla_asimdsame2_g"},
+ {"x100111"_b, "usdot_asimdsame2_d"},
+ {"xxx0101"_b, "sdot_asimdsame2_d"},
},
},
- { "Decode_rtlzxv",
+ { "_rtlzxv",
{13, 12},
- { {"01", "Visit_sqdmull_asisddiff_only"},
+ { {"01"_b, "sqdmull_asisddiff_only"},
},
},
- { "Decode_rtpztp",
+ { "_rtpztp",
{22},
- { {"0", "Visit_umullb_z_zzi_s"},
- {"1", "Visit_umullb_z_zzi_d"},
+ { {"0"_b, "umullb_z_zzi_s"},
+ {"1"_b, "umullb_z_zzi_d"},
},
},
- { "Decode_rtrlts",
+ { "_rtrlts",
{23, 22, 12, 11, 10},
- { {"01000", "Visit_bfdot_z_zzz"},
- {"10000", "Visit_fmlalb_z_zzz"},
- {"10001", "Visit_fmlalt_z_zzz"},
- {"11000", "Visit_bfmlalb_z_zzz"},
- {"11001", "Visit_bfmlalt_z_zzz"},
+ { {"01000"_b, "bfdot_z_zzz"},
+ {"10000"_b, "fmlalb_z_zzz"},
+ {"10001"_b, "fmlalt_z_zzz"},
+ {"11000"_b, "bfmlalb_z_zzz"},
+ {"11001"_b, "bfmlalt_z_zzz"},
},
},
- { "Decode_rvjzgt",
+ { "_rvjzgt",
{23, 22, 4},
- { {"000", "Visit_fccmp_s_floatccmp"},
- {"001", "Visit_fccmpe_s_floatccmp"},
- {"010", "Visit_fccmp_d_floatccmp"},
- {"011", "Visit_fccmpe_d_floatccmp"},
- {"110", "Visit_fccmp_h_floatccmp"},
- {"111", "Visit_fccmpe_h_floatccmp"},
+ { {"000"_b, "fccmp_s_floatccmp"},
+ {"001"_b, "fccmpe_s_floatccmp"},
+ {"010"_b, "fccmp_d_floatccmp"},
+ {"011"_b, "fccmpe_d_floatccmp"},
+ {"110"_b, "fccmp_h_floatccmp"},
+ {"111"_b, "fccmpe_h_floatccmp"},
},
},
- { "Decode_rvzhhx",
+ { "_rvzhhx",
{18, 17, 12},
- { {"000", "Visit_st3_asisdlso_d3_3d"},
+ { {"000"_b, "st3_asisdlso_d3_3d"},
},
},
- { "Decode_rxjrmn",
+ { "_rxjrmn",
{22, 13, 12},
- { {"000", "Visit_swpa_32_memop"},
- {"100", "Visit_swpal_32_memop"},
+ { {"000"_b, "swpa_32_memop"},
+ {"100"_b, "swpal_32_memop"},
},
},
- { "Decode_rxpspy",
+ { "_rxpspy",
{30, 23, 22, 12, 11, 10},
- { {"0000xx", "Visit_adds_32s_addsub_ext"},
- {"000100", "Visit_adds_32s_addsub_ext"},
- {"1000xx", "Visit_subs_32s_addsub_ext"},
- {"100100", "Visit_subs_32s_addsub_ext"},
+ { {"0000xx"_b, "adds_32s_addsub_ext"},
+ {"000100"_b, "adds_32s_addsub_ext"},
+ {"1000xx"_b, "subs_32s_addsub_ext"},
+ {"100100"_b, "subs_32s_addsub_ext"},
},
},
- { "Decode_ryglvl",
+ { "_ryglvl",
{4},
- { {"0", "Visit_ccmp_32_condcmp_reg"},
+ { {"0"_b, "ccmp_32_condcmp_reg"},
},
},
- { "Decode_rykykh",
+ { "_rykykh",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_rev64_asimdmisc_r"},
+ { {"00000"_b, "rev64_asimdmisc_r"},
},
},
- { "Decode_rzkmny",
+ { "_rzkmny",
{30},
- { {"0", "Visit_and_64_log_shift"},
- {"1", "Visit_eor_64_log_shift"},
+ { {"0"_b, "and_64_log_shift"},
+ {"1"_b, "eor_64_log_shift"},
},
},
- { "Decode_rznrqt",
+ { "_rznrqt",
{22},
- { {"0", "Visit_umullt_z_zzi_s"},
- {"1", "Visit_umullt_z_zzi_d"},
+ { {"0"_b, "umullt_z_zzi_s"},
+ {"1"_b, "umullt_z_zzi_d"},
},
},
- { "Decode_rzqzlq",
+ { "_rzqzlq",
{23, 22, 20, 19, 16, 13, 12},
- { {"0111110", "Visit_fcvtns_asisdmiscfp16_r"},
- {"0111111", "Visit_fcvtms_asisdmiscfp16_r"},
- {"0x00110", "Visit_fcvtns_asisdmisc_r"},
- {"0x00111", "Visit_fcvtms_asisdmisc_r"},
- {"1111110", "Visit_fcvtps_asisdmiscfp16_r"},
- {"1111111", "Visit_fcvtzs_asisdmiscfp16_r"},
- {"1x00110", "Visit_fcvtps_asisdmisc_r"},
- {"1x00111", "Visit_fcvtzs_asisdmisc_r"},
- {"xx00000", "Visit_cmgt_asisdmisc_z"},
- {"xx00001", "Visit_cmeq_asisdmisc_z"},
- {"xx00010", "Visit_cmlt_asisdmisc_z"},
- {"xx00011", "Visit_abs_asisdmisc_r"},
- {"xx10111", "Visit_addp_asisdpair_only"},
+ { {"0111110"_b, "fcvtns_asisdmiscfp16_r"},
+ {"0111111"_b, "fcvtms_asisdmiscfp16_r"},
+ {"0x00110"_b, "fcvtns_asisdmisc_r"},
+ {"0x00111"_b, "fcvtms_asisdmisc_r"},
+ {"1111110"_b, "fcvtps_asisdmiscfp16_r"},
+ {"1111111"_b, "fcvtzs_asisdmiscfp16_r"},
+ {"1x00110"_b, "fcvtps_asisdmisc_r"},
+ {"1x00111"_b, "fcvtzs_asisdmisc_r"},
+ {"xx00000"_b, "cmgt_asisdmisc_z"},
+ {"xx00001"_b, "cmeq_asisdmisc_z"},
+ {"xx00010"_b, "cmlt_asisdmisc_z"},
+ {"xx00011"_b, "abs_asisdmisc_r"},
+ {"xx10111"_b, "addp_asisdpair_only"},
},
},
- { "Decode_rztvnl",
+ { "_rztvnl",
{20, 19, 18, 17, 16},
- { {"0000x", "Visit_fcadd_z_p_zz"},
- {"10000", "Visit_faddp_z_p_zz"},
- {"10100", "Visit_fmaxnmp_z_p_zz"},
- {"10101", "Visit_fminnmp_z_p_zz"},
- {"10110", "Visit_fmaxp_z_p_zz"},
- {"10111", "Visit_fminp_z_p_zz"},
+ { {"0000x"_b, "fcadd_z_p_zz"},
+ {"10000"_b, "faddp_z_p_zz"},
+ {"10100"_b, "fmaxnmp_z_p_zz"},
+ {"10101"_b, "fminnmp_z_p_zz"},
+ {"10110"_b, "fmaxp_z_p_zz"},
+ {"10111"_b, "fminp_z_p_zz"},
},
},
- { "Decode_rzzxsn",
+ { "_rzzxsn",
{30, 13},
- { {"00", "Decode_nvyxmh"},
- {"01", "Decode_hykhmt"},
- {"10", "Decode_yszjsm"},
- {"11", "Decode_jrnxzh"},
+ { {"00"_b, "_nvyxmh"},
+ {"01"_b, "_hykhmt"},
+ {"10"_b, "_yszjsm"},
+ {"11"_b, "_jrnxzh"},
},
},
- { "Decode_sghgtk",
+ { "_sghgtk",
{4},
- { {"0", "Visit_cmplo_p_p_zi"},
- {"1", "Visit_cmpls_p_p_zi"},
+ { {"0"_b, "cmplo_p_p_zi"},
+ {"1"_b, "cmpls_p_p_zi"},
},
},
- { "Decode_sgnknz",
+ { "_sgnknz",
{23, 22, 20, 19, 11},
- { {"00011", "Visit_fcvtzs_asisdshf_c"},
- {"001x1", "Visit_fcvtzs_asisdshf_c"},
- {"01xx1", "Visit_fcvtzs_asisdshf_c"},
+ { {"00011"_b, "fcvtzs_asisdshf_c"},
+ {"001x1"_b, "fcvtzs_asisdshf_c"},
+ {"01xx1"_b, "fcvtzs_asisdshf_c"},
},
},
- { "Decode_sgztlj",
+ { "_sgztlj",
{23, 22, 20, 19, 18, 17, 16},
- { {"0010000", "Visit_fmaxnmv_asimdall_only_h"},
- {"0111001", "Visit_fcvtas_asimdmiscfp16_r"},
- {"0x00001", "Visit_fcvtas_asimdmisc_r"},
- {"1010000", "Visit_fminnmv_asimdall_only_h"},
- {"1111000", "Visit_fcmgt_asimdmiscfp16_fz"},
- {"1x00000", "Visit_fcmgt_asimdmisc_fz"},
- {"1x00001", "Visit_urecpe_asimdmisc_r"},
+ { {"0010000"_b, "fmaxnmv_asimdall_only_h"},
+ {"0111001"_b, "fcvtas_asimdmiscfp16_r"},
+ {"0x00001"_b, "fcvtas_asimdmisc_r"},
+ {"1010000"_b, "fminnmv_asimdall_only_h"},
+ {"1111000"_b, "fcmgt_asimdmiscfp16_fz"},
+ {"1x00000"_b, "fcmgt_asimdmisc_fz"},
+ {"1x00001"_b, "urecpe_asimdmisc_r"},
},
},
- { "Decode_shgkvq",
+ { "_shgkvq",
{18, 17},
- { {"00", "Visit_st2_asisdlso_s2_2s"},
+ { {"00"_b, "st2_asisdlso_s2_2s"},
},
},
- { "Decode_shqygv",
+ { "_shqygv",
{30, 4},
- { {"00", "Decode_thvxym"},
- {"01", "Decode_mrhtxt"},
- {"10", "Decode_ptjyqx"},
- {"11", "Decode_rshyht"},
+ { {"00"_b, "_thvxym"},
+ {"01"_b, "_mrhtxt"},
+ {"10"_b, "_ptjyqx"},
+ {"11"_b, "_rshyht"},
},
},
- { "Decode_shrsxr",
+ { "_shrsxr",
{30, 23, 22},
- { {"000", "Visit_stnp_64_ldstnapair_offs"},
- {"001", "Visit_ldnp_64_ldstnapair_offs"},
- {"010", "Visit_stp_64_ldstpair_post"},
- {"011", "Visit_ldp_64_ldstpair_post"},
+ { {"000"_b, "stnp_64_ldstnapair_offs"},
+ {"001"_b, "ldnp_64_ldstnapair_offs"},
+ {"010"_b, "stp_64_ldstpair_post"},
+ {"011"_b, "ldp_64_ldstpair_post"},
},
},
- { "Decode_shzysp",
+ { "_shzysp",
{30, 23, 22, 19, 18, 17, 16},
- { {"1001000", "Visit_ins_asimdins_ir_r"},
- {"100x100", "Visit_ins_asimdins_ir_r"},
- {"100xx10", "Visit_ins_asimdins_ir_r"},
- {"100xxx1", "Visit_ins_asimdins_ir_r"},
- {"x01xxxx", "Visit_fmulx_asimdsamefp16_only"},
+ { {"1001000"_b, "ins_asimdins_ir_r"},
+ {"100x100"_b, "ins_asimdins_ir_r"},
+ {"100xx10"_b, "ins_asimdins_ir_r"},
+ {"100xxx1"_b, "ins_asimdins_ir_r"},
+ {"x01xxxx"_b, "fmulx_asimdsamefp16_only"},
},
},
- { "Decode_sjlpxn",
+ { "_sjlpxn",
{23, 22},
- { {"01", "Visit_fcmla_asimdelem_c_h"},
- {"10", "Visit_fcmla_asimdelem_c_s"},
+ { {"01"_b, "fcmla_asimdelem_c_h"},
+ {"10"_b, "fcmla_asimdelem_c_s"},
},
},
- { "Decode_sjlrxn",
+ { "_sjlrxn",
{10},
- { {"0", "Decode_mpzqxm"},
+ { {"0"_b, "_mpzqxm"},
},
},
- { "Decode_sjnqvx",
+ { "_sjnqvx",
{23, 22, 4},
- { {"000", "Visit_fccmp_s_floatccmp"},
- {"001", "Visit_fccmpe_s_floatccmp"},
- {"010", "Visit_fccmp_d_floatccmp"},
- {"011", "Visit_fccmpe_d_floatccmp"},
- {"110", "Visit_fccmp_h_floatccmp"},
- {"111", "Visit_fccmpe_h_floatccmp"},
+ { {"000"_b, "fccmp_s_floatccmp"},
+ {"001"_b, "fccmpe_s_floatccmp"},
+ {"010"_b, "fccmp_d_floatccmp"},
+ {"011"_b, "fccmpe_d_floatccmp"},
+ {"110"_b, "fccmp_h_floatccmp"},
+ {"111"_b, "fccmpe_h_floatccmp"},
},
},
- { "Decode_sjnspg",
+ { "_sjnspg",
{4},
- { {"0", "Visit_nors_p_p_pp_z"},
- {"1", "Visit_nands_p_p_pp_z"},
+ { {"0"_b, "nors_p_p_pp_z"},
+ {"1"_b, "nands_p_p_pp_z"},
},
},
- { "Decode_sjnxky",
+ { "_sjnxky",
{30},
- { {"1", "Decode_ylyskq"},
+ { {"1"_b, "_ylyskq"},
},
},
- { "Decode_sjrqth",
+ { "_sjrqth",
{23, 22},
- { {"00", "Visit_fmov_s_floatimm"},
- {"01", "Visit_fmov_d_floatimm"},
- {"11", "Visit_fmov_h_floatimm"},
+ { {"00"_b, "fmov_s_floatimm"},
+ {"01"_b, "fmov_d_floatimm"},
+ {"11"_b, "fmov_h_floatimm"},
},
},
- { "Decode_sjsltg",
+ { "_sjsltg",
{17},
- { {"0", "Visit_st2_asisdlsop_hx2_r2h"},
- {"1", "Visit_st2_asisdlsop_h2_i2h"},
+ { {"0"_b, "st2_asisdlsop_hx2_r2h"},
+ {"1"_b, "st2_asisdlsop_h2_i2h"},
},
},
- { "Decode_sjtrhm",
+ { "_sjtrhm",
{30, 23, 22, 20, 13},
- { {"00001", "Visit_ld1rqb_z_p_bi_u8"},
- {"000x0", "Visit_ld1rqb_z_p_br_contiguous"},
- {"01001", "Visit_ld1rqh_z_p_bi_u16"},
- {"010x0", "Visit_ld1rqh_z_p_br_contiguous"},
- {"100x1", "Visit_stnt1b_z_p_ar_d_64_unscaled"},
- {"101x1", "Visit_stnt1b_z_p_ar_s_x32_unscaled"},
- {"110x1", "Visit_stnt1h_z_p_ar_d_64_unscaled"},
- {"111x1", "Visit_stnt1h_z_p_ar_s_x32_unscaled"},
+ { {"00001"_b, "ld1rqb_z_p_bi_u8"},
+ {"000x0"_b, "ld1rqb_z_p_br_contiguous"},
+ {"01001"_b, "ld1rqh_z_p_bi_u16"},
+ {"010x0"_b, "ld1rqh_z_p_br_contiguous"},
+ {"100x1"_b, "stnt1b_z_p_ar_d_64_unscaled"},
+ {"101x1"_b, "stnt1b_z_p_ar_s_x32_unscaled"},
+ {"110x1"_b, "stnt1h_z_p_ar_d_64_unscaled"},
+ {"111x1"_b, "stnt1h_z_p_ar_s_x32_unscaled"},
},
},
- { "Decode_sjvhlq",
+ { "_sjvhlq",
{22},
- { {"0", "Visit_smullb_z_zzi_s"},
- {"1", "Visit_smullb_z_zzi_d"},
+ { {"0"_b, "smullb_z_zzi_s"},
+ {"1"_b, "smullb_z_zzi_d"},
},
},
- { "Decode_sjzsvv",
+ { "_sjzsvv",
{30, 23, 13, 12, 11, 10},
- { {"101001", "Visit_ucvtf_asisdshf_c"},
- {"101111", "Visit_fcvtzu_asisdshf_c"},
- {"1x01x0", "Visit_sqrdmlah_asisdelem_r"},
- {"1x11x0", "Visit_sqrdmlsh_asisdelem_r"},
+ { {"101001"_b, "ucvtf_asisdshf_c"},
+ {"101111"_b, "fcvtzu_asisdshf_c"},
+ {"1x01x0"_b, "sqrdmlah_asisdelem_r"},
+ {"1x11x0"_b, "sqrdmlsh_asisdelem_r"},
},
},
- { "Decode_skglrt",
+ { "_skglrt",
{23, 22, 20, 19, 13, 11},
- { {"0000x0", "Visit_mvni_asimdimm_l_sl"},
- {"00x100", "Visit_ushr_asimdshf_r"},
- {"00x110", "Visit_urshr_asimdshf_r"},
- {"010x00", "Visit_ushr_asimdshf_r"},
- {"010x10", "Visit_urshr_asimdshf_r"},
- {"011100", "Visit_ushr_asimdshf_r"},
- {"011110", "Visit_urshr_asimdshf_r"},
- {"0x1000", "Visit_ushr_asimdshf_r"},
- {"0x1010", "Visit_urshr_asimdshf_r"},
+ { {"0000x0"_b, "mvni_asimdimm_l_sl"},
+ {"00x100"_b, "ushr_asimdshf_r"},
+ {"00x110"_b, "urshr_asimdshf_r"},
+ {"010x00"_b, "ushr_asimdshf_r"},
+ {"010x10"_b, "urshr_asimdshf_r"},
+ {"011100"_b, "ushr_asimdshf_r"},
+ {"011110"_b, "urshr_asimdshf_r"},
+ {"0x1000"_b, "ushr_asimdshf_r"},
+ {"0x1010"_b, "urshr_asimdshf_r"},
},
},
- { "Decode_skpjrp",
+ { "_skpjrp",
{23, 22, 12},
- { {"000", "Decode_xzyylk"},
- {"001", "Decode_hpgqlp"},
- {"010", "Decode_qnsxkj"},
- {"011", "Decode_nnlvqz"},
- {"110", "Decode_vylhvl"},
- {"111", "Decode_stgkpy"},
+ { {"000"_b, "_xzyylk"},
+ {"001"_b, "_hpgqlp"},
+ {"010"_b, "_qnsxkj"},
+ {"011"_b, "_nnlvqz"},
+ {"110"_b, "_vylhvl"},
+ {"111"_b, "_stgkpy"},
},
},
- { "Decode_slhpgp",
+ { "_slhpgp",
{23},
- { {"0", "Visit_facge_asimdsame_only"},
- {"1", "Visit_facgt_asimdsame_only"},
+ { {"0"_b, "facge_asimdsame_only"},
+ {"1"_b, "facgt_asimdsame_only"},
},
},
- { "Decode_sllkpt",
+ { "_sllkpt",
{13, 12},
- { {"10", "Visit_lsrv_32_dp_2src"},
+ { {"10"_b, "lsrv_32_dp_2src"},
},
},
- { "Decode_slnkst",
+ { "_slnkst",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_fcvtmu_asimdmiscfp16_r"},
- {"0x00001", "Visit_fcvtmu_asimdmisc_r"},
- {"1111001", "Visit_fcvtzu_asimdmiscfp16_r"},
- {"1x00001", "Visit_fcvtzu_asimdmisc_r"},
- {"xx00000", "Visit_neg_asimdmisc_r"},
+ { {"0111001"_b, "fcvtmu_asimdmiscfp16_r"},
+ {"0x00001"_b, "fcvtmu_asimdmisc_r"},
+ {"1111001"_b, "fcvtzu_asimdmiscfp16_r"},
+ {"1x00001"_b, "fcvtzu_asimdmisc_r"},
+ {"xx00000"_b, "neg_asimdmisc_r"},
},
},
- { "Decode_sltqpy",
+ { "_sltqpy",
{30, 23, 22, 13, 12, 11, 10},
- { {"000xx10", "Visit_strb_32b_ldst_regoff"},
- {"001xx10", "Visit_ldrb_32b_ldst_regoff"},
- {"0100000", "Visit_ldaprb_32l_memop"},
- {"010xx10", "Visit_ldrsb_64b_ldst_regoff"},
- {"011xx10", "Visit_ldrsb_32b_ldst_regoff"},
- {"100xx10", "Visit_strh_32_ldst_regoff"},
- {"101xx10", "Visit_ldrh_32_ldst_regoff"},
- {"1100000", "Visit_ldaprh_32l_memop"},
- {"110xx10", "Visit_ldrsh_64_ldst_regoff"},
- {"111xx10", "Visit_ldrsh_32_ldst_regoff"},
+ { {"000xx10"_b, "strb_32b_ldst_regoff"},
+ {"001xx10"_b, "ldrb_32b_ldst_regoff"},
+ {"0100000"_b, "ldaprb_32l_memop"},
+ {"010xx10"_b, "ldrsb_64b_ldst_regoff"},
+ {"011xx10"_b, "ldrsb_32b_ldst_regoff"},
+ {"100xx10"_b, "strh_32_ldst_regoff"},
+ {"101xx10"_b, "ldrh_32_ldst_regoff"},
+ {"1100000"_b, "ldaprh_32l_memop"},
+ {"110xx10"_b, "ldrsh_64_ldst_regoff"},
+ {"111xx10"_b, "ldrsh_32_ldst_regoff"},
},
},
- { "Decode_smplhv",
+ { "_smplhv",
{10},
- { {"0", "Visit_braa_64p_branch_reg"},
- {"1", "Visit_brab_64p_branch_reg"},
+ { {"0"_b, "braa_64p_branch_reg"},
+ {"1"_b, "brab_64p_branch_reg"},
},
},
- { "Decode_smqvrs",
+ { "_smqvrs",
{18, 17},
- { {"00", "Visit_st1_asisdlse_r1_1v"},
+ { {"00"_b, "st1_asisdlse_r1_1v"},
},
},
- { "Decode_smrtxq",
+ { "_smrtxq",
{13, 12},
- { {"00", "Visit_sbcs_32_addsub_carry"},
+ { {"00"_b, "sbcs_32_addsub_carry"},
},
},
- { "Decode_snjpvy",
+ { "_snjpvy",
{23, 22, 13, 12, 11, 10},
- { {"0001x0", "Visit_fmulx_asimdelem_rh_h"},
- {"0x0001", "Visit_sqshrun_asimdshf_n"},
- {"0x0011", "Visit_sqrshrun_asimdshf_n"},
- {"0x0101", "Visit_uqshrn_asimdshf_n"},
- {"0x0111", "Visit_uqrshrn_asimdshf_n"},
- {"0x1001", "Visit_ushll_asimdshf_l"},
- {"1000x0", "Visit_fmlal2_asimdelem_lh"},
- {"1x01x0", "Visit_fmulx_asimdelem_r_sd"},
- {"xx10x0", "Visit_umull_asimdelem_l"},
+ { {"0001x0"_b, "fmulx_asimdelem_rh_h"},
+ {"0x0001"_b, "sqshrun_asimdshf_n"},
+ {"0x0011"_b, "sqrshrun_asimdshf_n"},
+ {"0x0101"_b, "uqshrn_asimdshf_n"},
+ {"0x0111"_b, "uqrshrn_asimdshf_n"},
+ {"0x1001"_b, "ushll_asimdshf_l"},
+ {"1000x0"_b, "fmlal2_asimdelem_lh"},
+ {"1x01x0"_b, "fmulx_asimdelem_r_sd"},
+ {"xx10x0"_b, "umull_asimdelem_l"},
},
},
- { "Decode_snkqvp",
+ { "_snkqvp",
{23, 22, 20, 19, 18, 17, 16, 13, 12, 11},
- { {"0011111001", "Decode_gkpvxz"},
+ { {"0011111001"_b, "_gkpvxz"},
},
},
- { "Decode_sntyqy",
+ { "_sntyqy",
{4},
- { {"0", "Visit_cmphs_p_p_zi"},
- {"1", "Visit_cmphi_p_p_zi"},
+ { {"0"_b, "cmphs_p_p_zi"},
+ {"1"_b, "cmphi_p_p_zi"},
},
},
- { "Decode_sntzjg",
+ { "_sntzjg",
{23, 22, 11, 10},
- { {"0000", "Decode_qssyls"},
- {"0001", "Visit_stg_64spost_ldsttags"},
- {"0010", "Visit_stg_64soffset_ldsttags"},
- {"0011", "Visit_stg_64spre_ldsttags"},
- {"0100", "Visit_ldg_64loffset_ldsttags"},
- {"0101", "Visit_stzg_64spost_ldsttags"},
- {"0110", "Visit_stzg_64soffset_ldsttags"},
- {"0111", "Visit_stzg_64spre_ldsttags"},
- {"1000", "Decode_kyxqgg"},
- {"1001", "Visit_st2g_64spost_ldsttags"},
- {"1010", "Visit_st2g_64soffset_ldsttags"},
- {"1011", "Visit_st2g_64spre_ldsttags"},
- {"1100", "Decode_stjrgx"},
- {"1101", "Visit_stz2g_64spost_ldsttags"},
- {"1110", "Visit_stz2g_64soffset_ldsttags"},
- {"1111", "Visit_stz2g_64spre_ldsttags"},
+ { {"0000"_b, "_qssyls"},
+ {"0001"_b, "stg_64spost_ldsttags"},
+ {"0010"_b, "stg_64soffset_ldsttags"},
+ {"0011"_b, "stg_64spre_ldsttags"},
+ {"0100"_b, "ldg_64loffset_ldsttags"},
+ {"0101"_b, "stzg_64spost_ldsttags"},
+ {"0110"_b, "stzg_64soffset_ldsttags"},
+ {"0111"_b, "stzg_64spre_ldsttags"},
+ {"1000"_b, "_kyxqgg"},
+ {"1001"_b, "st2g_64spost_ldsttags"},
+ {"1010"_b, "st2g_64soffset_ldsttags"},
+ {"1011"_b, "st2g_64spre_ldsttags"},
+ {"1100"_b, "_stjrgx"},
+ {"1101"_b, "stz2g_64spost_ldsttags"},
+ {"1110"_b, "stz2g_64soffset_ldsttags"},
+ {"1111"_b, "stz2g_64spre_ldsttags"},
},
},
- { "Decode_spglxn",
+ { "_spglxn",
{4, 3, 2, 1, 0},
- { {"11111", "Decode_yqmvxk"},
+ { {"11111"_b, "_yqmvxk"},
},
},
- { "Decode_sphpkr",
+ { "_sphpkr",
{4, 3, 2, 1, 0},
- { {"11111", "Decode_thsxvg"},
+ { {"11111"_b, "_thsxvg"},
},
},
- { "Decode_spjjkg",
+ { "_spjjkg",
{23, 22, 13, 12, 11, 10},
- { {"0011x0", "Visit_sudot_asimdelem_d"},
- {"0111x0", "Visit_bfdot_asimdelem_e"},
- {"0x1001", "Visit_scvtf_asimdshf_c"},
- {"0x1111", "Visit_fcvtzs_asimdshf_c"},
- {"1011x0", "Visit_usdot_asimdelem_d"},
- {"1111x0", "Visit_bfmlal_asimdelem_f"},
- {"xx00x0", "Visit_sqdmulh_asimdelem_r"},
- {"xx01x0", "Visit_sqrdmulh_asimdelem_r"},
- {"xx10x0", "Visit_sdot_asimdelem_d"},
+ { {"0011x0"_b, "sudot_asimdelem_d"},
+ {"0111x0"_b, "bfdot_asimdelem_e"},
+ {"0x1001"_b, "scvtf_asimdshf_c"},
+ {"0x1111"_b, "fcvtzs_asimdshf_c"},
+ {"1011x0"_b, "usdot_asimdelem_d"},
+ {"1111x0"_b, "bfmlal_asimdelem_f"},
+ {"xx00x0"_b, "sqdmulh_asimdelem_r"},
+ {"xx01x0"_b, "sqrdmulh_asimdelem_r"},
+ {"xx10x0"_b, "sdot_asimdelem_d"},
},
},
- { "Decode_spmkmm",
+ { "_spmkmm",
{30, 19, 18, 17, 16, 10},
- { {"110001", "Visit_ins_asimdins_iv_v"},
- {"1x1001", "Visit_ins_asimdins_iv_v"},
- {"1xx101", "Visit_ins_asimdins_iv_v"},
- {"1xxx11", "Visit_ins_asimdins_iv_v"},
- {"xxxxx0", "Visit_ext_asimdext_only"},
+ { {"110001"_b, "ins_asimdins_iv_v"},
+ {"1x1001"_b, "ins_asimdins_iv_v"},
+ {"1xx101"_b, "ins_asimdins_iv_v"},
+ {"1xxx11"_b, "ins_asimdins_iv_v"},
+ {"xxxxx0"_b, "ext_asimdext_only"},
},
},
- { "Decode_spzgkt",
+ { "_spzgkt",
{23, 22, 13, 12, 11, 10},
- { {"0x1001", "Visit_ucvtf_asimdshf_c"},
- {"0x1111", "Visit_fcvtzu_asimdshf_c"},
- {"1000x0", "Visit_fmlsl2_asimdelem_lh"},
- {"xx01x0", "Visit_sqrdmlah_asimdelem_r"},
- {"xx10x0", "Visit_udot_asimdelem_d"},
- {"xx11x0", "Visit_sqrdmlsh_asimdelem_r"},
+ { {"0x1001"_b, "ucvtf_asimdshf_c"},
+ {"0x1111"_b, "fcvtzu_asimdshf_c"},
+ {"1000x0"_b, "fmlsl2_asimdelem_lh"},
+ {"xx01x0"_b, "sqrdmlah_asimdelem_r"},
+ {"xx10x0"_b, "udot_asimdelem_d"},
+ {"xx11x0"_b, "sqrdmlsh_asimdelem_r"},
},
},
- { "Decode_sqgjmn",
+ { "_sqgjmn",
{20, 9},
- { {"00", "Decode_mxgykv"},
+ { {"00"_b, "_mxgykv"},
},
},
- { "Decode_sqgxzn",
+ { "_sqgxzn",
{9, 8, 7, 6, 5},
- { {"11111", "Visit_paciza_64z_dp_1src"},
+ { {"11111"_b, "paciza_64z_dp_1src"},
},
},
- { "Decode_sqjpsl",
+ { "_sqjpsl",
{30, 13, 12, 11, 10},
- { {"10001", "Visit_sqrdmlah_asisdsame2_only"},
- {"10011", "Visit_sqrdmlsh_asisdsame2_only"},
+ { {"10001"_b, "sqrdmlah_asisdsame2_only"},
+ {"10011"_b, "sqrdmlsh_asisdsame2_only"},
},
},
- { "Decode_sqpjtr",
+ { "_sqpjtr",
{20, 18, 17},
- { {"000", "Decode_nllnsg"},
+ { {"000"_b, "_nllnsg"},
},
},
- { "Decode_srggzy",
+ { "_srggzy",
{19},
- { {"0", "Decode_xqgxjp"},
- {"1", "Visit_sysl_rc_systeminstrs"},
+ { {"0"_b, "_xqgxjp"},
+ {"1"_b, "sysl_rc_systeminstrs"},
},
},
- { "Decode_srglgl",
+ { "_srglgl",
{18, 17},
- { {"0x", "Visit_st3_asisdlsop_sx3_r3s"},
- {"10", "Visit_st3_asisdlsop_sx3_r3s"},
- {"11", "Visit_st3_asisdlsop_s3_i3s"},
+ { {"0x"_b, "st3_asisdlsop_sx3_r3s"},
+ {"10"_b, "st3_asisdlsop_sx3_r3s"},
+ {"11"_b, "st3_asisdlsop_s3_i3s"},
},
},
- { "Decode_srmhjk",
+ { "_srmhjk",
{30},
- { {"0", "Visit_ldr_s_loadlit"},
- {"1", "Visit_ldr_d_loadlit"},
+ { {"0"_b, "ldr_s_loadlit"},
+ {"1"_b, "ldr_d_loadlit"},
},
},
- { "Decode_srmhlk",
+ { "_srmhlk",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_uaddlp_asimdmisc_p"},
- {"00001", "Visit_sqxtun_asimdmisc_n"},
+ { {"00000"_b, "uaddlp_asimdmisc_p"},
+ {"00001"_b, "sqxtun_asimdmisc_n"},
},
},
- { "Decode_srvnql",
+ { "_srvnql",
{18, 17, 12},
- { {"0x0", "Visit_ld1_asisdlsop_dx1_r1d"},
- {"100", "Visit_ld1_asisdlsop_dx1_r1d"},
- {"110", "Visit_ld1_asisdlsop_d1_i1d"},
+ { {"0x0"_b, "ld1_asisdlsop_dx1_r1d"},
+ {"100"_b, "ld1_asisdlsop_dx1_r1d"},
+ {"110"_b, "ld1_asisdlsop_d1_i1d"},
},
},
- { "Decode_stgkpy",
+ { "_stgkpy",
{9, 8, 7, 6, 5},
- { {"00000", "Visit_fmov_h_floatimm"},
+ { {"00000"_b, "fmov_h_floatimm"},
},
},
- { "Decode_stjrgx",
+ { "_stjrgx",
{20, 19, 18, 17, 16, 13, 12},
- { {"0000000", "Visit_ldgm_64bulk_ldsttags"},
+ { {"0000000"_b, "ldgm_64bulk_ldsttags"},
},
},
- { "Decode_stqmps",
+ { "_stqmps",
{12},
- { {"0", "Visit_ld3_asisdlsop_dx3_r3d"},
+ { {"0"_b, "ld3_asisdlsop_dx3_r3d"},
},
},
- { "Decode_strkph",
+ { "_strkph",
{23, 22},
- { {"00", "Visit_tbl_asimdtbl_l2_2"},
+ { {"00"_b, "tbl_asimdtbl_l2_2"},
},
},
- { "Decode_svnyyx",
+ { "_svnyyx",
{13, 12},
- { {"00", "Visit_adcs_32_addsub_carry"},
+ { {"00"_b, "adcs_32_addsub_carry"},
},
},
- { "Decode_svrnxq",
+ { "_svrnxq",
{12},
- { {"0", "Visit_st3_asisdlsop_dx3_r3d"},
+ { {"0"_b, "st3_asisdlsop_dx3_r3d"},
},
},
- { "Decode_svvyrz",
+ { "_svvyrz",
{23, 22, 20, 19, 18, 17, 16},
- { {"00xxxxx", "Visit_addvl_r_ri"},
- {"01xxxxx", "Visit_addpl_r_ri"},
- {"1011111", "Visit_rdvl_r_i"},
+ { {"00xxxxx"_b, "addvl_r_ri"},
+ {"01xxxxx"_b, "addpl_r_ri"},
+ {"1011111"_b, "rdvl_r_i"},
},
},
- { "Decode_sxnkrh",
+ { "_sxnkrh",
{23},
- { {"1", "Decode_xxkvsy"},
+ { {"1"_b, "_xxkvsy"},
},
},
- { "Decode_sxpvym",
+ { "_sxpvym",
{30, 23, 22, 13},
- { {"0000", "Visit_ldnt1sb_z_p_ar_s_x32_unscaled"},
- {"0001", "Visit_ldnt1b_z_p_ar_s_x32_unscaled"},
- {"0010", "Visit_ld1rb_z_p_bi_u8"},
- {"0011", "Visit_ld1rb_z_p_bi_u16"},
- {"0100", "Visit_ldnt1sh_z_p_ar_s_x32_unscaled"},
- {"0101", "Visit_ldnt1h_z_p_ar_s_x32_unscaled"},
- {"0110", "Visit_ld1rsw_z_p_bi_s64"},
- {"0111", "Visit_ld1rh_z_p_bi_u16"},
- {"1000", "Visit_ldnt1sb_z_p_ar_d_64_unscaled"},
- {"1010", "Visit_ld1sb_z_p_bz_d_64_unscaled"},
- {"1011", "Visit_ldff1sb_z_p_bz_d_64_unscaled"},
- {"1100", "Visit_ldnt1sh_z_p_ar_d_64_unscaled"},
- {"1110", "Visit_ld1sh_z_p_bz_d_64_unscaled"},
- {"1111", "Visit_ldff1sh_z_p_bz_d_64_unscaled"},
+ { {"0000"_b, "ldnt1sb_z_p_ar_s_x32_unscaled"},
+ {"0001"_b, "ldnt1b_z_p_ar_s_x32_unscaled"},
+ {"0010"_b, "ld1rb_z_p_bi_u8"},
+ {"0011"_b, "ld1rb_z_p_bi_u16"},
+ {"0100"_b, "ldnt1sh_z_p_ar_s_x32_unscaled"},
+ {"0101"_b, "ldnt1h_z_p_ar_s_x32_unscaled"},
+ {"0110"_b, "ld1rsw_z_p_bi_s64"},
+ {"0111"_b, "ld1rh_z_p_bi_u16"},
+ {"1000"_b, "ldnt1sb_z_p_ar_d_64_unscaled"},
+ {"1010"_b, "ld1sb_z_p_bz_d_64_unscaled"},
+ {"1011"_b, "ldff1sb_z_p_bz_d_64_unscaled"},
+ {"1100"_b, "ldnt1sh_z_p_ar_d_64_unscaled"},
+ {"1110"_b, "ld1sh_z_p_bz_d_64_unscaled"},
+ {"1111"_b, "ldff1sh_z_p_bz_d_64_unscaled"},
},
},
- { "Decode_syktsg",
+ { "_syktsg",
{13, 12},
- { {"00", "Visit_udiv_64_dp_2src"},
- {"10", "Visit_asrv_64_dp_2src"},
+ { {"00"_b, "udiv_64_dp_2src"},
+ {"10"_b, "asrv_64_dp_2src"},
},
},
- { "Decode_syzjtz",
+ { "_syzjtz",
{13, 12, 10},
- { {"010", "Visit_sqrdmlah_asisdelem_r"},
- {"101", "Decode_jqnglz"},
- {"110", "Visit_sqrdmlsh_asisdelem_r"},
- {"111", "Decode_zslsvj"},
+ { {"010"_b, "sqrdmlah_asisdelem_r"},
+ {"101"_b, "_jqnglz"},
+ {"110"_b, "sqrdmlsh_asisdelem_r"},
+ {"111"_b, "_zslsvj"},
},
},
- { "Decode_szttjy",
+ { "_szttjy",
{30, 23, 22, 19, 18, 17, 16},
- { {"00000x1", "Visit_umov_asimdins_w_w"},
- {"0000x10", "Visit_umov_asimdins_w_w"},
- {"00010xx", "Visit_umov_asimdins_w_w"},
- {"0001110", "Visit_umov_asimdins_w_w"},
- {"000x10x", "Visit_umov_asimdins_w_w"},
- {"000x111", "Visit_umov_asimdins_w_w"},
- {"1001000", "Visit_umov_asimdins_x_x"},
- {"x01xxxx", "Visit_frecps_asimdsamefp16_only"},
- {"x11xxxx", "Visit_frsqrts_asimdsamefp16_only"},
+ { {"00000x1"_b, "umov_asimdins_w_w"},
+ {"0000x10"_b, "umov_asimdins_w_w"},
+ {"00010xx"_b, "umov_asimdins_w_w"},
+ {"0001110"_b, "umov_asimdins_w_w"},
+ {"000x10x"_b, "umov_asimdins_w_w"},
+ {"000x111"_b, "umov_asimdins_w_w"},
+ {"1001000"_b, "umov_asimdins_x_x"},
+ {"x01xxxx"_b, "frecps_asimdsamefp16_only"},
+ {"x11xxxx"_b, "frsqrts_asimdsamefp16_only"},
},
},
- { "Decode_tgmljr",
+ { "_tgmljr",
{23, 22, 20, 19, 12, 11},
- { {"000000", "Visit_movi_asimdimm_n_b"},
- {"000010", "Visit_fmov_asimdimm_s_s"},
- {"000011", "Visit_fmov_asimdimm_h_h"},
- {"00x100", "Visit_scvtf_asimdshf_c"},
- {"00x111", "Visit_fcvtzs_asimdshf_c"},
- {"010x00", "Visit_scvtf_asimdshf_c"},
- {"010x11", "Visit_fcvtzs_asimdshf_c"},
- {"011100", "Visit_scvtf_asimdshf_c"},
- {"011111", "Visit_fcvtzs_asimdshf_c"},
- {"0x1000", "Visit_scvtf_asimdshf_c"},
- {"0x1011", "Visit_fcvtzs_asimdshf_c"},
+ { {"000000"_b, "movi_asimdimm_n_b"},
+ {"000010"_b, "fmov_asimdimm_s_s"},
+ {"000011"_b, "fmov_asimdimm_h_h"},
+ {"00x100"_b, "scvtf_asimdshf_c"},
+ {"00x111"_b, "fcvtzs_asimdshf_c"},
+ {"010x00"_b, "scvtf_asimdshf_c"},
+ {"010x11"_b, "fcvtzs_asimdshf_c"},
+ {"011100"_b, "scvtf_asimdshf_c"},
+ {"011111"_b, "fcvtzs_asimdshf_c"},
+ {"0x1000"_b, "scvtf_asimdshf_c"},
+ {"0x1011"_b, "fcvtzs_asimdshf_c"},
},
},
- { "Decode_tgqsyg",
+ { "_tgqsyg",
{22},
- { {"0", "Visit_prfm_p_ldst_regoff"},
+ { {"0"_b, "prfm_p_ldst_regoff"},
},
},
- { "Decode_thqvrp",
+ { "_thqvrp",
{17},
- { {"0", "Visit_st1_asisdlsep_r2_r2"},
- {"1", "Visit_st1_asisdlsep_i2_i2"},
+ { {"0"_b, "st1_asisdlsep_r2_r2"},
+ {"1"_b, "st1_asisdlsep_i2_i2"},
},
},
- { "Decode_thrxph",
+ { "_thrxph",
{23, 22, 10},
- { {"100", "Visit_umlalb_z_zzzi_s"},
- {"101", "Visit_umlalt_z_zzzi_s"},
- {"110", "Visit_umlalb_z_zzzi_d"},
- {"111", "Visit_umlalt_z_zzzi_d"},
+ { {"100"_b, "umlalb_z_zzzi_s"},
+ {"101"_b, "umlalt_z_zzzi_s"},
+ {"110"_b, "umlalb_z_zzzi_d"},
+ {"111"_b, "umlalt_z_zzzi_d"},
},
},
- { "Decode_thsxvg",
+ { "_thsxvg",
{11, 10, 9, 8, 7, 6},
- { {"000010", "Visit_ssbb_only_barriers"},
- {"010010", "Visit_pssbb_only_barriers"},
- {"0x1010", "Visit_dsb_bo_barriers"},
- {"0xx110", "Visit_dsb_bo_barriers"},
- {"1xxx10", "Visit_dsb_bo_barriers"},
- {"xxxx01", "Visit_clrex_bn_barriers"},
- {"xxxx11", "Visit_isb_bi_barriers"},
+ { {"000010"_b, "ssbb_only_barriers"},
+ {"010010"_b, "pssbb_only_barriers"},
+ {"0x1010"_b, "dsb_bo_barriers"},
+ {"0xx110"_b, "dsb_bo_barriers"},
+ {"1xxx10"_b, "dsb_bo_barriers"},
+ {"xxxx01"_b, "clrex_bn_barriers"},
+ {"xxxx11"_b, "isb_bi_barriers"},
},
},
- { "Decode_thvvzp",
+ { "_thvvzp",
{18, 17, 12},
- { {"0x0", "Visit_st1_asisdlsop_dx1_r1d"},
- {"100", "Visit_st1_asisdlsop_dx1_r1d"},
- {"110", "Visit_st1_asisdlsop_d1_i1d"},
+ { {"0x0"_b, "st1_asisdlsop_dx1_r1d"},
+ {"100"_b, "st1_asisdlsop_dx1_r1d"},
+ {"110"_b, "st1_asisdlsop_d1_i1d"},
},
},
- { "Decode_thvxym",
+ { "_thvxym",
{20},
- { {"0", "Decode_prkmty"},
- {"1", "Decode_pjgkjs"},
+ { {"0"_b, "_prkmty"},
+ {"1"_b, "_pjgkjs"},
},
},
- { "Decode_tjktkm",
+ { "_tjktkm",
{30},
- { {"1", "Decode_gntpyh"},
+ { {"1"_b, "_gntpyh"},
},
},
- { "Decode_tjltls",
+ { "_tjltls",
{18, 17},
- { {"0x", "Visit_st1_asisdlsep_r1_r1"},
- {"10", "Visit_st1_asisdlsep_r1_r1"},
- {"11", "Visit_st1_asisdlsep_i1_i1"},
+ { {"0x"_b, "st1_asisdlsep_r1_r1"},
+ {"10"_b, "st1_asisdlsep_r1_r1"},
+ {"11"_b, "st1_asisdlsep_i1_i1"},
},
},
- { "Decode_tjpjng",
+ { "_tjpjng",
{23, 22, 13, 12},
- { {"0000", "Visit_fmax_s_floatdp2"},
- {"0001", "Visit_fmin_s_floatdp2"},
- {"0010", "Visit_fmaxnm_s_floatdp2"},
- {"0011", "Visit_fminnm_s_floatdp2"},
- {"0100", "Visit_fmax_d_floatdp2"},
- {"0101", "Visit_fmin_d_floatdp2"},
- {"0110", "Visit_fmaxnm_d_floatdp2"},
- {"0111", "Visit_fminnm_d_floatdp2"},
- {"1100", "Visit_fmax_h_floatdp2"},
- {"1101", "Visit_fmin_h_floatdp2"},
- {"1110", "Visit_fmaxnm_h_floatdp2"},
- {"1111", "Visit_fminnm_h_floatdp2"},
+ { {"0000"_b, "fmax_s_floatdp2"},
+ {"0001"_b, "fmin_s_floatdp2"},
+ {"0010"_b, "fmaxnm_s_floatdp2"},
+ {"0011"_b, "fminnm_s_floatdp2"},
+ {"0100"_b, "fmax_d_floatdp2"},
+ {"0101"_b, "fmin_d_floatdp2"},
+ {"0110"_b, "fmaxnm_d_floatdp2"},
+ {"0111"_b, "fminnm_d_floatdp2"},
+ {"1100"_b, "fmax_h_floatdp2"},
+ {"1101"_b, "fmin_h_floatdp2"},
+ {"1110"_b, "fmaxnm_h_floatdp2"},
+ {"1111"_b, "fminnm_h_floatdp2"},
},
},
- { "Decode_tjtgjy",
+ { "_tjtgjy",
{20, 19, 18, 17},
- { {"0000", "Decode_gjsnly"},
+ { {"0000"_b, "_gjsnly"},
},
},
- { "Decode_tjzqnp",
+ { "_tjzqnp",
{30, 23, 22, 20, 13},
- { {"00001", "Visit_ldnt1b_z_p_bi_contiguous"},
- {"000x0", "Visit_ldnt1b_z_p_br_contiguous"},
- {"00101", "Visit_ld3b_z_p_bi_contiguous"},
- {"001x0", "Visit_ld3b_z_p_br_contiguous"},
- {"01001", "Visit_ldnt1h_z_p_bi_contiguous"},
- {"010x0", "Visit_ldnt1h_z_p_br_contiguous"},
- {"01101", "Visit_ld3h_z_p_bi_contiguous"},
- {"011x0", "Visit_ld3h_z_p_br_contiguous"},
- {"10011", "Visit_stnt1b_z_p_bi_contiguous"},
- {"100x0", "Visit_st1b_z_p_bz_d_x32_unscaled"},
- {"10111", "Visit_st3b_z_p_bi_contiguous"},
- {"101x0", "Visit_st1b_z_p_bz_s_x32_unscaled"},
- {"10x01", "Visit_st1b_z_p_bi"},
- {"11011", "Visit_stnt1h_z_p_bi_contiguous"},
- {"110x0", "Visit_st1h_z_p_bz_d_x32_unscaled"},
- {"11111", "Visit_st3h_z_p_bi_contiguous"},
- {"111x0", "Visit_st1h_z_p_bz_s_x32_unscaled"},
- {"11x01", "Visit_st1h_z_p_bi"},
+ { {"00001"_b, "ldnt1b_z_p_bi_contiguous"},
+ {"000x0"_b, "ldnt1b_z_p_br_contiguous"},
+ {"00101"_b, "ld3b_z_p_bi_contiguous"},
+ {"001x0"_b, "ld3b_z_p_br_contiguous"},
+ {"01001"_b, "ldnt1h_z_p_bi_contiguous"},
+ {"010x0"_b, "ldnt1h_z_p_br_contiguous"},
+ {"01101"_b, "ld3h_z_p_bi_contiguous"},
+ {"011x0"_b, "ld3h_z_p_br_contiguous"},
+ {"10011"_b, "stnt1b_z_p_bi_contiguous"},
+ {"100x0"_b, "st1b_z_p_bz_d_x32_unscaled"},
+ {"10111"_b, "st3b_z_p_bi_contiguous"},
+ {"101x0"_b, "st1b_z_p_bz_s_x32_unscaled"},
+ {"10x01"_b, "st1b_z_p_bi"},
+ {"11011"_b, "stnt1h_z_p_bi_contiguous"},
+ {"110x0"_b, "st1h_z_p_bz_d_x32_unscaled"},
+ {"11111"_b, "st3h_z_p_bi_contiguous"},
+ {"111x0"_b, "st1h_z_p_bz_s_x32_unscaled"},
+ {"11x01"_b, "st1h_z_p_bi"},
},
},
- { "Decode_tkjtgp",
+ { "_tkjtgp",
{30},
- { {"0", "Decode_sqgjmn"},
- {"1", "Decode_ztpryr"},
+ { {"0"_b, "_sqgjmn"},
+ {"1"_b, "_ztpryr"},
},
},
- { "Decode_tkzqqp",
+ { "_tkzqqp",
{4, 3, 2, 1, 0},
- { {"11111", "Decode_ntkqhk"},
+ { {"11111"_b, "_ntkqhk"},
},
},
- { "Decode_tlstgz",
+ { "_tlstgz",
{30, 23, 22},
- { {"000", "Visit_stlxp_sp32_ldstexcl"},
- {"001", "Visit_ldaxp_lp32_ldstexcl"},
- {"100", "Visit_stlxp_sp64_ldstexcl"},
- {"101", "Visit_ldaxp_lp64_ldstexcl"},
+ { {"000"_b, "stlxp_sp32_ldstexcl"},
+ {"001"_b, "ldaxp_lp32_ldstexcl"},
+ {"100"_b, "stlxp_sp64_ldstexcl"},
+ {"101"_b, "ldaxp_lp64_ldstexcl"},
},
},
- { "Decode_tlzlrj",
+ { "_tlzlrj",
{17},
- { {"0", "Visit_st2_asisdlso_b2_2b"},
+ { {"0"_b, "st2_asisdlso_b2_2b"},
},
},
- { "Decode_tmhlvh",
+ { "_tmhlvh",
{20, 9, 4},
- { {"000", "Visit_zip2_p_pp"},
+ { {"000"_b, "zip2_p_pp"},
},
},
- { "Decode_tmrnzq",
+ { "_tmrnzq",
{17},
- { {"0", "Visit_st2_asisdlsep_r2_r"},
- {"1", "Visit_st2_asisdlsep_i2_i"},
+ { {"0"_b, "st2_asisdlsep_r2_r"},
+ {"1"_b, "st2_asisdlsep_i2_i"},
},
},
- { "Decode_tmshps",
+ { "_tmshps",
{17},
- { {"0", "Visit_fmaxnmv_v_p_z"},
- {"1", "Visit_fmaxv_v_p_z"},
+ { {"0"_b, "fmaxnmv_v_p_z"},
+ {"1"_b, "fmaxv_v_p_z"},
},
},
- { "Decode_tmthqm",
+ { "_tmthqm",
{22},
- { {"0", "Visit_str_32_ldst_regoff"},
- {"1", "Visit_ldr_32_ldst_regoff"},
+ { {"0"_b, "str_32_ldst_regoff"},
+ {"1"_b, "ldr_32_ldst_regoff"},
},
},
- { "Decode_tmtnkq",
+ { "_tmtnkq",
{23, 18, 17, 16},
- { {"0000", "Visit_uqxtnb_z_zz"},
+ { {"0000"_b, "uqxtnb_z_zz"},
},
},
- { "Decode_tnhmpx",
+ { "_tnhmpx",
{30, 23, 22, 13, 12, 11, 10},
- { {"1011001", "Visit_fcmge_asisdsamefp16_only"},
- {"1011011", "Visit_facge_asisdsamefp16_only"},
- {"1110101", "Visit_fabd_asisdsamefp16_only"},
- {"1111001", "Visit_fcmgt_asisdsamefp16_only"},
- {"1111011", "Visit_facgt_asisdsamefp16_only"},
+ { {"1011001"_b, "fcmge_asisdsamefp16_only"},
+ {"1011011"_b, "facge_asisdsamefp16_only"},
+ {"1110101"_b, "fabd_asisdsamefp16_only"},
+ {"1111001"_b, "fcmgt_asisdsamefp16_only"},
+ {"1111011"_b, "facgt_asisdsamefp16_only"},
},
},
- { "Decode_tnrrjk",
+ { "_tnrrjk",
{30, 23, 22, 11, 10},
- { {"01000", "Visit_csel_32_condsel"},
- {"01001", "Visit_csinc_32_condsel"},
- {"11000", "Visit_csinv_32_condsel"},
- {"11001", "Visit_csneg_32_condsel"},
+ { {"01000"_b, "csel_32_condsel"},
+ {"01001"_b, "csinc_32_condsel"},
+ {"11000"_b, "csinv_32_condsel"},
+ {"11001"_b, "csneg_32_condsel"},
},
},
- { "Decode_tnxlnl",
+ { "_tnxlnl",
{13, 12},
- { {"00", "Visit_crc32x_64c_dp_2src"},
- {"01", "Visit_crc32cx_64c_dp_2src"},
+ { {"00"_b, "crc32x_64c_dp_2src"},
+ {"01"_b, "crc32cx_64c_dp_2src"},
},
},
- { "Decode_tnzytv",
+ { "_tnzytv",
{11, 10, 9, 8, 7, 6},
- { {"000000", "Visit_wfet_only_systeminstrswithreg"},
+ { {"000000"_b, "wfet_only_systeminstrswithreg"},
},
},
- { "Decode_tpkslq",
+ { "_tpkslq",
{30, 23, 22, 20, 13, 4},
- { {"00001x", "Visit_ld1rqw_z_p_bi_u32"},
- {"000x0x", "Visit_ld1rqw_z_p_br_contiguous"},
- {"01001x", "Visit_ld1rqd_z_p_bi_u64"},
- {"010x0x", "Visit_ld1rqd_z_p_br_contiguous"},
- {"100x1x", "Visit_stnt1w_z_p_ar_d_64_unscaled"},
- {"101x1x", "Visit_stnt1w_z_p_ar_s_x32_unscaled"},
- {"110x00", "Visit_str_p_bi"},
- {"110x1x", "Visit_stnt1d_z_p_ar_d_64_unscaled"},
+ { {"00001x"_b, "ld1rqw_z_p_bi_u32"},
+ {"000x0x"_b, "ld1rqw_z_p_br_contiguous"},
+ {"01001x"_b, "ld1rqd_z_p_bi_u64"},
+ {"010x0x"_b, "ld1rqd_z_p_br_contiguous"},
+ {"100x1x"_b, "stnt1w_z_p_ar_d_64_unscaled"},
+ {"101x1x"_b, "stnt1w_z_p_ar_s_x32_unscaled"},
+ {"110x00"_b, "str_p_bi"},
+ {"110x1x"_b, "stnt1d_z_p_ar_d_64_unscaled"},
},
},
- { "Decode_tpkzxg",
+ { "_tpkzxg",
{4},
- { {"0", "Visit_ccmp_64_condcmp_imm"},
+ { {"0"_b, "ccmp_64_condcmp_imm"},
},
},
- { "Decode_tpsylx",
+ { "_tpsylx",
{13},
- { {"0", "Decode_gjylrt"},
- {"1", "Decode_ygjslq"},
+ { {"0"_b, "_gjylrt"},
+ {"1"_b, "_ygjslq"},
},
},
- { "Decode_trlhgn",
+ { "_trlhgn",
{30, 23, 22, 11, 10},
- { {"00010", "Visit_str_b_ldst_regoff"},
- {"00110", "Visit_ldr_b_ldst_regoff"},
- {"01010", "Visit_str_q_ldst_regoff"},
- {"01110", "Visit_ldr_q_ldst_regoff"},
- {"10010", "Visit_str_h_ldst_regoff"},
- {"10110", "Visit_ldr_h_ldst_regoff"},
+ { {"00010"_b, "str_b_ldst_regoff"},
+ {"00110"_b, "ldr_b_ldst_regoff"},
+ {"01010"_b, "str_q_ldst_regoff"},
+ {"01110"_b, "ldr_q_ldst_regoff"},
+ {"10010"_b, "str_h_ldst_regoff"},
+ {"10110"_b, "ldr_h_ldst_regoff"},
},
},
- { "Decode_tsksxr",
+ { "_tsksxr",
{17},
- { {"0", "Visit_fminnmv_v_p_z"},
- {"1", "Visit_fminv_v_p_z"},
+ { {"0"_b, "fminnmv_v_p_z"},
+ {"1"_b, "fminv_v_p_z"},
},
},
- { "Decode_tssqsr",
+ { "_tssqsr",
{30},
- { {"1", "Decode_syzjtz"},
+ { {"1"_b, "_syzjtz"},
},
},
- { "Decode_tsvsgh",
+ { "_tsvsgh",
{17},
- { {"0", "Visit_st1_asisdlso_b1_1b"},
+ { {"0"_b, "st1_asisdlso_b1_1b"},
},
},
- { "Decode_tszvvk",
+ { "_tszvvk",
{18, 17, 12},
- { {"000", "Visit_ld2_asisdlso_d2_2d"},
+ { {"000"_b, "ld2_asisdlso_d2_2d"},
},
},
- { "Decode_ttplgp",
+ { "_ttplgp",
{12, 11, 10},
- { {"000", "Visit_sqincp_z_p_z"},
- {"010", "Visit_sqincp_r_p_r_sx"},
- {"011", "Visit_sqincp_r_p_r_x"},
- {"100", "Decode_zqmrhp"},
+ { {"000"_b, "sqincp_z_p_z"},
+ {"010"_b, "sqincp_r_p_r_sx"},
+ {"011"_b, "sqincp_r_p_r_x"},
+ {"100"_b, "_zqmrhp"},
},
},
- { "Decode_ttstyt",
+ { "_ttstyt",
{12, 10},
- { {"00", "Decode_rkqtvs"},
- {"01", "Decode_mtlhnl"},
- {"10", "Decode_zlmgyp"},
- {"11", "Decode_kjghlk"},
+ { {"00"_b, "_rkqtvs"},
+ {"01"_b, "_mtlhnl"},
+ {"10"_b, "_zlmgyp"},
+ {"11"_b, "_kjghlk"},
},
},
- { "Decode_tvgvvq",
+ { "_tvgvvq",
{30},
- { {"0", "Visit_cbnz_32_compbranch"},
+ { {"0"_b, "cbnz_32_compbranch"},
},
},
- { "Decode_tvsszp",
+ { "_tvsszp",
{23, 22},
- { {"00", "Visit_fmadd_s_floatdp3"},
- {"01", "Visit_fmadd_d_floatdp3"},
- {"11", "Visit_fmadd_h_floatdp3"},
+ { {"00"_b, "fmadd_s_floatdp3"},
+ {"01"_b, "fmadd_d_floatdp3"},
+ {"11"_b, "fmadd_h_floatdp3"},
},
},
- { "Decode_txhzxq",
+ { "_txhzxq",
{30, 22, 11},
- { {"000", "Decode_svnyyx"},
- {"001", "Decode_qsxpyq"},
- {"010", "Decode_pnqxjg"},
- {"011", "Decode_myrshl"},
- {"100", "Decode_smrtxq"},
- {"110", "Decode_ryglvl"},
- {"111", "Decode_qqsmlt"},
+ { {"000"_b, "_svnyyx"},
+ {"001"_b, "_qsxpyq"},
+ {"010"_b, "_pnqxjg"},
+ {"011"_b, "_myrshl"},
+ {"100"_b, "_smrtxq"},
+ {"110"_b, "_ryglvl"},
+ {"111"_b, "_qqsmlt"},
},
},
- { "Decode_txjyxr",
+ { "_txjyxr",
{18, 17},
- { {"0x", "Visit_ld1_asisdlsep_r1_r1"},
- {"10", "Visit_ld1_asisdlsep_r1_r1"},
- {"11", "Visit_ld1_asisdlsep_i1_i1"},
+ { {"0x"_b, "ld1_asisdlsep_r1_r1"},
+ {"10"_b, "ld1_asisdlsep_r1_r1"},
+ {"11"_b, "ld1_asisdlsep_i1_i1"},
},
},
- { "Decode_txnqzy",
+ { "_txnqzy",
{30, 23, 22},
- { {"000", "Visit_smsubl_64wa_dp_3src"},
- {"010", "Visit_umsubl_64wa_dp_3src"},
+ { {"000"_b, "smsubl_64wa_dp_3src"},
+ {"010"_b, "umsubl_64wa_dp_3src"},
},
},
- { "Decode_txsmts",
+ { "_txsmts",
{13, 12, 11, 10},
- { {"0000", "Visit_smlal_asimddiff_l"},
- {"0001", "Visit_add_asimdsame_only"},
- {"0010", "Decode_qhsplz"},
- {"0011", "Visit_cmtst_asimdsame_only"},
- {"0100", "Visit_sqdmlal_asimddiff_l"},
- {"0101", "Visit_mla_asimdsame_only"},
- {"0110", "Decode_yvxgrr"},
- {"0111", "Visit_mul_asimdsame_only"},
- {"1000", "Visit_smlsl_asimddiff_l"},
- {"1001", "Visit_smaxp_asimdsame_only"},
- {"1010", "Decode_mnxmst"},
- {"1011", "Visit_sminp_asimdsame_only"},
- {"1100", "Visit_sqdmlsl_asimddiff_l"},
- {"1101", "Visit_sqdmulh_asimdsame_only"},
- {"1110", "Decode_klkgqk"},
- {"1111", "Visit_addp_asimdsame_only"},
+ { {"0000"_b, "smlal_asimddiff_l"},
+ {"0001"_b, "add_asimdsame_only"},
+ {"0010"_b, "_qhsplz"},
+ {"0011"_b, "cmtst_asimdsame_only"},
+ {"0100"_b, "sqdmlal_asimddiff_l"},
+ {"0101"_b, "mla_asimdsame_only"},
+ {"0110"_b, "_yvxgrr"},
+ {"0111"_b, "mul_asimdsame_only"},
+ {"1000"_b, "smlsl_asimddiff_l"},
+ {"1001"_b, "smaxp_asimdsame_only"},
+ {"1010"_b, "_mnxmst"},
+ {"1011"_b, "sminp_asimdsame_only"},
+ {"1100"_b, "sqdmlsl_asimddiff_l"},
+ {"1101"_b, "sqdmulh_asimdsame_only"},
+ {"1110"_b, "_klkgqk"},
+ {"1111"_b, "addp_asimdsame_only"},
},
},
- { "Decode_txzxzs",
+ { "_txzxzs",
{23, 22, 20, 19, 18},
- { {"00000", "Visit_orr_z_zi"},
- {"01000", "Visit_eor_z_zi"},
- {"10000", "Visit_and_z_zi"},
- {"11000", "Visit_dupm_z_i"},
- {"xx1xx", "Visit_cpy_z_p_i"},
+ { {"00000"_b, "orr_z_zi"},
+ {"01000"_b, "eor_z_zi"},
+ {"10000"_b, "and_z_zi"},
+ {"11000"_b, "dupm_z_i"},
+ {"xx1xx"_b, "cpy_z_p_i"},
},
},
- { "Decode_tyjqvt",
+ { "_tyjqvt",
{18, 17},
- { {"00", "Visit_ld4_asisdlso_s4_4s"},
+ { {"00"_b, "ld4_asisdlso_s4_4s"},
},
},
- { "Decode_tylqpt",
+ { "_tylqpt",
{23, 22, 13},
- { {"000", "Visit_fmulx_asimdelem_rh_h"},
- {"1x0", "Visit_fmulx_asimdelem_r_sd"},
+ { {"000"_b, "fmulx_asimdelem_rh_h"},
+ {"1x0"_b, "fmulx_asimdelem_r_sd"},
},
},
- { "Decode_typysz",
+ { "_typysz",
{23, 22, 20, 19, 13, 11, 10},
- { {"00x1001", "Visit_sqshrn_asisdshf_n"},
- {"00x1011", "Visit_sqrshrn_asisdshf_n"},
- {"00xx0x0", "Visit_fmul_asisdelem_rh_h"},
- {"010x001", "Visit_sqshrn_asisdshf_n"},
- {"010x011", "Visit_sqrshrn_asisdshf_n"},
- {"0111001", "Visit_sqshrn_asisdshf_n"},
- {"0111011", "Visit_sqrshrn_asisdshf_n"},
- {"0x10001", "Visit_sqshrn_asisdshf_n"},
- {"0x10011", "Visit_sqrshrn_asisdshf_n"},
- {"1xxx0x0", "Visit_fmul_asisdelem_r_sd"},
- {"xxxx1x0", "Visit_sqdmull_asisdelem_l"},
+ { {"00x1001"_b, "sqshrn_asisdshf_n"},
+ {"00x1011"_b, "sqrshrn_asisdshf_n"},
+ {"00xx0x0"_b, "fmul_asisdelem_rh_h"},
+ {"010x001"_b, "sqshrn_asisdshf_n"},
+ {"010x011"_b, "sqrshrn_asisdshf_n"},
+ {"0111001"_b, "sqshrn_asisdshf_n"},
+ {"0111011"_b, "sqrshrn_asisdshf_n"},
+ {"0x10001"_b, "sqshrn_asisdshf_n"},
+ {"0x10011"_b, "sqrshrn_asisdshf_n"},
+ {"1xxx0x0"_b, "fmul_asisdelem_r_sd"},
+ {"xxxx1x0"_b, "sqdmull_asisdelem_l"},
},
},
- { "Decode_tytvjk",
+ { "_tytvjk",
{13, 12, 11},
- { {"000", "Decode_lylpyx"},
- {"001", "Decode_kyxrqg"},
- {"010", "Decode_zmkqxl"},
- {"011", "Decode_gngjxr"},
- {"100", "Decode_mlxtxs"},
- {"101", "Decode_mnmtql"},
- {"110", "Decode_xmxpnx"},
- {"111", "Decode_lkttgy"},
+ { {"000"_b, "_lylpyx"},
+ {"001"_b, "_kyxrqg"},
+ {"010"_b, "_zmkqxl"},
+ {"011"_b, "_gngjxr"},
+ {"100"_b, "_mlxtxs"},
+ {"101"_b, "_mnmtql"},
+ {"110"_b, "_xmxpnx"},
+ {"111"_b, "_lkttgy"},
},
},
- { "Decode_tzzhsk",
+ { "_tzzhsk",
{13, 12},
- { {"01", "Visit_sqdmlal_asisddiff_only"},
- {"11", "Visit_sqdmlsl_asisddiff_only"},
+ { {"01"_b, "sqdmlal_asisddiff_only"},
+ {"11"_b, "sqdmlsl_asisddiff_only"},
},
},
- { "Decode_tzzssm",
+ { "_tzzssm",
{12, 11, 10},
- { {"000", "Visit_histseg_z_zz"},
+ { {"000"_b, "histseg_z_zz"},
},
},
- { "Decode_tzzzxz",
+ { "_tzzzxz",
{30, 23, 22, 20, 19},
- { {"0xxxx", "Visit_bl_only_branch_imm"},
- {"10001", "Visit_sysl_rc_systeminstrs"},
- {"1001x", "Visit_mrs_rs_systemmove"},
+ { {"0xxxx"_b, "bl_only_branch_imm"},
+ {"10001"_b, "sysl_rc_systeminstrs"},
+ {"1001x"_b, "mrs_rs_systemmove"},
},
},
- { "Decode_vgrhsz",
+ { "_vgrhsz",
{30, 23, 11, 10},
- { {"0010", "Decode_hljrqn"},
- {"0100", "Decode_htnmls"},
- {"0110", "Decode_vxgzqy"},
- {"1000", "Decode_lpsxhz"},
- {"1001", "Visit_ldraa_64_ldst_pac"},
- {"1010", "Decode_jtqlhs"},
- {"1011", "Visit_ldraa_64w_ldst_pac"},
- {"1100", "Decode_yrlzqp"},
- {"1101", "Visit_ldrab_64_ldst_pac"},
- {"1110", "Decode_xyhxzt"},
- {"1111", "Visit_ldrab_64w_ldst_pac"},
+ { {"0010"_b, "_hljrqn"},
+ {"0100"_b, "_htnmls"},
+ {"0110"_b, "_vxgzqy"},
+ {"1000"_b, "_lpsxhz"},
+ {"1001"_b, "ldraa_64_ldst_pac"},
+ {"1010"_b, "_jtqlhs"},
+ {"1011"_b, "ldraa_64w_ldst_pac"},
+ {"1100"_b, "_yrlzqp"},
+ {"1101"_b, "ldrab_64_ldst_pac"},
+ {"1110"_b, "_xyhxzt"},
+ {"1111"_b, "ldrab_64w_ldst_pac"},
},
},
- { "Decode_vgrtjz",
+ { "_vgrtjz",
{12},
- { {"0", "Visit_sqdmulh_asimdelem_r"},
- {"1", "Visit_sqrdmulh_asimdelem_r"},
+ { {"0"_b, "sqdmulh_asimdelem_r"},
+ {"1"_b, "sqrdmulh_asimdelem_r"},
},
},
- { "Decode_vgtnjh",
+ { "_vgtnjh",
{23, 22, 20, 19, 18, 17, 16},
- { {"0001010", "Visit_fcvtxnt_z_p_z_d2s"},
- {"1001000", "Visit_fcvtnt_z_p_z_s2h"},
- {"1001001", "Visit_fcvtlt_z_p_z_h2s"},
- {"1001010", "Visit_bfcvtnt_z_p_z_s2bf"},
- {"1101010", "Visit_fcvtnt_z_p_z_d2s"},
- {"1101011", "Visit_fcvtlt_z_p_z_s2d"},
+ { {"0001010"_b, "fcvtxnt_z_p_z_d2s"},
+ {"1001000"_b, "fcvtnt_z_p_z_s2h"},
+ {"1001001"_b, "fcvtlt_z_p_z_h2s"},
+ {"1001010"_b, "bfcvtnt_z_p_z_s2bf"},
+ {"1101010"_b, "fcvtnt_z_p_z_d2s"},
+ {"1101011"_b, "fcvtlt_z_p_z_s2d"},
},
},
- { "Decode_vhhktl",
+ { "_vhhktl",
{18, 17},
- { {"0x", "Visit_st4_asisdlsop_sx4_r4s"},
- {"10", "Visit_st4_asisdlsop_sx4_r4s"},
- {"11", "Visit_st4_asisdlsop_s4_i4s"},
+ { {"0x"_b, "st4_asisdlsop_sx4_r4s"},
+ {"10"_b, "st4_asisdlsop_sx4_r4s"},
+ {"11"_b, "st4_asisdlsop_s4_i4s"},
},
},
- { "Decode_vhmsgj",
+ { "_vhmsgj",
{18, 17, 12},
- { {"000", "Visit_ld1_asisdlso_d1_1d"},
+ { {"000"_b, "ld1_asisdlso_d1_1d"},
},
},
- { "Decode_vjlnqj",
+ { "_vjlnqj",
{23, 22, 13, 12},
- { {"0000", "Visit_fnmul_s_floatdp2"},
- {"0100", "Visit_fnmul_d_floatdp2"},
- {"1100", "Visit_fnmul_h_floatdp2"},
+ { {"0000"_b, "fnmul_s_floatdp2"},
+ {"0100"_b, "fnmul_d_floatdp2"},
+ {"1100"_b, "fnmul_h_floatdp2"},
},
},
- { "Decode_vjmklj",
+ { "_vjmklj",
{23, 22},
- { {"10", "Visit_sqrdcmlah_z_zzzi_h"},
- {"11", "Visit_sqrdcmlah_z_zzzi_s"},
+ { {"10"_b, "sqrdcmlah_z_zzzi_h"},
+ {"11"_b, "sqrdcmlah_z_zzzi_s"},
},
},
- { "Decode_vjqsqs",
+ { "_vjqsqs",
{30},
- { {"0", "Visit_and_32_log_shift"},
- {"1", "Visit_eor_32_log_shift"},
+ { {"0"_b, "and_32_log_shift"},
+ {"1"_b, "eor_32_log_shift"},
},
},
- { "Decode_vjxqhp",
+ { "_vjxqhp",
{23, 22, 20, 19, 18, 16, 13},
- { {"0000000", "Decode_jlrvpl"},
- {"0000001", "Decode_pmkxlj"},
- {"0100000", "Decode_qmgtyq"},
- {"0100001", "Decode_qhxzxl"},
- {"100xxx0", "Visit_st2_asisdlsep_r2_r"},
- {"100xxx1", "Visit_st1_asisdlsep_r2_r2"},
- {"1010xx0", "Visit_st2_asisdlsep_r2_r"},
- {"1010xx1", "Visit_st1_asisdlsep_r2_r2"},
- {"10110x0", "Visit_st2_asisdlsep_r2_r"},
- {"10110x1", "Visit_st1_asisdlsep_r2_r2"},
- {"1011100", "Visit_st2_asisdlsep_r2_r"},
- {"1011101", "Visit_st1_asisdlsep_r2_r2"},
- {"1011110", "Decode_tmrnzq"},
- {"1011111", "Decode_thqvrp"},
- {"110xxx0", "Visit_ld2_asisdlsep_r2_r"},
- {"110xxx1", "Visit_ld1_asisdlsep_r2_r2"},
- {"1110xx0", "Visit_ld2_asisdlsep_r2_r"},
- {"1110xx1", "Visit_ld1_asisdlsep_r2_r2"},
- {"11110x0", "Visit_ld2_asisdlsep_r2_r"},
- {"11110x1", "Visit_ld1_asisdlsep_r2_r2"},
- {"1111100", "Visit_ld2_asisdlsep_r2_r"},
- {"1111101", "Visit_ld1_asisdlsep_r2_r2"},
- {"1111110", "Decode_nszhhy"},
- {"1111111", "Decode_qxrzgv"},
+ { {"0000000"_b, "_jlrvpl"},
+ {"0000001"_b, "_pmkxlj"},
+ {"0100000"_b, "_qmgtyq"},
+ {"0100001"_b, "_qhxzxl"},
+ {"100xxx0"_b, "st2_asisdlsep_r2_r"},
+ {"100xxx1"_b, "st1_asisdlsep_r2_r2"},
+ {"1010xx0"_b, "st2_asisdlsep_r2_r"},
+ {"1010xx1"_b, "st1_asisdlsep_r2_r2"},
+ {"10110x0"_b, "st2_asisdlsep_r2_r"},
+ {"10110x1"_b, "st1_asisdlsep_r2_r2"},
+ {"1011100"_b, "st2_asisdlsep_r2_r"},
+ {"1011101"_b, "st1_asisdlsep_r2_r2"},
+ {"1011110"_b, "_tmrnzq"},
+ {"1011111"_b, "_thqvrp"},
+ {"110xxx0"_b, "ld2_asisdlsep_r2_r"},
+ {"110xxx1"_b, "ld1_asisdlsep_r2_r2"},
+ {"1110xx0"_b, "ld2_asisdlsep_r2_r"},
+ {"1110xx1"_b, "ld1_asisdlsep_r2_r2"},
+ {"11110x0"_b, "ld2_asisdlsep_r2_r"},
+ {"11110x1"_b, "ld1_asisdlsep_r2_r2"},
+ {"1111100"_b, "ld2_asisdlsep_r2_r"},
+ {"1111101"_b, "ld1_asisdlsep_r2_r2"},
+ {"1111110"_b, "_nszhhy"},
+ {"1111111"_b, "_qxrzgv"},
},
},
- { "Decode_vjymzn",
+ { "_vjymzn",
{23, 22},
- { {"00", "Visit_fcsel_s_floatsel"},
- {"01", "Visit_fcsel_d_floatsel"},
- {"11", "Visit_fcsel_h_floatsel"},
+ { {"00"_b, "fcsel_s_floatsel"},
+ {"01"_b, "fcsel_d_floatsel"},
+ {"11"_b, "fcsel_h_floatsel"},
},
},
- { "Decode_vkhhkk",
+ { "_vkhhkk",
{30, 23, 22, 11, 10, 4},
- { {"001000", "Visit_ccmn_64_condcmp_reg"},
- {"001100", "Visit_ccmn_64_condcmp_imm"},
- {"101000", "Visit_ccmp_64_condcmp_reg"},
- {"101100", "Visit_ccmp_64_condcmp_imm"},
+ { {"001000"_b, "ccmn_64_condcmp_reg"},
+ {"001100"_b, "ccmn_64_condcmp_imm"},
+ {"101000"_b, "ccmp_64_condcmp_reg"},
+ {"101100"_b, "ccmp_64_condcmp_imm"},
},
},
- { "Decode_vkrkks",
+ { "_vkrkks",
{30, 23, 22, 13, 4},
- { {"00000", "Visit_prfb_i_p_br_s"},
- {"00010", "Visit_prfb_i_p_ai_s"},
- {"0010x", "Visit_ld1rb_z_p_bi_u32"},
- {"0011x", "Visit_ld1rb_z_p_bi_u64"},
- {"01000", "Visit_prfh_i_p_br_s"},
- {"01010", "Visit_prfh_i_p_ai_s"},
- {"0110x", "Visit_ld1rh_z_p_bi_u32"},
- {"0111x", "Visit_ld1rh_z_p_bi_u64"},
- {"1000x", "Visit_ldnt1b_z_p_ar_d_64_unscaled"},
- {"10010", "Visit_prfb_i_p_ai_d"},
- {"1010x", "Visit_ld1b_z_p_bz_d_64_unscaled"},
- {"1011x", "Visit_ldff1b_z_p_bz_d_64_unscaled"},
- {"1100x", "Visit_ldnt1h_z_p_ar_d_64_unscaled"},
- {"11010", "Visit_prfh_i_p_ai_d"},
- {"1110x", "Visit_ld1h_z_p_bz_d_64_unscaled"},
- {"1111x", "Visit_ldff1h_z_p_bz_d_64_unscaled"},
+ { {"00000"_b, "prfb_i_p_br_s"},
+ {"00010"_b, "prfb_i_p_ai_s"},
+ {"0010x"_b, "ld1rb_z_p_bi_u32"},
+ {"0011x"_b, "ld1rb_z_p_bi_u64"},
+ {"01000"_b, "prfh_i_p_br_s"},
+ {"01010"_b, "prfh_i_p_ai_s"},
+ {"0110x"_b, "ld1rh_z_p_bi_u32"},
+ {"0111x"_b, "ld1rh_z_p_bi_u64"},
+ {"1000x"_b, "ldnt1b_z_p_ar_d_64_unscaled"},
+ {"10010"_b, "prfb_i_p_ai_d"},
+ {"1010x"_b, "ld1b_z_p_bz_d_64_unscaled"},
+ {"1011x"_b, "ldff1b_z_p_bz_d_64_unscaled"},
+ {"1100x"_b, "ldnt1h_z_p_ar_d_64_unscaled"},
+ {"11010"_b, "prfh_i_p_ai_d"},
+ {"1110x"_b, "ld1h_z_p_bz_d_64_unscaled"},
+ {"1111x"_b, "ldff1h_z_p_bz_d_64_unscaled"},
},
},
- { "Decode_vkvgnm",
+ { "_vkvgnm",
{30, 13},
- { {"10", "Decode_vyygqs"},
+ { {"10"_b, "_vyygqs"},
},
},
- { "Decode_vkyngx",
+ { "_vkyngx",
{23, 22, 19, 18, 17, 16},
- { {"0000x1", "Visit_dup_asimdins_dv_v"},
- {"000x10", "Visit_dup_asimdins_dv_v"},
- {"0010xx", "Visit_dup_asimdins_dv_v"},
- {"001110", "Visit_dup_asimdins_dv_v"},
- {"00x10x", "Visit_dup_asimdins_dv_v"},
- {"00x111", "Visit_dup_asimdins_dv_v"},
- {"01xxxx", "Visit_fmaxnm_asimdsamefp16_only"},
- {"11xxxx", "Visit_fminnm_asimdsamefp16_only"},
+ { {"0000x1"_b, "dup_asimdins_dv_v"},
+ {"000x10"_b, "dup_asimdins_dv_v"},
+ {"0010xx"_b, "dup_asimdins_dv_v"},
+ {"001110"_b, "dup_asimdins_dv_v"},
+ {"00x10x"_b, "dup_asimdins_dv_v"},
+ {"00x111"_b, "dup_asimdins_dv_v"},
+ {"01xxxx"_b, "fmaxnm_asimdsamefp16_only"},
+ {"11xxxx"_b, "fminnm_asimdsamefp16_only"},
},
},
- { "Decode_vllqmp",
+ { "_vllqmp",
{30, 23, 22, 13, 12, 11, 10},
- { {"000xxxx", "Visit_stxp_sp32_ldstexcl"},
- {"001xxxx", "Visit_ldxp_lp32_ldstexcl"},
- {"0101111", "Visit_cas_c32_ldstexcl"},
- {"0111111", "Visit_casa_c32_ldstexcl"},
- {"100xxxx", "Visit_stxp_sp64_ldstexcl"},
- {"101xxxx", "Visit_ldxp_lp64_ldstexcl"},
- {"1101111", "Visit_cas_c64_ldstexcl"},
- {"1111111", "Visit_casa_c64_ldstexcl"},
+ { {"000xxxx"_b, "stxp_sp32_ldstexcl"},
+ {"001xxxx"_b, "ldxp_lp32_ldstexcl"},
+ {"0101111"_b, "cas_c32_ldstexcl"},
+ {"0111111"_b, "casa_c32_ldstexcl"},
+ {"100xxxx"_b, "stxp_sp64_ldstexcl"},
+ {"101xxxx"_b, "ldxp_lp64_ldstexcl"},
+ {"1101111"_b, "cas_c64_ldstexcl"},
+ {"1111111"_b, "casa_c64_ldstexcl"},
},
},
- { "Decode_vlrhpy",
+ { "_vlrhpy",
{30, 23, 22, 13, 4},
- { {"0000x", "Visit_ld1sb_z_p_ai_s"},
- {"0001x", "Visit_ldff1sb_z_p_ai_s"},
- {"0010x", "Visit_ld1rb_z_p_bi_u8"},
- {"0011x", "Visit_ld1rb_z_p_bi_u16"},
- {"0100x", "Visit_ld1sh_z_p_ai_s"},
- {"0101x", "Visit_ldff1sh_z_p_ai_s"},
- {"0110x", "Visit_ld1rsw_z_p_bi_s64"},
- {"0111x", "Visit_ld1rh_z_p_bi_u16"},
- {"1000x", "Visit_ld1sb_z_p_ai_d"},
- {"1001x", "Visit_ldff1sb_z_p_ai_d"},
- {"10100", "Visit_prfb_i_p_bz_d_64_scaled"},
- {"10110", "Visit_prfh_i_p_bz_d_64_scaled"},
- {"1100x", "Visit_ld1sh_z_p_ai_d"},
- {"1101x", "Visit_ldff1sh_z_p_ai_d"},
- {"1110x", "Visit_ld1sh_z_p_bz_d_64_scaled"},
- {"1111x", "Visit_ldff1sh_z_p_bz_d_64_scaled"},
+ { {"0000x"_b, "ld1sb_z_p_ai_s"},
+ {"0001x"_b, "ldff1sb_z_p_ai_s"},
+ {"0010x"_b, "ld1rb_z_p_bi_u8"},
+ {"0011x"_b, "ld1rb_z_p_bi_u16"},
+ {"0100x"_b, "ld1sh_z_p_ai_s"},
+ {"0101x"_b, "ldff1sh_z_p_ai_s"},
+ {"0110x"_b, "ld1rsw_z_p_bi_s64"},
+ {"0111x"_b, "ld1rh_z_p_bi_u16"},
+ {"1000x"_b, "ld1sb_z_p_ai_d"},
+ {"1001x"_b, "ldff1sb_z_p_ai_d"},
+ {"10100"_b, "prfb_i_p_bz_d_64_scaled"},
+ {"10110"_b, "prfh_i_p_bz_d_64_scaled"},
+ {"1100x"_b, "ld1sh_z_p_ai_d"},
+ {"1101x"_b, "ldff1sh_z_p_ai_d"},
+ {"1110x"_b, "ld1sh_z_p_bz_d_64_scaled"},
+ {"1111x"_b, "ldff1sh_z_p_bz_d_64_scaled"},
},
},
- { "Decode_vlrrtz",
+ { "_vlrrtz",
{30, 23, 22},
- { {"001", "Visit_bfm_64m_bitfield"},
+ { {"001"_b, "bfm_64m_bitfield"},
},
},
- { "Decode_vlsmsn",
+ { "_vlsmsn",
{22, 20, 19, 18, 17, 16},
- { {"111000", "Visit_fcmle_asisdmiscfp16_fz"},
- {"111001", "Visit_frsqrte_asisdmiscfp16_r"},
- {"x00000", "Visit_fcmle_asisdmisc_fz"},
- {"x00001", "Visit_frsqrte_asisdmisc_r"},
+ { {"111000"_b, "fcmle_asisdmiscfp16_fz"},
+ {"111001"_b, "frsqrte_asisdmiscfp16_r"},
+ {"x00000"_b, "fcmle_asisdmisc_fz"},
+ {"x00001"_b, "frsqrte_asisdmisc_r"},
},
},
- { "Decode_vlzrlm",
+ { "_vlzrlm",
{23, 22, 20, 19, 13, 11},
- { {"0000x0", "Visit_mvni_asimdimm_l_sl"},
- {"00x100", "Visit_sri_asimdshf_r"},
- {"00x110", "Visit_sqshlu_asimdshf_r"},
- {"010x00", "Visit_sri_asimdshf_r"},
- {"010x10", "Visit_sqshlu_asimdshf_r"},
- {"011100", "Visit_sri_asimdshf_r"},
- {"011110", "Visit_sqshlu_asimdshf_r"},
- {"0x1000", "Visit_sri_asimdshf_r"},
- {"0x1010", "Visit_sqshlu_asimdshf_r"},
+ { {"0000x0"_b, "mvni_asimdimm_l_sl"},
+ {"00x100"_b, "sri_asimdshf_r"},
+ {"00x110"_b, "sqshlu_asimdshf_r"},
+ {"010x00"_b, "sri_asimdshf_r"},
+ {"010x10"_b, "sqshlu_asimdshf_r"},
+ {"011100"_b, "sri_asimdshf_r"},
+ {"011110"_b, "sqshlu_asimdshf_r"},
+ {"0x1000"_b, "sri_asimdshf_r"},
+ {"0x1010"_b, "sqshlu_asimdshf_r"},
},
},
- { "Decode_vmjgmg",
+ { "_vmjgmg",
{30, 23, 22},
- { {"000", "Visit_stxrb_sr32_ldstexcl"},
- {"001", "Visit_ldxrb_lr32_ldstexcl"},
- {"010", "Visit_stllrb_sl32_ldstexcl"},
- {"011", "Visit_ldlarb_lr32_ldstexcl"},
- {"100", "Visit_stxrh_sr32_ldstexcl"},
- {"101", "Visit_ldxrh_lr32_ldstexcl"},
- {"110", "Visit_stllrh_sl32_ldstexcl"},
- {"111", "Visit_ldlarh_lr32_ldstexcl"},
+ { {"000"_b, "stxrb_sr32_ldstexcl"},
+ {"001"_b, "ldxrb_lr32_ldstexcl"},
+ {"010"_b, "stllrb_sl32_ldstexcl"},
+ {"011"_b, "ldlarb_lr32_ldstexcl"},
+ {"100"_b, "stxrh_sr32_ldstexcl"},
+ {"101"_b, "ldxrh_lr32_ldstexcl"},
+ {"110"_b, "stllrh_sl32_ldstexcl"},
+ {"111"_b, "ldlarh_lr32_ldstexcl"},
},
},
- { "Decode_vmjtrx",
+ { "_vmjtrx",
{23, 22, 12},
- { {"001", "Visit_sudot_asimdelem_d"},
- {"011", "Visit_bfdot_asimdelem_e"},
- {"101", "Visit_usdot_asimdelem_d"},
- {"111", "Visit_bfmlal_asimdelem_f"},
- {"xx0", "Visit_sdot_asimdelem_d"},
+ { {"001"_b, "sudot_asimdelem_d"},
+ {"011"_b, "bfdot_asimdelem_e"},
+ {"101"_b, "usdot_asimdelem_d"},
+ {"111"_b, "bfmlal_asimdelem_f"},
+ {"xx0"_b, "sdot_asimdelem_d"},
},
},
- { "Decode_vmjzyk",
+ { "_vmjzyk",
{30, 23, 22},
- { {"000", "Visit_stp_32_ldstpair_off"},
- {"001", "Visit_ldp_32_ldstpair_off"},
- {"010", "Visit_stp_32_ldstpair_pre"},
- {"011", "Visit_ldp_32_ldstpair_pre"},
- {"100", "Visit_stgp_64_ldstpair_off"},
- {"101", "Visit_ldpsw_64_ldstpair_off"},
- {"110", "Visit_stgp_64_ldstpair_pre"},
- {"111", "Visit_ldpsw_64_ldstpair_pre"},
+ { {"000"_b, "stp_32_ldstpair_off"},
+ {"001"_b, "ldp_32_ldstpair_off"},
+ {"010"_b, "stp_32_ldstpair_pre"},
+ {"011"_b, "ldp_32_ldstpair_pre"},
+ {"100"_b, "stgp_64_ldstpair_off"},
+ {"101"_b, "ldpsw_64_ldstpair_off"},
+ {"110"_b, "stgp_64_ldstpair_pre"},
+ {"111"_b, "ldpsw_64_ldstpair_pre"},
},
},
- { "Decode_vmplgv",
+ { "_vmplgv",
{12},
- { {"0", "Visit_ld1_asisdlsop_dx1_r1d"},
+ { {"0"_b, "ld1_asisdlsop_dx1_r1d"},
},
},
- { "Decode_vmpnlv",
+ { "_vmpnlv",
{11, 10, 9, 8, 7, 6},
- { {"000000", "Visit_wfit_only_systeminstrswithreg"},
+ { {"000000"_b, "wfit_only_systeminstrswithreg"},
},
},
- { "Decode_vnpqrh",
+ { "_vnpqrh",
{30, 23, 22},
- { {"000", "Visit_stp_s_ldstpair_off"},
- {"001", "Visit_ldp_s_ldstpair_off"},
- {"010", "Visit_stp_s_ldstpair_pre"},
- {"011", "Visit_ldp_s_ldstpair_pre"},
- {"100", "Visit_stp_d_ldstpair_off"},
- {"101", "Visit_ldp_d_ldstpair_off"},
- {"110", "Visit_stp_d_ldstpair_pre"},
- {"111", "Visit_ldp_d_ldstpair_pre"},
+ { {"000"_b, "stp_s_ldstpair_off"},
+ {"001"_b, "ldp_s_ldstpair_off"},
+ {"010"_b, "stp_s_ldstpair_pre"},
+ {"011"_b, "ldp_s_ldstpair_pre"},
+ {"100"_b, "stp_d_ldstpair_off"},
+ {"101"_b, "ldp_d_ldstpair_off"},
+ {"110"_b, "stp_d_ldstpair_pre"},
+ {"111"_b, "ldp_d_ldstpair_pre"},
},
},
- { "Decode_vnrnmg",
+ { "_vnrnmg",
{17},
- { {"0", "Visit_st4_asisdlse_r4"},
+ { {"0"_b, "st4_asisdlse_r4"},
},
},
- { "Decode_vpkhvh",
+ { "_vpkhvh",
{17},
- { {"0", "Visit_st2_asisdlso_h2_2h"},
+ { {"0"_b, "st2_asisdlso_h2_2h"},
},
},
- { "Decode_vpkptr",
+ { "_vpkptr",
{30, 23, 22},
- { {"000", "Visit_stnp_32_ldstnapair_offs"},
- {"001", "Visit_ldnp_32_ldstnapair_offs"},
- {"010", "Visit_stp_32_ldstpair_post"},
- {"011", "Visit_ldp_32_ldstpair_post"},
- {"110", "Visit_stgp_64_ldstpair_post"},
- {"111", "Visit_ldpsw_64_ldstpair_post"},
+ { {"000"_b, "stnp_32_ldstnapair_offs"},
+ {"001"_b, "ldnp_32_ldstnapair_offs"},
+ {"010"_b, "stp_32_ldstpair_post"},
+ {"011"_b, "ldp_32_ldstpair_post"},
+ {"110"_b, "stgp_64_ldstpair_post"},
+ {"111"_b, "ldpsw_64_ldstpair_post"},
},
},
- { "Decode_vpmxrj",
+ { "_vpmxrj",
{13},
- { {"0", "Visit_histcnt_z_p_zz"},
- {"1", "Decode_jxszhy"},
+ { {"0"_b, "histcnt_z_p_zz"},
+ {"1"_b, "_jxszhy"},
},
},
- { "Decode_vppthj",
+ { "_vppthj",
{30, 23},
- { {"00", "Visit_add_32_addsub_imm"},
- {"10", "Visit_sub_32_addsub_imm"},
+ { {"00"_b, "add_32_addsub_imm"},
+ {"10"_b, "sub_32_addsub_imm"},
},
},
- { "Decode_vprkpq",
+ { "_vprkpq",
{13, 12, 11, 10},
- { {"0000", "Visit_saddwb_z_zz"},
- {"0001", "Visit_saddwt_z_zz"},
- {"0010", "Visit_uaddwb_z_zz"},
- {"0011", "Visit_uaddwt_z_zz"},
- {"0100", "Visit_ssubwb_z_zz"},
- {"0101", "Visit_ssubwt_z_zz"},
- {"0110", "Visit_usubwb_z_zz"},
- {"0111", "Visit_usubwt_z_zz"},
- {"1000", "Visit_sqdmullb_z_zz"},
- {"1001", "Visit_sqdmullt_z_zz"},
- {"1010", "Visit_pmullb_z_zz"},
- {"1011", "Visit_pmullt_z_zz"},
- {"1100", "Visit_smullb_z_zz"},
- {"1101", "Visit_smullt_z_zz"},
- {"1110", "Visit_umullb_z_zz"},
- {"1111", "Visit_umullt_z_zz"},
+ { {"0000"_b, "saddwb_z_zz"},
+ {"0001"_b, "saddwt_z_zz"},
+ {"0010"_b, "uaddwb_z_zz"},
+ {"0011"_b, "uaddwt_z_zz"},
+ {"0100"_b, "ssubwb_z_zz"},
+ {"0101"_b, "ssubwt_z_zz"},
+ {"0110"_b, "usubwb_z_zz"},
+ {"0111"_b, "usubwt_z_zz"},
+ {"1000"_b, "sqdmullb_z_zz"},
+ {"1001"_b, "sqdmullt_z_zz"},
+ {"1010"_b, "pmullb_z_zz"},
+ {"1011"_b, "pmullt_z_zz"},
+ {"1100"_b, "smullb_z_zz"},
+ {"1101"_b, "smullt_z_zz"},
+ {"1110"_b, "umullb_z_zz"},
+ {"1111"_b, "umullt_z_zz"},
},
},
- { "Decode_vpxvjs",
+ { "_vpxvjs",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_fcvtns_32s_float2int"},
- {"00001", "Visit_fcvtnu_32s_float2int"},
- {"00010", "Visit_scvtf_s32_float2int"},
- {"00011", "Visit_ucvtf_s32_float2int"},
- {"00100", "Visit_fcvtas_32s_float2int"},
- {"00101", "Visit_fcvtau_32s_float2int"},
- {"00110", "Visit_fmov_32s_float2int"},
- {"00111", "Visit_fmov_s32_float2int"},
- {"01000", "Visit_fcvtps_32s_float2int"},
- {"01001", "Visit_fcvtpu_32s_float2int"},
- {"10000", "Visit_fcvtms_32s_float2int"},
- {"10001", "Visit_fcvtmu_32s_float2int"},
- {"11000", "Visit_fcvtzs_32s_float2int"},
- {"11001", "Visit_fcvtzu_32s_float2int"},
+ { {"00000"_b, "fcvtns_32s_float2int"},
+ {"00001"_b, "fcvtnu_32s_float2int"},
+ {"00010"_b, "scvtf_s32_float2int"},
+ {"00011"_b, "ucvtf_s32_float2int"},
+ {"00100"_b, "fcvtas_32s_float2int"},
+ {"00101"_b, "fcvtau_32s_float2int"},
+ {"00110"_b, "fmov_32s_float2int"},
+ {"00111"_b, "fmov_s32_float2int"},
+ {"01000"_b, "fcvtps_32s_float2int"},
+ {"01001"_b, "fcvtpu_32s_float2int"},
+ {"10000"_b, "fcvtms_32s_float2int"},
+ {"10001"_b, "fcvtmu_32s_float2int"},
+ {"11000"_b, "fcvtzs_32s_float2int"},
+ {"11001"_b, "fcvtzu_32s_float2int"},
},
},
- { "Decode_vpykkg",
+ { "_vpykkg",
{23, 22, 10},
- { {"000", "Visit_ext_asimdext_only"},
- {"001", "Decode_jnmgrh"},
- {"011", "Decode_vytgtz"},
- {"111", "Decode_jrnlzs"},
+ { {"000"_b, "ext_asimdext_only"},
+ {"001"_b, "_jnmgrh"},
+ {"011"_b, "_vytgtz"},
+ {"111"_b, "_jrnlzs"},
},
},
- { "Decode_vqlytp",
+ { "_vqlytp",
{12},
- { {"0", "Visit_st3_asisdlsop_dx3_r3d"},
+ { {"0"_b, "st3_asisdlsop_dx3_r3d"},
},
},
- { "Decode_vqqrjl",
+ { "_vqqrjl",
{23, 22, 20, 19, 13, 11, 10},
- { {"0001001", "Visit_shl_asisdshf_r"},
- {"0001101", "Visit_sqshl_asisdshf_r"},
- {"001x001", "Visit_shl_asisdshf_r"},
- {"001x101", "Visit_sqshl_asisdshf_r"},
- {"00xx0x0", "Visit_fmls_asisdelem_rh_h"},
- {"01xx001", "Visit_shl_asisdshf_r"},
- {"01xx101", "Visit_sqshl_asisdshf_r"},
- {"1xxx0x0", "Visit_fmls_asisdelem_r_sd"},
- {"xxxx1x0", "Visit_sqdmlsl_asisdelem_l"},
+ { {"0001001"_b, "shl_asisdshf_r"},
+ {"0001101"_b, "sqshl_asisdshf_r"},
+ {"001x001"_b, "shl_asisdshf_r"},
+ {"001x101"_b, "sqshl_asisdshf_r"},
+ {"00xx0x0"_b, "fmls_asisdelem_rh_h"},
+ {"01xx001"_b, "shl_asisdshf_r"},
+ {"01xx101"_b, "sqshl_asisdshf_r"},
+ {"1xxx0x0"_b, "fmls_asisdelem_r_sd"},
+ {"xxxx1x0"_b, "sqdmlsl_asisdelem_l"},
},
},
- { "Decode_vqvqhp",
+ { "_vqvqhp",
{30, 23, 22},
- { {"000", "Visit_str_32_ldst_pos"},
- {"001", "Visit_ldr_32_ldst_pos"},
- {"010", "Visit_ldrsw_64_ldst_pos"},
- {"100", "Visit_str_64_ldst_pos"},
- {"101", "Visit_ldr_64_ldst_pos"},
- {"110", "Visit_prfm_p_ldst_pos"},
+ { {"000"_b, "str_32_ldst_pos"},
+ {"001"_b, "ldr_32_ldst_pos"},
+ {"010"_b, "ldrsw_64_ldst_pos"},
+ {"100"_b, "str_64_ldst_pos"},
+ {"101"_b, "ldr_64_ldst_pos"},
+ {"110"_b, "prfm_p_ldst_pos"},
},
},
- { "Decode_vqzlzt",
+ { "_vqzlzt",
{30, 23},
- { {"00", "Visit_and_64_log_imm"},
- {"01", "Visit_movn_64_movewide"},
- {"10", "Visit_eor_64_log_imm"},
- {"11", "Visit_movz_64_movewide"},
+ { {"00"_b, "and_64_log_imm"},
+ {"01"_b, "movn_64_movewide"},
+ {"10"_b, "eor_64_log_imm"},
+ {"11"_b, "movz_64_movewide"},
},
},
- { "Decode_vsqlkr",
+ { "_vsqlkr",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_frintx_asimdmiscfp16_r"},
- {"0x00001", "Visit_frintx_asimdmisc_r"},
- {"1111001", "Visit_frinti_asimdmiscfp16_r"},
- {"1x00001", "Visit_frinti_asimdmisc_r"},
- {"xx00000", "Visit_cmle_asimdmisc_z"},
+ { {"0111001"_b, "frintx_asimdmiscfp16_r"},
+ {"0x00001"_b, "frintx_asimdmisc_r"},
+ {"1111001"_b, "frinti_asimdmiscfp16_r"},
+ {"1x00001"_b, "frinti_asimdmisc_r"},
+ {"xx00000"_b, "cmle_asimdmisc_z"},
},
},
- { "Decode_vsqpzr",
+ { "_vsqpzr",
{23},
- { {"0", "Visit_faddp_asimdsame_only"},
- {"1", "Visit_fabd_asimdsame_only"},
+ { {"0"_b, "faddp_asimdsame_only"},
+ {"1"_b, "fabd_asimdsame_only"},
},
},
- { "Decode_vsvrgt",
+ { "_vsvrgt",
{17},
- { {"0", "Visit_fadda_v_p_z"},
+ { {"0"_b, "fadda_v_p_z"},
},
},
- { "Decode_vsvtqz",
+ { "_vsvtqz",
{30, 23, 22},
- { {"00x", "Visit_add_64_addsub_imm"},
- {"010", "Visit_addg_64_addsub_immtags"},
- {"10x", "Visit_sub_64_addsub_imm"},
- {"110", "Visit_subg_64_addsub_immtags"},
+ { {"00x"_b, "add_64_addsub_imm"},
+ {"010"_b, "addg_64_addsub_immtags"},
+ {"10x"_b, "sub_64_addsub_imm"},
+ {"110"_b, "subg_64_addsub_immtags"},
},
},
- { "Decode_vtxyxz",
+ { "_vtxyxz",
{23, 22, 13, 12, 11, 10},
- { {"01x1x0", "Visit_fcmla_asimdelem_c_h"},
- {"0x0001", "Visit_ushr_asimdshf_r"},
- {"0x0101", "Visit_usra_asimdshf_r"},
- {"0x1001", "Visit_urshr_asimdshf_r"},
- {"0x1101", "Visit_ursra_asimdshf_r"},
- {"10x1x0", "Visit_fcmla_asimdelem_c_s"},
- {"xx00x0", "Visit_mla_asimdelem_r"},
- {"xx10x0", "Visit_umlal_asimdelem_l"},
+ { {"01x1x0"_b, "fcmla_asimdelem_c_h"},
+ {"0x0001"_b, "ushr_asimdshf_r"},
+ {"0x0101"_b, "usra_asimdshf_r"},
+ {"0x1001"_b, "urshr_asimdshf_r"},
+ {"0x1101"_b, "ursra_asimdshf_r"},
+ {"10x1x0"_b, "fcmla_asimdelem_c_s"},
+ {"xx00x0"_b, "mla_asimdelem_r"},
+ {"xx10x0"_b, "umlal_asimdelem_l"},
},
},
- { "Decode_vvhzhv",
+ { "_vvhzhv",
{30, 23, 22, 13, 12, 11, 10},
- { {"0000000", "Visit_swpb_32_memop"},
- {"000xx10", "Visit_strb_32b_ldst_regoff"},
- {"0010000", "Visit_swplb_32_memop"},
- {"001xx10", "Visit_ldrb_32b_ldst_regoff"},
- {"0100000", "Visit_swpab_32_memop"},
- {"010xx10", "Visit_ldrsb_64b_ldst_regoff"},
- {"0110000", "Visit_swpalb_32_memop"},
- {"011xx10", "Visit_ldrsb_32b_ldst_regoff"},
- {"1000000", "Visit_swph_32_memop"},
- {"100xx10", "Visit_strh_32_ldst_regoff"},
- {"1010000", "Visit_swplh_32_memop"},
- {"101xx10", "Visit_ldrh_32_ldst_regoff"},
- {"1100000", "Visit_swpah_32_memop"},
- {"110xx10", "Visit_ldrsh_64_ldst_regoff"},
- {"1110000", "Visit_swpalh_32_memop"},
- {"111xx10", "Visit_ldrsh_32_ldst_regoff"},
+ { {"0000000"_b, "swpb_32_memop"},
+ {"000xx10"_b, "strb_32b_ldst_regoff"},
+ {"0010000"_b, "swplb_32_memop"},
+ {"001xx10"_b, "ldrb_32b_ldst_regoff"},
+ {"0100000"_b, "swpab_32_memop"},
+ {"010xx10"_b, "ldrsb_64b_ldst_regoff"},
+ {"0110000"_b, "swpalb_32_memop"},
+ {"011xx10"_b, "ldrsb_32b_ldst_regoff"},
+ {"1000000"_b, "swph_32_memop"},
+ {"100xx10"_b, "strh_32_ldst_regoff"},
+ {"1010000"_b, "swplh_32_memop"},
+ {"101xx10"_b, "ldrh_32_ldst_regoff"},
+ {"1100000"_b, "swpah_32_memop"},
+ {"110xx10"_b, "ldrsh_64_ldst_regoff"},
+ {"1110000"_b, "swpalh_32_memop"},
+ {"111xx10"_b, "ldrsh_32_ldst_regoff"},
},
},
- { "Decode_vvprhx",
+ { "_vvprhx",
{0},
- { {"0", "Visit_blr_64_branch_reg"},
+ { {"0"_b, "blr_64_branch_reg"},
},
},
- { "Decode_vvrmvg",
+ { "_vvrmvg",
{12},
- { {"1", "Decode_typysz"},
+ { {"1"_b, "_typysz"},
},
},
- { "Decode_vvtnrv",
+ { "_vvtnrv",
{23, 22, 20, 19, 18},
- { {"00000", "Visit_orr_z_zi"},
- {"01000", "Visit_eor_z_zi"},
- {"10000", "Visit_and_z_zi"},
- {"11000", "Visit_dupm_z_i"},
+ { {"00000"_b, "orr_z_zi"},
+ {"01000"_b, "eor_z_zi"},
+ {"10000"_b, "and_z_zi"},
+ {"11000"_b, "dupm_z_i"},
},
},
- { "Decode_vvxsxt",
+ { "_vvxsxt",
{4},
- { {"0", "Visit_ands_p_p_pp_z"},
- {"1", "Visit_bics_p_p_pp_z"},
+ { {"0"_b, "ands_p_p_pp_z"},
+ {"1"_b, "bics_p_p_pp_z"},
},
},
- { "Decode_vxgzqy",
+ { "_vxgzqy",
{22},
- { {"0", "Visit_ldrsw_64_ldst_regoff"},
+ { {"0"_b, "ldrsw_64_ldst_regoff"},
},
},
- { "Decode_vxhgzz",
+ { "_vxhgzz",
{23, 22, 12, 11, 10},
- { {"00xxx", "Visit_ext_z_zi_des"},
- {"01xxx", "Visit_ext_z_zi_con"},
- {"10000", "Visit_zip1_z_zz_q"},
- {"10001", "Visit_zip2_z_zz_q"},
- {"10010", "Visit_uzp1_z_zz_q"},
- {"10011", "Visit_uzp2_z_zz_q"},
- {"10110", "Visit_trn1_z_zz_q"},
- {"10111", "Visit_trn2_z_zz_q"},
+ { {"00xxx"_b, "ext_z_zi_des"},
+ {"01xxx"_b, "ext_z_zi_con"},
+ {"10000"_b, "zip1_z_zz_q"},
+ {"10001"_b, "zip2_z_zz_q"},
+ {"10010"_b, "uzp1_z_zz_q"},
+ {"10011"_b, "uzp2_z_zz_q"},
+ {"10110"_b, "trn1_z_zz_q"},
+ {"10111"_b, "trn2_z_zz_q"},
},
},
- { "Decode_vxsjgg",
+ { "_vxsjgg",
{30, 22, 11},
- { {"001", "Decode_pxnnrz"},
- {"010", "Visit_ccmn_32_condcmp_reg"},
- {"011", "Visit_ccmn_32_condcmp_imm"},
- {"110", "Visit_ccmp_32_condcmp_reg"},
- {"111", "Visit_ccmp_32_condcmp_imm"},
+ { {"001"_b, "_pxnnrz"},
+ {"010"_b, "ccmn_32_condcmp_reg"},
+ {"011"_b, "ccmn_32_condcmp_imm"},
+ {"110"_b, "ccmp_32_condcmp_reg"},
+ {"111"_b, "ccmp_32_condcmp_imm"},
},
},
- { "Decode_vxsvhs",
+ { "_vxsvhs",
{13, 12},
- { {"00", "Visit_adcs_64_addsub_carry"},
+ { {"00"_b, "adcs_64_addsub_carry"},
},
},
- { "Decode_vxylhh",
+ { "_vxylhh",
{23, 22},
- { {"01", "Visit_fcmla_asimdelem_c_h"},
- {"10", "Visit_fcmla_asimdelem_c_s"},
+ { {"01"_b, "fcmla_asimdelem_c_h"},
+ {"10"_b, "fcmla_asimdelem_c_s"},
},
},
- { "Decode_vylhvl",
+ { "_vylhvl",
{20, 19, 18, 17, 16, 13},
- { {"000000", "Visit_fabs_h_floatdp1"},
- {"000010", "Visit_fsqrt_h_floatdp1"},
- {"000100", "Visit_fcvt_dh_floatdp1"},
- {"001000", "Visit_frintp_h_floatdp1"},
- {"001010", "Visit_frintz_h_floatdp1"},
- {"001110", "Visit_frinti_h_floatdp1"},
+ { {"000000"_b, "fabs_h_floatdp1"},
+ {"000010"_b, "fsqrt_h_floatdp1"},
+ {"000100"_b, "fcvt_dh_floatdp1"},
+ {"001000"_b, "frintp_h_floatdp1"},
+ {"001010"_b, "frintz_h_floatdp1"},
+ {"001110"_b, "frinti_h_floatdp1"},
},
},
- { "Decode_vytgtz",
+ { "_vytgtz",
{13, 12, 11},
- { {"000", "Visit_fmaxnmp_asimdsamefp16_only"},
- {"010", "Visit_faddp_asimdsamefp16_only"},
- {"011", "Visit_fmul_asimdsamefp16_only"},
- {"100", "Visit_fcmge_asimdsamefp16_only"},
- {"101", "Visit_facge_asimdsamefp16_only"},
- {"110", "Visit_fmaxp_asimdsamefp16_only"},
- {"111", "Visit_fdiv_asimdsamefp16_only"},
+ { {"000"_b, "fmaxnmp_asimdsamefp16_only"},
+ {"010"_b, "faddp_asimdsamefp16_only"},
+ {"011"_b, "fmul_asimdsamefp16_only"},
+ {"100"_b, "fcmge_asimdsamefp16_only"},
+ {"101"_b, "facge_asimdsamefp16_only"},
+ {"110"_b, "fmaxp_asimdsamefp16_only"},
+ {"111"_b, "fdiv_asimdsamefp16_only"},
},
},
- { "Decode_vytxll",
+ { "_vytxll",
{18, 17, 12},
- { {"000", "Visit_st2_asisdlso_d2_2d"},
+ { {"000"_b, "st2_asisdlso_d2_2d"},
},
},
- { "Decode_vyygqs",
+ { "_vyygqs",
{23, 22, 20, 19, 12, 11, 10},
- { {"00x1001", "Visit_sqshrun_asisdshf_n"},
- {"00x1011", "Visit_sqrshrun_asisdshf_n"},
- {"00x1101", "Visit_uqshrn_asisdshf_n"},
- {"00x1111", "Visit_uqrshrn_asisdshf_n"},
- {"00xx1x0", "Visit_fmulx_asisdelem_rh_h"},
- {"010x001", "Visit_sqshrun_asisdshf_n"},
- {"010x011", "Visit_sqrshrun_asisdshf_n"},
- {"010x101", "Visit_uqshrn_asisdshf_n"},
- {"010x111", "Visit_uqrshrn_asisdshf_n"},
- {"0111001", "Visit_sqshrun_asisdshf_n"},
- {"0111011", "Visit_sqrshrun_asisdshf_n"},
- {"0111101", "Visit_uqshrn_asisdshf_n"},
- {"0111111", "Visit_uqrshrn_asisdshf_n"},
- {"0x10001", "Visit_sqshrun_asisdshf_n"},
- {"0x10011", "Visit_sqrshrun_asisdshf_n"},
- {"0x10101", "Visit_uqshrn_asisdshf_n"},
- {"0x10111", "Visit_uqrshrn_asisdshf_n"},
- {"1xxx1x0", "Visit_fmulx_asisdelem_r_sd"},
+ { {"00x1001"_b, "sqshrun_asisdshf_n"},
+ {"00x1011"_b, "sqrshrun_asisdshf_n"},
+ {"00x1101"_b, "uqshrn_asisdshf_n"},
+ {"00x1111"_b, "uqrshrn_asisdshf_n"},
+ {"00xx1x0"_b, "fmulx_asisdelem_rh_h"},
+ {"010x001"_b, "sqshrun_asisdshf_n"},
+ {"010x011"_b, "sqrshrun_asisdshf_n"},
+ {"010x101"_b, "uqshrn_asisdshf_n"},
+ {"010x111"_b, "uqrshrn_asisdshf_n"},
+ {"0111001"_b, "sqshrun_asisdshf_n"},
+ {"0111011"_b, "sqrshrun_asisdshf_n"},
+ {"0111101"_b, "uqshrn_asisdshf_n"},
+ {"0111111"_b, "uqrshrn_asisdshf_n"},
+ {"0x10001"_b, "sqshrun_asisdshf_n"},
+ {"0x10011"_b, "sqrshrun_asisdshf_n"},
+ {"0x10101"_b, "uqshrn_asisdshf_n"},
+ {"0x10111"_b, "uqrshrn_asisdshf_n"},
+ {"1xxx1x0"_b, "fmulx_asisdelem_r_sd"},
},
},
- { "Decode_vyztqx",
+ { "_vyztqx",
{8},
- { {"0", "Visit_tstart_br_systemresult"},
- {"1", "Visit_ttest_br_systemresult"},
+ { {"0"_b, "tstart_br_systemresult"},
+ {"1"_b, "ttest_br_systemresult"},
},
},
- { "Decode_vzjvtv",
+ { "_vzjvtv",
{23, 22, 12, 11, 10},
- { {"01001", "Visit_bfmmla_z_zzz"},
- {"10001", "Visit_fmmla_z_zzz_s"},
- {"11001", "Visit_fmmla_z_zzz_d"},
+ { {"01001"_b, "bfmmla_z_zzz"},
+ {"10001"_b, "fmmla_z_zzz_s"},
+ {"11001"_b, "fmmla_z_zzz_d"},
},
},
- { "Decode_vzzvlr",
+ { "_vzzvlr",
{23, 22, 20, 19, 18, 16, 13},
- { {"0000000", "Decode_tlzlrj"},
- {"0000001", "Decode_yhxvhy"},
- {"0100000", "Decode_hqhzgj"},
- {"0100001", "Decode_kzrklp"},
- {"100xxx0", "Visit_st2_asisdlsop_bx2_r2b"},
- {"100xxx1", "Visit_st4_asisdlsop_bx4_r4b"},
- {"1010xx0", "Visit_st2_asisdlsop_bx2_r2b"},
- {"1010xx1", "Visit_st4_asisdlsop_bx4_r4b"},
- {"10110x0", "Visit_st2_asisdlsop_bx2_r2b"},
- {"10110x1", "Visit_st4_asisdlsop_bx4_r4b"},
- {"1011100", "Visit_st2_asisdlsop_bx2_r2b"},
- {"1011101", "Visit_st4_asisdlsop_bx4_r4b"},
- {"1011110", "Decode_mykjss"},
- {"1011111", "Decode_xkkggt"},
- {"110xxx0", "Visit_ld2_asisdlsop_bx2_r2b"},
- {"110xxx1", "Visit_ld4_asisdlsop_bx4_r4b"},
- {"1110xx0", "Visit_ld2_asisdlsop_bx2_r2b"},
- {"1110xx1", "Visit_ld4_asisdlsop_bx4_r4b"},
- {"11110x0", "Visit_ld2_asisdlsop_bx2_r2b"},
- {"11110x1", "Visit_ld4_asisdlsop_bx4_r4b"},
- {"1111100", "Visit_ld2_asisdlsop_bx2_r2b"},
- {"1111101", "Visit_ld4_asisdlsop_bx4_r4b"},
- {"1111110", "Decode_gvstrp"},
- {"1111111", "Decode_qtgvhn"},
+ { {"0000000"_b, "_tlzlrj"},
+ {"0000001"_b, "_yhxvhy"},
+ {"0100000"_b, "_hqhzgj"},
+ {"0100001"_b, "_kzrklp"},
+ {"100xxx0"_b, "st2_asisdlsop_bx2_r2b"},
+ {"100xxx1"_b, "st4_asisdlsop_bx4_r4b"},
+ {"1010xx0"_b, "st2_asisdlsop_bx2_r2b"},
+ {"1010xx1"_b, "st4_asisdlsop_bx4_r4b"},
+ {"10110x0"_b, "st2_asisdlsop_bx2_r2b"},
+ {"10110x1"_b, "st4_asisdlsop_bx4_r4b"},
+ {"1011100"_b, "st2_asisdlsop_bx2_r2b"},
+ {"1011101"_b, "st4_asisdlsop_bx4_r4b"},
+ {"1011110"_b, "_mykjss"},
+ {"1011111"_b, "_xkkggt"},
+ {"110xxx0"_b, "ld2_asisdlsop_bx2_r2b"},
+ {"110xxx1"_b, "ld4_asisdlsop_bx4_r4b"},
+ {"1110xx0"_b, "ld2_asisdlsop_bx2_r2b"},
+ {"1110xx1"_b, "ld4_asisdlsop_bx4_r4b"},
+ {"11110x0"_b, "ld2_asisdlsop_bx2_r2b"},
+ {"11110x1"_b, "ld4_asisdlsop_bx4_r4b"},
+ {"1111100"_b, "ld2_asisdlsop_bx2_r2b"},
+ {"1111101"_b, "ld4_asisdlsop_bx4_r4b"},
+ {"1111110"_b, "_gvstrp"},
+ {"1111111"_b, "_qtgvhn"},
},
},
- { "Decode_xgvgmk",
+ { "_xgvgmk",
{23, 22, 4},
- { {"000", "Visit_fccmp_s_floatccmp"},
- {"001", "Visit_fccmpe_s_floatccmp"},
- {"010", "Visit_fccmp_d_floatccmp"},
- {"011", "Visit_fccmpe_d_floatccmp"},
- {"110", "Visit_fccmp_h_floatccmp"},
- {"111", "Visit_fccmpe_h_floatccmp"},
+ { {"000"_b, "fccmp_s_floatccmp"},
+ {"001"_b, "fccmpe_s_floatccmp"},
+ {"010"_b, "fccmp_d_floatccmp"},
+ {"011"_b, "fccmpe_d_floatccmp"},
+ {"110"_b, "fccmp_h_floatccmp"},
+ {"111"_b, "fccmpe_h_floatccmp"},
},
},
- { "Decode_xhkgqh",
+ { "_xhkgqh",
{30, 23, 22},
- { {"000", "Visit_stp_64_ldstpair_off"},
- {"001", "Visit_ldp_64_ldstpair_off"},
- {"010", "Visit_stp_64_ldstpair_pre"},
- {"011", "Visit_ldp_64_ldstpair_pre"},
+ { {"000"_b, "stp_64_ldstpair_off"},
+ {"001"_b, "ldp_64_ldstpair_off"},
+ {"010"_b, "stp_64_ldstpair_pre"},
+ {"011"_b, "ldp_64_ldstpair_pre"},
},
},
- { "Decode_xhktsk",
+ { "_xhktsk",
{22},
- { {"0", "Visit_smullt_z_zzi_s"},
- {"1", "Visit_smullt_z_zzi_d"},
+ { {"0"_b, "smullt_z_zzi_s"},
+ {"1"_b, "smullt_z_zzi_d"},
},
},
- { "Decode_xhlhmh",
+ { "_xhlhmh",
{4},
- { {"0", "Visit_cmplo_p_p_zi"},
- {"1", "Visit_cmpls_p_p_zi"},
+ { {"0"_b, "cmplo_p_p_zi"},
+ {"1"_b, "cmpls_p_p_zi"},
},
},
- { "Decode_xhltxn",
+ { "_xhltxn",
{12, 10},
- { {"00", "Decode_jqtltz"},
- {"01", "Decode_rkvyqk"},
- {"10", "Decode_zpnsrv"},
- {"11", "Decode_lhvtrp"},
+ { {"00"_b, "_jqtltz"},
+ {"01"_b, "_rkvyqk"},
+ {"10"_b, "_zpnsrv"},
+ {"11"_b, "_lhvtrp"},
},
},
- { "Decode_xhmpmy",
+ { "_xhmpmy",
{4},
- { {"0", "Visit_and_p_p_pp_z"},
- {"1", "Visit_bic_p_p_pp_z"},
+ { {"0"_b, "and_p_p_pp_z"},
+ {"1"_b, "bic_p_p_pp_z"},
},
},
- { "Decode_xhvtjg",
+ { "_xhvtjg",
{11},
- { {"0", "Decode_mpyklp"},
+ { {"0"_b, "_mpyklp"},
},
},
- { "Decode_xhxrnt",
+ { "_xhxrnt",
{30},
- { {"0", "Decode_zxhhny"},
- {"1", "Decode_lhpgsn"},
+ { {"0"_b, "_zxhhny"},
+ {"1"_b, "_lhpgsn"},
},
},
- { "Decode_xjghst",
+ { "_xjghst",
{13, 12, 11, 10},
- { {"0000", "Decode_kvmrng"},
- {"0001", "Decode_vkyngx"},
- {"0011", "Decode_lxqynh"},
- {"0100", "Decode_kjngjl"},
- {"0101", "Decode_xmqgmz"},
- {"0110", "Visit_uzp1_asimdperm_only"},
- {"0111", "Decode_shzysp"},
- {"1000", "Decode_strkph"},
- {"1001", "Decode_jpvljz"},
- {"1010", "Visit_trn1_asimdperm_only"},
- {"1011", "Decode_jryylt"},
- {"1100", "Decode_grxzzg"},
- {"1101", "Decode_lnnyzt"},
- {"1110", "Visit_zip1_asimdperm_only"},
- {"1111", "Decode_szttjy"},
+ { {"0000"_b, "_kvmrng"},
+ {"0001"_b, "_vkyngx"},
+ {"0011"_b, "_lxqynh"},
+ {"0100"_b, "_kjngjl"},
+ {"0101"_b, "_xmqgmz"},
+ {"0110"_b, "uzp1_asimdperm_only"},
+ {"0111"_b, "_shzysp"},
+ {"1000"_b, "_strkph"},
+ {"1001"_b, "_jpvljz"},
+ {"1010"_b, "trn1_asimdperm_only"},
+ {"1011"_b, "_jryylt"},
+ {"1100"_b, "_grxzzg"},
+ {"1101"_b, "_lnnyzt"},
+ {"1110"_b, "zip1_asimdperm_only"},
+ {"1111"_b, "_szttjy"},
},
},
- { "Decode_xjxppp",
+ { "_xjxppp",
{1, 0},
- { {"11", "Visit_brabz_64_branch_reg"},
+ { {"11"_b, "brabz_64_branch_reg"},
},
},
- { "Decode_xkkggt",
+ { "_xkkggt",
{17},
- { {"0", "Visit_st4_asisdlsop_bx4_r4b"},
- {"1", "Visit_st4_asisdlsop_b4_i4b"},
+ { {"0"_b, "st4_asisdlsop_bx4_r4b"},
+ {"1"_b, "st4_asisdlsop_b4_i4b"},
},
},
- { "Decode_xlhjhx",
+ { "_xlhjhx",
{30},
- { {"0", "Visit_bl_only_branch_imm"},
- {"1", "Decode_zhrtts"},
+ { {"0"_b, "bl_only_branch_imm"},
+ {"1"_b, "_zhrtts"},
},
},
- { "Decode_xmqgmz",
+ { "_xmqgmz",
{23, 22},
- { {"01", "Visit_fadd_asimdsamefp16_only"},
- {"11", "Visit_fsub_asimdsamefp16_only"},
+ { {"01"_b, "fadd_asimdsamefp16_only"},
+ {"11"_b, "fsub_asimdsamefp16_only"},
},
},
- { "Decode_xmqvpl",
+ { "_xmqvpl",
{12},
- { {"0", "Visit_ld1_asisdlsop_dx1_r1d"},
+ { {"0"_b, "ld1_asisdlsop_dx1_r1d"},
},
},
- { "Decode_xmtlmj",
+ { "_xmtlmj",
{23, 22, 20, 19, 11},
- { {"00010", "Visit_srshr_asisdshf_r"},
- {"001x0", "Visit_srshr_asisdshf_r"},
- {"01xx0", "Visit_srshr_asisdshf_r"},
+ { {"00010"_b, "srshr_asisdshf_r"},
+ {"001x0"_b, "srshr_asisdshf_r"},
+ {"01xx0"_b, "srshr_asisdshf_r"},
},
},
- { "Decode_xmxpnx",
+ { "_xmxpnx",
{10},
- { {"0", "Visit_sri_z_zzi"},
- {"1", "Visit_sli_z_zzi"},
+ { {"0"_b, "sri_z_zzi"},
+ {"1"_b, "sli_z_zzi"},
},
},
- { "Decode_xnsrny",
+ { "_xnsrny",
{30, 23, 22},
- { {"000", "Visit_madd_64a_dp_3src"},
- {"001", "Visit_smulh_64_dp_3src"},
- {"011", "Visit_umulh_64_dp_3src"},
+ { {"000"_b, "madd_64a_dp_3src"},
+ {"001"_b, "smulh_64_dp_3src"},
+ {"011"_b, "umulh_64_dp_3src"},
},
},
- { "Decode_xpkkpn",
+ { "_xpkkpn",
{17},
- { {"1", "Visit_frsqrte_z_z"},
+ { {"1"_b, "frsqrte_z_z"},
},
},
- { "Decode_xpmvjv",
+ { "_xpmvjv",
{13, 12},
- { {"00", "Visit_sqshl_asisdsame_only"},
- {"01", "Visit_sqrshl_asisdsame_only"},
+ { {"00"_b, "sqshl_asisdsame_only"},
+ {"01"_b, "sqrshl_asisdsame_only"},
},
},
- { "Decode_xpqglq",
+ { "_xpqglq",
{4},
- { {"0", "Visit_cmpeq_p_p_zi"},
- {"1", "Visit_cmpne_p_p_zi"},
+ { {"0"_b, "cmpeq_p_p_zi"},
+ {"1"_b, "cmpne_p_p_zi"},
},
},
- { "Decode_xprlgy",
+ { "_xprlgy",
{30, 23, 22, 11, 10},
- { {"00010", "Visit_str_s_ldst_regoff"},
- {"00110", "Visit_ldr_s_ldst_regoff"},
- {"10010", "Visit_str_d_ldst_regoff"},
- {"10110", "Visit_ldr_d_ldst_regoff"},
+ { {"00010"_b, "str_s_ldst_regoff"},
+ {"00110"_b, "ldr_s_ldst_regoff"},
+ {"10010"_b, "str_d_ldst_regoff"},
+ {"10110"_b, "ldr_d_ldst_regoff"},
},
},
- { "Decode_xpvpqq",
+ { "_xpvpqq",
{23, 22, 11, 10, 4, 3, 2},
- { {"0000000", "Decode_hngpxg"},
- {"0010111", "Decode_gnytkh"},
- {"0011111", "Decode_xjxppp"},
- {"0100000", "Decode_nnhprs"},
- {"0110111", "Decode_hmtxlh"},
- {"0111111", "Decode_qtxypt"},
- {"1000000", "Decode_rmltms"},
- {"1010111", "Decode_qqpkkm"},
- {"1011111", "Decode_klnhpj"},
+ { {"0000000"_b, "_hngpxg"},
+ {"0010111"_b, "_gnytkh"},
+ {"0011111"_b, "_xjxppp"},
+ {"0100000"_b, "_nnhprs"},
+ {"0110111"_b, "_hmtxlh"},
+ {"0111111"_b, "_qtxypt"},
+ {"1000000"_b, "_rmltms"},
+ {"1010111"_b, "_qqpkkm"},
+ {"1011111"_b, "_klnhpj"},
},
},
- { "Decode_xqgxjp",
+ { "_xqgxjp",
{18, 17, 16, 13, 12, 11, 10, 9, 7, 6, 5},
- { {"01111000011", "Decode_vyztqx"},
+ { {"01111000011"_b, "_vyztqx"},
},
},
- { "Decode_xqhgkk",
+ { "_xqhgkk",
{30},
- { {"0", "Visit_b_only_branch_imm"},
+ { {"0"_b, "b_only_branch_imm"},
},
},
- { "Decode_xqjrgk",
+ { "_xqjrgk",
{12},
- { {"0", "Visit_ld4_asisdlsop_dx4_r4d"},
+ { {"0"_b, "ld4_asisdlsop_dx4_r4d"},
},
},
- { "Decode_xrhhjz",
+ { "_xrhhjz",
{11},
- { {"0", "Decode_hzxjsp"},
+ { {"0"_b, "_hzxjsp"},
},
},
- { "Decode_xrhmtg",
+ { "_xrhmtg",
{30, 23, 22, 11, 10},
- { {"00000", "Visit_stur_s_ldst_unscaled"},
- {"00001", "Visit_str_s_ldst_immpost"},
- {"00011", "Visit_str_s_ldst_immpre"},
- {"00100", "Visit_ldur_s_ldst_unscaled"},
- {"00101", "Visit_ldr_s_ldst_immpost"},
- {"00111", "Visit_ldr_s_ldst_immpre"},
- {"10000", "Visit_stur_d_ldst_unscaled"},
- {"10001", "Visit_str_d_ldst_immpost"},
- {"10011", "Visit_str_d_ldst_immpre"},
- {"10100", "Visit_ldur_d_ldst_unscaled"},
- {"10101", "Visit_ldr_d_ldst_immpost"},
- {"10111", "Visit_ldr_d_ldst_immpre"},
+ { {"00000"_b, "stur_s_ldst_unscaled"},
+ {"00001"_b, "str_s_ldst_immpost"},
+ {"00011"_b, "str_s_ldst_immpre"},
+ {"00100"_b, "ldur_s_ldst_unscaled"},
+ {"00101"_b, "ldr_s_ldst_immpost"},
+ {"00111"_b, "ldr_s_ldst_immpre"},
+ {"10000"_b, "stur_d_ldst_unscaled"},
+ {"10001"_b, "str_d_ldst_immpost"},
+ {"10011"_b, "str_d_ldst_immpre"},
+ {"10100"_b, "ldur_d_ldst_unscaled"},
+ {"10101"_b, "ldr_d_ldst_immpost"},
+ {"10111"_b, "ldr_d_ldst_immpre"},
},
},
- { "Decode_xrpmzt",
+ { "_xrpmzt",
{17},
- { {"0", "Visit_st4_asisdlsop_hx4_r4h"},
- {"1", "Visit_st4_asisdlsop_h4_i4h"},
+ { {"0"_b, "st4_asisdlsop_hx4_r4h"},
+ {"1"_b, "st4_asisdlsop_h4_i4h"},
},
},
- { "Decode_xrxvpr",
+ { "_xrxvpr",
{23, 22},
- { {"00", "Decode_spmkmm"},
+ { {"00"_b, "_spmkmm"},
},
},
- { "Decode_xryzqs",
+ { "_xryzqs",
{30, 23, 22, 13, 12, 11, 10},
- { {"0001111", "Visit_caspl_cp32_ldstexcl"},
- {"0011111", "Visit_caspal_cp32_ldstexcl"},
- {"0101111", "Visit_caslb_c32_ldstexcl"},
- {"0111111", "Visit_casalb_c32_ldstexcl"},
- {"1001111", "Visit_caspl_cp64_ldstexcl"},
- {"1011111", "Visit_caspal_cp64_ldstexcl"},
- {"1101111", "Visit_caslh_c32_ldstexcl"},
- {"1111111", "Visit_casalh_c32_ldstexcl"},
+ { {"0001111"_b, "caspl_cp32_ldstexcl"},
+ {"0011111"_b, "caspal_cp32_ldstexcl"},
+ {"0101111"_b, "caslb_c32_ldstexcl"},
+ {"0111111"_b, "casalb_c32_ldstexcl"},
+ {"1001111"_b, "caspl_cp64_ldstexcl"},
+ {"1011111"_b, "caspal_cp64_ldstexcl"},
+ {"1101111"_b, "caslh_c32_ldstexcl"},
+ {"1111111"_b, "casalh_c32_ldstexcl"},
},
},
- { "Decode_xsgxyy",
+ { "_xsgxyy",
{9, 8, 7, 6, 5},
- { {"11111", "Visit_autizb_64z_dp_1src"},
+ { {"11111"_b, "autizb_64z_dp_1src"},
},
},
- { "Decode_xstkrn",
+ { "_xstkrn",
{20, 19},
- { {"00", "Decode_hrllsn"},
- {"01", "Decode_kqvljp"},
- {"10", "Decode_lxhlkx"},
- {"11", "Decode_rjysnh"},
+ { {"00"_b, "_hrllsn"},
+ {"01"_b, "_kqvljp"},
+ {"10"_b, "_lxhlkx"},
+ {"11"_b, "_rjysnh"},
},
},
- { "Decode_xtgtyz",
+ { "_xtgtyz",
{19, 18, 17, 16},
- { {"0000", "Visit_brkb_p_p_p"},
+ { {"0000"_b, "brkb_p_p_p"},
},
},
- { "Decode_xtqmyj",
+ { "_xtqmyj",
{30, 23, 22},
- { {"000", "Visit_orr_32_log_imm"},
- {"100", "Visit_ands_32s_log_imm"},
- {"110", "Visit_movk_32_movewide"},
+ { {"000"_b, "orr_32_log_imm"},
+ {"100"_b, "ands_32s_log_imm"},
+ {"110"_b, "movk_32_movewide"},
},
},
- { "Decode_xtxyxj",
+ { "_xtxyxj",
{4},
- { {"0", "Visit_orr_p_p_pp_z"},
- {"1", "Visit_orn_p_p_pp_z"},
+ { {"0"_b, "orr_p_p_pp_z"},
+ {"1"_b, "orn_p_p_pp_z"},
},
},
- { "Decode_xtzlzy",
+ { "_xtzlzy",
{12, 11, 10},
- { {"000", "Visit_fadd_z_zz"},
- {"001", "Visit_fsub_z_zz"},
- {"010", "Visit_fmul_z_zz"},
- {"011", "Visit_ftsmul_z_zz"},
- {"110", "Visit_frecps_z_zz"},
- {"111", "Visit_frsqrts_z_zz"},
+ { {"000"_b, "fadd_z_zz"},
+ {"001"_b, "fsub_z_zz"},
+ {"010"_b, "fmul_z_zz"},
+ {"011"_b, "ftsmul_z_zz"},
+ {"110"_b, "frecps_z_zz"},
+ {"111"_b, "frsqrts_z_zz"},
},
},
- { "Decode_xvlnmy",
+ { "_xvlnmy",
{9, 8, 7, 6, 5},
- { {"11111", "Visit_autdza_64z_dp_1src"},
+ { {"11111"_b, "autdza_64z_dp_1src"},
},
},
- { "Decode_xvnyxq",
+ { "_xvnyxq",
{30, 23, 13, 4},
- { {"0000", "Visit_prfb_i_p_bz_s_x32_scaled"},
- {"0010", "Visit_prfh_i_p_bz_s_x32_scaled"},
- {"010x", "Visit_ld1sh_z_p_bz_s_x32_scaled"},
- {"011x", "Visit_ldff1sh_z_p_bz_s_x32_scaled"},
- {"1000", "Visit_prfb_i_p_bz_d_x32_scaled"},
- {"1010", "Visit_prfh_i_p_bz_d_x32_scaled"},
- {"110x", "Visit_ld1sh_z_p_bz_d_x32_scaled"},
- {"111x", "Visit_ldff1sh_z_p_bz_d_x32_scaled"},
+ { {"0000"_b, "prfb_i_p_bz_s_x32_scaled"},
+ {"0010"_b, "prfh_i_p_bz_s_x32_scaled"},
+ {"010x"_b, "ld1sh_z_p_bz_s_x32_scaled"},
+ {"011x"_b, "ldff1sh_z_p_bz_s_x32_scaled"},
+ {"1000"_b, "prfb_i_p_bz_d_x32_scaled"},
+ {"1010"_b, "prfh_i_p_bz_d_x32_scaled"},
+ {"110x"_b, "ld1sh_z_p_bz_d_x32_scaled"},
+ {"111x"_b, "ldff1sh_z_p_bz_d_x32_scaled"},
},
},
- { "Decode_xvppmm",
+ { "_xvppmm",
{30, 23, 22, 13, 12, 11, 10},
- { {"0xx0xxx", "Visit_mla_z_p_zzz"},
- {"0xx1xxx", "Visit_mls_z_p_zzz"},
- {"1101110", "Visit_usdot_z_zzz_s"},
- {"1xx0000", "Visit_smlalb_z_zzz"},
- {"1xx0001", "Visit_smlalt_z_zzz"},
- {"1xx0010", "Visit_umlalb_z_zzz"},
- {"1xx0011", "Visit_umlalt_z_zzz"},
- {"1xx0100", "Visit_smlslb_z_zzz"},
- {"1xx0101", "Visit_smlslt_z_zzz"},
- {"1xx0110", "Visit_umlslb_z_zzz"},
- {"1xx0111", "Visit_umlslt_z_zzz"},
- {"1xx1000", "Visit_sqdmlalb_z_zzz"},
- {"1xx1001", "Visit_sqdmlalt_z_zzz"},
- {"1xx1010", "Visit_sqdmlslb_z_zzz"},
- {"1xx1011", "Visit_sqdmlslt_z_zzz"},
- {"1xx1100", "Visit_sqrdmlah_z_zzz"},
- {"1xx1101", "Visit_sqrdmlsh_z_zzz"},
+ { {"0xx0xxx"_b, "mla_z_p_zzz"},
+ {"0xx1xxx"_b, "mls_z_p_zzz"},
+ {"1101110"_b, "usdot_z_zzz_s"},
+ {"1xx0000"_b, "smlalb_z_zzz"},
+ {"1xx0001"_b, "smlalt_z_zzz"},
+ {"1xx0010"_b, "umlalb_z_zzz"},
+ {"1xx0011"_b, "umlalt_z_zzz"},
+ {"1xx0100"_b, "smlslb_z_zzz"},
+ {"1xx0101"_b, "smlslt_z_zzz"},
+ {"1xx0110"_b, "umlslb_z_zzz"},
+ {"1xx0111"_b, "umlslt_z_zzz"},
+ {"1xx1000"_b, "sqdmlalb_z_zzz"},
+ {"1xx1001"_b, "sqdmlalt_z_zzz"},
+ {"1xx1010"_b, "sqdmlslb_z_zzz"},
+ {"1xx1011"_b, "sqdmlslt_z_zzz"},
+ {"1xx1100"_b, "sqrdmlah_z_zzz"},
+ {"1xx1101"_b, "sqrdmlsh_z_zzz"},
},
},
- { "Decode_xxjrsy",
+ { "_xxjrsy",
{23, 22, 9},
- { {"000", "Visit_rdffr_p_p_f"},
- {"010", "Visit_rdffrs_p_p_f"},
+ { {"000"_b, "rdffr_p_p_f"},
+ {"010"_b, "rdffrs_p_p_f"},
},
},
- { "Decode_xxkvsy",
+ { "_xxkvsy",
{30, 22, 11, 10},
- { {"0000", "Visit_csel_64_condsel"},
- {"0001", "Visit_csinc_64_condsel"},
- {"0111", "Decode_tnxlnl"},
- {"1000", "Visit_csinv_64_condsel"},
- {"1001", "Visit_csneg_64_condsel"},
- {"1100", "Decode_qjyvln"},
- {"1101", "Decode_nvthzh"},
+ { {"0000"_b, "csel_64_condsel"},
+ {"0001"_b, "csinc_64_condsel"},
+ {"0111"_b, "_tnxlnl"},
+ {"1000"_b, "csinv_64_condsel"},
+ {"1001"_b, "csneg_64_condsel"},
+ {"1100"_b, "_qjyvln"},
+ {"1101"_b, "_nvthzh"},
},
},
- { "Decode_xxpqgg",
+ { "_xxpqgg",
{30, 23, 22},
- { {"001", "Visit_sbfm_64m_bitfield"},
- {"011", "Visit_extr_64_extract"},
- {"101", "Visit_ubfm_64m_bitfield"},
+ { {"001"_b, "sbfm_64m_bitfield"},
+ {"011"_b, "extr_64_extract"},
+ {"101"_b, "ubfm_64m_bitfield"},
},
},
- { "Decode_xxpzrl",
+ { "_xxpzrl",
{13},
- { {"0", "Visit_mls_asimdelem_r"},
- {"1", "Visit_umlsl_asimdelem_l"},
+ { {"0"_b, "mls_asimdelem_r"},
+ {"1"_b, "umlsl_asimdelem_l"},
},
},
- { "Decode_xxxxlh",
+ { "_xxxxlh",
{4},
- { {"0", "Visit_ccmn_64_condcmp_imm"},
+ { {"0"_b, "ccmn_64_condcmp_imm"},
},
},
- { "Decode_xxyklv",
+ { "_xxyklv",
{23, 22, 13, 12, 11, 10},
- { {"000000", "Visit_tbl_asimdtbl_l3_3"},
- {"000100", "Visit_tbx_asimdtbl_l3_3"},
- {"001000", "Visit_tbl_asimdtbl_l4_4"},
- {"001100", "Visit_tbx_asimdtbl_l4_4"},
- {"xx0110", "Visit_uzp2_asimdperm_only"},
- {"xx1010", "Visit_trn2_asimdperm_only"},
- {"xx1110", "Visit_zip2_asimdperm_only"},
+ { {"000000"_b, "tbl_asimdtbl_l3_3"},
+ {"000100"_b, "tbx_asimdtbl_l3_3"},
+ {"001000"_b, "tbl_asimdtbl_l4_4"},
+ {"001100"_b, "tbx_asimdtbl_l4_4"},
+ {"xx0110"_b, "uzp2_asimdperm_only"},
+ {"xx1010"_b, "trn2_asimdperm_only"},
+ {"xx1110"_b, "zip2_asimdperm_only"},
},
},
- { "Decode_xygxsv",
+ { "_xygxsv",
{17},
- { {"0", "Visit_ld3_asisdlsop_hx3_r3h"},
- {"1", "Visit_ld3_asisdlsop_h3_i3h"},
+ { {"0"_b, "ld3_asisdlsop_hx3_r3h"},
+ {"1"_b, "ld3_asisdlsop_h3_i3h"},
},
},
- { "Decode_xyhmgh",
+ { "_xyhmgh",
{23, 22, 20, 9},
- { {"0000", "Decode_xhmpmy"},
- {"0001", "Decode_qnprqt"},
- {"0010", "Decode_nnzhgm"},
- {"0100", "Decode_vvxsxt"},
- {"0101", "Decode_yzmjhn"},
- {"0110", "Decode_mkgsly"},
- {"1000", "Decode_xtxyxj"},
- {"1001", "Decode_hmtmlq"},
- {"1010", "Decode_xtgtyz"},
- {"1100", "Decode_yynmjl"},
- {"1101", "Decode_sjnspg"},
- {"1110", "Decode_jzjvtv"},
+ { {"0000"_b, "_xhmpmy"},
+ {"0001"_b, "_qnprqt"},
+ {"0010"_b, "_nnzhgm"},
+ {"0100"_b, "_vvxsxt"},
+ {"0101"_b, "_yzmjhn"},
+ {"0110"_b, "_mkgsly"},
+ {"1000"_b, "_xtxyxj"},
+ {"1001"_b, "_hmtmlq"},
+ {"1010"_b, "_xtgtyz"},
+ {"1100"_b, "_yynmjl"},
+ {"1101"_b, "_sjnspg"},
+ {"1110"_b, "_jzjvtv"},
},
},
- { "Decode_xyhxzt",
+ { "_xyhxzt",
{22},
- { {"0", "Visit_prfm_p_ldst_regoff"},
+ { {"0"_b, "prfm_p_ldst_regoff"},
},
},
- { "Decode_xyljvp",
+ { "_xyljvp",
{30, 23, 22, 11, 10},
- { {"00000", "Decode_yjpstj"},
- {"01000", "Visit_csel_64_condsel"},
- {"01001", "Visit_csinc_64_condsel"},
- {"01100", "Decode_qghmks"},
- {"01101", "Decode_qzzlpv"},
- {"01110", "Decode_syktsg"},
- {"01111", "Decode_hjtvvm"},
- {"10000", "Decode_pvrylp"},
- {"11000", "Visit_csinv_64_condsel"},
- {"11001", "Visit_csneg_64_condsel"},
- {"11100", "Decode_kkgpjl"},
- {"11101", "Decode_tjtgjy"},
- {"11110", "Decode_qmzqsy"},
- {"11111", "Decode_nmkqzt"},
+ { {"00000"_b, "_yjpstj"},
+ {"01000"_b, "csel_64_condsel"},
+ {"01001"_b, "csinc_64_condsel"},
+ {"01100"_b, "_qghmks"},
+ {"01101"_b, "_qzzlpv"},
+ {"01110"_b, "_syktsg"},
+ {"01111"_b, "_hjtvvm"},
+ {"10000"_b, "_pvrylp"},
+ {"11000"_b, "csinv_64_condsel"},
+ {"11001"_b, "csneg_64_condsel"},
+ {"11100"_b, "_kkgpjl"},
+ {"11101"_b, "_tjtgjy"},
+ {"11110"_b, "_qmzqsy"},
+ {"11111"_b, "_nmkqzt"},
},
},
- { "Decode_xylmmp",
+ { "_xylmmp",
{22, 12},
- { {"10", "Decode_nkjgpq"},
+ { {"10"_b, "_nkjgpq"},
},
},
- { "Decode_xyzpvp",
+ { "_xyzpvp",
{23, 22, 13},
- { {"100", "Visit_fmlsl_asimdelem_lh"},
- {"xx1", "Visit_smlsl_asimdelem_l"},
+ { {"100"_b, "fmlsl_asimdelem_lh"},
+ {"xx1"_b, "smlsl_asimdelem_l"},
},
},
- { "Decode_xzmjxk",
+ { "_xzmjxk",
{30},
- { {"1", "Decode_sntzjg"},
+ { {"1"_b, "_sntzjg"},
},
},
- { "Decode_xznsqh",
+ { "_xznsqh",
{22, 20, 11},
- { {"000", "Visit_cntw_r_s"},
- {"010", "Visit_incw_r_rs"},
- {"100", "Visit_cntd_r_s"},
- {"110", "Visit_incd_r_rs"},
+ { {"000"_b, "cntw_r_s"},
+ {"010"_b, "incw_r_rs"},
+ {"100"_b, "cntd_r_s"},
+ {"110"_b, "incd_r_rs"},
},
},
- { "Decode_xzyxnr",
+ { "_xzyxnr",
{30, 23, 22, 11, 10},
- { {"10001", "Visit_stg_64spost_ldsttags"},
- {"10010", "Visit_stg_64soffset_ldsttags"},
- {"10011", "Visit_stg_64spre_ldsttags"},
- {"10100", "Visit_ldg_64loffset_ldsttags"},
- {"10101", "Visit_stzg_64spost_ldsttags"},
- {"10110", "Visit_stzg_64soffset_ldsttags"},
- {"10111", "Visit_stzg_64spre_ldsttags"},
- {"11001", "Visit_st2g_64spost_ldsttags"},
- {"11010", "Visit_st2g_64soffset_ldsttags"},
- {"11011", "Visit_st2g_64spre_ldsttags"},
- {"11101", "Visit_stz2g_64spost_ldsttags"},
- {"11110", "Visit_stz2g_64soffset_ldsttags"},
- {"11111", "Visit_stz2g_64spre_ldsttags"},
+ { {"10001"_b, "stg_64spost_ldsttags"},
+ {"10010"_b, "stg_64soffset_ldsttags"},
+ {"10011"_b, "stg_64spre_ldsttags"},
+ {"10100"_b, "ldg_64loffset_ldsttags"},
+ {"10101"_b, "stzg_64spost_ldsttags"},
+ {"10110"_b, "stzg_64soffset_ldsttags"},
+ {"10111"_b, "stzg_64spre_ldsttags"},
+ {"11001"_b, "st2g_64spost_ldsttags"},
+ {"11010"_b, "st2g_64soffset_ldsttags"},
+ {"11011"_b, "st2g_64spre_ldsttags"},
+ {"11101"_b, "stz2g_64spost_ldsttags"},
+ {"11110"_b, "stz2g_64soffset_ldsttags"},
+ {"11111"_b, "stz2g_64spre_ldsttags"},
},
},
- { "Decode_xzyylk",
+ { "_xzyylk",
{20, 19, 18, 17, 16, 13},
- { {"000000", "Visit_fabs_s_floatdp1"},
- {"000010", "Visit_fsqrt_s_floatdp1"},
- {"000100", "Visit_fcvt_ds_floatdp1"},
- {"000110", "Visit_fcvt_hs_floatdp1"},
- {"001000", "Visit_frintp_s_floatdp1"},
- {"001010", "Visit_frintz_s_floatdp1"},
- {"001110", "Visit_frinti_s_floatdp1"},
- {"010000", "Visit_frint32x_s_floatdp1"},
- {"010010", "Visit_frint64x_s_floatdp1"},
+ { {"000000"_b, "fabs_s_floatdp1"},
+ {"000010"_b, "fsqrt_s_floatdp1"},
+ {"000100"_b, "fcvt_ds_floatdp1"},
+ {"000110"_b, "fcvt_hs_floatdp1"},
+ {"001000"_b, "frintp_s_floatdp1"},
+ {"001010"_b, "frintz_s_floatdp1"},
+ {"001110"_b, "frinti_s_floatdp1"},
+ {"010000"_b, "frint32x_s_floatdp1"},
+ {"010010"_b, "frint64x_s_floatdp1"},
},
},
- { "Decode_ygjslq",
+ { "_ygjslq",
{4, 3, 2, 1, 0},
- { {"00000", "Visit_fcmp_h_floatcmp"},
- {"01000", "Visit_fcmp_hz_floatcmp"},
- {"10000", "Visit_fcmpe_h_floatcmp"},
- {"11000", "Visit_fcmpe_hz_floatcmp"},
+ { {"00000"_b, "fcmp_h_floatcmp"},
+ {"01000"_b, "fcmp_hz_floatcmp"},
+ {"10000"_b, "fcmpe_h_floatcmp"},
+ {"11000"_b, "fcmpe_hz_floatcmp"},
},
},
- { "Decode_ygnypk",
+ { "_ygnypk",
{22, 12},
- { {"10", "Decode_nqlgtn"},
+ { {"10"_b, "_nqlgtn"},
},
},
- { "Decode_ygpjrl",
+ { "_ygpjrl",
{13, 12},
- { {"00", "Visit_adc_32_addsub_carry"},
+ { {"00"_b, "adc_32_addsub_carry"},
},
},
- { "Decode_ygxhyg",
+ { "_ygxhyg",
{23, 22, 4},
- { {"000", "Visit_fccmp_s_floatccmp"},
- {"001", "Visit_fccmpe_s_floatccmp"},
- {"010", "Visit_fccmp_d_floatccmp"},
- {"011", "Visit_fccmpe_d_floatccmp"},
- {"110", "Visit_fccmp_h_floatccmp"},
- {"111", "Visit_fccmpe_h_floatccmp"},
+ { {"000"_b, "fccmp_s_floatccmp"},
+ {"001"_b, "fccmpe_s_floatccmp"},
+ {"010"_b, "fccmp_d_floatccmp"},
+ {"011"_b, "fccmpe_d_floatccmp"},
+ {"110"_b, "fccmp_h_floatccmp"},
+ {"111"_b, "fccmpe_h_floatccmp"},
},
},
- { "Decode_ygyxvx",
+ { "_ygyxvx",
{18, 17},
- { {"00", "Visit_ld2_asisdlso_s2_2s"},
+ { {"00"_b, "ld2_asisdlso_s2_2s"},
},
},
- { "Decode_yhlntp",
+ { "_yhlntp",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_fexpa_z_z"},
+ { {"00000"_b, "fexpa_z_z"},
},
},
- { "Decode_yhmlxk",
+ { "_yhmlxk",
{13, 12, 11, 10},
- { {"0000", "Visit_decp_z_p_z"},
- {"0010", "Visit_decp_r_p_r"},
+ { {"0000"_b, "decp_z_p_z"},
+ {"0010"_b, "decp_r_p_r"},
},
},
- { "Decode_yhqyzj",
+ { "_yhqyzj",
{9, 8, 7, 6, 5},
- { {"00000", "Visit_fmov_d_floatimm"},
+ { {"00000"_b, "fmov_d_floatimm"},
},
},
- { "Decode_yhxvhy",
+ { "_yhxvhy",
{17},
- { {"0", "Visit_st4_asisdlso_b4_4b"},
+ { {"0"_b, "st4_asisdlso_b4_4b"},
},
},
- { "Decode_yjjrgg",
+ { "_yjjrgg",
{30},
- { {"0", "Visit_cbnz_64_compbranch"},
+ { {"0"_b, "cbnz_64_compbranch"},
},
},
- { "Decode_yjmngt",
+ { "_yjmngt",
{30},
- { {"0", "Visit_sel_z_p_zz"},
- {"1", "Decode_vpmxrj"},
+ { {"0"_b, "sel_z_p_zz"},
+ {"1"_b, "_vpmxrj"},
},
},
- { "Decode_yjpstj",
+ { "_yjpstj",
{13, 12},
- { {"00", "Visit_adc_64_addsub_carry"},
+ { {"00"_b, "adc_64_addsub_carry"},
},
},
- { "Decode_yjsjvt",
+ { "_yjsjvt",
{30, 23, 22, 11, 10},
- { {"00000", "Decode_vxsvhs"},
- {"00001", "Decode_rhzhyz"},
- {"00100", "Decode_zjsgkm"},
- {"00110", "Decode_xxxxlh"},
- {"01100", "Decode_mtjrtt"},
- {"10000", "Decode_yskkjs"},
- {"10100", "Decode_mjxzks"},
- {"10110", "Decode_tpkzxg"},
+ { {"00000"_b, "_vxsvhs"},
+ {"00001"_b, "_rhzhyz"},
+ {"00100"_b, "_zjsgkm"},
+ {"00110"_b, "_xxxxlh"},
+ {"01100"_b, "_mtjrtt"},
+ {"10000"_b, "_yskkjs"},
+ {"10100"_b, "_mjxzks"},
+ {"10110"_b, "_tpkzxg"},
},
},
- { "Decode_yjxshz",
+ { "_yjxshz",
{30, 23, 22, 11, 10},
- { {"00000", "Visit_stlurb_32_ldapstl_unscaled"},
- {"00100", "Visit_ldapurb_32_ldapstl_unscaled"},
- {"01000", "Visit_ldapursb_64_ldapstl_unscaled"},
- {"01100", "Visit_ldapursb_32_ldapstl_unscaled"},
- {"10000", "Visit_stlurh_32_ldapstl_unscaled"},
- {"10100", "Visit_ldapurh_32_ldapstl_unscaled"},
- {"11000", "Visit_ldapursh_64_ldapstl_unscaled"},
- {"11100", "Visit_ldapursh_32_ldapstl_unscaled"},
+ { {"00000"_b, "stlurb_32_ldapstl_unscaled"},
+ {"00100"_b, "ldapurb_32_ldapstl_unscaled"},
+ {"01000"_b, "ldapursb_64_ldapstl_unscaled"},
+ {"01100"_b, "ldapursb_32_ldapstl_unscaled"},
+ {"10000"_b, "stlurh_32_ldapstl_unscaled"},
+ {"10100"_b, "ldapurh_32_ldapstl_unscaled"},
+ {"11000"_b, "ldapursh_64_ldapstl_unscaled"},
+ {"11100"_b, "ldapursh_32_ldapstl_unscaled"},
},
},
- { "Decode_yjxvkp",
+ { "_yjxvkp",
{18, 17, 12},
- { {"0x0", "Visit_st4_asisdlsop_dx4_r4d"},
- {"100", "Visit_st4_asisdlsop_dx4_r4d"},
- {"110", "Visit_st4_asisdlsop_d4_i4d"},
+ { {"0x0"_b, "st4_asisdlsop_dx4_r4d"},
+ {"100"_b, "st4_asisdlsop_dx4_r4d"},
+ {"110"_b, "st4_asisdlsop_d4_i4d"},
},
},
- { "Decode_yjzknm",
+ { "_yjzknm",
{13, 12, 11, 10},
- { {"0000", "Visit_uqdecp_z_p_z"},
- {"0010", "Visit_uqdecp_r_p_r_uw"},
- {"0011", "Visit_uqdecp_r_p_r_x"},
+ { {"0000"_b, "uqdecp_z_p_z"},
+ {"0010"_b, "uqdecp_r_p_r_uw"},
+ {"0011"_b, "uqdecp_r_p_r_x"},
},
},
- { "Decode_yjztsq",
+ { "_yjztsq",
{20, 19, 18, 17, 16},
- { {"11111", "Visit_st64b_64l_memop"},
+ { {"11111"_b, "st64b_64l_memop"},
},
},
- { "Decode_ylhxlt",
+ { "_ylhxlt",
{30},
- { {"0", "Visit_ldrsw_64_loadlit"},
- {"1", "Visit_prfm_p_loadlit"},
+ { {"0"_b, "ldrsw_64_loadlit"},
+ {"1"_b, "prfm_p_loadlit"},
},
},
- { "Decode_ylnsvy",
+ { "_ylnsvy",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_dup_z_r"},
- {"00100", "Visit_insr_z_r"},
- {"10000", "Visit_sunpklo_z_z"},
- {"10001", "Visit_sunpkhi_z_z"},
- {"10010", "Visit_uunpklo_z_z"},
- {"10011", "Visit_uunpkhi_z_z"},
- {"10100", "Visit_insr_z_v"},
- {"11000", "Visit_rev_z_z"},
+ { {"00000"_b, "dup_z_r"},
+ {"00100"_b, "insr_z_r"},
+ {"10000"_b, "sunpklo_z_z"},
+ {"10001"_b, "sunpkhi_z_z"},
+ {"10010"_b, "uunpklo_z_z"},
+ {"10011"_b, "uunpkhi_z_z"},
+ {"10100"_b, "insr_z_v"},
+ {"11000"_b, "rev_z_z"},
},
},
- { "Decode_ylqnqt",
+ { "_ylqnqt",
{18, 17, 12},
- { {"000", "Visit_ld4_asisdlso_d4_4d"},
+ { {"000"_b, "ld4_asisdlso_d4_4d"},
},
},
- { "Decode_ylyskq",
+ { "_ylyskq",
{13, 12, 11, 10},
- { {"0011", "Visit_uqadd_asisdsame_only"},
- {"1010", "Decode_yzqtyl"},
- {"1011", "Visit_uqsub_asisdsame_only"},
- {"1101", "Visit_cmhi_asisdsame_only"},
- {"1110", "Decode_jxzrxm"},
- {"1111", "Visit_cmhs_asisdsame_only"},
+ { {"0011"_b, "uqadd_asisdsame_only"},
+ {"1010"_b, "_yzqtyl"},
+ {"1011"_b, "uqsub_asisdsame_only"},
+ {"1101"_b, "cmhi_asisdsame_only"},
+ {"1110"_b, "_jxzrxm"},
+ {"1111"_b, "cmhs_asisdsame_only"},
},
},
- { "Decode_ymgrgx",
+ { "_ymgrgx",
{22, 20, 19, 18, 17, 16},
- { {"111001", "Visit_ucvtf_asisdmiscfp16_r"},
- {"x00001", "Visit_ucvtf_asisdmisc_r"},
- {"x10000", "Visit_faddp_asisdpair_only_sd"},
+ { {"111001"_b, "ucvtf_asisdmiscfp16_r"},
+ {"x00001"_b, "ucvtf_asisdmisc_r"},
+ {"x10000"_b, "faddp_asisdpair_only_sd"},
},
},
- { "Decode_ymhgxg",
+ { "_ymhgxg",
{30, 13},
- { {"00", "Decode_yrmmmg"},
- {"01", "Decode_sghgtk"},
- {"10", "Decode_nxjkqs"},
- {"11", "Decode_yvyhlh"},
+ { {"00"_b, "_yrmmmg"},
+ {"01"_b, "_sghgtk"},
+ {"10"_b, "_nxjkqs"},
+ {"11"_b, "_yvyhlh"},
},
},
- { "Decode_ymhkrx",
+ { "_ymhkrx",
{30, 23, 22, 13, 4},
- { {"0000x", "Visit_ld1b_z_p_ai_s"},
- {"0001x", "Visit_ldff1b_z_p_ai_s"},
- {"0010x", "Visit_ld1rb_z_p_bi_u32"},
- {"0011x", "Visit_ld1rb_z_p_bi_u64"},
- {"0100x", "Visit_ld1h_z_p_ai_s"},
- {"0101x", "Visit_ldff1h_z_p_ai_s"},
- {"0110x", "Visit_ld1rh_z_p_bi_u32"},
- {"0111x", "Visit_ld1rh_z_p_bi_u64"},
- {"1000x", "Visit_ld1b_z_p_ai_d"},
- {"1001x", "Visit_ldff1b_z_p_ai_d"},
- {"10100", "Visit_prfw_i_p_bz_d_64_scaled"},
- {"10110", "Visit_prfd_i_p_bz_d_64_scaled"},
- {"1100x", "Visit_ld1h_z_p_ai_d"},
- {"1101x", "Visit_ldff1h_z_p_ai_d"},
- {"1110x", "Visit_ld1h_z_p_bz_d_64_scaled"},
- {"1111x", "Visit_ldff1h_z_p_bz_d_64_scaled"},
+ { {"0000x"_b, "ld1b_z_p_ai_s"},
+ {"0001x"_b, "ldff1b_z_p_ai_s"},
+ {"0010x"_b, "ld1rb_z_p_bi_u32"},
+ {"0011x"_b, "ld1rb_z_p_bi_u64"},
+ {"0100x"_b, "ld1h_z_p_ai_s"},
+ {"0101x"_b, "ldff1h_z_p_ai_s"},
+ {"0110x"_b, "ld1rh_z_p_bi_u32"},
+ {"0111x"_b, "ld1rh_z_p_bi_u64"},
+ {"1000x"_b, "ld1b_z_p_ai_d"},
+ {"1001x"_b, "ldff1b_z_p_ai_d"},
+ {"10100"_b, "prfw_i_p_bz_d_64_scaled"},
+ {"10110"_b, "prfd_i_p_bz_d_64_scaled"},
+ {"1100x"_b, "ld1h_z_p_ai_d"},
+ {"1101x"_b, "ldff1h_z_p_ai_d"},
+ {"1110x"_b, "ld1h_z_p_bz_d_64_scaled"},
+ {"1111x"_b, "ldff1h_z_p_bz_d_64_scaled"},
},
},
- { "Decode_ymkthj",
+ { "_ymkthj",
{20, 9, 4},
- { {"000", "Visit_uzp2_p_pp"},
+ { {"000"_b, "uzp2_p_pp"},
},
},
- { "Decode_ympyng",
+ { "_ympyng",
{30, 23, 22, 13},
- { {"0000", "Visit_ld1sh_z_p_br_s64"},
- {"0001", "Visit_ldff1sh_z_p_br_s64"},
- {"0010", "Visit_ld1w_z_p_br_u32"},
- {"0011", "Visit_ldff1w_z_p_br_u32"},
- {"0100", "Visit_ld1sb_z_p_br_s64"},
- {"0101", "Visit_ldff1sb_z_p_br_s64"},
- {"0110", "Visit_ld1sb_z_p_br_s16"},
- {"0111", "Visit_ldff1sb_z_p_br_s16"},
- {"1001", "Visit_stnt1w_z_p_br_contiguous"},
- {"1011", "Visit_st3w_z_p_br_contiguous"},
- {"10x0", "Visit_st1w_z_p_br"},
- {"1100", "Visit_str_z_bi"},
- {"1101", "Visit_stnt1d_z_p_br_contiguous"},
- {"1111", "Visit_st3d_z_p_br_contiguous"},
+ { {"0000"_b, "ld1sh_z_p_br_s64"},
+ {"0001"_b, "ldff1sh_z_p_br_s64"},
+ {"0010"_b, "ld1w_z_p_br_u32"},
+ {"0011"_b, "ldff1w_z_p_br_u32"},
+ {"0100"_b, "ld1sb_z_p_br_s64"},
+ {"0101"_b, "ldff1sb_z_p_br_s64"},
+ {"0110"_b, "ld1sb_z_p_br_s16"},
+ {"0111"_b, "ldff1sb_z_p_br_s16"},
+ {"1001"_b, "stnt1w_z_p_br_contiguous"},
+ {"1011"_b, "st3w_z_p_br_contiguous"},
+ {"10x0"_b, "st1w_z_p_br"},
+ {"1100"_b, "str_z_bi"},
+ {"1101"_b, "stnt1d_z_p_br_contiguous"},
+ {"1111"_b, "st3d_z_p_br_contiguous"},
},
},
- { "Decode_ymznlj",
+ { "_ymznlj",
{13, 10},
- { {"00", "Decode_vgrtjz"},
- {"01", "Decode_kxjgsz"},
- {"10", "Decode_vmjtrx"},
- {"11", "Decode_tgmljr"},
+ { {"00"_b, "_vgrtjz"},
+ {"01"_b, "_kxjgsz"},
+ {"10"_b, "_vmjtrx"},
+ {"11"_b, "_tgmljr"},
},
},
- { "Decode_ynnrny",
+ { "_ynnrny",
{18, 17},
- { {"00", "Decode_jplmmr"},
+ { {"00"_b, "_jplmmr"},
},
},
- { "Decode_ynqsgl",
+ { "_ynqsgl",
{17},
- { {"0", "Visit_ld4_asisdlso_h4_4h"},
+ { {"0"_b, "ld4_asisdlso_h4_4h"},
},
},
- { "Decode_ypjyqh",
+ { "_ypjyqh",
{9, 8, 7, 6, 5, 0},
- { {"111110", "Visit_drps_64e_branch_reg"},
+ { {"111110"_b, "drps_64e_branch_reg"},
},
},
- { "Decode_yplktv",
+ { "_yplktv",
{13, 12, 11, 10},
- { {"0001", "Visit_sub_asisdsame_only"},
- {"0010", "Decode_llxlqz"},
- {"0011", "Visit_cmeq_asisdsame_only"},
- {"0110", "Decode_pxkqxn"},
- {"1010", "Decode_rhvksm"},
- {"1101", "Visit_sqrdmulh_asisdsame_only"},
- {"1110", "Decode_gkkpjz"},
+ { {"0001"_b, "sub_asisdsame_only"},
+ {"0010"_b, "_llxlqz"},
+ {"0011"_b, "cmeq_asisdsame_only"},
+ {"0110"_b, "_pxkqxn"},
+ {"1010"_b, "_rhvksm"},
+ {"1101"_b, "sqrdmulh_asisdsame_only"},
+ {"1110"_b, "_gkkpjz"},
},
},
- { "Decode_yppszx",
+ { "_yppszx",
{23, 22, 10},
- { {"100", "Visit_umlslb_z_zzzi_s"},
- {"101", "Visit_umlslt_z_zzzi_s"},
- {"110", "Visit_umlslb_z_zzzi_d"},
- {"111", "Visit_umlslt_z_zzzi_d"},
+ { {"100"_b, "umlslb_z_zzzi_s"},
+ {"101"_b, "umlslt_z_zzzi_s"},
+ {"110"_b, "umlslb_z_zzzi_d"},
+ {"111"_b, "umlslt_z_zzzi_d"},
},
},
- { "Decode_yppyky",
+ { "_yppyky",
{30, 13},
- { {"00", "Decode_gyrjrm"},
- {"01", "Decode_hhkqtn"},
- {"10", "Decode_jgmlpk"},
- {"11", "Decode_tzzssm"},
+ { {"00"_b, "_gyrjrm"},
+ {"01"_b, "_hhkqtn"},
+ {"10"_b, "_jgmlpk"},
+ {"11"_b, "_tzzssm"},
},
},
- { "Decode_ypqgyp",
+ { "_ypqgyp",
{22},
- { {"0", "Visit_ldrsw_64_ldst_regoff"},
+ { {"0"_b, "ldrsw_64_ldst_regoff"},
},
},
- { "Decode_ypznsm",
+ { "_ypznsm",
{23},
- { {"0", "Visit_fmaxnm_asimdsame_only"},
- {"1", "Visit_fminnm_asimdsame_only"},
+ { {"0"_b, "fmaxnm_asimdsame_only"},
+ {"1"_b, "fminnm_asimdsame_only"},
},
},
- { "Decode_yqmqzp",
+ { "_yqmqzp",
{18, 17, 12},
- { {"000", "Visit_st1_asisdlso_d1_1d"},
+ { {"000"_b, "st1_asisdlso_d1_1d"},
},
},
- { "Decode_yqmvxk",
+ { "_yqmvxk",
{11, 10, 9, 8, 7, 6},
- { {"000001", "Visit_tcommit_only_barriers"},
- {"xx1000", "Visit_dsb_bon_barriers"},
- {"xxxx10", "Visit_dmb_bo_barriers"},
- {"xxxx11", "Visit_sb_only_barriers"},
+ { {"000001"_b, "tcommit_only_barriers"},
+ {"xx1000"_b, "dsb_bon_barriers"},
+ {"xxxx10"_b, "dmb_bo_barriers"},
+ {"xxxx11"_b, "sb_only_barriers"},
},
},
- { "Decode_yqsgrt",
+ { "_yqsgrt",
{23, 22, 20, 19, 16, 13, 12},
- { {"0000000", "Decode_znmhps"},
- {"0000010", "Decode_zssjpv"},
- {"0000011", "Decode_smqvrs"},
- {"0100000", "Decode_jrgzxt"},
- {"0100010", "Decode_ppllxt"},
- {"0100011", "Decode_hqlskj"},
- {"100xx00", "Visit_st3_asisdlsep_r3_r"},
- {"100xx10", "Visit_st1_asisdlsep_r3_r3"},
- {"100xx11", "Visit_st1_asisdlsep_r1_r1"},
- {"1010x00", "Visit_st3_asisdlsep_r3_r"},
- {"1010x10", "Visit_st1_asisdlsep_r3_r3"},
- {"1010x11", "Visit_st1_asisdlsep_r1_r1"},
- {"1011000", "Visit_st3_asisdlsep_r3_r"},
- {"1011010", "Visit_st1_asisdlsep_r3_r3"},
- {"1011011", "Visit_st1_asisdlsep_r1_r1"},
- {"1011100", "Decode_ngxkmp"},
- {"1011110", "Decode_qgryzh"},
- {"1011111", "Decode_tjltls"},
- {"110xx00", "Visit_ld3_asisdlsep_r3_r"},
- {"110xx10", "Visit_ld1_asisdlsep_r3_r3"},
- {"110xx11", "Visit_ld1_asisdlsep_r1_r1"},
- {"1110x00", "Visit_ld3_asisdlsep_r3_r"},
- {"1110x10", "Visit_ld1_asisdlsep_r3_r3"},
- {"1110x11", "Visit_ld1_asisdlsep_r1_r1"},
- {"1111000", "Visit_ld3_asisdlsep_r3_r"},
- {"1111010", "Visit_ld1_asisdlsep_r3_r3"},
- {"1111011", "Visit_ld1_asisdlsep_r1_r1"},
- {"1111100", "Decode_zzgrjz"},
- {"1111110", "Decode_phtnny"},
- {"1111111", "Decode_txjyxr"},
+ { {"0000000"_b, "_znmhps"},
+ {"0000010"_b, "_zssjpv"},
+ {"0000011"_b, "_smqvrs"},
+ {"0100000"_b, "_jrgzxt"},
+ {"0100010"_b, "_ppllxt"},
+ {"0100011"_b, "_hqlskj"},
+ {"100xx00"_b, "st3_asisdlsep_r3_r"},
+ {"100xx10"_b, "st1_asisdlsep_r3_r3"},
+ {"100xx11"_b, "st1_asisdlsep_r1_r1"},
+ {"1010x00"_b, "st3_asisdlsep_r3_r"},
+ {"1010x10"_b, "st1_asisdlsep_r3_r3"},
+ {"1010x11"_b, "st1_asisdlsep_r1_r1"},
+ {"1011000"_b, "st3_asisdlsep_r3_r"},
+ {"1011010"_b, "st1_asisdlsep_r3_r3"},
+ {"1011011"_b, "st1_asisdlsep_r1_r1"},
+ {"1011100"_b, "_ngxkmp"},
+ {"1011110"_b, "_qgryzh"},
+ {"1011111"_b, "_tjltls"},
+ {"110xx00"_b, "ld3_asisdlsep_r3_r"},
+ {"110xx10"_b, "ld1_asisdlsep_r3_r3"},
+ {"110xx11"_b, "ld1_asisdlsep_r1_r1"},
+ {"1110x00"_b, "ld3_asisdlsep_r3_r"},
+ {"1110x10"_b, "ld1_asisdlsep_r3_r3"},
+ {"1110x11"_b, "ld1_asisdlsep_r1_r1"},
+ {"1111000"_b, "ld3_asisdlsep_r3_r"},
+ {"1111010"_b, "ld1_asisdlsep_r3_r3"},
+ {"1111011"_b, "ld1_asisdlsep_r1_r1"},
+ {"1111100"_b, "_zzgrjz"},
+ {"1111110"_b, "_phtnny"},
+ {"1111111"_b, "_txjyxr"},
},
},
- { "Decode_yqvqtx",
+ { "_yqvqtx",
{30, 23, 22, 20, 13},
- { {"00001", "Visit_ld1rob_z_p_bi_u8"},
- {"000x0", "Visit_ld1rob_z_p_br_contiguous"},
- {"01001", "Visit_ld1roh_z_p_bi_u16"},
- {"010x0", "Visit_ld1roh_z_p_br_contiguous"},
+ { {"00001"_b, "ld1rob_z_p_bi_u8"},
+ {"000x0"_b, "ld1rob_z_p_br_contiguous"},
+ {"01001"_b, "ld1roh_z_p_bi_u16"},
+ {"010x0"_b, "ld1roh_z_p_br_contiguous"},
},
},
- { "Decode_yqxnzl",
+ { "_yqxnzl",
{11, 10},
- { {"00", "Visit_sqdmulh_z_zz"},
- {"01", "Visit_sqrdmulh_z_zz"},
+ { {"00"_b, "sqdmulh_z_zz"},
+ {"01"_b, "sqrdmulh_z_zz"},
},
},
- { "Decode_yrgnqz",
+ { "_yrgnqz",
{13, 12},
- { {"00", "Visit_sshl_asisdsame_only"},
- {"01", "Visit_srshl_asisdsame_only"},
+ { {"00"_b, "sshl_asisdsame_only"},
+ {"01"_b, "srshl_asisdsame_only"},
},
},
- { "Decode_yrlzqp",
+ { "_yrlzqp",
{22, 13, 12},
- { {"000", "Visit_ldapr_64l_memop"},
+ { {"000"_b, "ldapr_64l_memop"},
},
},
- { "Decode_yrmmmg",
+ { "_yrmmmg",
{4},
- { {"0", "Visit_cmphs_p_p_zi"},
- {"1", "Visit_cmphi_p_p_zi"},
+ { {"0"_b, "cmphs_p_p_zi"},
+ {"1"_b, "cmphi_p_p_zi"},
},
},
- { "Decode_yrrppk",
+ { "_yrrppk",
{20, 19, 18, 17, 16},
- { {"00000", "Visit_fcvtns_32d_float2int"},
- {"00001", "Visit_fcvtnu_32d_float2int"},
- {"00010", "Visit_scvtf_d32_float2int"},
- {"00011", "Visit_ucvtf_d32_float2int"},
- {"00100", "Visit_fcvtas_32d_float2int"},
- {"00101", "Visit_fcvtau_32d_float2int"},
- {"01000", "Visit_fcvtps_32d_float2int"},
- {"01001", "Visit_fcvtpu_32d_float2int"},
- {"10000", "Visit_fcvtms_32d_float2int"},
- {"10001", "Visit_fcvtmu_32d_float2int"},
- {"11000", "Visit_fcvtzs_32d_float2int"},
- {"11001", "Visit_fcvtzu_32d_float2int"},
- {"11110", "Visit_fjcvtzs_32d_float2int"},
+ { {"00000"_b, "fcvtns_32d_float2int"},
+ {"00001"_b, "fcvtnu_32d_float2int"},
+ {"00010"_b, "scvtf_d32_float2int"},
+ {"00011"_b, "ucvtf_d32_float2int"},
+ {"00100"_b, "fcvtas_32d_float2int"},
+ {"00101"_b, "fcvtau_32d_float2int"},
+ {"01000"_b, "fcvtps_32d_float2int"},
+ {"01001"_b, "fcvtpu_32d_float2int"},
+ {"10000"_b, "fcvtms_32d_float2int"},
+ {"10001"_b, "fcvtmu_32d_float2int"},
+ {"11000"_b, "fcvtzs_32d_float2int"},
+ {"11001"_b, "fcvtzu_32d_float2int"},
+ {"11110"_b, "fjcvtzs_32d_float2int"},
},
},
- { "Decode_ysjqhn",
+ { "_ysjqhn",
{30, 23, 22},
- { {"00x", "Visit_adds_64_addsub_shift"},
- {"010", "Visit_adds_64_addsub_shift"},
- {"10x", "Visit_subs_64_addsub_shift"},
- {"110", "Visit_subs_64_addsub_shift"},
+ { {"00x"_b, "adds_64_addsub_shift"},
+ {"010"_b, "adds_64_addsub_shift"},
+ {"10x"_b, "subs_64_addsub_shift"},
+ {"110"_b, "subs_64_addsub_shift"},
},
},
- { "Decode_yskkjs",
+ { "_yskkjs",
{13, 12},
- { {"00", "Visit_sbcs_64_addsub_carry"},
+ { {"00"_b, "sbcs_64_addsub_carry"},
},
},
- { "Decode_yszjsm",
+ { "_yszjsm",
{12, 11, 10},
- { {"000", "Visit_sdot_z_zzz"},
- {"001", "Visit_udot_z_zzz"},
- {"010", "Visit_sqdmlalbt_z_zzz"},
- {"011", "Visit_sqdmlslbt_z_zzz"},
- {"1xx", "Visit_cdot_z_zzz"},
+ { {"000"_b, "sdot_z_zzz"},
+ {"001"_b, "udot_z_zzz"},
+ {"010"_b, "sqdmlalbt_z_zzz"},
+ {"011"_b, "sqdmlslbt_z_zzz"},
+ {"1xx"_b, "cdot_z_zzz"},
},
},
- { "Decode_ytkjxx",
+ { "_ytkjxx",
{30, 23, 22, 13, 4},
- { {"00x0x", "Visit_ld1w_z_p_bz_s_x32_scaled"},
- {"00x1x", "Visit_ldff1w_z_p_bz_s_x32_scaled"},
- {"0100x", "Visit_ldr_z_bi"},
- {"01100", "Visit_prfw_i_p_bi_s"},
- {"01110", "Visit_prfd_i_p_bi_s"},
- {"10x0x", "Visit_ld1w_z_p_bz_d_x32_scaled"},
- {"10x1x", "Visit_ldff1w_z_p_bz_d_x32_scaled"},
- {"11x0x", "Visit_ld1d_z_p_bz_d_x32_scaled"},
- {"11x1x", "Visit_ldff1d_z_p_bz_d_x32_scaled"},
+ { {"00x0x"_b, "ld1w_z_p_bz_s_x32_scaled"},
+ {"00x1x"_b, "ldff1w_z_p_bz_s_x32_scaled"},
+ {"0100x"_b, "ldr_z_bi"},
+ {"01100"_b, "prfw_i_p_bi_s"},
+ {"01110"_b, "prfd_i_p_bi_s"},
+ {"10x0x"_b, "ld1w_z_p_bz_d_x32_scaled"},
+ {"10x1x"_b, "ldff1w_z_p_bz_d_x32_scaled"},
+ {"11x0x"_b, "ld1d_z_p_bz_d_x32_scaled"},
+ {"11x1x"_b, "ldff1d_z_p_bz_d_x32_scaled"},
},
},
- { "Decode_ytsghm",
+ { "_ytsghm",
{30, 23, 22},
- { {"000", "Visit_msub_32a_dp_3src"},
+ { {"000"_b, "msub_32a_dp_3src"},
},
},
- { "Decode_ytvtqn",
+ { "_ytvtqn",
{30, 23, 22, 20, 13},
- { {"00001", "Visit_ld1sh_z_p_bi_s64"},
- {"00011", "Visit_ldnf1sh_z_p_bi_s64"},
- {"00101", "Visit_ld1w_z_p_bi_u32"},
- {"00111", "Visit_ldnf1w_z_p_bi_u32"},
- {"01001", "Visit_ld1sb_z_p_bi_s64"},
- {"01011", "Visit_ldnf1sb_z_p_bi_s64"},
- {"01101", "Visit_ld1sb_z_p_bi_s16"},
- {"01111", "Visit_ldnf1sb_z_p_bi_s16"},
- {"100x0", "Visit_st1w_z_p_bz_d_x32_unscaled"},
- {"100x1", "Visit_st1w_z_p_bz_d_64_unscaled"},
- {"101x0", "Visit_st1w_z_p_bz_s_x32_unscaled"},
- {"101x1", "Visit_st1w_z_p_ai_d"},
- {"110x0", "Visit_st1d_z_p_bz_d_x32_unscaled"},
- {"110x1", "Visit_st1d_z_p_bz_d_64_unscaled"},
- {"111x1", "Visit_st1d_z_p_ai_d"},
+ { {"00001"_b, "ld1sh_z_p_bi_s64"},
+ {"00011"_b, "ldnf1sh_z_p_bi_s64"},
+ {"00101"_b, "ld1w_z_p_bi_u32"},
+ {"00111"_b, "ldnf1w_z_p_bi_u32"},
+ {"01001"_b, "ld1sb_z_p_bi_s64"},
+ {"01011"_b, "ldnf1sb_z_p_bi_s64"},
+ {"01101"_b, "ld1sb_z_p_bi_s16"},
+ {"01111"_b, "ldnf1sb_z_p_bi_s16"},
+ {"100x0"_b, "st1w_z_p_bz_d_x32_unscaled"},
+ {"100x1"_b, "st1w_z_p_bz_d_64_unscaled"},
+ {"101x0"_b, "st1w_z_p_bz_s_x32_unscaled"},
+ {"101x1"_b, "st1w_z_p_ai_d"},
+ {"110x0"_b, "st1d_z_p_bz_d_x32_unscaled"},
+ {"110x1"_b, "st1d_z_p_bz_d_64_unscaled"},
+ {"111x1"_b, "st1d_z_p_ai_d"},
},
},
- { "Decode_ytvxsl",
+ { "_ytvxsl",
{30, 23, 22},
- { {"000", "Visit_stlxrb_sr32_ldstexcl"},
- {"001", "Visit_ldaxrb_lr32_ldstexcl"},
- {"010", "Visit_stlrb_sl32_ldstexcl"},
- {"011", "Visit_ldarb_lr32_ldstexcl"},
- {"100", "Visit_stlxrh_sr32_ldstexcl"},
- {"101", "Visit_ldaxrh_lr32_ldstexcl"},
- {"110", "Visit_stlrh_sl32_ldstexcl"},
- {"111", "Visit_ldarh_lr32_ldstexcl"},
+ { {"000"_b, "stlxrb_sr32_ldstexcl"},
+ {"001"_b, "ldaxrb_lr32_ldstexcl"},
+ {"010"_b, "stlrb_sl32_ldstexcl"},
+ {"011"_b, "ldarb_lr32_ldstexcl"},
+ {"100"_b, "stlxrh_sr32_ldstexcl"},
+ {"101"_b, "ldaxrh_lr32_ldstexcl"},
+ {"110"_b, "stlrh_sl32_ldstexcl"},
+ {"111"_b, "ldarh_lr32_ldstexcl"},
},
},
- { "Decode_yvgqjx",
+ { "_yvgqjx",
{13, 12, 5},
- { {"010", "Decode_tnzytv"},
- {"011", "Decode_vmpnlv"},
- {"100", "Decode_hhhqjk"},
- {"101", "Decode_tkzqqp"},
- {"110", "Decode_sphpkr"},
- {"111", "Decode_spglxn"},
+ { {"010"_b, "_tnzytv"},
+ {"011"_b, "_vmpnlv"},
+ {"100"_b, "_hhhqjk"},
+ {"101"_b, "_tkzqqp"},
+ {"110"_b, "_sphpkr"},
+ {"111"_b, "_spglxn"},
},
},
- { "Decode_yvhnlk",
+ { "_yvhnlk",
{30, 23, 22, 13, 12, 11, 10},
- { {"0001111", "Visit_casp_cp32_ldstexcl"},
- {"0011111", "Visit_caspa_cp32_ldstexcl"},
- {"0101111", "Visit_casb_c32_ldstexcl"},
- {"0111111", "Visit_casab_c32_ldstexcl"},
- {"1001111", "Visit_casp_cp64_ldstexcl"},
- {"1011111", "Visit_caspa_cp64_ldstexcl"},
- {"1101111", "Visit_cash_c32_ldstexcl"},
- {"1111111", "Visit_casah_c32_ldstexcl"},
+ { {"0001111"_b, "casp_cp32_ldstexcl"},
+ {"0011111"_b, "caspa_cp32_ldstexcl"},
+ {"0101111"_b, "casb_c32_ldstexcl"},
+ {"0111111"_b, "casab_c32_ldstexcl"},
+ {"1001111"_b, "casp_cp64_ldstexcl"},
+ {"1011111"_b, "caspa_cp64_ldstexcl"},
+ {"1101111"_b, "cash_c32_ldstexcl"},
+ {"1111111"_b, "casah_c32_ldstexcl"},
},
},
- { "Decode_yvlhjg",
+ { "_yvlhjg",
{23},
- { {"0", "Visit_frecps_asimdsame_only"},
- {"1", "Visit_frsqrts_asimdsame_only"},
+ { {"0"_b, "frecps_asimdsame_only"},
+ {"1"_b, "frsqrts_asimdsame_only"},
},
},
- { "Decode_yvnjkr",
+ { "_yvnjkr",
{9, 8, 7, 6, 5},
- { {"11111", "Visit_autdzb_64z_dp_1src"},
+ { {"11111"_b, "autdzb_64z_dp_1src"},
},
},
- { "Decode_yvptvx",
+ { "_yvptvx",
{23, 12, 11, 10},
- { {"0000", "Visit_sqshrnb_z_zi"},
- {"0001", "Visit_sqshrnt_z_zi"},
- {"0010", "Visit_sqrshrnb_z_zi"},
- {"0011", "Visit_sqrshrnt_z_zi"},
- {"0100", "Visit_uqshrnb_z_zi"},
- {"0101", "Visit_uqshrnt_z_zi"},
- {"0110", "Visit_uqrshrnb_z_zi"},
- {"0111", "Visit_uqrshrnt_z_zi"},
+ { {"0000"_b, "sqshrnb_z_zi"},
+ {"0001"_b, "sqshrnt_z_zi"},
+ {"0010"_b, "sqrshrnb_z_zi"},
+ {"0011"_b, "sqrshrnt_z_zi"},
+ {"0100"_b, "uqshrnb_z_zi"},
+ {"0101"_b, "uqshrnt_z_zi"},
+ {"0110"_b, "uqrshrnb_z_zi"},
+ {"0111"_b, "uqrshrnt_z_zi"},
},
},
- { "Decode_yvxgrr",
+ { "_yvxgrr",
{23, 22, 20, 19, 18, 17, 16},
- { {"0111001", "Visit_frintm_asimdmiscfp16_r"},
- {"0x00001", "Visit_frintm_asimdmisc_r"},
- {"1111001", "Visit_frintz_asimdmiscfp16_r"},
- {"1x00001", "Visit_frintz_asimdmisc_r"},
- {"xx00000", "Visit_cmeq_asimdmisc_z"},
+ { {"0111001"_b, "frintm_asimdmiscfp16_r"},
+ {"0x00001"_b, "frintm_asimdmisc_r"},
+ {"1111001"_b, "frintz_asimdmiscfp16_r"},
+ {"1x00001"_b, "frintz_asimdmisc_r"},
+ {"xx00000"_b, "cmeq_asimdmisc_z"},
},
},
- { "Decode_yvygml",
+ { "_yvygml",
{30},
- { {"0", "Decode_jkrlsg"},
- {"1", "Decode_vvrmvg"},
+ { {"0"_b, "_jkrlsg"},
+ {"1"_b, "_vvrmvg"},
},
},
- { "Decode_yvyhlh",
+ { "_yvyhlh",
{23, 22, 12, 11, 10},
- { {"0x000", "Visit_fmul_z_zzi_h"},
- {"10000", "Visit_fmul_z_zzi_s"},
- {"11000", "Visit_fmul_z_zzi_d"},
+ { {"0x000"_b, "fmul_z_zzi_h"},
+ {"10000"_b, "fmul_z_zzi_s"},
+ {"11000"_b, "fmul_z_zzi_d"},
},
},
- { "Decode_yvyxkx",
+ { "_yvyxkx",
{10},
- { {"0", "Visit_sha512su0_vv2_cryptosha512_2"},
- {"1", "Visit_sm4e_vv4_cryptosha512_2"},
+ { {"0"_b, "sha512su0_vv2_cryptosha512_2"},
+ {"1"_b, "sm4e_vv4_cryptosha512_2"},
},
},
- { "Decode_yxhrpk",
+ { "_yxhrpk",
{23, 22},
- { {"00", "Visit_fmlal2_asimdsame_f"},
- {"10", "Visit_fmlsl2_asimdsame_f"},
+ { {"00"_b, "fmlal2_asimdsame_f"},
+ {"10"_b, "fmlsl2_asimdsame_f"},
},
},
- { "Decode_yxmkzr",
+ { "_yxmkzr",
{12},
- { {"0", "Visit_st1_asisdlsop_dx1_r1d"},
+ { {"0"_b, "st1_asisdlsop_dx1_r1d"},
},
},
- { "Decode_yxnslx",
+ { "_yxnslx",
{23, 22},
- { {"00", "Visit_adr_z_az_d_s32_scaled"},
- {"01", "Visit_adr_z_az_d_u32_scaled"},
- {"1x", "Visit_adr_z_az_sd_same_scaled"},
+ { {"00"_b, "adr_z_az_d_s32_scaled"},
+ {"01"_b, "adr_z_az_d_u32_scaled"},
+ {"1x"_b, "adr_z_az_sd_same_scaled"},
},
},
- { "Decode_yykhjv",
+ { "_yykhjv",
{23, 22, 13, 12, 11, 10},
- { {"000110", "Visit_smmla_z_zzz"},
- {"0x1000", "Visit_sshllb_z_zi"},
- {"0x1001", "Visit_sshllt_z_zi"},
- {"0x1010", "Visit_ushllb_z_zi"},
- {"0x1011", "Visit_ushllt_z_zi"},
- {"100110", "Visit_usmmla_z_zzz"},
- {"110110", "Visit_ummla_z_zzz"},
- {"xx0000", "Visit_saddlbt_z_zz"},
- {"xx0010", "Visit_ssublbt_z_zz"},
- {"xx0011", "Visit_ssubltb_z_zz"},
- {"xx0100", "Visit_eorbt_z_zz"},
- {"xx0101", "Visit_eortb_z_zz"},
- {"xx1100", "Visit_bext_z_zz"},
- {"xx1101", "Visit_bdep_z_zz"},
- {"xx1110", "Visit_bgrp_z_zz"},
+ { {"000110"_b, "smmla_z_zzz"},
+ {"0x1000"_b, "sshllb_z_zi"},
+ {"0x1001"_b, "sshllt_z_zi"},
+ {"0x1010"_b, "ushllb_z_zi"},
+ {"0x1011"_b, "ushllt_z_zi"},
+ {"100110"_b, "usmmla_z_zzz"},
+ {"110110"_b, "ummla_z_zzz"},
+ {"xx0000"_b, "saddlbt_z_zz"},
+ {"xx0010"_b, "ssublbt_z_zz"},
+ {"xx0011"_b, "ssubltb_z_zz"},
+ {"xx0100"_b, "eorbt_z_zz"},
+ {"xx0101"_b, "eortb_z_zz"},
+ {"xx1100"_b, "bext_z_zz"},
+ {"xx1101"_b, "bdep_z_zz"},
+ {"xx1110"_b, "bgrp_z_zz"},
},
},
- { "Decode_yynmjl",
+ { "_yynmjl",
{4},
- { {"0", "Visit_orrs_p_p_pp_z"},
- {"1", "Visit_orns_p_p_pp_z"},
+ { {"0"_b, "orrs_p_p_pp_z"},
+ {"1"_b, "orns_p_p_pp_z"},
},
},
- { "Decode_yyrkmn",
+ { "_yyrkmn",
{17, 16, 9, 8, 7, 6, 5},
- { {"0000000", "Visit_aesmc_z_z"},
- {"10xxxxx", "Visit_aese_z_zz"},
- {"11xxxxx", "Visit_sm4e_z_zz"},
+ { {"0000000"_b, "aesmc_z_z"},
+ {"10xxxxx"_b, "aese_z_zz"},
+ {"11xxxxx"_b, "sm4e_z_zz"},
},
},
- { "Decode_yytvxh",
+ { "_yytvxh",
{30, 23, 22, 13, 4},
- { {"00000", "Visit_prfw_i_p_br_s"},
- {"00010", "Visit_prfw_i_p_ai_s"},
- {"0010x", "Visit_ld1rw_z_p_bi_u32"},
- {"0011x", "Visit_ld1rw_z_p_bi_u64"},
- {"01000", "Visit_prfd_i_p_br_s"},
- {"01010", "Visit_prfd_i_p_ai_s"},
- {"0110x", "Visit_ld1rsb_z_p_bi_s16"},
- {"0111x", "Visit_ld1rd_z_p_bi_u64"},
- {"1000x", "Visit_ldnt1w_z_p_ar_d_64_unscaled"},
- {"10010", "Visit_prfw_i_p_ai_d"},
- {"1010x", "Visit_ld1w_z_p_bz_d_64_unscaled"},
- {"1011x", "Visit_ldff1w_z_p_bz_d_64_unscaled"},
- {"1100x", "Visit_ldnt1d_z_p_ar_d_64_unscaled"},
- {"11010", "Visit_prfd_i_p_ai_d"},
- {"1110x", "Visit_ld1d_z_p_bz_d_64_unscaled"},
- {"1111x", "Visit_ldff1d_z_p_bz_d_64_unscaled"},
+ { {"00000"_b, "prfw_i_p_br_s"},
+ {"00010"_b, "prfw_i_p_ai_s"},
+ {"0010x"_b, "ld1rw_z_p_bi_u32"},
+ {"0011x"_b, "ld1rw_z_p_bi_u64"},
+ {"01000"_b, "prfd_i_p_br_s"},
+ {"01010"_b, "prfd_i_p_ai_s"},
+ {"0110x"_b, "ld1rsb_z_p_bi_s16"},
+ {"0111x"_b, "ld1rd_z_p_bi_u64"},
+ {"1000x"_b, "ldnt1w_z_p_ar_d_64_unscaled"},
+ {"10010"_b, "prfw_i_p_ai_d"},
+ {"1010x"_b, "ld1w_z_p_bz_d_64_unscaled"},
+ {"1011x"_b, "ldff1w_z_p_bz_d_64_unscaled"},
+ {"1100x"_b, "ldnt1d_z_p_ar_d_64_unscaled"},
+ {"11010"_b, "prfd_i_p_ai_d"},
+ {"1110x"_b, "ld1d_z_p_bz_d_64_unscaled"},
+ {"1111x"_b, "ldff1d_z_p_bz_d_64_unscaled"},
},
},
- { "Decode_yyyshx",
+ { "_yyyshx",
{30, 13, 4},
- { {"000", "Visit_cmphs_p_p_zz"},
- {"001", "Visit_cmphi_p_p_zz"},
- {"010", "Visit_cmpeq_p_p_zw"},
- {"011", "Visit_cmpne_p_p_zw"},
- {"1xx", "Visit_fcmla_z_p_zzz"},
+ { {"000"_b, "cmphs_p_p_zz"},
+ {"001"_b, "cmphi_p_p_zz"},
+ {"010"_b, "cmpeq_p_p_zw"},
+ {"011"_b, "cmpne_p_p_zw"},
+ {"1xx"_b, "fcmla_z_p_zzz"},
},
},
- { "Decode_yzmjhn",
+ { "_yzmjhn",
{4},
- { {"0", "Visit_eors_p_p_pp_z"},
+ { {"0"_b, "eors_p_p_pp_z"},
},
},
- { "Decode_yzqtyl",
+ { "_yzqtyl",
{20, 19, 18, 17, 16},
- { {"00001", "Visit_sqxtun_asisdmisc_n"},
+ { {"00001"_b, "sqxtun_asisdmisc_n"},
},
},
- { "Decode_yzzlxs",
+ { "_yzzlxs",
{23, 4},
- { {"00", "Decode_mpgrgp"},
+ { {"00"_b, "_mpgrgp"},
},
},
- { "Decode_zgjpym",
+ { "_zgjpym",
{23, 22, 20, 19, 11},
- { {"00010", "Visit_srsra_asisdshf_r"},
- {"001x0", "Visit_srsra_asisdshf_r"},
- {"01xx0", "Visit_srsra_asisdshf_r"},
+ { {"00010"_b, "srsra_asisdshf_r"},
+ {"001x0"_b, "srsra_asisdshf_r"},
+ {"01xx0"_b, "srsra_asisdshf_r"},
},
},
- { "Decode_zglksl",
+ { "_zglksl",
{30, 23, 22, 13, 12, 11, 10},
- { {"1101001", "Visit_ummla_asimdsame2_g"},
- {"xxx0001", "Visit_sqrdmlah_asimdsame2_only"},
- {"xxx0011", "Visit_sqrdmlsh_asimdsame2_only"},
- {"xxx0101", "Visit_udot_asimdsame2_d"},
+ { {"1101001"_b, "ummla_asimdsame2_g"},
+ {"xxx0001"_b, "sqrdmlah_asimdsame2_only"},
+ {"xxx0011"_b, "sqrdmlsh_asimdsame2_only"},
+ {"xxx0101"_b, "udot_asimdsame2_d"},
},
},
- { "Decode_zgysvr",
+ { "_zgysvr",
{30, 13},
- { {"00", "Decode_xpqglq"},
- {"10", "Decode_xstkrn"},
- {"11", "Decode_zjzmvh"},
+ { {"00"_b, "_xpqglq"},
+ {"10"_b, "_xstkrn"},
+ {"11"_b, "_zjzmvh"},
},
},
- { "Decode_zgzlhq",
+ { "_zgzlhq",
{17},
- { {"0", "Visit_ld1_asisdlso_b1_1b"},
+ { {"0"_b, "ld1_asisdlso_b1_1b"},
},
},
- { "Decode_zhkjzg",
+ { "_zhkjzg",
{23, 22, 13},
- { {"000", "Visit_fmls_asimdelem_rh_h"},
- {"1x0", "Visit_fmls_asimdelem_r_sd"},
- {"xx1", "Visit_sqdmlsl_asimdelem_l"},
+ { {"000"_b, "fmls_asimdelem_rh_h"},
+ {"1x0"_b, "fmls_asimdelem_r_sd"},
+ {"xx1"_b, "sqdmlsl_asimdelem_l"},
},
},
- { "Decode_zhpxqz",
+ { "_zhpxqz",
{9, 8, 7, 6, 5},
- { {"00000", "Visit_fmov_h_floatimm"},
+ { {"00000"_b, "fmov_h_floatimm"},
},
},
- { "Decode_zhrtts",
+ { "_zhrtts",
{23, 22},
- { {"00", "Decode_qlqhzg"},
+ { {"00"_b, "_qlqhzg"},
},
},
- { "Decode_zjgvyp",
+ { "_zjgvyp",
{30, 13, 12, 11, 10},
- { {"00000", "Decode_ghnljt"},
+ { {"00000"_b, "_ghnljt"},
},
},
- { "Decode_zjjxjl",
+ { "_zjjxjl",
{9},
- { {"0", "Visit_pnext_p_p_p"},
+ { {"0"_b, "pnext_p_p_p"},
},
},
- { "Decode_zjsgkm",
+ { "_zjsgkm",
{4},
- { {"0", "Visit_ccmn_64_condcmp_reg"},
+ { {"0"_b, "ccmn_64_condcmp_reg"},
},
},
- { "Decode_zjslnr",
+ { "_zjslnr",
{30, 23, 22},
- { {"000", "Visit_sbfm_32m_bitfield"},
- {"010", "Visit_extr_32_extract"},
- {"100", "Visit_ubfm_32m_bitfield"},
+ { {"000"_b, "sbfm_32m_bitfield"},
+ {"010"_b, "extr_32_extract"},
+ {"100"_b, "ubfm_32m_bitfield"},
},
},
- { "Decode_zjzmvh",
+ { "_zjzmvh",
{23, 22, 20, 19, 18, 17, 16},
- { {"0001010", "Visit_fcvtx_z_p_z_d2s"},
- {"0011xx0", "Visit_flogb_z_p_z"},
- {"0110010", "Visit_scvtf_z_p_z_h2fp16"},
- {"0110011", "Visit_ucvtf_z_p_z_h2fp16"},
- {"0110100", "Visit_scvtf_z_p_z_w2fp16"},
- {"0110101", "Visit_ucvtf_z_p_z_w2fp16"},
- {"0110110", "Visit_scvtf_z_p_z_x2fp16"},
- {"0110111", "Visit_ucvtf_z_p_z_x2fp16"},
- {"0111010", "Visit_fcvtzs_z_p_z_fp162h"},
- {"0111011", "Visit_fcvtzu_z_p_z_fp162h"},
- {"0111100", "Visit_fcvtzs_z_p_z_fp162w"},
- {"0111101", "Visit_fcvtzu_z_p_z_fp162w"},
- {"0111110", "Visit_fcvtzs_z_p_z_fp162x"},
- {"0111111", "Visit_fcvtzu_z_p_z_fp162x"},
- {"1001000", "Visit_fcvt_z_p_z_s2h"},
- {"1001001", "Visit_fcvt_z_p_z_h2s"},
- {"1001010", "Visit_bfcvt_z_p_z_s2bf"},
- {"1010100", "Visit_scvtf_z_p_z_w2s"},
- {"1010101", "Visit_ucvtf_z_p_z_w2s"},
- {"1011100", "Visit_fcvtzs_z_p_z_s2w"},
- {"1011101", "Visit_fcvtzu_z_p_z_s2w"},
- {"1101000", "Visit_fcvt_z_p_z_d2h"},
- {"1101001", "Visit_fcvt_z_p_z_h2d"},
- {"1101010", "Visit_fcvt_z_p_z_d2s"},
- {"1101011", "Visit_fcvt_z_p_z_s2d"},
- {"1110000", "Visit_scvtf_z_p_z_w2d"},
- {"1110001", "Visit_ucvtf_z_p_z_w2d"},
- {"1110100", "Visit_scvtf_z_p_z_x2s"},
- {"1110101", "Visit_ucvtf_z_p_z_x2s"},
- {"1110110", "Visit_scvtf_z_p_z_x2d"},
- {"1110111", "Visit_ucvtf_z_p_z_x2d"},
- {"1111000", "Visit_fcvtzs_z_p_z_d2w"},
- {"1111001", "Visit_fcvtzu_z_p_z_d2w"},
- {"1111100", "Visit_fcvtzs_z_p_z_s2x"},
- {"1111101", "Visit_fcvtzu_z_p_z_s2x"},
- {"1111110", "Visit_fcvtzs_z_p_z_d2x"},
- {"1111111", "Visit_fcvtzu_z_p_z_d2x"},
- {"xx00000", "Visit_frintn_z_p_z"},
- {"xx00001", "Visit_frintp_z_p_z"},
- {"xx00010", "Visit_frintm_z_p_z"},
- {"xx00011", "Visit_frintz_z_p_z"},
- {"xx00100", "Visit_frinta_z_p_z"},
- {"xx00110", "Visit_frintx_z_p_z"},
- {"xx00111", "Visit_frinti_z_p_z"},
- {"xx01100", "Visit_frecpx_z_p_z"},
- {"xx01101", "Visit_fsqrt_z_p_z"},
+ { {"0001010"_b, "fcvtx_z_p_z_d2s"},
+ {"0011xx0"_b, "flogb_z_p_z"},
+ {"0110010"_b, "scvtf_z_p_z_h2fp16"},
+ {"0110011"_b, "ucvtf_z_p_z_h2fp16"},
+ {"0110100"_b, "scvtf_z_p_z_w2fp16"},
+ {"0110101"_b, "ucvtf_z_p_z_w2fp16"},
+ {"0110110"_b, "scvtf_z_p_z_x2fp16"},
+ {"0110111"_b, "ucvtf_z_p_z_x2fp16"},
+ {"0111010"_b, "fcvtzs_z_p_z_fp162h"},
+ {"0111011"_b, "fcvtzu_z_p_z_fp162h"},
+ {"0111100"_b, "fcvtzs_z_p_z_fp162w"},
+ {"0111101"_b, "fcvtzu_z_p_z_fp162w"},
+ {"0111110"_b, "fcvtzs_z_p_z_fp162x"},
+ {"0111111"_b, "fcvtzu_z_p_z_fp162x"},
+ {"1001000"_b, "fcvt_z_p_z_s2h"},
+ {"1001001"_b, "fcvt_z_p_z_h2s"},
+ {"1001010"_b, "bfcvt_z_p_z_s2bf"},
+ {"1010100"_b, "scvtf_z_p_z_w2s"},
+ {"1010101"_b, "ucvtf_z_p_z_w2s"},
+ {"1011100"_b, "fcvtzs_z_p_z_s2w"},
+ {"1011101"_b, "fcvtzu_z_p_z_s2w"},
+ {"1101000"_b, "fcvt_z_p_z_d2h"},
+ {"1101001"_b, "fcvt_z_p_z_h2d"},
+ {"1101010"_b, "fcvt_z_p_z_d2s"},
+ {"1101011"_b, "fcvt_z_p_z_s2d"},
+ {"1110000"_b, "scvtf_z_p_z_w2d"},
+ {"1110001"_b, "ucvtf_z_p_z_w2d"},
+ {"1110100"_b, "scvtf_z_p_z_x2s"},
+ {"1110101"_b, "ucvtf_z_p_z_x2s"},
+ {"1110110"_b, "scvtf_z_p_z_x2d"},
+ {"1110111"_b, "ucvtf_z_p_z_x2d"},
+ {"1111000"_b, "fcvtzs_z_p_z_d2w"},
+ {"1111001"_b, "fcvtzu_z_p_z_d2w"},
+ {"1111100"_b, "fcvtzs_z_p_z_s2x"},
+ {"1111101"_b, "fcvtzu_z_p_z_s2x"},
+ {"1111110"_b, "fcvtzs_z_p_z_d2x"},
+ {"1111111"_b, "fcvtzu_z_p_z_d2x"},
+ {"xx00000"_b, "frintn_z_p_z"},
+ {"xx00001"_b, "frintp_z_p_z"},
+ {"xx00010"_b, "frintm_z_p_z"},
+ {"xx00011"_b, "frintz_z_p_z"},
+ {"xx00100"_b, "frinta_z_p_z"},
+ {"xx00110"_b, "frintx_z_p_z"},
+ {"xx00111"_b, "frinti_z_p_z"},
+ {"xx01100"_b, "frecpx_z_p_z"},
+ {"xx01101"_b, "fsqrt_z_p_z"},
},
},
- { "Decode_zkhjsp",
+ { "_zkhjsp",
{11},
- { {"0", "Visit_sqdmulh_z_zzi_h"},
- {"1", "Visit_mul_z_zzi_h"},
+ { {"0"_b, "sqdmulh_z_zzi_h"},
+ {"1"_b, "mul_z_zzi_h"},
},
},
- { "Decode_zkqtrj",
+ { "_zkqtrj",
{30},
- { {"0", "Visit_b_only_branch_imm"},
+ { {"0"_b, "b_only_branch_imm"},
},
},
- { "Decode_zkttzl",
+ { "_zkttzl",
{23, 22, 20, 19, 18, 16, 13},
- { {"0000000", "Decode_tsvsgh"},
- {"0000001", "Decode_rkrltp"},
- {"0100000", "Decode_zgzlhq"},
- {"0100001", "Decode_nrssjz"},
- {"100xxx0", "Visit_st1_asisdlsop_bx1_r1b"},
- {"100xxx1", "Visit_st3_asisdlsop_bx3_r3b"},
- {"1010xx0", "Visit_st1_asisdlsop_bx1_r1b"},
- {"1010xx1", "Visit_st3_asisdlsop_bx3_r3b"},
- {"10110x0", "Visit_st1_asisdlsop_bx1_r1b"},
- {"10110x1", "Visit_st3_asisdlsop_bx3_r3b"},
- {"1011100", "Visit_st1_asisdlsop_bx1_r1b"},
- {"1011101", "Visit_st3_asisdlsop_bx3_r3b"},
- {"1011110", "Decode_rnypvh"},
- {"1011111", "Decode_nxjgmm"},
- {"110xxx0", "Visit_ld1_asisdlsop_bx1_r1b"},
- {"110xxx1", "Visit_ld3_asisdlsop_bx3_r3b"},
- {"1110xx0", "Visit_ld1_asisdlsop_bx1_r1b"},
- {"1110xx1", "Visit_ld3_asisdlsop_bx3_r3b"},
- {"11110x0", "Visit_ld1_asisdlsop_bx1_r1b"},
- {"11110x1", "Visit_ld3_asisdlsop_bx3_r3b"},
- {"1111100", "Visit_ld1_asisdlsop_bx1_r1b"},
- {"1111101", "Visit_ld3_asisdlsop_bx3_r3b"},
- {"1111110", "Decode_qqtpln"},
- {"1111111", "Decode_glhxyj"},
+ { {"0000000"_b, "_tsvsgh"},
+ {"0000001"_b, "_rkrltp"},
+ {"0100000"_b, "_zgzlhq"},
+ {"0100001"_b, "_nrssjz"},
+ {"100xxx0"_b, "st1_asisdlsop_bx1_r1b"},
+ {"100xxx1"_b, "st3_asisdlsop_bx3_r3b"},
+ {"1010xx0"_b, "st1_asisdlsop_bx1_r1b"},
+ {"1010xx1"_b, "st3_asisdlsop_bx3_r3b"},
+ {"10110x0"_b, "st1_asisdlsop_bx1_r1b"},
+ {"10110x1"_b, "st3_asisdlsop_bx3_r3b"},
+ {"1011100"_b, "st1_asisdlsop_bx1_r1b"},
+ {"1011101"_b, "st3_asisdlsop_bx3_r3b"},
+ {"1011110"_b, "_rnypvh"},
+ {"1011111"_b, "_nxjgmm"},
+ {"110xxx0"_b, "ld1_asisdlsop_bx1_r1b"},
+ {"110xxx1"_b, "ld3_asisdlsop_bx3_r3b"},
+ {"1110xx0"_b, "ld1_asisdlsop_bx1_r1b"},
+ {"1110xx1"_b, "ld3_asisdlsop_bx3_r3b"},
+ {"11110x0"_b, "ld1_asisdlsop_bx1_r1b"},
+ {"11110x1"_b, "ld3_asisdlsop_bx3_r3b"},
+ {"1111100"_b, "ld1_asisdlsop_bx1_r1b"},
+ {"1111101"_b, "ld3_asisdlsop_bx3_r3b"},
+ {"1111110"_b, "_qqtpln"},
+ {"1111111"_b, "_glhxyj"},
},
},
- { "Decode_zlmgyp",
+ { "_zlmgyp",
{23, 22, 13},
- { {"000", "Visit_fmla_asimdelem_rh_h"},
- {"1x0", "Visit_fmla_asimdelem_r_sd"},
- {"xx1", "Visit_sqdmlal_asimdelem_l"},
+ { {"000"_b, "fmla_asimdelem_rh_h"},
+ {"1x0"_b, "fmla_asimdelem_r_sd"},
+ {"xx1"_b, "sqdmlal_asimdelem_l"},
},
},
- { "Decode_zmkqxl",
+ { "_zmkqxl",
{23, 10},
- { {"00", "Visit_adclb_z_zzz"},
- {"01", "Visit_adclt_z_zzz"},
- {"10", "Visit_sbclb_z_zzz"},
- {"11", "Visit_sbclt_z_zzz"},
+ { {"00"_b, "adclb_z_zzz"},
+ {"01"_b, "adclt_z_zzz"},
+ {"10"_b, "sbclb_z_zzz"},
+ {"11"_b, "sbclt_z_zzz"},
},
},
- { "Decode_zmpzkg",
+ { "_zmpzkg",
{23, 22, 20, 19, 13, 11},
- { {"0000x0", "Visit_orr_asimdimm_l_sl"},
- {"00x100", "Visit_shl_asimdshf_r"},
- {"00x110", "Visit_sqshl_asimdshf_r"},
- {"010x00", "Visit_shl_asimdshf_r"},
- {"010x10", "Visit_sqshl_asimdshf_r"},
- {"011100", "Visit_shl_asimdshf_r"},
- {"011110", "Visit_sqshl_asimdshf_r"},
- {"0x1000", "Visit_shl_asimdshf_r"},
- {"0x1010", "Visit_sqshl_asimdshf_r"},
+ { {"0000x0"_b, "orr_asimdimm_l_sl"},
+ {"00x100"_b, "shl_asimdshf_r"},
+ {"00x110"_b, "sqshl_asimdshf_r"},
+ {"010x00"_b, "shl_asimdshf_r"},
+ {"010x10"_b, "sqshl_asimdshf_r"},
+ {"011100"_b, "shl_asimdshf_r"},
+ {"011110"_b, "sqshl_asimdshf_r"},
+ {"0x1000"_b, "shl_asimdshf_r"},
+ {"0x1010"_b, "sqshl_asimdshf_r"},
},
},
- { "Decode_zmtkvx",
+ { "_zmtkvx",
{13, 10},
- { {"00", "Decode_rhpmjz"},
+ { {"00"_b, "_rhpmjz"},
},
},
- { "Decode_zmzxjm",
+ { "_zmzxjm",
{17},
- { {"0", "Visit_faddv_v_p_z"},
+ { {"0"_b, "faddv_v_p_z"},
},
},
- { "Decode_znmhps",
+ { "_znmhps",
{18, 17},
- { {"00", "Visit_st3_asisdlse_r3"},
+ { {"00"_b, "st3_asisdlse_r3"},
},
},
- { "Decode_zpmkvt",
+ { "_zpmkvt",
{12},
- { {"1", "Decode_vqqrjl"},
+ { {"1"_b, "_vqqrjl"},
},
},
- { "Decode_zpnsrv",
+ { "_zpnsrv",
{23, 22, 13},
- { {"000", "Visit_fmul_asimdelem_rh_h"},
- {"1x0", "Visit_fmul_asimdelem_r_sd"},
- {"xx1", "Visit_sqdmull_asimdelem_l"},
+ { {"000"_b, "fmul_asimdelem_rh_h"},
+ {"1x0"_b, "fmul_asimdelem_r_sd"},
+ {"xx1"_b, "sqdmull_asimdelem_l"},
},
},
- { "Decode_zppjvk",
+ { "_zppjvk",
{12},
- { {"0", "Visit_ld2_asisdlsop_dx2_r2d"},
+ { {"0"_b, "ld2_asisdlsop_dx2_r2d"},
},
},
- { "Decode_zpsymj",
+ { "_zpsymj",
{22, 13, 12},
- { {"000", "Visit_swp_64_memop"},
- {"001", "Decode_yjztsq"},
- {"010", "Visit_st64bv0_64_memop"},
- {"011", "Visit_st64bv_64_memop"},
- {"100", "Visit_swpl_64_memop"},
+ { {"000"_b, "swp_64_memop"},
+ {"001"_b, "_yjztsq"},
+ {"010"_b, "st64bv0_64_memop"},
+ {"011"_b, "st64bv_64_memop"},
+ {"100"_b, "swpl_64_memop"},
},
},
- { "Decode_zpzghs",
+ { "_zpzghs",
{30, 23, 22},
- { {"000", "Visit_stnp_q_ldstnapair_offs"},
- {"001", "Visit_ldnp_q_ldstnapair_offs"},
- {"010", "Visit_stp_q_ldstpair_post"},
- {"011", "Visit_ldp_q_ldstpair_post"},
+ { {"000"_b, "stnp_q_ldstnapair_offs"},
+ {"001"_b, "ldnp_q_ldstnapair_offs"},
+ {"010"_b, "stp_q_ldstpair_post"},
+ {"011"_b, "ldp_q_ldstpair_post"},
},
},
- { "Decode_zqltpy",
+ { "_zqltpy",
{9, 8, 7, 6, 5},
- { {"00000", "Visit_fmov_s_floatimm"},
+ { {"00000"_b, "fmov_s_floatimm"},
},
},
- { "Decode_zqmmsk",
+ { "_zqmmsk",
{30, 23, 22, 13, 12, 11, 10},
- { {"0000000", "Visit_ldaddb_32_memop"},
- {"0000100", "Visit_ldclrb_32_memop"},
- {"0001000", "Visit_ldeorb_32_memop"},
- {"0001100", "Visit_ldsetb_32_memop"},
- {"000xx10", "Visit_strb_32b_ldst_regoff"},
- {"0010000", "Visit_ldaddlb_32_memop"},
- {"0010100", "Visit_ldclrlb_32_memop"},
- {"0011000", "Visit_ldeorlb_32_memop"},
- {"0011100", "Visit_ldsetlb_32_memop"},
- {"001xx10", "Visit_ldrb_32b_ldst_regoff"},
- {"0100000", "Visit_ldaddab_32_memop"},
- {"0100100", "Visit_ldclrab_32_memop"},
- {"0101000", "Visit_ldeorab_32_memop"},
- {"0101100", "Visit_ldsetab_32_memop"},
- {"010xx10", "Visit_ldrsb_64b_ldst_regoff"},
- {"0110000", "Visit_ldaddalb_32_memop"},
- {"0110100", "Visit_ldclralb_32_memop"},
- {"0111000", "Visit_ldeoralb_32_memop"},
- {"0111100", "Visit_ldsetalb_32_memop"},
- {"011xx10", "Visit_ldrsb_32b_ldst_regoff"},
- {"1000000", "Visit_ldaddh_32_memop"},
- {"1000100", "Visit_ldclrh_32_memop"},
- {"1001000", "Visit_ldeorh_32_memop"},
- {"1001100", "Visit_ldseth_32_memop"},
- {"100xx10", "Visit_strh_32_ldst_regoff"},
- {"1010000", "Visit_ldaddlh_32_memop"},
- {"1010100", "Visit_ldclrlh_32_memop"},
- {"1011000", "Visit_ldeorlh_32_memop"},
- {"1011100", "Visit_ldsetlh_32_memop"},
- {"101xx10", "Visit_ldrh_32_ldst_regoff"},
- {"1100000", "Visit_ldaddah_32_memop"},
- {"1100100", "Visit_ldclrah_32_memop"},
- {"1101000", "Visit_ldeorah_32_memop"},
- {"1101100", "Visit_ldsetah_32_memop"},
- {"110xx10", "Visit_ldrsh_64_ldst_regoff"},
- {"1110000", "Visit_ldaddalh_32_memop"},
- {"1110100", "Visit_ldclralh_32_memop"},
- {"1111000", "Visit_ldeoralh_32_memop"},
- {"1111100", "Visit_ldsetalh_32_memop"},
- {"111xx10", "Visit_ldrsh_32_ldst_regoff"},
+ { {"0000000"_b, "ldaddb_32_memop"},
+ {"0000100"_b, "ldclrb_32_memop"},
+ {"0001000"_b, "ldeorb_32_memop"},
+ {"0001100"_b, "ldsetb_32_memop"},
+ {"000xx10"_b, "strb_32b_ldst_regoff"},
+ {"0010000"_b, "ldaddlb_32_memop"},
+ {"0010100"_b, "ldclrlb_32_memop"},
+ {"0011000"_b, "ldeorlb_32_memop"},
+ {"0011100"_b, "ldsetlb_32_memop"},
+ {"001xx10"_b, "ldrb_32b_ldst_regoff"},
+ {"0100000"_b, "ldaddab_32_memop"},
+ {"0100100"_b, "ldclrab_32_memop"},
+ {"0101000"_b, "ldeorab_32_memop"},
+ {"0101100"_b, "ldsetab_32_memop"},
+ {"010xx10"_b, "ldrsb_64b_ldst_regoff"},
+ {"0110000"_b, "ldaddalb_32_memop"},
+ {"0110100"_b, "ldclralb_32_memop"},
+ {"0111000"_b, "ldeoralb_32_memop"},
+ {"0111100"_b, "ldsetalb_32_memop"},
+ {"011xx10"_b, "ldrsb_32b_ldst_regoff"},
+ {"1000000"_b, "ldaddh_32_memop"},
+ {"1000100"_b, "ldclrh_32_memop"},
+ {"1001000"_b, "ldeorh_32_memop"},
+ {"1001100"_b, "ldseth_32_memop"},
+ {"100xx10"_b, "strh_32_ldst_regoff"},
+ {"1010000"_b, "ldaddlh_32_memop"},
+ {"1010100"_b, "ldclrlh_32_memop"},
+ {"1011000"_b, "ldeorlh_32_memop"},
+ {"1011100"_b, "ldsetlh_32_memop"},
+ {"101xx10"_b, "ldrh_32_ldst_regoff"},
+ {"1100000"_b, "ldaddah_32_memop"},
+ {"1100100"_b, "ldclrah_32_memop"},
+ {"1101000"_b, "ldeorah_32_memop"},
+ {"1101100"_b, "ldsetah_32_memop"},
+ {"110xx10"_b, "ldrsh_64_ldst_regoff"},
+ {"1110000"_b, "ldaddalh_32_memop"},
+ {"1110100"_b, "ldclralh_32_memop"},
+ {"1111000"_b, "ldeoralh_32_memop"},
+ {"1111100"_b, "ldsetalh_32_memop"},
+ {"111xx10"_b, "ldrsh_32_ldst_regoff"},
},
},
- { "Decode_zqmrhp",
+ { "_zqmrhp",
{23, 22, 4, 3, 2, 1, 0},
- { {"0000000", "Visit_wrffr_f_p"},
+ { {"0000000"_b, "wrffr_f_p"},
},
},
- { "Decode_zrmgjx",
+ { "_zrmgjx",
{30, 23, 22, 13, 4},
- { {"01000", "Visit_ldr_p_bi"},
- {"01100", "Visit_prfb_i_p_bi_s"},
- {"01110", "Visit_prfh_i_p_bi_s"},
- {"10x0x", "Visit_ld1sw_z_p_bz_d_x32_unscaled"},
- {"10x1x", "Visit_ldff1sw_z_p_bz_d_x32_unscaled"},
+ { {"01000"_b, "ldr_p_bi"},
+ {"01100"_b, "prfb_i_p_bi_s"},
+ {"01110"_b, "prfh_i_p_bi_s"},
+ {"10x0x"_b, "ld1sw_z_p_bz_d_x32_unscaled"},
+ {"10x1x"_b, "ldff1sw_z_p_bz_d_x32_unscaled"},
},
},
- { "Decode_zrvlnx",
+ { "_zrvlnx",
{13, 12},
- { {"00", "Visit_sbc_32_addsub_carry"},
+ { {"00"_b, "sbc_32_addsub_carry"},
},
},
- { "Decode_zryvjk",
+ { "_zryvjk",
{20, 9, 4},
- { {"000", "Visit_trn2_p_pp"},
+ { {"000"_b, "trn2_p_pp"},
},
},
- { "Decode_zslsvj",
+ { "_zslsvj",
{23, 22, 20, 19, 11},
- { {"00011", "Visit_fcvtzu_asisdshf_c"},
- {"001x1", "Visit_fcvtzu_asisdshf_c"},
- {"01xx1", "Visit_fcvtzu_asisdshf_c"},
+ { {"00011"_b, "fcvtzu_asisdshf_c"},
+ {"001x1"_b, "fcvtzu_asisdshf_c"},
+ {"01xx1"_b, "fcvtzu_asisdshf_c"},
},
},
- { "Decode_zsltyl",
+ { "_zsltyl",
{22, 20, 11},
- { {"000", "Visit_uqincw_r_rs_uw"},
- {"001", "Visit_uqdecw_r_rs_uw"},
- {"010", "Visit_uqincw_r_rs_x"},
- {"011", "Visit_uqdecw_r_rs_x"},
- {"100", "Visit_uqincd_r_rs_uw"},
- {"101", "Visit_uqdecd_r_rs_uw"},
- {"110", "Visit_uqincd_r_rs_x"},
- {"111", "Visit_uqdecd_r_rs_x"},
+ { {"000"_b, "uqincw_r_rs_uw"},
+ {"001"_b, "uqdecw_r_rs_uw"},
+ {"010"_b, "uqincw_r_rs_x"},
+ {"011"_b, "uqdecw_r_rs_x"},
+ {"100"_b, "uqincd_r_rs_uw"},
+ {"101"_b, "uqdecd_r_rs_uw"},
+ {"110"_b, "uqincd_r_rs_x"},
+ {"111"_b, "uqdecd_r_rs_x"},
},
},
- { "Decode_zssjpv",
+ { "_zssjpv",
{18, 17},
- { {"00", "Visit_st1_asisdlse_r3_3v"},
+ { {"00"_b, "st1_asisdlse_r3_3v"},
},
},
- { "Decode_zsyggq",
+ { "_zsyggq",
{23, 10},
- { {"00", "Decode_txhzxq"},
+ { {"00"_b, "_txhzxq"},
},
},
- { "Decode_ztpryr",
+ { "_ztpryr",
{13},
- { {"0", "Visit_fmad_z_p_zzz"},
- {"1", "Visit_fmsb_z_p_zzz"},
+ { {"0"_b, "fmad_z_p_zzz"},
+ {"1"_b, "fmsb_z_p_zzz"},
},
},
- { "Decode_ztyqrj",
+ { "_ztyqrj",
{30, 23, 13, 12, 10},
- { {"00000", "Decode_jmvgsp"},
- {"00001", "Decode_jkkqvy"},
- {"00100", "Decode_nkxhsy"},
- {"00101", "Decode_gshrzq"},
- {"00110", "Decode_zvjrlz"},
- {"00111", "Decode_ntjpsx"},
- {"01000", "Decode_mqrzzk"},
- {"01001", "Decode_jqxqql"},
- {"01100", "Decode_xznsqh"},
- {"01101", "Decode_qvlnll"},
- {"01110", "Decode_kvnqhn"},
- {"01111", "Decode_zsltyl"},
- {"10110", "Decode_zkhjsp"},
- {"10111", "Decode_hvyjnk"},
- {"11000", "Decode_sjvhlq"},
- {"11001", "Decode_xhktsk"},
- {"11010", "Decode_rtpztp"},
- {"11011", "Decode_rznrqt"},
- {"11100", "Decode_kyspnn"},
- {"11101", "Decode_qljhnp"},
- {"11110", "Decode_pxyrpm"},
- {"11111", "Decode_khjvqq"},
+ { {"00000"_b, "_jmvgsp"},
+ {"00001"_b, "_jkkqvy"},
+ {"00100"_b, "_nkxhsy"},
+ {"00101"_b, "_gshrzq"},
+ {"00110"_b, "_zvjrlz"},
+ {"00111"_b, "_ntjpsx"},
+ {"01000"_b, "_mqrzzk"},
+ {"01001"_b, "_jqxqql"},
+ {"01100"_b, "_xznsqh"},
+ {"01101"_b, "_qvlnll"},
+ {"01110"_b, "_kvnqhn"},
+ {"01111"_b, "_zsltyl"},
+ {"10110"_b, "_zkhjsp"},
+ {"10111"_b, "_hvyjnk"},
+ {"11000"_b, "_sjvhlq"},
+ {"11001"_b, "_xhktsk"},
+ {"11010"_b, "_rtpztp"},
+ {"11011"_b, "_rznrqt"},
+ {"11100"_b, "_kyspnn"},
+ {"11101"_b, "_qljhnp"},
+ {"11110"_b, "_pxyrpm"},
+ {"11111"_b, "_khjvqq"},
},
},
- { "Decode_zvjrlz",
+ { "_zvjrlz",
{22, 20, 11},
- { {"000", "Visit_sqincb_r_rs_sx"},
- {"001", "Visit_sqdecb_r_rs_sx"},
- {"010", "Visit_sqincb_r_rs_x"},
- {"011", "Visit_sqdecb_r_rs_x"},
- {"100", "Visit_sqinch_r_rs_sx"},
- {"101", "Visit_sqdech_r_rs_sx"},
- {"110", "Visit_sqinch_r_rs_x"},
- {"111", "Visit_sqdech_r_rs_x"},
+ { {"000"_b, "sqincb_r_rs_sx"},
+ {"001"_b, "sqdecb_r_rs_sx"},
+ {"010"_b, "sqincb_r_rs_x"},
+ {"011"_b, "sqdecb_r_rs_x"},
+ {"100"_b, "sqinch_r_rs_sx"},
+ {"101"_b, "sqdech_r_rs_sx"},
+ {"110"_b, "sqinch_r_rs_x"},
+ {"111"_b, "sqdech_r_rs_x"},
},
},
- { "Decode_zvlxrl",
+ { "_zvlxrl",
{23, 13, 12},
- { {"010", "Visit_fcmeq_asisdsame_only"},
+ { {"010"_b, "fcmeq_asisdsame_only"},
},
},
- { "Decode_zvqghy",
+ { "_zvqghy",
{30, 23, 22, 13, 12, 11, 10},
- { {"1000000", "Visit_sha256h_qqv_cryptosha3"},
- {"1000100", "Visit_sha256h2_qqv_cryptosha3"},
- {"1001000", "Visit_sha256su1_vvv_cryptosha3"},
+ { {"1000000"_b, "sha256h_qqv_cryptosha3"},
+ {"1000100"_b, "sha256h2_qqv_cryptosha3"},
+ {"1001000"_b, "sha256su1_vvv_cryptosha3"},
},
},
- { "Decode_zxhhny",
+ { "_zxhhny",
{23, 22},
- { {"00", "Visit_fmsub_s_floatdp3"},
- {"01", "Visit_fmsub_d_floatdp3"},
- {"11", "Visit_fmsub_h_floatdp3"},
+ { {"00"_b, "fmsub_s_floatdp3"},
+ {"01"_b, "fmsub_d_floatdp3"},
+ {"11"_b, "fmsub_h_floatdp3"},
},
},
- { "Decode_zxspnk",
+ { "_zxspnk",
{30, 23, 22, 11, 10},
- { {"00000", "Visit_sturb_32_ldst_unscaled"},
- {"00001", "Visit_strb_32_ldst_immpost"},
- {"00010", "Visit_sttrb_32_ldst_unpriv"},
- {"00011", "Visit_strb_32_ldst_immpre"},
- {"00100", "Visit_ldurb_32_ldst_unscaled"},
- {"00101", "Visit_ldrb_32_ldst_immpost"},
- {"00110", "Visit_ldtrb_32_ldst_unpriv"},
- {"00111", "Visit_ldrb_32_ldst_immpre"},
- {"01000", "Visit_ldursb_64_ldst_unscaled"},
- {"01001", "Visit_ldrsb_64_ldst_immpost"},
- {"01010", "Visit_ldtrsb_64_ldst_unpriv"},
- {"01011", "Visit_ldrsb_64_ldst_immpre"},
- {"01100", "Visit_ldursb_32_ldst_unscaled"},
- {"01101", "Visit_ldrsb_32_ldst_immpost"},
- {"01110", "Visit_ldtrsb_32_ldst_unpriv"},
- {"01111", "Visit_ldrsb_32_ldst_immpre"},
- {"10000", "Visit_sturh_32_ldst_unscaled"},
- {"10001", "Visit_strh_32_ldst_immpost"},
- {"10010", "Visit_sttrh_32_ldst_unpriv"},
- {"10011", "Visit_strh_32_ldst_immpre"},
- {"10100", "Visit_ldurh_32_ldst_unscaled"},
- {"10101", "Visit_ldrh_32_ldst_immpost"},
- {"10110", "Visit_ldtrh_32_ldst_unpriv"},
- {"10111", "Visit_ldrh_32_ldst_immpre"},
- {"11000", "Visit_ldursh_64_ldst_unscaled"},
- {"11001", "Visit_ldrsh_64_ldst_immpost"},
- {"11010", "Visit_ldtrsh_64_ldst_unpriv"},
- {"11011", "Visit_ldrsh_64_ldst_immpre"},
- {"11100", "Visit_ldursh_32_ldst_unscaled"},
- {"11101", "Visit_ldrsh_32_ldst_immpost"},
- {"11110", "Visit_ldtrsh_32_ldst_unpriv"},
- {"11111", "Visit_ldrsh_32_ldst_immpre"},
+ { {"00000"_b, "sturb_32_ldst_unscaled"},
+ {"00001"_b, "strb_32_ldst_immpost"},
+ {"00010"_b, "sttrb_32_ldst_unpriv"},
+ {"00011"_b, "strb_32_ldst_immpre"},
+ {"00100"_b, "ldurb_32_ldst_unscaled"},
+ {"00101"_b, "ldrb_32_ldst_immpost"},
+ {"00110"_b, "ldtrb_32_ldst_unpriv"},
+ {"00111"_b, "ldrb_32_ldst_immpre"},
+ {"01000"_b, "ldursb_64_ldst_unscaled"},
+ {"01001"_b, "ldrsb_64_ldst_immpost"},
+ {"01010"_b, "ldtrsb_64_ldst_unpriv"},
+ {"01011"_b, "ldrsb_64_ldst_immpre"},
+ {"01100"_b, "ldursb_32_ldst_unscaled"},
+ {"01101"_b, "ldrsb_32_ldst_immpost"},
+ {"01110"_b, "ldtrsb_32_ldst_unpriv"},
+ {"01111"_b, "ldrsb_32_ldst_immpre"},
+ {"10000"_b, "sturh_32_ldst_unscaled"},
+ {"10001"_b, "strh_32_ldst_immpost"},
+ {"10010"_b, "sttrh_32_ldst_unpriv"},
+ {"10011"_b, "strh_32_ldst_immpre"},
+ {"10100"_b, "ldurh_32_ldst_unscaled"},
+ {"10101"_b, "ldrh_32_ldst_immpost"},
+ {"10110"_b, "ldtrh_32_ldst_unpriv"},
+ {"10111"_b, "ldrh_32_ldst_immpre"},
+ {"11000"_b, "ldursh_64_ldst_unscaled"},
+ {"11001"_b, "ldrsh_64_ldst_immpost"},
+ {"11010"_b, "ldtrsh_64_ldst_unpriv"},
+ {"11011"_b, "ldrsh_64_ldst_immpre"},
+ {"11100"_b, "ldursh_32_ldst_unscaled"},
+ {"11101"_b, "ldrsh_32_ldst_immpost"},
+ {"11110"_b, "ldtrsh_32_ldst_unpriv"},
+ {"11111"_b, "ldrsh_32_ldst_immpre"},
},
},
- { "Decode_zxtzmv",
+ { "_zxtzmv",
{30, 23, 22, 13},
- { {"0010", "Visit_ld1rsh_z_p_bi_s64"},
- {"0011", "Visit_ld1rsh_z_p_bi_s32"},
- {"0110", "Visit_ld1rsb_z_p_bi_s64"},
- {"0111", "Visit_ld1rsb_z_p_bi_s32"},
- {"1000", "Visit_ld1sw_z_p_ai_d"},
- {"1001", "Visit_ldff1sw_z_p_ai_d"},
- {"1010", "Visit_ld1sw_z_p_bz_d_64_scaled"},
- {"1011", "Visit_ldff1sw_z_p_bz_d_64_scaled"},
+ { {"0010"_b, "ld1rsh_z_p_bi_s64"},
+ {"0011"_b, "ld1rsh_z_p_bi_s32"},
+ {"0110"_b, "ld1rsb_z_p_bi_s64"},
+ {"0111"_b, "ld1rsb_z_p_bi_s32"},
+ {"1000"_b, "ld1sw_z_p_ai_d"},
+ {"1001"_b, "ldff1sw_z_p_ai_d"},
+ {"1010"_b, "ld1sw_z_p_bz_d_64_scaled"},
+ {"1011"_b, "ldff1sw_z_p_bz_d_64_scaled"},
},
},
- { "Decode_zyjjgs",
+ { "_zyjjgs",
{23, 22, 20, 19, 18},
- { {"00000", "Visit_orr_z_zi"},
- {"01000", "Visit_eor_z_zi"},
- {"10000", "Visit_and_z_zi"},
- {"11000", "Visit_dupm_z_i"},
- {"xx1xx", "Visit_cpy_z_o_i"},
+ { {"00000"_b, "orr_z_zi"},
+ {"01000"_b, "eor_z_zi"},
+ {"10000"_b, "and_z_zi"},
+ {"11000"_b, "dupm_z_i"},
+ {"xx1xx"_b, "cpy_z_o_i"},
},
},
- { "Decode_zylnnn",
+ { "_zylnnn",
{30},
- { {"0", "Visit_cbz_64_compbranch"},
+ { {"0"_b, "cbz_64_compbranch"},
},
},
- { "Decode_zytrsq",
+ { "_zytrsq",
{30},
- { {"0", "Visit_tbz_only_testbranch"},
+ { {"0"_b, "tbz_only_testbranch"},
},
},
- { "Decode_zyzzhm",
+ { "_zyzzhm",
{23, 20, 19, 18, 17, 16},
- { {"000001", "Visit_frint32x_asimdmisc_r"},
+ { {"000001"_b, "frint32x_asimdmisc_r"},
},
},
- { "Decode_zzgrjz",
+ { "_zzgrjz",
{18, 17},
- { {"0x", "Visit_ld3_asisdlsep_r3_r"},
- {"10", "Visit_ld3_asisdlsep_r3_r"},
- {"11", "Visit_ld3_asisdlsep_i3_i"},
+ { {"0x"_b, "ld3_asisdlsep_r3_r"},
+ {"10"_b, "ld3_asisdlsep_r3_r"},
+ {"11"_b, "ld3_asisdlsep_i3_i"},
},
},
- { "Decode_zzhgng",
+ { "_zzhgng",
{30, 23, 22, 13, 12, 11, 10},
- { {"1000000", "Visit_sha1c_qsv_cryptosha3"},
- {"1000001", "Visit_dup_asisdone_only"},
- {"1000100", "Visit_sha1p_qsv_cryptosha3"},
- {"1001000", "Visit_sha1m_qsv_cryptosha3"},
- {"1001100", "Visit_sha1su0_vvv_cryptosha3"},
- {"1010111", "Visit_fmulx_asisdsamefp16_only"},
- {"1011001", "Visit_fcmeq_asisdsamefp16_only"},
- {"1011111", "Visit_frecps_asisdsamefp16_only"},
- {"1111111", "Visit_frsqrts_asisdsamefp16_only"},
+ { {"1000000"_b, "sha1c_qsv_cryptosha3"},
+ {"1000001"_b, "dup_asisdone_only"},
+ {"1000100"_b, "sha1p_qsv_cryptosha3"},
+ {"1001000"_b, "sha1m_qsv_cryptosha3"},
+ {"1001100"_b, "sha1su0_vvv_cryptosha3"},
+ {"1010111"_b, "fmulx_asisdsamefp16_only"},
+ {"1011001"_b, "fcmeq_asisdsamefp16_only"},
+ {"1011111"_b, "frecps_asisdsamefp16_only"},
+ {"1111111"_b, "frsqrts_asisdsamefp16_only"},
},
},
- { "Decode_zzrqlh",
+ { "_zzrqlh",
{30, 23, 22, 11, 10},
- { {"00000", "Decode_ygpjrl"},
- {"01000", "Visit_csel_32_condsel"},
- {"01001", "Visit_csinc_32_condsel"},
- {"01100", "Decode_hggmnk"},
- {"01101", "Decode_sllkpt"},
- {"01110", "Decode_mgsvlj"},
- {"01111", "Decode_kyyzks"},
- {"10000", "Decode_zrvlnx"},
- {"11000", "Visit_csinv_32_condsel"},
- {"11001", "Visit_csneg_32_condsel"},
- {"11100", "Decode_ghmzhr"},
- {"11101", "Decode_gnqjhz"},
- {"11110", "Decode_mmmjkx"},
+ { {"00000"_b, "_ygpjrl"},
+ {"01000"_b, "csel_32_condsel"},
+ {"01001"_b, "csinc_32_condsel"},
+ {"01100"_b, "_hggmnk"},
+ {"01101"_b, "_sllkpt"},
+ {"01110"_b, "_mgsvlj"},
+ {"01111"_b, "_kyyzks"},
+ {"10000"_b, "_zrvlnx"},
+ {"11000"_b, "csinv_32_condsel"},
+ {"11001"_b, "csneg_32_condsel"},
+ {"11100"_b, "_ghmzhr"},
+ {"11101"_b, "_gnqjhz"},
+ {"11110"_b, "_mmmjkx"},
},
},
- { "Decode_zzvxvh",
+ { "_zzvxvh",
{23, 22, 11, 10},
- { {"0001", "Visit_pmul_z_zz"},
- {"xx00", "Visit_mul_z_zz"},
- {"xx10", "Visit_smulh_z_zz"},
- {"xx11", "Visit_umulh_z_zz"},
+ { {"0001"_b, "pmul_z_zz"},
+ {"xx00"_b, "mul_z_zz"},
+ {"xx10"_b, "smulh_z_zz"},
+ {"xx11"_b, "umulh_z_zz"},
},
},
{ "Root",
{31, 29, 28, 27, 26, 25, 24, 21, 15, 14},
- { {"00000000xx", "Decode_qzjnpr"},
- {"0000100000", "Decode_rzzxsn"},
- {"0000100001", "Decode_xvppmm"},
- {"0000100010", "Decode_ptsjnr"},
- {"0000100011", "Decode_nlpmvl"},
- {"0000100100", "Decode_ljljkv"},
- {"0000100101", "Decode_kktglv"},
- {"0000100110", "Decode_ppnssm"},
- {"0000100111", "Decode_ztyqrj"},
- {"0000101000", "Decode_rnqtmt"},
- {"0000101001", "Decode_njgxlz"},
- {"0000101010", "Decode_mpvsng"},
- {"0000101011", "Decode_qlxksl"},
- {"0000101100", "Decode_mhrjvp"},
- {"0000101101", "Decode_pgjjsz"},
- {"0000101110", "Decode_yppyky"},
- {"0000101111", "Decode_yjmngt"},
- {"000100000x", "Decode_vmjgmg"},
- {"000100001x", "Decode_ytvxsl"},
- {"0001000101", "Decode_yvhnlk"},
- {"0001000111", "Decode_xryzqs"},
- {"000101000x", "Decode_vjqsqs"},
- {"000101010x", "Decode_phvnqh"},
- {"000101100x", "Decode_pphhym"},
- {"00010111xx", "Decode_qsygjs"},
- {"0001100000", "Decode_jxrlyh"},
- {"0001100001", "Decode_yqsgrt"},
- {"0001100010", "Decode_kpyqyv"},
- {"0001101000", "Decode_zkttzl"},
- {"0001101001", "Decode_llqjlh"},
- {"0001101010", "Decode_xhvtjg"},
- {"0001101011", "Decode_xylmmp"},
- {"0001101100", "Decode_vzzvlr"},
- {"0001101101", "Decode_sjlrxn"},
- {"0001101110", "Decode_xrhhjz"},
- {"0001101111", "Decode_ygnypk"},
- {"0001110000", "Decode_xjghst"},
- {"0001110001", "Decode_xxyklv"},
- {"0001110010", "Decode_rtgkkg"},
- {"0001110100", "Decode_hqnxvt"},
- {"0001110101", "Decode_hmxlny"},
- {"0001110110", "Decode_txsmts"},
- {"0001110111", "Decode_mtnpmr"},
- {"0001111000", "Decode_ttstyt"},
- {"0001111001", "Decode_krhrrr"},
- {"0001111010", "Decode_xhltxn"},
- {"0001111011", "Decode_ymznlj"},
- {"0001111100", "Decode_kkgzst"},
- {"0001111101", "Decode_gvjgyp"},
- {"0001111110", "Decode_mjqvxq"},
- {"0001111111", "Decode_spjjkg"},
- {"0010001xxx", "Decode_vppthj"},
- {"0010010xxx", "Decode_qzzlhq"},
- {"001001100x", "Decode_zjslnr"},
- {"001001110x", "Decode_jpxgqh"},
- {"0010011x1x", "Decode_gkhhjm"},
- {"0010100xxx", "Decode_jyxszq"},
- {"0010110xxx", "Decode_xqhgkk"},
- {"00101x1xxx", "Decode_zkqtrj"},
- {"0011000xxx", "Decode_qkyjhg"},
- {"00110010xx", "Decode_yjxshz"},
- {"0011010000", "Decode_zzrqlh"},
- {"0011010001", "Decode_qsrlql"},
- {"001101001x", "Decode_tnrrjk"},
- {"001101100x", "Decode_pnxgrg"},
- {"001101101x", "Decode_ytsghm"},
- {"0011100xxx", "Decode_srmhjk"},
- {"0011110000", "Decode_zzhgng"},
- {"0011110001", "Decode_zvqghy"},
- {"001111001x", "Decode_hnzzkj"},
- {"0011110100", "Decode_qntssm"},
- {"0011110101", "Decode_mrqqlp"},
- {"0011110110", "Decode_nxyhyv"},
- {"0011110111", "Decode_qtknlp"},
- {"0011111000", "Decode_gszlvl"},
- {"0011111001", "Decode_mlnqrm"},
- {"0011111010", "Decode_yvygml"},
- {"0011111011", "Decode_xhxrnt"},
- {"0011111100", "Decode_grqnlm"},
- {"0011111101", "Decode_ktnjrx"},
- {"0011111110", "Decode_gkpzhr"},
- {"0011111111", "Decode_mpyhkm"},
- {"0100100000", "Decode_yyyshx"},
- {"0100100001", "Decode_mylphg"},
- {"0100100010", "Decode_nsjhhg"},
- {"0100100011", "Decode_rhhrhg"},
- {"0100100100", "Decode_ymhgxg"},
- {"0100100101", "Decode_nvkthr"},
- {"0100100110", "Decode_phthqj"},
- {"0100100111", "Decode_kyjxrr"},
- {"0100101000", "Decode_gtvhmp"},
- {"0100101001", "Decode_pppsmg"},
- {"0100101010", "Decode_zgysvr"},
- {"0100101011", "Decode_shqygv"},
- {"0100101100", "Decode_lpsvyy"},
- {"0100101101", "Decode_nqkhrv"},
- {"0100101110", "Decode_tkjtgp"},
- {"0100101111", "Decode_htqpks"},
- {"0101000xxx", "Decode_vpkptr"},
- {"0101001xxx", "Decode_vmjzyk"},
- {"010101000x", "Decode_gmrxlp"},
- {"010101010x", "Decode_jmgkrl"},
- {"010101100x", "Decode_qhgtvk"},
- {"01010111xx", "Decode_rxpspy"},
- {"0101100xxx", "Decode_qhtqrj"},
- {"0101101xxx", "Decode_vnpqrh"},
- {"0101110000", "Decode_vpykkg"},
- {"0101110001", "Decode_xrxvpr"},
- {"0101110010", "Decode_zglksl"},
- {"0101110011", "Decode_gtjskz"},
- {"0101110100", "Decode_qntygx"},
- {"0101110101", "Decode_kxprqm"},
- {"0101110110", "Decode_qxtvzy"},
- {"0101110111", "Decode_mstthg"},
- {"0101111000", "Decode_qmqmpj"},
- {"0101111001", "Decode_rhttgj"},
- {"0101111010", "Decode_jqnhrj"},
- {"0101111011", "Decode_nlqglq"},
- {"0101111100", "Decode_vtxyxz"},
- {"0101111101", "Decode_pqtjgx"},
- {"0101111110", "Decode_snjpvy"},
- {"0101111111", "Decode_spzgkt"},
- {"0110001xxx", "Decode_plktrh"},
- {"0110010xxx", "Decode_xtqmyj"},
- {"0110011xxx", "Decode_lzpykk"},
- {"0110100xxx", "Decode_mtzgpn"},
- {"0110101xxx", "Decode_tvgvvq"},
- {"01110000xx", "Decode_zxspnk"},
- {"0111000100", "Decode_zqmmsk"},
- {"0111000101", "Decode_nmzyvt"},
- {"0111000110", "Decode_vvhzhv"},
- {"0111000111", "Decode_sltqpy"},
- {"0111001xxx", "Decode_qzsthq"},
- {"0111010000", "Decode_zsyggq"},
- {"0111010001", "Decode_hngpgx"},
- {"011101001x", "Decode_njxtpv"},
- {"01111000xx", "Decode_kpmvkn"},
- {"0111100101", "Decode_jhytlg"},
- {"0111100111", "Decode_rksxpn"},
- {"01111001x0", "Decode_trlhgn"},
- {"0111101xxx", "Decode_jxtgtx"},
- {"0111110000", "Decode_tnhmpx"},
- {"0111110010", "Decode_sqjpsl"},
- {"0111110100", "Decode_sjnxky"},
- {"0111110101", "Decode_kykymg"},
- {"0111110110", "Decode_pxzkjy"},
- {"0111110111", "Decode_tjktkm"},
- {"0111111000", "Decode_hhkhkk"},
- {"0111111001", "Decode_nxmjvy"},
- {"0111111010", "Decode_vkvgnm"},
- {"0111111011", "Decode_tssqsr"},
- {"0111111100", "Decode_mthzvm"},
- {"0111111101", "Decode_nlgqsk"},
- {"0111111110", "Decode_gvykrp"},
- {"0111111111", "Decode_sjzsvv"},
- {"0x10000xxx", "Visit_adr_only_pcreladdr"},
- {"1000100000", "Decode_lspzrv"},
- {"1000100001", "Decode_kxvvkq"},
- {"1000100010", "Decode_sxpvym"},
- {"1000100011", "Decode_vkrkks"},
- {"1000100100", "Decode_xvnyxq"},
- {"1000100101", "Decode_gtxpgx"},
- {"1000100110", "Decode_vlrhpy"},
- {"1000100111", "Decode_ymhkrx"},
- {"1000101000", "Decode_zrmgjx"},
- {"1000101001", "Decode_qqyryl"},
- {"1000101010", "Decode_hgxtqy"},
- {"1000101011", "Decode_yytvxh"},
- {"1000101100", "Decode_ptslzg"},
- {"1000101101", "Decode_ytkjxx"},
- {"1000101110", "Decode_zxtzmv"},
- {"1000101111", "Decode_kgmqkh"},
- {"100100000x", "Decode_jhqlkv"},
- {"100100001x", "Decode_lxgltj"},
- {"1001000100", "Decode_hxzlmm"},
- {"1001000101", "Decode_vllqmp"},
- {"1001000110", "Decode_tlstgz"},
- {"1001000111", "Decode_mrmpgh"},
- {"10010100xx", "Decode_rzkmny"},
- {"10010101xx", "Decode_jggvph"},
- {"10010110xx", "Decode_nhkstj"},
- {"10010111xx", "Decode_jsygzs"},
- {"100111000x", "Decode_gmsgqz"},
- {"1001110010", "Decode_grrjlh"},
- {"1001110011", "Decode_jhkglp"},
- {"100111010x", "Decode_qytrjj"},
- {"1001110110", "Decode_qsqqxg"},
- {"1001110111", "Decode_kypqpy"},
- {"1010001xxx", "Decode_vsvtqz"},
- {"1010010xxx", "Decode_vqzlzt"},
- {"10100110xx", "Decode_xxpqgg"},
- {"10100111xx", "Decode_rgjqzs"},
- {"10101000xx", "Decode_qmrgkn"},
- {"10101001xx", "Decode_jkxlnq"},
- {"1010101000", "Decode_ggvztl"},
- {"1010101001", "Decode_xlhjhx"},
- {"101010101x", "Decode_nqgqjh"},
- {"1010101100", "Decode_qsrtzz"},
- {"1010101110", "Decode_tzzzxz"},
- {"10101011x1", "Decode_lhmlrj"},
- {"1010110000", "Decode_kkmxxx"},
- {"1010110100", "Decode_ltvrrg"},
- {"1010111000", "Decode_mqkjxj"},
- {"1010111100", "Decode_pmrngh"},
- {"101011xx10", "Decode_hsjynv"},
- {"101011xxx1", "Decode_kmhtqp"},
- {"1011000xxx", "Decode_ylhxlt"},
- {"10110010xx", "Decode_gkxgsn"},
- {"1011001100", "Decode_xzmjxk"},
- {"1011001110", "Decode_ppqkym"},
- {"10110011x1", "Decode_xzyxnr"},
- {"1011010000", "Decode_xyljvp"},
- {"1011010001", "Decode_sxnkrh"},
- {"101101001x", "Decode_klthpn"},
- {"101101100x", "Decode_xnsrny"},
- {"101101101x", "Decode_htppjj"},
- {"101101110x", "Decode_rmmmjj"},
- {"101101111x", "Decode_txnqzy"},
- {"1011100xxx", "Decode_gmvtss"},
- {"10111100xx", "Decode_gnxgxs"},
- {"1011110100", "Decode_zjgvyp"},
- {"1100100000", "Decode_sjtrhm"},
- {"1100100001", "Decode_hzkglv"},
- {"1100100010", "Decode_qrygny"},
- {"1100100011", "Decode_tjzqnp"},
- {"1100100100", "Decode_yqvqtx"},
- {"1100100101", "Decode_ngttyj"},
- {"1100100110", "Decode_kqzmtr"},
- {"1100100111", "Decode_qpvgnh"},
- {"1100101000", "Decode_tpkslq"},
- {"1100101001", "Decode_ympyng"},
- {"1100101010", "Decode_ytvtqn"},
- {"1100101011", "Decode_qvsypn"},
- {"1100101100", "Decode_lqmksm"},
- {"1100101101", "Decode_mkskxj"},
- {"1100101110", "Decode_knkjnz"},
- {"1100101111", "Decode_hxnmsl"},
- {"1101000xxx", "Decode_shrsxr"},
- {"1101001xxx", "Decode_xhkgqh"},
- {"11010100xx", "Decode_rmxjsn"},
- {"11010101xx", "Decode_mvzvpk"},
- {"11010110xx", "Decode_ysjqhn"},
- {"11010111xx", "Decode_lpkqzl"},
- {"1101100xxx", "Decode_zpzghs"},
- {"1101101xxx", "Decode_gmrxqq"},
- {"1110001xxx", "Decode_jlqjzr"},
- {"1110010xxx", "Decode_qgmngg"},
- {"1110011xxx", "Decode_vlrrtz"},
- {"1110100xxx", "Decode_zylnnn"},
- {"1110101xxx", "Decode_yjjrgg"},
- {"11110000xx", "Decode_qhtrnn"},
- {"1111000100", "Decode_lrqkvp"},
- {"1111000101", "Decode_pvkmmv"},
- {"1111000110", "Decode_lxmyjh"},
- {"1111000111", "Decode_vgrhsz"},
- {"1111001xxx", "Decode_vqvqhp"},
- {"1111010000", "Decode_yjsjvt"},
- {"1111010010", "Decode_yzzlxs"},
- {"11110100x1", "Decode_vkhhkk"},
- {"11111000xx", "Decode_xrhmtg"},
- {"11111001xx", "Decode_xprlgy"},
- {"1111101xxx", "Decode_hjgylh"},
- {"1x10000xxx", "Visit_adrp_only_pcreladdr"},
- {"x110110xxx", "Decode_zytrsq"},
- {"x110111xxx", "Decode_kxsysq"},
+ { {"00000000xx"_b, "_qzjnpr"},
+ {"0000100000"_b, "_rzzxsn"},
+ {"0000100001"_b, "_xvppmm"},
+ {"0000100010"_b, "_ptsjnr"},
+ {"0000100011"_b, "_nlpmvl"},
+ {"0000100100"_b, "_ljljkv"},
+ {"0000100101"_b, "_kktglv"},
+ {"0000100110"_b, "_ppnssm"},
+ {"0000100111"_b, "_ztyqrj"},
+ {"0000101000"_b, "_rnqtmt"},
+ {"0000101001"_b, "_njgxlz"},
+ {"0000101010"_b, "_mpvsng"},
+ {"0000101011"_b, "_qlxksl"},
+ {"0000101100"_b, "_mhrjvp"},
+ {"0000101101"_b, "_pgjjsz"},
+ {"0000101110"_b, "_yppyky"},
+ {"0000101111"_b, "_yjmngt"},
+ {"000100000x"_b, "_vmjgmg"},
+ {"000100001x"_b, "_ytvxsl"},
+ {"0001000101"_b, "_yvhnlk"},
+ {"0001000111"_b, "_xryzqs"},
+ {"000101000x"_b, "_vjqsqs"},
+ {"000101010x"_b, "_phvnqh"},
+ {"000101100x"_b, "_pphhym"},
+ {"00010111xx"_b, "_qsygjs"},
+ {"0001100000"_b, "_jxrlyh"},
+ {"0001100001"_b, "_yqsgrt"},
+ {"0001100010"_b, "_kpyqyv"},
+ {"0001101000"_b, "_zkttzl"},
+ {"0001101001"_b, "_llqjlh"},
+ {"0001101010"_b, "_xhvtjg"},
+ {"0001101011"_b, "_xylmmp"},
+ {"0001101100"_b, "_vzzvlr"},
+ {"0001101101"_b, "_sjlrxn"},
+ {"0001101110"_b, "_xrhhjz"},
+ {"0001101111"_b, "_ygnypk"},
+ {"0001110000"_b, "_xjghst"},
+ {"0001110001"_b, "_xxyklv"},
+ {"0001110010"_b, "_rtgkkg"},
+ {"0001110100"_b, "_hqnxvt"},
+ {"0001110101"_b, "_hmxlny"},
+ {"0001110110"_b, "_txsmts"},
+ {"0001110111"_b, "_mtnpmr"},
+ {"0001111000"_b, "_ttstyt"},
+ {"0001111001"_b, "_krhrrr"},
+ {"0001111010"_b, "_xhltxn"},
+ {"0001111011"_b, "_ymznlj"},
+ {"0001111100"_b, "_kkgzst"},
+ {"0001111101"_b, "_gvjgyp"},
+ {"0001111110"_b, "_mjqvxq"},
+ {"0001111111"_b, "_spjjkg"},
+ {"0010001xxx"_b, "_vppthj"},
+ {"0010010xxx"_b, "_qzzlhq"},
+ {"001001100x"_b, "_zjslnr"},
+ {"001001110x"_b, "_jpxgqh"},
+ {"0010011x1x"_b, "_gkhhjm"},
+ {"0010100xxx"_b, "_jyxszq"},
+ {"0010110xxx"_b, "_xqhgkk"},
+ {"00101x1xxx"_b, "_zkqtrj"},
+ {"0011000xxx"_b, "_qkyjhg"},
+ {"00110010xx"_b, "_yjxshz"},
+ {"0011010000"_b, "_zzrqlh"},
+ {"0011010001"_b, "_qsrlql"},
+ {"001101001x"_b, "_tnrrjk"},
+ {"001101100x"_b, "_pnxgrg"},
+ {"001101101x"_b, "_ytsghm"},
+ {"0011100xxx"_b, "_srmhjk"},
+ {"0011110000"_b, "_zzhgng"},
+ {"0011110001"_b, "_zvqghy"},
+ {"001111001x"_b, "_hnzzkj"},
+ {"0011110100"_b, "_qntssm"},
+ {"0011110101"_b, "_mrqqlp"},
+ {"0011110110"_b, "_nxyhyv"},
+ {"0011110111"_b, "_qtknlp"},
+ {"0011111000"_b, "_gszlvl"},
+ {"0011111001"_b, "_mlnqrm"},
+ {"0011111010"_b, "_yvygml"},
+ {"0011111011"_b, "_xhxrnt"},
+ {"0011111100"_b, "_grqnlm"},
+ {"0011111101"_b, "_ktnjrx"},
+ {"0011111110"_b, "_gkpzhr"},
+ {"0011111111"_b, "_mpyhkm"},
+ {"0100100000"_b, "_yyyshx"},
+ {"0100100001"_b, "_mylphg"},
+ {"0100100010"_b, "_nsjhhg"},
+ {"0100100011"_b, "_rhhrhg"},
+ {"0100100100"_b, "_ymhgxg"},
+ {"0100100101"_b, "_nvkthr"},
+ {"0100100110"_b, "_phthqj"},
+ {"0100100111"_b, "_kyjxrr"},
+ {"0100101000"_b, "_gtvhmp"},
+ {"0100101001"_b, "_pppsmg"},
+ {"0100101010"_b, "_zgysvr"},
+ {"0100101011"_b, "_shqygv"},
+ {"0100101100"_b, "_lpsvyy"},
+ {"0100101101"_b, "_nqkhrv"},
+ {"0100101110"_b, "_tkjtgp"},
+ {"0100101111"_b, "_htqpks"},
+ {"0101000xxx"_b, "_vpkptr"},
+ {"0101001xxx"_b, "_vmjzyk"},
+ {"010101000x"_b, "_gmrxlp"},
+ {"010101010x"_b, "_jmgkrl"},
+ {"010101100x"_b, "_qhgtvk"},
+ {"01010111xx"_b, "_rxpspy"},
+ {"0101100xxx"_b, "_qhtqrj"},
+ {"0101101xxx"_b, "_vnpqrh"},
+ {"0101110000"_b, "_vpykkg"},
+ {"0101110001"_b, "_xrxvpr"},
+ {"0101110010"_b, "_zglksl"},
+ {"0101110011"_b, "_gtjskz"},
+ {"0101110100"_b, "_qntygx"},
+ {"0101110101"_b, "_kxprqm"},
+ {"0101110110"_b, "_qxtvzy"},
+ {"0101110111"_b, "_mstthg"},
+ {"0101111000"_b, "_qmqmpj"},
+ {"0101111001"_b, "_rhttgj"},
+ {"0101111010"_b, "_jqnhrj"},
+ {"0101111011"_b, "_nlqglq"},
+ {"0101111100"_b, "_vtxyxz"},
+ {"0101111101"_b, "_pqtjgx"},
+ {"0101111110"_b, "_snjpvy"},
+ {"0101111111"_b, "_spzgkt"},
+ {"0110001xxx"_b, "_plktrh"},
+ {"0110010xxx"_b, "_xtqmyj"},
+ {"0110011xxx"_b, "_lzpykk"},
+ {"0110100xxx"_b, "_mtzgpn"},
+ {"0110101xxx"_b, "_tvgvvq"},
+ {"01110000xx"_b, "_zxspnk"},
+ {"0111000100"_b, "_zqmmsk"},
+ {"0111000101"_b, "_nmzyvt"},
+ {"0111000110"_b, "_vvhzhv"},
+ {"0111000111"_b, "_sltqpy"},
+ {"0111001xxx"_b, "_qzsthq"},
+ {"0111010000"_b, "_zsyggq"},
+ {"0111010001"_b, "_hngpgx"},
+ {"011101001x"_b, "_njxtpv"},
+ {"01111000xx"_b, "_kpmvkn"},
+ {"0111100101"_b, "_jhytlg"},
+ {"0111100111"_b, "_rksxpn"},
+ {"01111001x0"_b, "_trlhgn"},
+ {"0111101xxx"_b, "_jxtgtx"},
+ {"0111110000"_b, "_tnhmpx"},
+ {"0111110010"_b, "_sqjpsl"},
+ {"0111110100"_b, "_sjnxky"},
+ {"0111110101"_b, "_kykymg"},
+ {"0111110110"_b, "_pxzkjy"},
+ {"0111110111"_b, "_tjktkm"},
+ {"0111111000"_b, "_hhkhkk"},
+ {"0111111001"_b, "_nxmjvy"},
+ {"0111111010"_b, "_vkvgnm"},
+ {"0111111011"_b, "_tssqsr"},
+ {"0111111100"_b, "_mthzvm"},
+ {"0111111101"_b, "_nlgqsk"},
+ {"0111111110"_b, "_gvykrp"},
+ {"0111111111"_b, "_sjzsvv"},
+ {"0x10000xxx"_b, "adr_only_pcreladdr"},
+ {"1000100000"_b, "_lspzrv"},
+ {"1000100001"_b, "_kxvvkq"},
+ {"1000100010"_b, "_sxpvym"},
+ {"1000100011"_b, "_vkrkks"},
+ {"1000100100"_b, "_xvnyxq"},
+ {"1000100101"_b, "_gtxpgx"},
+ {"1000100110"_b, "_vlrhpy"},
+ {"1000100111"_b, "_ymhkrx"},
+ {"1000101000"_b, "_zrmgjx"},
+ {"1000101001"_b, "_qqyryl"},
+ {"1000101010"_b, "_hgxtqy"},
+ {"1000101011"_b, "_yytvxh"},
+ {"1000101100"_b, "_ptslzg"},
+ {"1000101101"_b, "_ytkjxx"},
+ {"1000101110"_b, "_zxtzmv"},
+ {"1000101111"_b, "_kgmqkh"},
+ {"100100000x"_b, "_jhqlkv"},
+ {"100100001x"_b, "_lxgltj"},
+ {"1001000100"_b, "_hxzlmm"},
+ {"1001000101"_b, "_vllqmp"},
+ {"1001000110"_b, "_tlstgz"},
+ {"1001000111"_b, "_mrmpgh"},
+ {"10010100xx"_b, "_rzkmny"},
+ {"10010101xx"_b, "_jggvph"},
+ {"10010110xx"_b, "_nhkstj"},
+ {"10010111xx"_b, "_jsygzs"},
+ {"100111000x"_b, "_gmsgqz"},
+ {"1001110010"_b, "_grrjlh"},
+ {"1001110011"_b, "_jhkglp"},
+ {"100111010x"_b, "_qytrjj"},
+ {"1001110110"_b, "_qsqqxg"},
+ {"1001110111"_b, "_kypqpy"},
+ {"1010001xxx"_b, "_vsvtqz"},
+ {"1010010xxx"_b, "_vqzlzt"},
+ {"10100110xx"_b, "_xxpqgg"},
+ {"10100111xx"_b, "_rgjqzs"},
+ {"10101000xx"_b, "_qmrgkn"},
+ {"10101001xx"_b, "_jkxlnq"},
+ {"1010101000"_b, "_ggvztl"},
+ {"1010101001"_b, "_xlhjhx"},
+ {"101010101x"_b, "_nqgqjh"},
+ {"1010101100"_b, "_qsrtzz"},
+ {"1010101110"_b, "_tzzzxz"},
+ {"10101011x1"_b, "_lhmlrj"},
+ {"1010110000"_b, "_kkmxxx"},
+ {"1010110100"_b, "_ltvrrg"},
+ {"1010111000"_b, "_mqkjxj"},
+ {"1010111100"_b, "_pmrngh"},
+ {"101011xx10"_b, "_hsjynv"},
+ {"101011xxx1"_b, "_kmhtqp"},
+ {"1011000xxx"_b, "_ylhxlt"},
+ {"10110010xx"_b, "_gkxgsn"},
+ {"1011001100"_b, "_xzmjxk"},
+ {"1011001110"_b, "_ppqkym"},
+ {"10110011x1"_b, "_xzyxnr"},
+ {"1011010000"_b, "_xyljvp"},
+ {"1011010001"_b, "_sxnkrh"},
+ {"101101001x"_b, "_klthpn"},
+ {"101101100x"_b, "_xnsrny"},
+ {"101101101x"_b, "_htppjj"},
+ {"101101110x"_b, "_rmmmjj"},
+ {"101101111x"_b, "_txnqzy"},
+ {"1011100xxx"_b, "_gmvtss"},
+ {"10111100xx"_b, "_gnxgxs"},
+ {"1011110100"_b, "_zjgvyp"},
+ {"1100100000"_b, "_sjtrhm"},
+ {"1100100001"_b, "_hzkglv"},
+ {"1100100010"_b, "_qrygny"},
+ {"1100100011"_b, "_tjzqnp"},
+ {"1100100100"_b, "_yqvqtx"},
+ {"1100100101"_b, "_ngttyj"},
+ {"1100100110"_b, "_kqzmtr"},
+ {"1100100111"_b, "_qpvgnh"},
+ {"1100101000"_b, "_tpkslq"},
+ {"1100101001"_b, "_ympyng"},
+ {"1100101010"_b, "_ytvtqn"},
+ {"1100101011"_b, "_qvsypn"},
+ {"1100101100"_b, "_lqmksm"},
+ {"1100101101"_b, "_mkskxj"},
+ {"1100101110"_b, "_knkjnz"},
+ {"1100101111"_b, "_hxnmsl"},
+ {"1101000xxx"_b, "_shrsxr"},
+ {"1101001xxx"_b, "_xhkgqh"},
+ {"11010100xx"_b, "_rmxjsn"},
+ {"11010101xx"_b, "_mvzvpk"},
+ {"11010110xx"_b, "_ysjqhn"},
+ {"11010111xx"_b, "_lpkqzl"},
+ {"1101100xxx"_b, "_zpzghs"},
+ {"1101101xxx"_b, "_gmrxqq"},
+ {"1110001xxx"_b, "_jlqjzr"},
+ {"1110010xxx"_b, "_qgmngg"},
+ {"1110011xxx"_b, "_vlrrtz"},
+ {"1110100xxx"_b, "_zylnnn"},
+ {"1110101xxx"_b, "_yjjrgg"},
+ {"11110000xx"_b, "_qhtrnn"},
+ {"1111000100"_b, "_lrqkvp"},
+ {"1111000101"_b, "_pvkmmv"},
+ {"1111000110"_b, "_lxmyjh"},
+ {"1111000111"_b, "_vgrhsz"},
+ {"1111001xxx"_b, "_vqvqhp"},
+ {"1111010000"_b, "_yjsjvt"},
+ {"1111010010"_b, "_yzzlxs"},
+ {"11110100x1"_b, "_vkhhkk"},
+ {"11111000xx"_b, "_xrhmtg"},
+ {"11111001xx"_b, "_xprlgy"},
+ {"1111101xxx"_b, "_hjgylh"},
+ {"1x10000xxx"_b, "adrp_only_pcreladdr"},
+ {"x110110xxx"_b, "_zytrsq"},
+ {"x110111xxx"_b, "_kxsysq"},
},
},
};
// clang-format on
-static const VisitorNode kVisitorNodes[] = {
-#define VISITOR_NODES(A) {"Visit_" #A, &Decoder::Visit_##A},
- INSTRUCTION_VISITOR_LIST(VISITOR_NODES)
-#undef VISITOR_NODES
-};
-
} // namespace aarch64
} // namespace vixl
diff --git a/src/aarch64/decoder-visitor-map-aarch64.h b/src/aarch64/decoder-visitor-map-aarch64.h
index 99e3b07..e242964 100644
--- a/src/aarch64/decoder-visitor-map-aarch64.h
+++ b/src/aarch64/decoder-visitor-map-aarch64.h
@@ -34,2828 +34,2918 @@
// shared.
#define DEFAULT_FORM_TO_VISITOR_MAP(VISITORCLASS) \
- {"abs_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"addpl_r_ri", &VISITORCLASS::VisitSVEStackFrameAdjustment}, \
- {"addvl_r_ri", &VISITORCLASS::VisitSVEStackFrameAdjustment}, \
- {"add_z_p_zz", &VISITORCLASS::VisitSVEIntAddSubtractVectors_Predicated}, \
- {"add_z_zi", &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
- {"add_z_zz", &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
- {"adr_z_az_d_s32_scaled", &VISITORCLASS::VisitSVEAddressGeneration}, \
- {"adr_z_az_d_u32_scaled", &VISITORCLASS::VisitSVEAddressGeneration}, \
- {"adr_z_az_sd_same_scaled", &VISITORCLASS::VisitSVEAddressGeneration}, \
- {"ands_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"andv_r_p_z", &VISITORCLASS::VisitSVEIntReduction}, \
- {"and_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"and_z_p_zz", &VISITORCLASS::VisitSVEBitwiseLogical_Predicated}, \
- {"and_z_zi", &VISITORCLASS::VisitSVEBitwiseLogicalWithImm_Unpredicated}, \
- {"and_z_zz", &VISITORCLASS::VisitSVEBitwiseLogicalUnpredicated}, \
- {"asrd_z_p_zi", &VISITORCLASS::VisitSVEBitwiseShiftByImm_Predicated}, \
- {"asrr_z_p_zz", &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
- {"asr_z_p_zi", &VISITORCLASS::VisitSVEBitwiseShiftByImm_Predicated}, \
- {"asr_z_p_zw", \
- &VISITORCLASS::VisitSVEBitwiseShiftByWideElements_Predicated}, \
- {"asr_z_p_zz", &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
- {"asr_z_zi", &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
- {"asr_z_zw", &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
- {"bics_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"bic_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"bic_z_p_zz", &VISITORCLASS::VisitSVEBitwiseLogical_Predicated}, \
- {"bic_z_zz", &VISITORCLASS::VisitSVEBitwiseLogicalUnpredicated}, \
- {"brkas_p_p_p_z", &VISITORCLASS::VisitSVEPartitionBreakCondition}, \
- {"brka_p_p_p", &VISITORCLASS::VisitSVEPartitionBreakCondition}, \
- {"brkbs_p_p_p_z", &VISITORCLASS::VisitSVEPartitionBreakCondition}, \
- {"brkb_p_p_p", &VISITORCLASS::VisitSVEPartitionBreakCondition}, \
- {"brkns_p_p_pp", &VISITORCLASS::VisitSVEPropagateBreakToNextPartition}, \
- {"brkn_p_p_pp", &VISITORCLASS::VisitSVEPropagateBreakToNextPartition}, \
- {"brkpas_p_p_pp", &VISITORCLASS::VisitSVEPropagateBreak}, \
- {"brkpa_p_p_pp", &VISITORCLASS::VisitSVEPropagateBreak}, \
- {"brkpbs_p_p_pp", &VISITORCLASS::VisitSVEPropagateBreak}, \
- {"brkpb_p_p_pp", &VISITORCLASS::VisitSVEPropagateBreak}, \
- {"clasta_r_p_z", \
- &VISITORCLASS::VisitSVEConditionallyExtractElementToGeneralRegister}, \
- {"clasta_v_p_z", \
- &VISITORCLASS::VisitSVEConditionallyExtractElementToSIMDFPScalar}, \
- {"clasta_z_p_zz", \
- &VISITORCLASS::VisitSVEConditionallyBroadcastElementToVector}, \
- {"clastb_r_p_z", \
- &VISITORCLASS::VisitSVEConditionallyExtractElementToGeneralRegister}, \
- {"clastb_v_p_z", \
- &VISITORCLASS::VisitSVEConditionallyExtractElementToSIMDFPScalar}, \
- {"clastb_z_p_zz", \
- &VISITORCLASS::VisitSVEConditionallyBroadcastElementToVector}, \
- {"cls_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"clz_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"cmpeq_p_p_zi", &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
- {"cmpeq_p_p_zw", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmpeq_p_p_zz", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmpge_p_p_zi", &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
- {"cmpge_p_p_zw", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmpge_p_p_zz", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmpgt_p_p_zi", &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
- {"cmpgt_p_p_zw", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmpgt_p_p_zz", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmphi_p_p_zi", &VISITORCLASS::VisitSVEIntCompareUnsignedImm}, \
- {"cmphi_p_p_zw", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmphi_p_p_zz", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmphs_p_p_zi", &VISITORCLASS::VisitSVEIntCompareUnsignedImm}, \
- {"cmphs_p_p_zw", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmphs_p_p_zz", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmple_p_p_zi", &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
- {"cmple_p_p_zw", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmplo_p_p_zi", &VISITORCLASS::VisitSVEIntCompareUnsignedImm}, \
- {"cmplo_p_p_zw", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmpls_p_p_zi", &VISITORCLASS::VisitSVEIntCompareUnsignedImm}, \
- {"cmpls_p_p_zw", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmplt_p_p_zi", &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
- {"cmplt_p_p_zw", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmpne_p_p_zi", &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
- {"cmpne_p_p_zw", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cmpne_p_p_zz", &VISITORCLASS::VisitSVEIntCompareVectors}, \
- {"cnot_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"cntb_r_s", &VISITORCLASS::VisitSVEElementCount}, \
- {"cntd_r_s", &VISITORCLASS::VisitSVEElementCount}, \
- {"cnth_r_s", &VISITORCLASS::VisitSVEElementCount}, \
- {"cntp_r_p_p", &VISITORCLASS::VisitSVEPredicateCount}, \
- {"cntw_r_s", &VISITORCLASS::VisitSVEElementCount}, \
- {"cnt_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"compact_z_p_z", &VISITORCLASS::VisitSVECompressActiveElements}, \
- {"cpy_z_o_i", &VISITORCLASS::VisitSVECopyIntImm_Predicated}, \
- {"cpy_z_p_i", &VISITORCLASS::VisitSVECopyIntImm_Predicated}, \
- {"cpy_z_p_r", \
- &VISITORCLASS::VisitSVECopyGeneralRegisterToVector_Predicated}, \
- {"cpy_z_p_v", \
- &VISITORCLASS::VisitSVECopySIMDFPScalarRegisterToVector_Predicated}, \
- {"ctermeq_rr", &VISITORCLASS::VisitSVEConditionallyTerminateScalars}, \
- {"ctermne_rr", &VISITORCLASS::VisitSVEConditionallyTerminateScalars}, \
- {"decb_r_rs", &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
- {"decd_r_rs", &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
- {"decd_z_zs", &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
- {"dech_r_rs", &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
- {"dech_z_zs", &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
- {"decp_r_p_r", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"decp_z_p_z", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"decw_r_rs", &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
- {"decw_z_zs", &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
- {"dupm_z_i", &VISITORCLASS::VisitSVEBroadcastBitmaskImm}, \
- {"dup_z_i", &VISITORCLASS::VisitSVEBroadcastIntImm_Unpredicated}, \
- {"dup_z_r", &VISITORCLASS::VisitSVEBroadcastGeneralRegister}, \
- {"dup_z_zi", &VISITORCLASS::VisitSVEBroadcastIndexElement}, \
- {"eors_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"eorv_r_p_z", &VISITORCLASS::VisitSVEIntReduction}, \
- {"eor_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"eor_z_p_zz", &VISITORCLASS::VisitSVEBitwiseLogical_Predicated}, \
- {"eor_z_zi", &VISITORCLASS::VisitSVEBitwiseLogicalWithImm_Unpredicated}, \
- {"eor_z_zz", &VISITORCLASS::VisitSVEBitwiseLogicalUnpredicated}, \
- {"ext_z_zi_des", &VISITORCLASS::VisitSVEPermuteVectorExtract}, \
- {"fabd_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fabs_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"facge_p_p_zz", &VISITORCLASS::VisitSVEFPCompareVectors}, \
- {"facgt_p_p_zz", &VISITORCLASS::VisitSVEFPCompareVectors}, \
- {"fadda_v_p_z", &VISITORCLASS::VisitSVEFPAccumulatingReduction}, \
- {"faddv_v_p_z", &VISITORCLASS::VisitSVEFPFastReduction}, \
- {"fadd_z_p_zs", &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
- {"fadd_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fadd_z_zz", &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
- {"fcadd_z_p_zz", &VISITORCLASS::VisitSVEFPComplexAddition}, \
- {"fcmeq_p_p_z0", &VISITORCLASS::VisitSVEFPCompareWithZero}, \
- {"fcmeq_p_p_zz", &VISITORCLASS::VisitSVEFPCompareVectors}, \
- {"fcmge_p_p_z0", &VISITORCLASS::VisitSVEFPCompareWithZero}, \
- {"fcmge_p_p_zz", &VISITORCLASS::VisitSVEFPCompareVectors}, \
- {"fcmgt_p_p_z0", &VISITORCLASS::VisitSVEFPCompareWithZero}, \
- {"fcmgt_p_p_zz", &VISITORCLASS::VisitSVEFPCompareVectors}, \
- {"fcmla_z_p_zzz", &VISITORCLASS::VisitSVEFPComplexMulAdd}, \
- {"fcmla_z_zzzi_h", &VISITORCLASS::VisitSVEFPComplexMulAddIndex}, \
- {"fcmla_z_zzzi_s", &VISITORCLASS::VisitSVEFPComplexMulAddIndex}, \
- {"fcmle_p_p_z0", &VISITORCLASS::VisitSVEFPCompareWithZero}, \
- {"fcmlt_p_p_z0", &VISITORCLASS::VisitSVEFPCompareWithZero}, \
- {"fcmne_p_p_z0", &VISITORCLASS::VisitSVEFPCompareWithZero}, \
- {"fcmne_p_p_zz", &VISITORCLASS::VisitSVEFPCompareVectors}, \
- {"fcmuo_p_p_zz", &VISITORCLASS::VisitSVEFPCompareVectors}, \
- {"fcpy_z_p_i", &VISITORCLASS::VisitSVECopyFPImm_Predicated}, \
- {"fcvtzs_z_p_z_d2w", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzs_z_p_z_d2x", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzs_z_p_z_fp162h", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzs_z_p_z_fp162w", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzs_z_p_z_fp162x", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzs_z_p_z_s2w", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzs_z_p_z_s2x", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzu_z_p_z_d2w", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzu_z_p_z_d2x", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzu_z_p_z_fp162h", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzu_z_p_z_fp162w", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzu_z_p_z_fp162x", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzu_z_p_z_s2w", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvtzu_z_p_z_s2x", &VISITORCLASS::VisitSVEFPConvertToInt}, \
- {"fcvt_z_p_z_d2h", &VISITORCLASS::VisitSVEFPConvertPrecision}, \
- {"fcvt_z_p_z_d2s", &VISITORCLASS::VisitSVEFPConvertPrecision}, \
- {"fcvt_z_p_z_h2d", &VISITORCLASS::VisitSVEFPConvertPrecision}, \
- {"fcvt_z_p_z_h2s", &VISITORCLASS::VisitSVEFPConvertPrecision}, \
- {"fcvt_z_p_z_s2d", &VISITORCLASS::VisitSVEFPConvertPrecision}, \
- {"fcvt_z_p_z_s2h", &VISITORCLASS::VisitSVEFPConvertPrecision}, \
- {"fdivr_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fdiv_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fdup_z_i", &VISITORCLASS::VisitSVEBroadcastFPImm_Unpredicated}, \
- {"fexpa_z_z", &VISITORCLASS::VisitSVEFPExponentialAccelerator}, \
- {"fmad_z_p_zzz", &VISITORCLASS::VisitSVEFPMulAdd}, \
- {"fmaxnmv_v_p_z", &VISITORCLASS::VisitSVEFPFastReduction}, \
- {"fmaxnm_z_p_zs", \
- &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
- {"fmaxnm_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fmaxv_v_p_z", &VISITORCLASS::VisitSVEFPFastReduction}, \
- {"fmax_z_p_zs", &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
- {"fmax_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fminnmv_v_p_z", &VISITORCLASS::VisitSVEFPFastReduction}, \
- {"fminnm_z_p_zs", \
- &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
- {"fminnm_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fminv_v_p_z", &VISITORCLASS::VisitSVEFPFastReduction}, \
- {"fmin_z_p_zs", &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
- {"fmin_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fmla_z_p_zzz", &VISITORCLASS::VisitSVEFPMulAdd}, \
- {"fmla_z_zzzi_d", &VISITORCLASS::VisitSVEFPMulAddIndex}, \
- {"fmla_z_zzzi_h", &VISITORCLASS::VisitSVEFPMulAddIndex}, \
- {"fmla_z_zzzi_s", &VISITORCLASS::VisitSVEFPMulAddIndex}, \
- {"fmls_z_p_zzz", &VISITORCLASS::VisitSVEFPMulAdd}, \
- {"fmls_z_zzzi_d", &VISITORCLASS::VisitSVEFPMulAddIndex}, \
- {"fmls_z_zzzi_h", &VISITORCLASS::VisitSVEFPMulAddIndex}, \
- {"fmls_z_zzzi_s", &VISITORCLASS::VisitSVEFPMulAddIndex}, \
- {"fmsb_z_p_zzz", &VISITORCLASS::VisitSVEFPMulAdd}, \
- {"fmulx_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fmul_z_p_zs", &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
- {"fmul_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fmul_z_zz", &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
- {"fmul_z_zzi_d", &VISITORCLASS::VisitSVEFPMulIndex}, \
- {"fmul_z_zzi_h", &VISITORCLASS::VisitSVEFPMulIndex}, \
- {"fmul_z_zzi_s", &VISITORCLASS::VisitSVEFPMulIndex}, \
- {"fneg_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"fnmad_z_p_zzz", &VISITORCLASS::VisitSVEFPMulAdd}, \
- {"fnmla_z_p_zzz", &VISITORCLASS::VisitSVEFPMulAdd}, \
- {"fnmls_z_p_zzz", &VISITORCLASS::VisitSVEFPMulAdd}, \
- {"fnmsb_z_p_zzz", &VISITORCLASS::VisitSVEFPMulAdd}, \
- {"frecpe_z_z", &VISITORCLASS::VisitSVEFPUnaryOpUnpredicated}, \
- {"frecps_z_zz", &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
- {"frecpx_z_p_z", &VISITORCLASS::VisitSVEFPUnaryOp}, \
- {"frinta_z_p_z", &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
- {"frinti_z_p_z", &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
- {"frintm_z_p_z", &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
- {"frintn_z_p_z", &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
- {"frintp_z_p_z", &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
- {"frintx_z_p_z", &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
- {"frintz_z_p_z", &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
- {"frsqrte_z_z", &VISITORCLASS::VisitSVEFPUnaryOpUnpredicated}, \
- {"frsqrts_z_zz", &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
- {"fscale_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fsqrt_z_p_z", &VISITORCLASS::VisitSVEFPUnaryOp}, \
- {"fsubr_z_p_zs", &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
- {"fsubr_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fsub_z_p_zs", &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
- {"fsub_z_p_zz", &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
- {"fsub_z_zz", &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
- {"ftmad_z_zzi", &VISITORCLASS::VisitSVEFPTrigMulAddCoefficient}, \
- {"ftsmul_z_zz", &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
- {"ftssel_z_zz", &VISITORCLASS::VisitSVEFPTrigSelectCoefficient}, \
- {"incb_r_rs", &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
- {"incd_r_rs", &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
- {"incd_z_zs", &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
- {"inch_r_rs", &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
- {"inch_z_zs", &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
- {"incp_r_p_r", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"incp_z_p_z", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"incw_r_rs", &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
- {"incw_z_zs", &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
- {"index_z_ii", &VISITORCLASS::VisitSVEIndexGeneration}, \
- {"index_z_ir", &VISITORCLASS::VisitSVEIndexGeneration}, \
- {"index_z_ri", &VISITORCLASS::VisitSVEIndexGeneration}, \
- {"index_z_rr", &VISITORCLASS::VisitSVEIndexGeneration}, \
- {"insr_z_r", &VISITORCLASS::VisitSVEInsertGeneralRegister}, \
- {"insr_z_v", &VISITORCLASS::VisitSVEInsertSIMDFPScalarRegister}, \
- {"lasta_r_p_z", &VISITORCLASS::VisitSVEExtractElementToGeneralRegister}, \
- {"lasta_v_p_z", \
- &VISITORCLASS::VisitSVEExtractElementToSIMDFPScalarRegister}, \
- {"lastb_r_p_z", &VISITORCLASS::VisitSVEExtractElementToGeneralRegister}, \
- {"lastb_v_p_z", \
- &VISITORCLASS::VisitSVEExtractElementToSIMDFPScalarRegister}, \
- {"ld1b_z_p_ai_d", &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ld1b_z_p_ai_s", &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
- {"ld1b_z_p_bi_u16", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1b_z_p_bi_u32", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1b_z_p_bi_u64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1b_z_p_bi_u8", &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1b_z_p_br_u16", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1b_z_p_br_u32", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1b_z_p_br_u64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1b_z_p_br_u8", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1b_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ld1b_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ld1b_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
- {"ld1d_z_p_ai_d", &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ld1d_z_p_bi_u64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1d_z_p_br_u64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1d_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
- {"ld1d_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ld1d_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
- {"ld1d_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ld1h_z_p_ai_d", &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ld1h_z_p_ai_s", &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
- {"ld1h_z_p_bi_u16", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1h_z_p_bi_u32", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1h_z_p_bi_u64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1h_z_p_br_u16", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1h_z_p_br_u32", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1h_z_p_br_u64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1h_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
- {"ld1h_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ld1h_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
- {"ld1h_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ld1h_z_p_bz_s_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets}, \
- {"ld1h_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
- {"ld1rb_z_p_bi_u16", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rb_z_p_bi_u32", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rb_z_p_bi_u64", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rb_z_p_bi_u8", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rd_z_p_bi_u64", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rh_z_p_bi_u16", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rh_z_p_bi_u32", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rh_z_p_bi_u64", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rqb_z_p_bi_u8", \
- &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm}, \
- {"ld1rqb_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar}, \
- {"ld1rqd_z_p_bi_u64", \
- &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm}, \
- {"ld1rqd_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar}, \
- {"ld1rqh_z_p_bi_u16", \
- &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm}, \
- {"ld1rqh_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar}, \
- {"ld1rqw_z_p_bi_u32", \
- &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm}, \
- {"ld1rqw_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar}, \
- {"ld1rsb_z_p_bi_s16", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rsb_z_p_bi_s32", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rsb_z_p_bi_s64", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rsh_z_p_bi_s32", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rsh_z_p_bi_s64", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rsw_z_p_bi_s64", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rw_z_p_bi_u32", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1rw_z_p_bi_u64", &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
- {"ld1sb_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ld1sb_z_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
- {"ld1sb_z_p_bi_s16", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1sb_z_p_bi_s32", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1sb_z_p_bi_s64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1sb_z_p_br_s16", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1sb_z_p_br_s32", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1sb_z_p_br_s64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1sb_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ld1sb_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ld1sb_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
- {"ld1sh_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ld1sh_z_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
- {"ld1sh_z_p_bi_s32", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1sh_z_p_bi_s64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1sh_z_p_br_s32", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1sh_z_p_br_s64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1sh_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
- {"ld1sh_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ld1sh_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
- {"ld1sh_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ld1sh_z_p_bz_s_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets}, \
- {"ld1sh_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
- {"ld1sw_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ld1sw_z_p_bi_s64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1sw_z_p_br_s64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1sw_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
- {"ld1sw_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ld1sw_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
- {"ld1sw_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ld1w_z_p_ai_d", &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ld1w_z_p_ai_s", &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
- {"ld1w_z_p_bi_u32", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1w_z_p_bi_u64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
- {"ld1w_z_p_br_u32", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1w_z_p_br_u64", \
- &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
- {"ld1w_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
- {"ld1w_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ld1w_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
- {"ld1w_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ld1w_z_p_bz_s_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets}, \
- {"ld1w_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
- {"ld2b_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld2b_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ld2d_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld2d_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ld2h_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld2h_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ld2w_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld2w_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ld3b_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld3b_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ld3d_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld3d_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ld3h_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld3h_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ld3w_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld3w_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ld4b_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld4b_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ld4d_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld4d_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ld4h_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld4h_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ld4w_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
- {"ld4w_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
- {"ldff1b_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ldff1b_z_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
- {"ldff1b_z_p_br_u16", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1b_z_p_br_u32", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1b_z_p_br_u64", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1b_z_p_br_u8", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1b_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ldff1b_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ldff1b_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
- {"ldff1d_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ldff1d_z_p_br_u64", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1d_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
- {"ldff1d_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ldff1d_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
- {"ldff1d_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ldff1h_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ldff1h_z_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
- {"ldff1h_z_p_br_u16", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1h_z_p_br_u32", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1h_z_p_br_u64", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1h_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
- {"ldff1h_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ldff1h_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
- {"ldff1h_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ldff1h_z_p_bz_s_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets}, \
- {"ldff1h_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
- {"ldff1sb_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ldff1sb_z_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
- {"ldff1sb_z_p_br_s16", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1sb_z_p_br_s32", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1sb_z_p_br_s64", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1sb_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ldff1sb_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ldff1sb_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
- {"ldff1sh_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ldff1sh_z_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
- {"ldff1sh_z_p_br_s32", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1sh_z_p_br_s64", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1sh_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
- {"ldff1sh_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ldff1sh_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
- {"ldff1sh_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ldff1sh_z_p_bz_s_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets}, \
- {"ldff1sh_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
- {"ldff1sw_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ldff1sw_z_p_br_s64", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1sw_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
- {"ldff1sw_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ldff1sw_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
- {"ldff1sw_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ldff1w_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
- {"ldff1w_z_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
- {"ldff1w_z_p_br_u32", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1w_z_p_br_u64", \
- &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
- {"ldff1w_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
- {"ldff1w_z_p_bz_d_64_unscaled", \
- &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
- {"ldff1w_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
- {"ldff1w_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"ldff1w_z_p_bz_s_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets}, \
- {"ldff1w_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
- {"ldnf1b_z_p_bi_u16", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1b_z_p_bi_u32", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1b_z_p_bi_u64", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1b_z_p_bi_u8", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1d_z_p_bi_u64", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1h_z_p_bi_u16", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1h_z_p_bi_u32", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1h_z_p_bi_u64", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1sb_z_p_bi_s16", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1sb_z_p_bi_s32", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1sb_z_p_bi_s64", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1sh_z_p_bi_s32", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1sh_z_p_bi_s64", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1sw_z_p_bi_s64", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1w_z_p_bi_u32", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnf1w_z_p_bi_u64", \
- &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
- {"ldnt1b_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm}, \
- {"ldnt1b_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar}, \
- {"ldnt1d_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm}, \
- {"ldnt1d_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar}, \
- {"ldnt1h_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm}, \
- {"ldnt1h_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar}, \
- {"ldnt1w_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm}, \
- {"ldnt1w_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar}, \
- {"ldr_p_bi", &VISITORCLASS::VisitSVELoadPredicateRegister}, \
- {"ldr_z_bi", &VISITORCLASS::VisitSVELoadVectorRegister}, \
- {"lslr_z_p_zz", &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
- {"lsl_z_p_zi", &VISITORCLASS::VisitSVEBitwiseShiftByImm_Predicated}, \
- {"lsl_z_p_zw", \
- &VISITORCLASS::VisitSVEBitwiseShiftByWideElements_Predicated}, \
- {"lsl_z_p_zz", &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
- {"lsl_z_zi", &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
- {"lsl_z_zw", &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
- {"lsrr_z_p_zz", &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
- {"lsr_z_p_zi", &VISITORCLASS::VisitSVEBitwiseShiftByImm_Predicated}, \
- {"lsr_z_p_zw", \
- &VISITORCLASS::VisitSVEBitwiseShiftByWideElements_Predicated}, \
- {"lsr_z_p_zz", &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
- {"lsr_z_zi", &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
- {"lsr_z_zw", &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
- {"mad_z_p_zzz", &VISITORCLASS::VisitSVEIntMulAddPredicated}, \
- {"mla_z_p_zzz", &VISITORCLASS::VisitSVEIntMulAddPredicated}, \
- {"mls_z_p_zzz", &VISITORCLASS::VisitSVEIntMulAddPredicated}, \
- {"movprfx_z_p_z", &VISITORCLASS::VisitSVEMovprfx}, \
- {"movprfx_z_z", &VISITORCLASS::VisitSVEConstructivePrefix_Unpredicated}, \
- {"msb_z_p_zzz", &VISITORCLASS::VisitSVEIntMulAddPredicated}, \
- {"mul_z_p_zz", &VISITORCLASS::VisitSVEIntMulVectors_Predicated}, \
- {"mul_z_zi", &VISITORCLASS::VisitSVEIntMulImm_Unpredicated}, \
- {"nands_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"nand_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"neg_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"nors_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"nor_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"not_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"orns_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"orn_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"orrs_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"orr_p_p_pp_z", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"orr_z_p_zz", &VISITORCLASS::VisitSVEBitwiseLogical_Predicated}, \
- {"orr_z_zi", &VISITORCLASS::VisitSVEBitwiseLogicalWithImm_Unpredicated}, \
- {"orr_z_zz", &VISITORCLASS::VisitSVEBitwiseLogicalUnpredicated}, \
- {"orv_r_p_z", &VISITORCLASS::VisitSVEIntReduction}, \
- {"pfalse_p", &VISITORCLASS::VisitSVEPredicateZero}, \
- {"pfirst_p_p_p", &VISITORCLASS::VisitSVEPredicateFirstActive}, \
- {"pnext_p_p_p", &VISITORCLASS::VisitSVEPredicateNextActive}, \
- {"prfb_i_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherPrefetch_VectorPlusImm}, \
- {"prfb_i_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitGatherPrefetch_VectorPlusImm}, \
- {"prfb_i_p_bi_s", \
- &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusImm}, \
- {"prfb_i_p_br_s", \
- &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusScalar}, \
- {"prfb_i_p_bz_d_64_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets}, \
- {"prfb_i_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets}, \
- {"prfb_i_p_bz_s_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets}, \
- {"prfd_i_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherPrefetch_VectorPlusImm}, \
- {"prfd_i_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitGatherPrefetch_VectorPlusImm}, \
- {"prfd_i_p_bi_s", \
- &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusImm}, \
- {"prfd_i_p_br_s", \
- &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusScalar}, \
- {"prfd_i_p_bz_d_64_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets}, \
- {"prfd_i_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets}, \
- {"prfd_i_p_bz_s_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets}, \
- {"prfh_i_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherPrefetch_VectorPlusImm}, \
- {"prfh_i_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitGatherPrefetch_VectorPlusImm}, \
- {"prfh_i_p_bi_s", \
- &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusImm}, \
- {"prfh_i_p_br_s", \
- &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusScalar}, \
- {"prfh_i_p_bz_d_64_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets}, \
- {"prfh_i_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets}, \
- {"prfh_i_p_bz_s_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets}, \
- {"prfw_i_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitGatherPrefetch_VectorPlusImm}, \
- {"prfw_i_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitGatherPrefetch_VectorPlusImm}, \
- {"prfw_i_p_bi_s", \
- &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusImm}, \
- {"prfw_i_p_br_s", \
- &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusScalar}, \
- {"prfw_i_p_bz_d_64_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets}, \
- {"prfw_i_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets}, \
- {"prfw_i_p_bz_s_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets}, \
- {"ptest_p_p", &VISITORCLASS::VisitSVEPredicateTest}, \
- {"ptrues_p_s", &VISITORCLASS::VisitSVEPredicateInitialize}, \
- {"ptrue_p_s", &VISITORCLASS::VisitSVEPredicateInitialize}, \
- {"punpkhi_p_p", &VISITORCLASS::VisitSVEUnpackPredicateElements}, \
- {"punpklo_p_p", &VISITORCLASS::VisitSVEUnpackPredicateElements}, \
- {"rbit_z_p_z", &VISITORCLASS::VisitSVEReverseWithinElements}, \
- {"rdffrs_p_p_f", \
- &VISITORCLASS::VisitSVEPredicateReadFromFFR_Predicated}, \
- {"rdffr_p_f", &VISITORCLASS::VisitSVEPredicateReadFromFFR_Unpredicated}, \
- {"rdffr_p_p_f", &VISITORCLASS::VisitSVEPredicateReadFromFFR_Predicated}, \
- {"rdvl_r_i", &VISITORCLASS::VisitSVEStackFrameSize}, \
- {"revb_z_z", &VISITORCLASS::VisitSVEReverseWithinElements}, \
- {"revh_z_z", &VISITORCLASS::VisitSVEReverseWithinElements}, \
- {"revw_z_z", &VISITORCLASS::VisitSVEReverseWithinElements}, \
- {"rev_p_p", &VISITORCLASS::VisitSVEReversePredicateElements}, \
- {"rev_z_z", &VISITORCLASS::VisitSVEReverseVectorElements}, \
- {"sabd_z_p_zz", &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
- {"saddv_r_p_z", &VISITORCLASS::VisitSVEIntReduction}, \
- {"scvtf_z_p_z_h2fp16", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"scvtf_z_p_z_w2d", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"scvtf_z_p_z_w2fp16", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"scvtf_z_p_z_w2s", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"scvtf_z_p_z_x2d", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"scvtf_z_p_z_x2fp16", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"scvtf_z_p_z_x2s", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"sdivr_z_p_zz", &VISITORCLASS::VisitSVEIntDivideVectors_Predicated}, \
- {"sdiv_z_p_zz", &VISITORCLASS::VisitSVEIntDivideVectors_Predicated}, \
- {"sdot_z_zzz", &VISITORCLASS::VisitSVEIntMulAddUnpredicated}, \
- {"sdot_z_zzzi_d", &VISITORCLASS::VisitSVEMulIndex}, \
- {"sdot_z_zzzi_s", &VISITORCLASS::VisitSVEMulIndex}, \
- {"sel_p_p_pp", &VISITORCLASS::VisitSVEPredicateLogical}, \
- {"sel_z_p_zz", &VISITORCLASS::VisitSVEVectorSelect}, \
- {"setffr_f", &VISITORCLASS::VisitSVEFFRInitialise}, \
- {"smaxv_r_p_z", &VISITORCLASS::VisitSVEIntReduction}, \
- {"smax_z_p_zz", &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
- {"smax_z_zi", &VISITORCLASS::VisitSVEIntMinMaxImm_Unpredicated}, \
- {"sminv_r_p_z", &VISITORCLASS::VisitSVEIntReduction}, \
- {"smin_z_p_zz", &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
- {"smin_z_zi", &VISITORCLASS::VisitSVEIntMinMaxImm_Unpredicated}, \
- {"smulh_z_p_zz", &VISITORCLASS::VisitSVEIntMulVectors_Predicated}, \
- {"splice_z_p_zz_des", &VISITORCLASS::VisitSVEVectorSplice}, \
- {"sqadd_z_zi", &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
- {"sqadd_z_zz", &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
- {"sqdecb_r_rs_sx", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqdecb_r_rs_x", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqdecd_r_rs_sx", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqdecd_r_rs_x", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqdecd_z_zs", \
- &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"sqdech_r_rs_sx", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqdech_r_rs_x", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqdech_z_zs", \
- &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"sqdecp_r_p_r_sx", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"sqdecp_r_p_r_x", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"sqdecp_z_p_z", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"sqdecw_r_rs_sx", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqdecw_r_rs_x", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqdecw_z_zs", \
- &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"sqincb_r_rs_sx", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqincb_r_rs_x", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqincd_r_rs_sx", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqincd_r_rs_x", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqincd_z_zs", \
- &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"sqinch_r_rs_sx", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqinch_r_rs_x", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqinch_z_zs", \
- &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"sqincp_r_p_r_sx", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"sqincp_r_p_r_x", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"sqincp_z_p_z", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"sqincw_r_rs_sx", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqincw_r_rs_x", \
- &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"sqincw_z_zs", \
- &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"sqsub_z_zi", &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
- {"sqsub_z_zz", &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
- {"st1b_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitScatterStore_VectorPlusImm}, \
- {"st1b_z_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitScatterStore_VectorPlusImm}, \
- {"st1b_z_p_bi", &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusImm}, \
- {"st1b_z_p_br", \
- &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusScalar}, \
- {"st1b_z_p_bz_d_64_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets}, \
- {"st1b_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"st1b_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets}, \
- {"st1d_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitScatterStore_VectorPlusImm}, \
- {"st1d_z_p_bi", &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusImm}, \
- {"st1d_z_p_br", \
- &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusScalar}, \
- {"st1d_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets}, \
- {"st1d_z_p_bz_d_64_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets}, \
- {"st1d_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets}, \
- {"st1d_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"st1h_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitScatterStore_VectorPlusImm}, \
- {"st1h_z_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitScatterStore_VectorPlusImm}, \
- {"st1h_z_p_bi", &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusImm}, \
- {"st1h_z_p_br", \
- &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusScalar}, \
- {"st1h_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets}, \
- {"st1h_z_p_bz_d_64_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets}, \
- {"st1h_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets}, \
- {"st1h_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"st1h_z_p_bz_s_x32_scaled", \
- &VISITORCLASS::VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets}, \
- {"st1h_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets}, \
- {"st1w_z_p_ai_d", \
- &VISITORCLASS::VisitSVE64BitScatterStore_VectorPlusImm}, \
- {"st1w_z_p_ai_s", \
- &VISITORCLASS::VisitSVE32BitScatterStore_VectorPlusImm}, \
- {"st1w_z_p_bi", &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusImm}, \
- {"st1w_z_p_br", \
- &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusScalar}, \
- {"st1w_z_p_bz_d_64_scaled", \
- &VISITORCLASS::VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets}, \
- {"st1w_z_p_bz_d_64_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets}, \
- {"st1w_z_p_bz_d_x32_scaled", \
- &VISITORCLASS:: \
- VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets}, \
- {"st1w_z_p_bz_d_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets}, \
- {"st1w_z_p_bz_s_x32_scaled", \
- &VISITORCLASS::VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets}, \
- {"st1w_z_p_bz_s_x32_unscaled", \
- &VISITORCLASS:: \
- VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets}, \
- {"st2b_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st2b_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"st2d_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st2d_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"st2h_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st2h_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"st2w_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st2w_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"st3b_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st3b_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"st3d_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st3d_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"st3h_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st3h_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"st3w_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st3w_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"st4b_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st4b_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"st4d_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st4d_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"st4h_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st4h_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"st4w_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
- {"st4w_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
- {"stnt1b_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusImm}, \
- {"stnt1b_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar}, \
- {"stnt1d_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusImm}, \
- {"stnt1d_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar}, \
- {"stnt1h_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusImm}, \
- {"stnt1h_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar}, \
- {"stnt1w_z_p_bi_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusImm}, \
- {"stnt1w_z_p_br_contiguous", \
- &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar}, \
- {"str_p_bi", &VISITORCLASS::VisitSVEStorePredicateRegister}, \
- {"str_z_bi", &VISITORCLASS::VisitSVEStoreVectorRegister}, \
- {"subr_z_p_zz", \
+ {"abs_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"addpl_r_ri"_h, &VISITORCLASS::VisitSVEStackFrameAdjustment}, \
+ {"addvl_r_ri"_h, &VISITORCLASS::VisitSVEStackFrameAdjustment}, \
+ {"add_z_p_zz"_h, \
&VISITORCLASS::VisitSVEIntAddSubtractVectors_Predicated}, \
- {"subr_z_zi", &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
- {"sub_z_p_zz", &VISITORCLASS::VisitSVEIntAddSubtractVectors_Predicated}, \
- {"sub_z_zi", &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
- {"sub_z_zz", &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
- {"sunpkhi_z_z", &VISITORCLASS::VisitSVEUnpackVectorElements}, \
- {"sunpklo_z_z", &VISITORCLASS::VisitSVEUnpackVectorElements}, \
- {"sxtb_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"sxth_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"sxtw_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"tbl_z_zz_1", &VISITORCLASS::VisitSVETableLookup}, \
- {"trn1_p_pp", &VISITORCLASS::VisitSVEPermutePredicateElements}, \
- {"trn1_z_zz", &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
- {"trn2_p_pp", &VISITORCLASS::VisitSVEPermutePredicateElements}, \
- {"trn2_z_zz", &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
- {"uabd_z_p_zz", &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
- {"uaddv_r_p_z", &VISITORCLASS::VisitSVEIntReduction}, \
- {"ucvtf_z_p_z_h2fp16", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"ucvtf_z_p_z_w2d", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"ucvtf_z_p_z_w2fp16", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"ucvtf_z_p_z_w2s", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"ucvtf_z_p_z_x2d", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"ucvtf_z_p_z_x2fp16", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"ucvtf_z_p_z_x2s", &VISITORCLASS::VisitSVEIntConvertToFP}, \
- {"udf_only_perm_undef", &VISITORCLASS::VisitReserved}, \
- {"udivr_z_p_zz", &VISITORCLASS::VisitSVEIntDivideVectors_Predicated}, \
- {"udiv_z_p_zz", &VISITORCLASS::VisitSVEIntDivideVectors_Predicated}, \
- {"udot_z_zzz", &VISITORCLASS::VisitSVEIntMulAddUnpredicated}, \
- {"udot_z_zzzi_d", &VISITORCLASS::VisitSVEMulIndex}, \
- {"udot_z_zzzi_s", &VISITORCLASS::VisitSVEMulIndex}, \
- {"umaxv_r_p_z", &VISITORCLASS::VisitSVEIntReduction}, \
- {"umax_z_p_zz", &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
- {"umax_z_zi", &VISITORCLASS::VisitSVEIntMinMaxImm_Unpredicated}, \
- {"uminv_r_p_z", &VISITORCLASS::VisitSVEIntReduction}, \
- {"umin_z_p_zz", &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
- {"umin_z_zi", &VISITORCLASS::VisitSVEIntMinMaxImm_Unpredicated}, \
- {"umulh_z_p_zz", &VISITORCLASS::VisitSVEIntMulVectors_Predicated}, \
- {"uqadd_z_zi", &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
- {"uqadd_z_zz", &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
- {"uqdecb_r_rs_uw", \
+ {"add_z_zi"_h, &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
+ {"add_z_zz"_h, &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
+ {"adr_z_az_d_s32_scaled"_h, &VISITORCLASS::VisitSVEAddressGeneration}, \
+ {"adr_z_az_d_u32_scaled"_h, &VISITORCLASS::VisitSVEAddressGeneration}, \
+ {"adr_z_az_sd_same_scaled"_h, &VISITORCLASS::VisitSVEAddressGeneration}, \
+ {"ands_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"andv_r_p_z"_h, &VISITORCLASS::VisitSVEIntReduction}, \
+ {"and_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"and_z_p_zz"_h, &VISITORCLASS::VisitSVEBitwiseLogical_Predicated}, \
+ {"and_z_zi"_h, \
+ &VISITORCLASS::VisitSVEBitwiseLogicalWithImm_Unpredicated}, \
+ {"and_z_zz"_h, &VISITORCLASS::VisitSVEBitwiseLogicalUnpredicated}, \
+ {"asrd_z_p_zi"_h, &VISITORCLASS::VisitSVEBitwiseShiftByImm_Predicated}, \
+ {"asrr_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
+ {"asr_z_p_zi"_h, &VISITORCLASS::VisitSVEBitwiseShiftByImm_Predicated}, \
+ {"asr_z_p_zw"_h, \
+ &VISITORCLASS::VisitSVEBitwiseShiftByWideElements_Predicated}, \
+ {"asr_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
+ {"asr_z_zi"_h, &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
+ {"asr_z_zw"_h, &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
+ {"bics_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"bic_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"bic_z_p_zz"_h, &VISITORCLASS::VisitSVEBitwiseLogical_Predicated}, \
+ {"bic_z_zz"_h, &VISITORCLASS::VisitSVEBitwiseLogicalUnpredicated}, \
+ {"brkas_p_p_p_z"_h, &VISITORCLASS::VisitSVEPartitionBreakCondition}, \
+ {"brka_p_p_p"_h, &VISITORCLASS::VisitSVEPartitionBreakCondition}, \
+ {"brkbs_p_p_p_z"_h, &VISITORCLASS::VisitSVEPartitionBreakCondition}, \
+ {"brkb_p_p_p"_h, &VISITORCLASS::VisitSVEPartitionBreakCondition}, \
+ {"brkns_p_p_pp"_h, \
+ &VISITORCLASS::VisitSVEPropagateBreakToNextPartition}, \
+ {"brkn_p_p_pp"_h, &VISITORCLASS::VisitSVEPropagateBreakToNextPartition}, \
+ {"brkpas_p_p_pp"_h, &VISITORCLASS::VisitSVEPropagateBreak}, \
+ {"brkpa_p_p_pp"_h, &VISITORCLASS::VisitSVEPropagateBreak}, \
+ {"brkpbs_p_p_pp"_h, &VISITORCLASS::VisitSVEPropagateBreak}, \
+ {"brkpb_p_p_pp"_h, &VISITORCLASS::VisitSVEPropagateBreak}, \
+ {"clasta_r_p_z"_h, \
+ &VISITORCLASS::VisitSVEConditionallyExtractElementToGeneralRegister}, \
+ {"clasta_v_p_z"_h, \
+ &VISITORCLASS::VisitSVEConditionallyExtractElementToSIMDFPScalar}, \
+ {"clasta_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEConditionallyBroadcastElementToVector}, \
+ {"clastb_r_p_z"_h, \
+ &VISITORCLASS::VisitSVEConditionallyExtractElementToGeneralRegister}, \
+ {"clastb_v_p_z"_h, \
+ &VISITORCLASS::VisitSVEConditionallyExtractElementToSIMDFPScalar}, \
+ {"clastb_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEConditionallyBroadcastElementToVector}, \
+ {"cls_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"clz_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"cmpeq_p_p_zi"_h, &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
+ {"cmpeq_p_p_zw"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmpeq_p_p_zz"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmpge_p_p_zi"_h, &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
+ {"cmpge_p_p_zw"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmpge_p_p_zz"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmpgt_p_p_zi"_h, &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
+ {"cmpgt_p_p_zw"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmpgt_p_p_zz"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmphi_p_p_zi"_h, &VISITORCLASS::VisitSVEIntCompareUnsignedImm}, \
+ {"cmphi_p_p_zw"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmphi_p_p_zz"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmphs_p_p_zi"_h, &VISITORCLASS::VisitSVEIntCompareUnsignedImm}, \
+ {"cmphs_p_p_zw"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmphs_p_p_zz"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmple_p_p_zi"_h, &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
+ {"cmple_p_p_zw"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmplo_p_p_zi"_h, &VISITORCLASS::VisitSVEIntCompareUnsignedImm}, \
+ {"cmplo_p_p_zw"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmpls_p_p_zi"_h, &VISITORCLASS::VisitSVEIntCompareUnsignedImm}, \
+ {"cmpls_p_p_zw"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmplt_p_p_zi"_h, &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
+ {"cmplt_p_p_zw"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmpne_p_p_zi"_h, &VISITORCLASS::VisitSVEIntCompareSignedImm}, \
+ {"cmpne_p_p_zw"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cmpne_p_p_zz"_h, &VISITORCLASS::VisitSVEIntCompareVectors}, \
+ {"cnot_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"cntb_r_s"_h, &VISITORCLASS::VisitSVEElementCount}, \
+ {"cntd_r_s"_h, &VISITORCLASS::VisitSVEElementCount}, \
+ {"cnth_r_s"_h, &VISITORCLASS::VisitSVEElementCount}, \
+ {"cntp_r_p_p"_h, &VISITORCLASS::VisitSVEPredicateCount}, \
+ {"cntw_r_s"_h, &VISITORCLASS::VisitSVEElementCount}, \
+ {"cnt_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"compact_z_p_z"_h, &VISITORCLASS::VisitSVECompressActiveElements}, \
+ {"cpy_z_o_i"_h, &VISITORCLASS::VisitSVECopyIntImm_Predicated}, \
+ {"cpy_z_p_i"_h, &VISITORCLASS::VisitSVECopyIntImm_Predicated}, \
+ {"cpy_z_p_r"_h, \
+ &VISITORCLASS::VisitSVECopyGeneralRegisterToVector_Predicated}, \
+ {"cpy_z_p_v"_h, \
+ &VISITORCLASS::VisitSVECopySIMDFPScalarRegisterToVector_Predicated}, \
+ {"ctermeq_rr"_h, &VISITORCLASS::VisitSVEConditionallyTerminateScalars}, \
+ {"ctermne_rr"_h, &VISITORCLASS::VisitSVEConditionallyTerminateScalars}, \
+ {"decb_r_rs"_h, &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
+ {"decd_r_rs"_h, &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
+ {"decd_z_zs"_h, &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
+ {"dech_r_rs"_h, &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
+ {"dech_z_zs"_h, &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
+ {"decp_r_p_r"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"decp_z_p_z"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"decw_r_rs"_h, &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
+ {"decw_z_zs"_h, &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
+ {"dupm_z_i"_h, &VISITORCLASS::VisitSVEBroadcastBitmaskImm}, \
+ {"dup_z_i"_h, &VISITORCLASS::VisitSVEBroadcastIntImm_Unpredicated}, \
+ {"dup_z_r"_h, &VISITORCLASS::VisitSVEBroadcastGeneralRegister}, \
+ {"dup_z_zi"_h, &VISITORCLASS::VisitSVEBroadcastIndexElement}, \
+ {"eors_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"eorv_r_p_z"_h, &VISITORCLASS::VisitSVEIntReduction}, \
+ {"eor_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"eor_z_p_zz"_h, &VISITORCLASS::VisitSVEBitwiseLogical_Predicated}, \
+ {"eor_z_zi"_h, \
+ &VISITORCLASS::VisitSVEBitwiseLogicalWithImm_Unpredicated}, \
+ {"eor_z_zz"_h, &VISITORCLASS::VisitSVEBitwiseLogicalUnpredicated}, \
+ {"ext_z_zi_des"_h, &VISITORCLASS::VisitSVEPermuteVectorExtract}, \
+ {"fabd_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fabs_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"facge_p_p_zz"_h, &VISITORCLASS::VisitSVEFPCompareVectors}, \
+ {"facgt_p_p_zz"_h, &VISITORCLASS::VisitSVEFPCompareVectors}, \
+ {"fadda_v_p_z"_h, &VISITORCLASS::VisitSVEFPAccumulatingReduction}, \
+ {"faddv_v_p_z"_h, &VISITORCLASS::VisitSVEFPFastReduction}, \
+ {"fadd_z_p_zs"_h, \
+ &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
+ {"fadd_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fadd_z_zz"_h, &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
+ {"fcadd_z_p_zz"_h, &VISITORCLASS::VisitSVEFPComplexAddition}, \
+ {"fcmeq_p_p_z0"_h, &VISITORCLASS::VisitSVEFPCompareWithZero}, \
+ {"fcmeq_p_p_zz"_h, &VISITORCLASS::VisitSVEFPCompareVectors}, \
+ {"fcmge_p_p_z0"_h, &VISITORCLASS::VisitSVEFPCompareWithZero}, \
+ {"fcmge_p_p_zz"_h, &VISITORCLASS::VisitSVEFPCompareVectors}, \
+ {"fcmgt_p_p_z0"_h, &VISITORCLASS::VisitSVEFPCompareWithZero}, \
+ {"fcmgt_p_p_zz"_h, &VISITORCLASS::VisitSVEFPCompareVectors}, \
+ {"fcmla_z_p_zzz"_h, &VISITORCLASS::VisitSVEFPComplexMulAdd}, \
+ {"fcmla_z_zzzi_h"_h, &VISITORCLASS::VisitSVEFPComplexMulAddIndex}, \
+ {"fcmla_z_zzzi_s"_h, &VISITORCLASS::VisitSVEFPComplexMulAddIndex}, \
+ {"fcmle_p_p_z0"_h, &VISITORCLASS::VisitSVEFPCompareWithZero}, \
+ {"fcmlt_p_p_z0"_h, &VISITORCLASS::VisitSVEFPCompareWithZero}, \
+ {"fcmne_p_p_z0"_h, &VISITORCLASS::VisitSVEFPCompareWithZero}, \
+ {"fcmne_p_p_zz"_h, &VISITORCLASS::VisitSVEFPCompareVectors}, \
+ {"fcmuo_p_p_zz"_h, &VISITORCLASS::VisitSVEFPCompareVectors}, \
+ {"fcpy_z_p_i"_h, &VISITORCLASS::VisitSVECopyFPImm_Predicated}, \
+ {"fcvtzs_z_p_z_d2w"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzs_z_p_z_d2x"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzs_z_p_z_fp162h"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzs_z_p_z_fp162w"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzs_z_p_z_fp162x"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzs_z_p_z_s2w"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzs_z_p_z_s2x"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzu_z_p_z_d2w"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzu_z_p_z_d2x"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzu_z_p_z_fp162h"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzu_z_p_z_fp162w"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzu_z_p_z_fp162x"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzu_z_p_z_s2w"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvtzu_z_p_z_s2x"_h, &VISITORCLASS::VisitSVEFPConvertToInt}, \
+ {"fcvt_z_p_z_d2h"_h, &VISITORCLASS::VisitSVEFPConvertPrecision}, \
+ {"fcvt_z_p_z_d2s"_h, &VISITORCLASS::VisitSVEFPConvertPrecision}, \
+ {"fcvt_z_p_z_h2d"_h, &VISITORCLASS::VisitSVEFPConvertPrecision}, \
+ {"fcvt_z_p_z_h2s"_h, &VISITORCLASS::VisitSVEFPConvertPrecision}, \
+ {"fcvt_z_p_z_s2d"_h, &VISITORCLASS::VisitSVEFPConvertPrecision}, \
+ {"fcvt_z_p_z_s2h"_h, &VISITORCLASS::VisitSVEFPConvertPrecision}, \
+ {"fdivr_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fdiv_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fdup_z_i"_h, &VISITORCLASS::VisitSVEBroadcastFPImm_Unpredicated}, \
+ {"fexpa_z_z"_h, &VISITORCLASS::VisitSVEFPExponentialAccelerator}, \
+ {"fmad_z_p_zzz"_h, &VISITORCLASS::VisitSVEFPMulAdd}, \
+ {"fmaxnmv_v_p_z"_h, &VISITORCLASS::VisitSVEFPFastReduction}, \
+ {"fmaxnm_z_p_zs"_h, \
+ &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
+ {"fmaxnm_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fmaxv_v_p_z"_h, &VISITORCLASS::VisitSVEFPFastReduction}, \
+ {"fmax_z_p_zs"_h, \
+ &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
+ {"fmax_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fminnmv_v_p_z"_h, &VISITORCLASS::VisitSVEFPFastReduction}, \
+ {"fminnm_z_p_zs"_h, \
+ &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
+ {"fminnm_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fminv_v_p_z"_h, &VISITORCLASS::VisitSVEFPFastReduction}, \
+ {"fmin_z_p_zs"_h, \
+ &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
+ {"fmin_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fmla_z_p_zzz"_h, &VISITORCLASS::VisitSVEFPMulAdd}, \
+ {"fmla_z_zzzi_d"_h, &VISITORCLASS::VisitSVEFPMulAddIndex}, \
+ {"fmla_z_zzzi_h"_h, &VISITORCLASS::VisitSVEFPMulAddIndex}, \
+ {"fmla_z_zzzi_s"_h, &VISITORCLASS::VisitSVEFPMulAddIndex}, \
+ {"fmls_z_p_zzz"_h, &VISITORCLASS::VisitSVEFPMulAdd}, \
+ {"fmls_z_zzzi_d"_h, &VISITORCLASS::VisitSVEFPMulAddIndex}, \
+ {"fmls_z_zzzi_h"_h, &VISITORCLASS::VisitSVEFPMulAddIndex}, \
+ {"fmls_z_zzzi_s"_h, &VISITORCLASS::VisitSVEFPMulAddIndex}, \
+ {"fmsb_z_p_zzz"_h, &VISITORCLASS::VisitSVEFPMulAdd}, \
+ {"fmulx_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fmul_z_p_zs"_h, \
+ &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
+ {"fmul_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fmul_z_zz"_h, &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
+ {"fmul_z_zzi_d"_h, &VISITORCLASS::VisitSVEFPMulIndex}, \
+ {"fmul_z_zzi_h"_h, &VISITORCLASS::VisitSVEFPMulIndex}, \
+ {"fmul_z_zzi_s"_h, &VISITORCLASS::VisitSVEFPMulIndex}, \
+ {"fneg_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"fnmad_z_p_zzz"_h, &VISITORCLASS::VisitSVEFPMulAdd}, \
+ {"fnmla_z_p_zzz"_h, &VISITORCLASS::VisitSVEFPMulAdd}, \
+ {"fnmls_z_p_zzz"_h, &VISITORCLASS::VisitSVEFPMulAdd}, \
+ {"fnmsb_z_p_zzz"_h, &VISITORCLASS::VisitSVEFPMulAdd}, \
+ {"frecpe_z_z"_h, &VISITORCLASS::VisitSVEFPUnaryOpUnpredicated}, \
+ {"frecps_z_zz"_h, &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
+ {"frecpx_z_p_z"_h, &VISITORCLASS::VisitSVEFPUnaryOp}, \
+ {"frinta_z_p_z"_h, &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
+ {"frinti_z_p_z"_h, &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
+ {"frintm_z_p_z"_h, &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
+ {"frintn_z_p_z"_h, &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
+ {"frintp_z_p_z"_h, &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
+ {"frintx_z_p_z"_h, &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
+ {"frintz_z_p_z"_h, &VISITORCLASS::VisitSVEFPRoundToIntegralValue}, \
+ {"frsqrte_z_z"_h, &VISITORCLASS::VisitSVEFPUnaryOpUnpredicated}, \
+ {"frsqrts_z_zz"_h, &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
+ {"fscale_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fsqrt_z_p_z"_h, &VISITORCLASS::VisitSVEFPUnaryOp}, \
+ {"fsubr_z_p_zs"_h, \
+ &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
+ {"fsubr_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fsub_z_p_zs"_h, \
+ &VISITORCLASS::VisitSVEFPArithmeticWithImm_Predicated}, \
+ {"fsub_z_p_zz"_h, &VISITORCLASS::VisitSVEFPArithmetic_Predicated}, \
+ {"fsub_z_zz"_h, &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
+ {"ftmad_z_zzi"_h, &VISITORCLASS::VisitSVEFPTrigMulAddCoefficient}, \
+ {"ftsmul_z_zz"_h, &VISITORCLASS::VisitSVEFPArithmeticUnpredicated}, \
+ {"ftssel_z_zz"_h, &VISITORCLASS::VisitSVEFPTrigSelectCoefficient}, \
+ {"incb_r_rs"_h, &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
+ {"incd_r_rs"_h, &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
+ {"incd_z_zs"_h, &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
+ {"inch_r_rs"_h, &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
+ {"inch_z_zs"_h, &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
+ {"incp_r_p_r"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"incp_z_p_z"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"incw_r_rs"_h, &VISITORCLASS::VisitSVEIncDecRegisterByElementCount}, \
+ {"incw_z_zs"_h, &VISITORCLASS::VisitSVEIncDecVectorByElementCount}, \
+ {"index_z_ii"_h, &VISITORCLASS::VisitSVEIndexGeneration}, \
+ {"index_z_ir"_h, &VISITORCLASS::VisitSVEIndexGeneration}, \
+ {"index_z_ri"_h, &VISITORCLASS::VisitSVEIndexGeneration}, \
+ {"index_z_rr"_h, &VISITORCLASS::VisitSVEIndexGeneration}, \
+ {"insr_z_r"_h, &VISITORCLASS::VisitSVEInsertGeneralRegister}, \
+ {"insr_z_v"_h, &VISITORCLASS::VisitSVEInsertSIMDFPScalarRegister}, \
+ {"lasta_r_p_z"_h, \
+ &VISITORCLASS::VisitSVEExtractElementToGeneralRegister}, \
+ {"lasta_v_p_z"_h, \
+ &VISITORCLASS::VisitSVEExtractElementToSIMDFPScalarRegister}, \
+ {"lastb_r_p_z"_h, \
+ &VISITORCLASS::VisitSVEExtractElementToGeneralRegister}, \
+ {"lastb_v_p_z"_h, \
+ &VISITORCLASS::VisitSVEExtractElementToSIMDFPScalarRegister}, \
+ {"ld1b_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ld1b_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
+ {"ld1b_z_p_bi_u16"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1b_z_p_bi_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1b_z_p_bi_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1b_z_p_bi_u8"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1b_z_p_br_u16"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1b_z_p_br_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1b_z_p_br_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1b_z_p_br_u8"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1b_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ld1b_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ld1b_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
+ {"ld1d_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ld1d_z_p_bi_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1d_z_p_br_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1d_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
+ {"ld1d_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ld1d_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
+ {"ld1d_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ld1h_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ld1h_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
+ {"ld1h_z_p_bi_u16"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1h_z_p_bi_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1h_z_p_bi_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1h_z_p_br_u16"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1h_z_p_br_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1h_z_p_br_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1h_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
+ {"ld1h_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ld1h_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
+ {"ld1h_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ld1h_z_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets}, \
+ {"ld1h_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
+ {"ld1rb_z_p_bi_u16"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rb_z_p_bi_u32"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rb_z_p_bi_u64"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rb_z_p_bi_u8"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rd_z_p_bi_u64"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rh_z_p_bi_u16"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rh_z_p_bi_u32"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rh_z_p_bi_u64"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rqb_z_p_bi_u8"_h, \
+ &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm}, \
+ {"ld1rqb_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar}, \
+ {"ld1rqd_z_p_bi_u64"_h, \
+ &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm}, \
+ {"ld1rqd_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar}, \
+ {"ld1rqh_z_p_bi_u16"_h, \
+ &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm}, \
+ {"ld1rqh_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar}, \
+ {"ld1rqw_z_p_bi_u32"_h, \
+ &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm}, \
+ {"ld1rqw_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar}, \
+ {"ld1rsb_z_p_bi_s16"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rsb_z_p_bi_s32"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rsb_z_p_bi_s64"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rsh_z_p_bi_s32"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rsh_z_p_bi_s64"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rsw_z_p_bi_s64"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rw_z_p_bi_u32"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1rw_z_p_bi_u64"_h, &VISITORCLASS::VisitSVELoadAndBroadcastElement}, \
+ {"ld1sb_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ld1sb_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
+ {"ld1sb_z_p_bi_s16"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1sb_z_p_bi_s32"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1sb_z_p_bi_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1sb_z_p_br_s16"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1sb_z_p_br_s32"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1sb_z_p_br_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1sb_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ld1sb_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ld1sb_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
+ {"ld1sh_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ld1sh_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
+ {"ld1sh_z_p_bi_s32"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1sh_z_p_bi_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1sh_z_p_br_s32"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1sh_z_p_br_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1sh_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
+ {"ld1sh_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ld1sh_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
+ {"ld1sh_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ld1sh_z_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets}, \
+ {"ld1sh_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
+ {"ld1sw_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ld1sw_z_p_bi_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1sw_z_p_br_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1sw_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
+ {"ld1sw_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ld1sw_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
+ {"ld1sw_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ld1w_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ld1w_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
+ {"ld1w_z_p_bi_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1w_z_p_bi_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusImm}, \
+ {"ld1w_z_p_br_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1w_z_p_br_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousLoad_ScalarPlusScalar}, \
+ {"ld1w_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
+ {"ld1w_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ld1w_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
+ {"ld1w_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ld1w_z_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets}, \
+ {"ld1w_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
+ {"ld2b_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld2b_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ld2d_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld2d_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ld2h_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld2h_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ld2w_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld2w_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ld3b_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld3b_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ld3d_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld3d_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ld3h_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld3h_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ld3w_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld3w_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ld4b_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld4b_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ld4d_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld4d_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ld4h_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld4h_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ld4w_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusImm}, \
+ {"ld4w_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVELoadMultipleStructures_ScalarPlusScalar}, \
+ {"ldff1b_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ldff1b_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
+ {"ldff1b_z_p_br_u16"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1b_z_p_br_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1b_z_p_br_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1b_z_p_br_u8"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1b_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ldff1b_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ldff1b_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
+ {"ldff1d_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ldff1d_z_p_br_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1d_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
+ {"ldff1d_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ldff1d_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
+ {"ldff1d_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ldff1h_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ldff1h_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
+ {"ldff1h_z_p_br_u16"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1h_z_p_br_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1h_z_p_br_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1h_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
+ {"ldff1h_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ldff1h_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
+ {"ldff1h_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ldff1h_z_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets}, \
+ {"ldff1h_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
+ {"ldff1sb_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ldff1sb_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
+ {"ldff1sb_z_p_br_s16"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1sb_z_p_br_s32"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1sb_z_p_br_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1sb_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ldff1sb_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ldff1sb_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
+ {"ldff1sh_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ldff1sh_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
+ {"ldff1sh_z_p_br_s32"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1sh_z_p_br_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1sh_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
+ {"ldff1sh_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ldff1sh_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
+ {"ldff1sh_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ldff1sh_z_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets}, \
+ {"ldff1sh_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
+ {"ldff1sw_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ldff1sw_z_p_br_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1sw_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
+ {"ldff1sw_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ldff1sw_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
+ {"ldff1sw_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ldff1w_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_VectorPlusImm}, \
+ {"ldff1w_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_VectorPlusImm}, \
+ {"ldff1w_z_p_br_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1w_z_p_br_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar}, \
+ {"ldff1w_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets}, \
+ {"ldff1w_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets}, \
+ {"ldff1w_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets}, \
+ {"ldff1w_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"ldff1w_z_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets}, \
+ {"ldff1w_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets}, \
+ {"ldnf1b_z_p_bi_u16"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1b_z_p_bi_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1b_z_p_bi_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1b_z_p_bi_u8"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1d_z_p_bi_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1h_z_p_bi_u16"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1h_z_p_bi_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1h_z_p_bi_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1sb_z_p_bi_s16"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1sb_z_p_bi_s32"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1sb_z_p_bi_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1sh_z_p_bi_s32"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1sh_z_p_bi_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1sw_z_p_bi_s64"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1w_z_p_bi_u32"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnf1w_z_p_bi_u64"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonFaultLoad_ScalarPlusImm}, \
+ {"ldnt1b_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm}, \
+ {"ldnt1b_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar}, \
+ {"ldnt1d_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm}, \
+ {"ldnt1d_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar}, \
+ {"ldnt1h_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm}, \
+ {"ldnt1h_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar}, \
+ {"ldnt1w_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm}, \
+ {"ldnt1w_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar}, \
+ {"ldr_p_bi"_h, &VISITORCLASS::VisitSVELoadPredicateRegister}, \
+ {"ldr_z_bi"_h, &VISITORCLASS::VisitSVELoadVectorRegister}, \
+ {"lslr_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
+ {"lsl_z_p_zi"_h, &VISITORCLASS::VisitSVEBitwiseShiftByImm_Predicated}, \
+ {"lsl_z_p_zw"_h, \
+ &VISITORCLASS::VisitSVEBitwiseShiftByWideElements_Predicated}, \
+ {"lsl_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
+ {"lsl_z_zi"_h, &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
+ {"lsl_z_zw"_h, &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
+ {"lsrr_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
+ {"lsr_z_p_zi"_h, &VISITORCLASS::VisitSVEBitwiseShiftByImm_Predicated}, \
+ {"lsr_z_p_zw"_h, \
+ &VISITORCLASS::VisitSVEBitwiseShiftByWideElements_Predicated}, \
+ {"lsr_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEBitwiseShiftByVector_Predicated}, \
+ {"lsr_z_zi"_h, &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
+ {"lsr_z_zw"_h, &VISITORCLASS::VisitSVEBitwiseShiftUnpredicated}, \
+ {"mad_z_p_zzz"_h, &VISITORCLASS::VisitSVEIntMulAddPredicated}, \
+ {"mla_z_p_zzz"_h, &VISITORCLASS::VisitSVEIntMulAddPredicated}, \
+ {"mls_z_p_zzz"_h, &VISITORCLASS::VisitSVEIntMulAddPredicated}, \
+ {"movprfx_z_p_z"_h, &VISITORCLASS::VisitSVEMovprfx}, \
+ {"movprfx_z_z"_h, \
+ &VISITORCLASS::VisitSVEConstructivePrefix_Unpredicated}, \
+ {"msb_z_p_zzz"_h, &VISITORCLASS::VisitSVEIntMulAddPredicated}, \
+ {"mul_z_p_zz"_h, &VISITORCLASS::VisitSVEIntMulVectors_Predicated}, \
+ {"mul_z_zi"_h, &VISITORCLASS::VisitSVEIntMulImm_Unpredicated}, \
+ {"nands_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"nand_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"neg_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"nors_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"nor_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"not_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"orns_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"orn_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"orrs_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"orr_p_p_pp_z"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"orr_z_p_zz"_h, &VISITORCLASS::VisitSVEBitwiseLogical_Predicated}, \
+ {"orr_z_zi"_h, \
+ &VISITORCLASS::VisitSVEBitwiseLogicalWithImm_Unpredicated}, \
+ {"orr_z_zz"_h, &VISITORCLASS::VisitSVEBitwiseLogicalUnpredicated}, \
+ {"orv_r_p_z"_h, &VISITORCLASS::VisitSVEIntReduction}, \
+ {"pfalse_p"_h, &VISITORCLASS::VisitSVEPredicateZero}, \
+ {"pfirst_p_p_p"_h, &VISITORCLASS::VisitSVEPredicateFirstActive}, \
+ {"pnext_p_p_p"_h, &VISITORCLASS::VisitSVEPredicateNextActive}, \
+ {"prfb_i_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherPrefetch_VectorPlusImm}, \
+ {"prfb_i_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherPrefetch_VectorPlusImm}, \
+ {"prfb_i_p_bi_s"_h, \
+ &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusImm}, \
+ {"prfb_i_p_br_s"_h, \
+ &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusScalar}, \
+ {"prfb_i_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets}, \
+ {"prfb_i_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets}, \
+ {"prfb_i_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets}, \
+ {"prfd_i_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherPrefetch_VectorPlusImm}, \
+ {"prfd_i_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherPrefetch_VectorPlusImm}, \
+ {"prfd_i_p_bi_s"_h, \
+ &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusImm}, \
+ {"prfd_i_p_br_s"_h, \
+ &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusScalar}, \
+ {"prfd_i_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets}, \
+ {"prfd_i_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets}, \
+ {"prfd_i_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets}, \
+ {"prfh_i_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherPrefetch_VectorPlusImm}, \
+ {"prfh_i_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherPrefetch_VectorPlusImm}, \
+ {"prfh_i_p_bi_s"_h, \
+ &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusImm}, \
+ {"prfh_i_p_br_s"_h, \
+ &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusScalar}, \
+ {"prfh_i_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets}, \
+ {"prfh_i_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets}, \
+ {"prfh_i_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets}, \
+ {"prfw_i_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitGatherPrefetch_VectorPlusImm}, \
+ {"prfw_i_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitGatherPrefetch_VectorPlusImm}, \
+ {"prfw_i_p_bi_s"_h, \
+ &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusImm}, \
+ {"prfw_i_p_br_s"_h, \
+ &VISITORCLASS::VisitSVEContiguousPrefetch_ScalarPlusScalar}, \
+ {"prfw_i_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets}, \
+ {"prfw_i_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets}, \
+ {"prfw_i_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets}, \
+ {"ptest_p_p"_h, &VISITORCLASS::VisitSVEPredicateTest}, \
+ {"ptrues_p_s"_h, &VISITORCLASS::VisitSVEPredicateInitialize}, \
+ {"ptrue_p_s"_h, &VISITORCLASS::VisitSVEPredicateInitialize}, \
+ {"punpkhi_p_p"_h, &VISITORCLASS::VisitSVEUnpackPredicateElements}, \
+ {"punpklo_p_p"_h, &VISITORCLASS::VisitSVEUnpackPredicateElements}, \
+ {"rbit_z_p_z"_h, &VISITORCLASS::VisitSVEReverseWithinElements}, \
+ {"rdffrs_p_p_f"_h, \
+ &VISITORCLASS::VisitSVEPredicateReadFromFFR_Predicated}, \
+ {"rdffr_p_f"_h, \
+ &VISITORCLASS::VisitSVEPredicateReadFromFFR_Unpredicated}, \
+ {"rdffr_p_p_f"_h, \
+ &VISITORCLASS::VisitSVEPredicateReadFromFFR_Predicated}, \
+ {"rdvl_r_i"_h, &VISITORCLASS::VisitSVEStackFrameSize}, \
+ {"revb_z_z"_h, &VISITORCLASS::VisitSVEReverseWithinElements}, \
+ {"revh_z_z"_h, &VISITORCLASS::VisitSVEReverseWithinElements}, \
+ {"revw_z_z"_h, &VISITORCLASS::VisitSVEReverseWithinElements}, \
+ {"rev_p_p"_h, &VISITORCLASS::VisitSVEReversePredicateElements}, \
+ {"rev_z_z"_h, &VISITORCLASS::VisitSVEReverseVectorElements}, \
+ {"sabd_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
+ {"saddv_r_p_z"_h, &VISITORCLASS::VisitSVEIntReduction}, \
+ {"scvtf_z_p_z_h2fp16"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"scvtf_z_p_z_w2d"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"scvtf_z_p_z_w2fp16"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"scvtf_z_p_z_w2s"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"scvtf_z_p_z_x2d"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"scvtf_z_p_z_x2fp16"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"scvtf_z_p_z_x2s"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"sdivr_z_p_zz"_h, &VISITORCLASS::VisitSVEIntDivideVectors_Predicated}, \
+ {"sdiv_z_p_zz"_h, &VISITORCLASS::VisitSVEIntDivideVectors_Predicated}, \
+ {"sdot_z_zzz"_h, &VISITORCLASS::VisitSVEIntMulAddUnpredicated}, \
+ {"sdot_z_zzzi_d"_h, &VISITORCLASS::VisitSVEMulIndex}, \
+ {"sdot_z_zzzi_s"_h, &VISITORCLASS::VisitSVEMulIndex}, \
+ {"sel_p_p_pp"_h, &VISITORCLASS::VisitSVEPredicateLogical}, \
+ {"sel_z_p_zz"_h, &VISITORCLASS::VisitSVEVectorSelect}, \
+ {"setffr_f"_h, &VISITORCLASS::VisitSVEFFRInitialise}, \
+ {"smaxv_r_p_z"_h, &VISITORCLASS::VisitSVEIntReduction}, \
+ {"smax_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
+ {"smax_z_zi"_h, &VISITORCLASS::VisitSVEIntMinMaxImm_Unpredicated}, \
+ {"sminv_r_p_z"_h, &VISITORCLASS::VisitSVEIntReduction}, \
+ {"smin_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
+ {"smin_z_zi"_h, &VISITORCLASS::VisitSVEIntMinMaxImm_Unpredicated}, \
+ {"smulh_z_p_zz"_h, &VISITORCLASS::VisitSVEIntMulVectors_Predicated}, \
+ {"splice_z_p_zz_des"_h, &VISITORCLASS::VisitSVEVectorSplice}, \
+ {"sqadd_z_zi"_h, &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
+ {"sqadd_z_zz"_h, &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
+ {"sqdecb_r_rs_sx"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqdecb_r_rs_x", \
+ {"sqdecb_r_rs_x"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqdecd_r_rs_uw", \
+ {"sqdecd_r_rs_sx"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqdecd_r_rs_x", \
+ {"sqdecd_r_rs_x"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqdecd_z_zs", \
+ {"sqdecd_z_zs"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"uqdech_r_rs_uw", \
+ {"sqdech_r_rs_sx"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqdech_r_rs_x", \
+ {"sqdech_r_rs_x"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqdech_z_zs", \
+ {"sqdech_z_zs"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"uqdecp_r_p_r_uw", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"uqdecp_r_p_r_x", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"uqdecp_z_p_z", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"uqdecw_r_rs_uw", \
+ {"sqdecp_r_p_r_sx"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"sqdecp_r_p_r_x"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"sqdecp_z_p_z"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"sqdecw_r_rs_sx"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqdecw_r_rs_x", \
+ {"sqdecw_r_rs_x"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqdecw_z_zs", \
+ {"sqdecw_z_zs"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"uqincb_r_rs_uw", \
+ {"sqincb_r_rs_sx"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqincb_r_rs_x", \
+ {"sqincb_r_rs_x"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqincd_r_rs_uw", \
+ {"sqincd_r_rs_sx"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqincd_r_rs_x", \
+ {"sqincd_r_rs_x"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqincd_z_zs", \
+ {"sqincd_z_zs"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"uqinch_r_rs_uw", \
+ {"sqinch_r_rs_sx"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqinch_r_rs_x", \
+ {"sqinch_r_rs_x"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqinch_z_zs", \
+ {"sqinch_z_zs"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"uqincp_r_p_r_uw", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"uqincp_r_p_r_x", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"uqincp_z_p_z", &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
- {"uqincw_r_rs_uw", \
+ {"sqincp_r_p_r_sx"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"sqincp_r_p_r_x"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"sqincp_z_p_z"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"sqincw_r_rs_sx"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqincw_r_rs_x", \
+ {"sqincw_r_rs_x"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
- {"uqincw_z_zs", \
+ {"sqincw_z_zs"_h, \
&VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
- {"uqsub_z_zi", &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
- {"uqsub_z_zz", &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
- {"uunpkhi_z_z", &VISITORCLASS::VisitSVEUnpackVectorElements}, \
- {"uunpklo_z_z", &VISITORCLASS::VisitSVEUnpackVectorElements}, \
- {"uxtb_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"uxth_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"uxtw_z_p_z", &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
- {"uzp1_p_pp", &VISITORCLASS::VisitSVEPermutePredicateElements}, \
- {"uzp1_z_zz", &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
- {"uzp2_p_pp", &VISITORCLASS::VisitSVEPermutePredicateElements}, \
- {"uzp2_z_zz", &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
- {"whilele_p_p_rr", \
+ {"sqsub_z_zi"_h, &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
+ {"sqsub_z_zz"_h, &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
+ {"st1b_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitScatterStore_VectorPlusImm}, \
+ {"st1b_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitScatterStore_VectorPlusImm}, \
+ {"st1b_z_p_bi"_h, &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusImm}, \
+ {"st1b_z_p_br"_h, \
+ &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusScalar}, \
+ {"st1b_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets}, \
+ {"st1b_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"st1b_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets}, \
+ {"st1d_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitScatterStore_VectorPlusImm}, \
+ {"st1d_z_p_bi"_h, &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusImm}, \
+ {"st1d_z_p_br"_h, \
+ &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusScalar}, \
+ {"st1d_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets}, \
+ {"st1d_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets}, \
+ {"st1d_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets}, \
+ {"st1d_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"st1h_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitScatterStore_VectorPlusImm}, \
+ {"st1h_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitScatterStore_VectorPlusImm}, \
+ {"st1h_z_p_bi"_h, &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusImm}, \
+ {"st1h_z_p_br"_h, \
+ &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusScalar}, \
+ {"st1h_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets}, \
+ {"st1h_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets}, \
+ {"st1h_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets}, \
+ {"st1h_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"st1h_z_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS::VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets}, \
+ {"st1h_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets}, \
+ {"st1w_z_p_ai_d"_h, \
+ &VISITORCLASS::VisitSVE64BitScatterStore_VectorPlusImm}, \
+ {"st1w_z_p_ai_s"_h, \
+ &VISITORCLASS::VisitSVE32BitScatterStore_VectorPlusImm}, \
+ {"st1w_z_p_bi"_h, &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusImm}, \
+ {"st1w_z_p_br"_h, \
+ &VISITORCLASS::VisitSVEContiguousStore_ScalarPlusScalar}, \
+ {"st1w_z_p_bz_d_64_scaled"_h, \
+ &VISITORCLASS::VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets}, \
+ {"st1w_z_p_bz_d_64_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets}, \
+ {"st1w_z_p_bz_d_x32_scaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets}, \
+ {"st1w_z_p_bz_d_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets}, \
+ {"st1w_z_p_bz_s_x32_scaled"_h, \
+ &VISITORCLASS::VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets}, \
+ {"st1w_z_p_bz_s_x32_unscaled"_h, \
+ &VISITORCLASS:: \
+ VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets}, \
+ {"st2b_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st2b_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"st2d_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st2d_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"st2h_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st2h_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"st2w_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st2w_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"st3b_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st3b_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"st3d_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st3d_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"st3h_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st3h_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"st3w_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st3w_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"st4b_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st4b_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"st4d_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st4d_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"st4h_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st4h_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"st4w_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusImm}, \
+ {"st4w_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEStoreMultipleStructures_ScalarPlusScalar}, \
+ {"stnt1b_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusImm}, \
+ {"stnt1b_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar}, \
+ {"stnt1d_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusImm}, \
+ {"stnt1d_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar}, \
+ {"stnt1h_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusImm}, \
+ {"stnt1h_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar}, \
+ {"stnt1w_z_p_bi_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusImm}, \
+ {"stnt1w_z_p_br_contiguous"_h, \
+ &VISITORCLASS::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar}, \
+ {"str_p_bi"_h, &VISITORCLASS::VisitSVEStorePredicateRegister}, \
+ {"str_z_bi"_h, &VISITORCLASS::VisitSVEStoreVectorRegister}, \
+ {"subr_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEIntAddSubtractVectors_Predicated}, \
+ {"subr_z_zi"_h, &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
+ {"sub_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEIntAddSubtractVectors_Predicated}, \
+ {"sub_z_zi"_h, &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
+ {"sub_z_zz"_h, &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
+ {"sunpkhi_z_z"_h, &VISITORCLASS::VisitSVEUnpackVectorElements}, \
+ {"sunpklo_z_z"_h, &VISITORCLASS::VisitSVEUnpackVectorElements}, \
+ {"sxtb_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"sxth_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"sxtw_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"tbl_z_zz_1"_h, &VISITORCLASS::VisitSVETableLookup}, \
+ {"trn1_p_pp"_h, &VISITORCLASS::VisitSVEPermutePredicateElements}, \
+ {"trn1_z_zz"_h, &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
+ {"trn2_p_pp"_h, &VISITORCLASS::VisitSVEPermutePredicateElements}, \
+ {"trn2_z_zz"_h, &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
+ {"uabd_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
+ {"uaddv_r_p_z"_h, &VISITORCLASS::VisitSVEIntReduction}, \
+ {"ucvtf_z_p_z_h2fp16"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"ucvtf_z_p_z_w2d"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"ucvtf_z_p_z_w2fp16"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"ucvtf_z_p_z_w2s"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"ucvtf_z_p_z_x2d"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"ucvtf_z_p_z_x2fp16"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"ucvtf_z_p_z_x2s"_h, &VISITORCLASS::VisitSVEIntConvertToFP}, \
+ {"udf_only_perm_undef"_h, &VISITORCLASS::VisitReserved}, \
+ {"udivr_z_p_zz"_h, &VISITORCLASS::VisitSVEIntDivideVectors_Predicated}, \
+ {"udiv_z_p_zz"_h, &VISITORCLASS::VisitSVEIntDivideVectors_Predicated}, \
+ {"udot_z_zzz"_h, &VISITORCLASS::VisitSVEIntMulAddUnpredicated}, \
+ {"udot_z_zzzi_d"_h, &VISITORCLASS::VisitSVEMulIndex}, \
+ {"udot_z_zzzi_s"_h, &VISITORCLASS::VisitSVEMulIndex}, \
+ {"umaxv_r_p_z"_h, &VISITORCLASS::VisitSVEIntReduction}, \
+ {"umax_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
+ {"umax_z_zi"_h, &VISITORCLASS::VisitSVEIntMinMaxImm_Unpredicated}, \
+ {"uminv_r_p_z"_h, &VISITORCLASS::VisitSVEIntReduction}, \
+ {"umin_z_p_zz"_h, \
+ &VISITORCLASS::VisitSVEIntMinMaxDifference_Predicated}, \
+ {"umin_z_zi"_h, &VISITORCLASS::VisitSVEIntMinMaxImm_Unpredicated}, \
+ {"umulh_z_p_zz"_h, &VISITORCLASS::VisitSVEIntMulVectors_Predicated}, \
+ {"uqadd_z_zi"_h, &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
+ {"uqadd_z_zz"_h, &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
+ {"uqdecb_r_rs_uw"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqdecb_r_rs_x"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqdecd_r_rs_uw"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqdecd_r_rs_x"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqdecd_z_zs"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
+ {"uqdech_r_rs_uw"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqdech_r_rs_x"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqdech_z_zs"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
+ {"uqdecp_r_p_r_uw"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"uqdecp_r_p_r_x"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"uqdecp_z_p_z"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"uqdecw_r_rs_uw"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqdecw_r_rs_x"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqdecw_z_zs"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
+ {"uqincb_r_rs_uw"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqincb_r_rs_x"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqincd_r_rs_uw"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqincd_r_rs_x"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqincd_z_zs"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
+ {"uqinch_r_rs_uw"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqinch_r_rs_x"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqinch_z_zs"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
+ {"uqincp_r_p_r_uw"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"uqincp_r_p_r_x"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"uqincp_z_p_z"_h, &VISITORCLASS::VisitSVEIncDecByPredicateCount}, \
+ {"uqincw_r_rs_uw"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqincw_r_rs_x"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecRegisterByElementCount}, \
+ {"uqincw_z_zs"_h, \
+ &VISITORCLASS::VisitSVESaturatingIncDecVectorByElementCount}, \
+ {"uqsub_z_zi"_h, &VISITORCLASS::VisitSVEIntAddSubtractImm_Unpredicated}, \
+ {"uqsub_z_zz"_h, &VISITORCLASS::VisitSVEIntArithmeticUnpredicated}, \
+ {"uunpkhi_z_z"_h, &VISITORCLASS::VisitSVEUnpackVectorElements}, \
+ {"uunpklo_z_z"_h, &VISITORCLASS::VisitSVEUnpackVectorElements}, \
+ {"uxtb_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"uxth_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"uxtw_z_p_z"_h, &VISITORCLASS::VisitSVEIntUnaryArithmeticPredicated}, \
+ {"uzp1_p_pp"_h, &VISITORCLASS::VisitSVEPermutePredicateElements}, \
+ {"uzp1_z_zz"_h, &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
+ {"uzp2_p_pp"_h, &VISITORCLASS::VisitSVEPermutePredicateElements}, \
+ {"uzp2_z_zz"_h, &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
+ {"whilele_p_p_rr"_h, \
&VISITORCLASS::VisitSVEIntCompareScalarCountAndLimit}, \
- {"whilelo_p_p_rr", \
+ {"whilelo_p_p_rr"_h, \
&VISITORCLASS::VisitSVEIntCompareScalarCountAndLimit}, \
- {"whilels_p_p_rr", \
+ {"whilels_p_p_rr"_h, \
&VISITORCLASS::VisitSVEIntCompareScalarCountAndLimit}, \
- {"whilelt_p_p_rr", \
+ {"whilelt_p_p_rr"_h, \
&VISITORCLASS::VisitSVEIntCompareScalarCountAndLimit}, \
- {"wrffr_f_p", &VISITORCLASS::VisitSVEFFRWriteFromPredicate}, \
- {"zip1_p_pp", &VISITORCLASS::VisitSVEPermutePredicateElements}, \
- {"zip1_z_zz", &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
- {"zip2_p_pp", &VISITORCLASS::VisitSVEPermutePredicateElements}, \
- {"zip2_z_zz", &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
- {"adds_32s_addsub_ext", &VISITORCLASS::VisitAddSubExtended}, \
- {"adds_64s_addsub_ext", &VISITORCLASS::VisitAddSubExtended}, \
- {"add_32_addsub_ext", &VISITORCLASS::VisitAddSubExtended}, \
- {"add_64_addsub_ext", &VISITORCLASS::VisitAddSubExtended}, \
- {"subs_32s_addsub_ext", &VISITORCLASS::VisitAddSubExtended}, \
- {"subs_64s_addsub_ext", &VISITORCLASS::VisitAddSubExtended}, \
- {"sub_32_addsub_ext", &VISITORCLASS::VisitAddSubExtended}, \
- {"sub_64_addsub_ext", &VISITORCLASS::VisitAddSubExtended}, \
- {"adds_32s_addsub_imm", &VISITORCLASS::VisitAddSubImmediate}, \
- {"adds_64s_addsub_imm", &VISITORCLASS::VisitAddSubImmediate}, \
- {"add_32_addsub_imm", &VISITORCLASS::VisitAddSubImmediate}, \
- {"add_64_addsub_imm", &VISITORCLASS::VisitAddSubImmediate}, \
- {"subs_32s_addsub_imm", &VISITORCLASS::VisitAddSubImmediate}, \
- {"subs_64s_addsub_imm", &VISITORCLASS::VisitAddSubImmediate}, \
- {"sub_32_addsub_imm", &VISITORCLASS::VisitAddSubImmediate}, \
- {"sub_64_addsub_imm", &VISITORCLASS::VisitAddSubImmediate}, \
- {"adds_32_addsub_shift", &VISITORCLASS::VisitAddSubShifted}, \
- {"adds_64_addsub_shift", &VISITORCLASS::VisitAddSubShifted}, \
- {"add_32_addsub_shift", &VISITORCLASS::VisitAddSubShifted}, \
- {"add_64_addsub_shift", &VISITORCLASS::VisitAddSubShifted}, \
- {"subs_32_addsub_shift", &VISITORCLASS::VisitAddSubShifted}, \
- {"subs_64_addsub_shift", &VISITORCLASS::VisitAddSubShifted}, \
- {"sub_32_addsub_shift", &VISITORCLASS::VisitAddSubShifted}, \
- {"sub_64_addsub_shift", &VISITORCLASS::VisitAddSubShifted}, \
- {"adcs_32_addsub_carry", &VISITORCLASS::VisitAddSubWithCarry}, \
- {"adcs_64_addsub_carry", &VISITORCLASS::VisitAddSubWithCarry}, \
- {"adc_32_addsub_carry", &VISITORCLASS::VisitAddSubWithCarry}, \
- {"adc_64_addsub_carry", &VISITORCLASS::VisitAddSubWithCarry}, \
- {"sbcs_32_addsub_carry", &VISITORCLASS::VisitAddSubWithCarry}, \
- {"sbcs_64_addsub_carry", &VISITORCLASS::VisitAddSubWithCarry}, \
- {"sbc_32_addsub_carry", &VISITORCLASS::VisitAddSubWithCarry}, \
- {"sbc_64_addsub_carry", &VISITORCLASS::VisitAddSubWithCarry}, \
- {"ldaddab_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaddah_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaddalb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaddalh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaddal_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaddal_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldadda_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldadda_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaddb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaddh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaddlb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaddlh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaddl_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaddl_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldadd_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldadd_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaprb_32l_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldaprh_32l_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldapr_32l_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldapr_64l_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclrab_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclrah_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclralb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclralh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclral_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclral_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclra_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclra_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclrb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclrh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclrlb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclrlh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclrl_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclrl_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclr_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldclr_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeorab_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeorah_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeoralb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeoralh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeoral_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeoral_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeora_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeora_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeorb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeorh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeorlb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeorlh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeorl_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeorl_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeor_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldeor_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsetab_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsetah_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsetalb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsetalh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsetal_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsetal_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldseta_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldseta_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsetb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldseth_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsetlb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsetlh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsetl_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsetl_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldset_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldset_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxab_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxah_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxalb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxalh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxal_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxal_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxa_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxa_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxlb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxlh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxl_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmaxl_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmax_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmax_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminab_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminah_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminalb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminalh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminal_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminal_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmina_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmina_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminlb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminlh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminl_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsminl_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmin_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldsmin_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxab_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxah_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxalb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxalh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxal_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxal_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxa_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxa_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxlb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxlh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxl_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumaxl_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumax_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumax_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminab_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminah_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminalb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminalh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminal_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminal_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumina_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumina_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminlb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminlh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminl_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"lduminl_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumin_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"ldumin_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swpab_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swpah_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swpalb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swpalh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swpal_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swpal_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swpa_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swpa_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swpb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swph_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swplb_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swplh_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swpl_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swpl_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swp_32_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"swp_64_memop", &VISITORCLASS::VisitAtomicMemory}, \
- {"bfm_32m_bitfield", &VISITORCLASS::VisitBitfield}, \
- {"bfm_64m_bitfield", &VISITORCLASS::VisitBitfield}, \
- {"sbfm_32m_bitfield", &VISITORCLASS::VisitBitfield}, \
- {"sbfm_64m_bitfield", &VISITORCLASS::VisitBitfield}, \
- {"ubfm_32m_bitfield", &VISITORCLASS::VisitBitfield}, \
- {"ubfm_64m_bitfield", &VISITORCLASS::VisitBitfield}, \
- {"cbnz_32_compbranch", &VISITORCLASS::VisitCompareBranch}, \
- {"cbnz_64_compbranch", &VISITORCLASS::VisitCompareBranch}, \
- {"cbz_32_compbranch", &VISITORCLASS::VisitCompareBranch}, \
- {"cbz_64_compbranch", &VISITORCLASS::VisitCompareBranch}, \
- {"b_only_condbranch", &VISITORCLASS::VisitConditionalBranch}, \
- {"ccmn_32_condcmp_imm", \
+ {"wrffr_f_p"_h, &VISITORCLASS::VisitSVEFFRWriteFromPredicate}, \
+ {"zip1_p_pp"_h, &VISITORCLASS::VisitSVEPermutePredicateElements}, \
+ {"zip1_z_zz"_h, &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
+ {"zip2_p_pp"_h, &VISITORCLASS::VisitSVEPermutePredicateElements}, \
+ {"zip2_z_zz"_h, &VISITORCLASS::VisitSVEPermuteVectorInterleaving}, \
+ {"adds_32s_addsub_ext"_h, &VISITORCLASS::VisitAddSubExtended}, \
+ {"adds_64s_addsub_ext"_h, &VISITORCLASS::VisitAddSubExtended}, \
+ {"add_32_addsub_ext"_h, &VISITORCLASS::VisitAddSubExtended}, \
+ {"add_64_addsub_ext"_h, &VISITORCLASS::VisitAddSubExtended}, \
+ {"subs_32s_addsub_ext"_h, &VISITORCLASS::VisitAddSubExtended}, \
+ {"subs_64s_addsub_ext"_h, &VISITORCLASS::VisitAddSubExtended}, \
+ {"sub_32_addsub_ext"_h, &VISITORCLASS::VisitAddSubExtended}, \
+ {"sub_64_addsub_ext"_h, &VISITORCLASS::VisitAddSubExtended}, \
+ {"adds_32s_addsub_imm"_h, &VISITORCLASS::VisitAddSubImmediate}, \
+ {"adds_64s_addsub_imm"_h, &VISITORCLASS::VisitAddSubImmediate}, \
+ {"add_32_addsub_imm"_h, &VISITORCLASS::VisitAddSubImmediate}, \
+ {"add_64_addsub_imm"_h, &VISITORCLASS::VisitAddSubImmediate}, \
+ {"subs_32s_addsub_imm"_h, &VISITORCLASS::VisitAddSubImmediate}, \
+ {"subs_64s_addsub_imm"_h, &VISITORCLASS::VisitAddSubImmediate}, \
+ {"sub_32_addsub_imm"_h, &VISITORCLASS::VisitAddSubImmediate}, \
+ {"sub_64_addsub_imm"_h, &VISITORCLASS::VisitAddSubImmediate}, \
+ {"adds_32_addsub_shift"_h, &VISITORCLASS::VisitAddSubShifted}, \
+ {"adds_64_addsub_shift"_h, &VISITORCLASS::VisitAddSubShifted}, \
+ {"add_32_addsub_shift"_h, &VISITORCLASS::VisitAddSubShifted}, \
+ {"add_64_addsub_shift"_h, &VISITORCLASS::VisitAddSubShifted}, \
+ {"subs_32_addsub_shift"_h, &VISITORCLASS::VisitAddSubShifted}, \
+ {"subs_64_addsub_shift"_h, &VISITORCLASS::VisitAddSubShifted}, \
+ {"sub_32_addsub_shift"_h, &VISITORCLASS::VisitAddSubShifted}, \
+ {"sub_64_addsub_shift"_h, &VISITORCLASS::VisitAddSubShifted}, \
+ {"adcs_32_addsub_carry"_h, &VISITORCLASS::VisitAddSubWithCarry}, \
+ {"adcs_64_addsub_carry"_h, &VISITORCLASS::VisitAddSubWithCarry}, \
+ {"adc_32_addsub_carry"_h, &VISITORCLASS::VisitAddSubWithCarry}, \
+ {"adc_64_addsub_carry"_h, &VISITORCLASS::VisitAddSubWithCarry}, \
+ {"sbcs_32_addsub_carry"_h, &VISITORCLASS::VisitAddSubWithCarry}, \
+ {"sbcs_64_addsub_carry"_h, &VISITORCLASS::VisitAddSubWithCarry}, \
+ {"sbc_32_addsub_carry"_h, &VISITORCLASS::VisitAddSubWithCarry}, \
+ {"sbc_64_addsub_carry"_h, &VISITORCLASS::VisitAddSubWithCarry}, \
+ {"ldaddab_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaddah_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaddalb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaddalh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaddal_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaddal_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldadda_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldadda_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaddb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaddh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaddlb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaddlh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaddl_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaddl_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldadd_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldadd_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaprb_32l_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldaprh_32l_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldapr_32l_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldapr_64l_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclrab_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclrah_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclralb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclralh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclral_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclral_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclra_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclra_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclrb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclrh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclrlb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclrlh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclrl_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclrl_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclr_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldclr_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeorab_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeorah_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeoralb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeoralh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeoral_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeoral_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeora_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeora_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeorb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeorh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeorlb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeorlh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeorl_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeorl_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeor_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldeor_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsetab_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsetah_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsetalb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsetalh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsetal_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsetal_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldseta_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldseta_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsetb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldseth_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsetlb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsetlh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsetl_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsetl_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldset_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldset_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxab_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxah_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxalb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxalh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxal_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxal_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxa_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxa_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxlb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxlh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxl_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmaxl_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmax_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmax_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminab_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminah_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminalb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminalh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminal_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminal_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmina_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmina_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminlb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminlh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminl_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsminl_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmin_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldsmin_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxab_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxah_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxalb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxalh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxal_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxal_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxa_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxa_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxlb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxlh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxl_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumaxl_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumax_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumax_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminab_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminah_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminalb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminalh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminal_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminal_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumina_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumina_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminlb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminlh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminl_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"lduminl_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumin_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"ldumin_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swpab_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swpah_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swpalb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swpalh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swpal_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swpal_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swpa_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swpa_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swpb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swph_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swplb_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swplh_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swpl_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swpl_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swp_32_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"swp_64_memop"_h, &VISITORCLASS::VisitAtomicMemory}, \
+ {"bfm_32m_bitfield"_h, &VISITORCLASS::VisitBitfield}, \
+ {"bfm_64m_bitfield"_h, &VISITORCLASS::VisitBitfield}, \
+ {"sbfm_32m_bitfield"_h, &VISITORCLASS::VisitBitfield}, \
+ {"sbfm_64m_bitfield"_h, &VISITORCLASS::VisitBitfield}, \
+ {"ubfm_32m_bitfield"_h, &VISITORCLASS::VisitBitfield}, \
+ {"ubfm_64m_bitfield"_h, &VISITORCLASS::VisitBitfield}, \
+ {"cbnz_32_compbranch"_h, &VISITORCLASS::VisitCompareBranch}, \
+ {"cbnz_64_compbranch"_h, &VISITORCLASS::VisitCompareBranch}, \
+ {"cbz_32_compbranch"_h, &VISITORCLASS::VisitCompareBranch}, \
+ {"cbz_64_compbranch"_h, &VISITORCLASS::VisitCompareBranch}, \
+ {"b_only_condbranch"_h, &VISITORCLASS::VisitConditionalBranch}, \
+ {"ccmn_32_condcmp_imm"_h, \
&VISITORCLASS::VisitConditionalCompareImmediate}, \
- {"ccmn_64_condcmp_imm", \
+ {"ccmn_64_condcmp_imm"_h, \
&VISITORCLASS::VisitConditionalCompareImmediate}, \
- {"ccmp_32_condcmp_imm", \
+ {"ccmp_32_condcmp_imm"_h, \
&VISITORCLASS::VisitConditionalCompareImmediate}, \
- {"ccmp_64_condcmp_imm", \
+ {"ccmp_64_condcmp_imm"_h, \
&VISITORCLASS::VisitConditionalCompareImmediate}, \
- {"ccmn_32_condcmp_reg", &VISITORCLASS::VisitConditionalCompareRegister}, \
- {"ccmn_64_condcmp_reg", &VISITORCLASS::VisitConditionalCompareRegister}, \
- {"ccmp_32_condcmp_reg", &VISITORCLASS::VisitConditionalCompareRegister}, \
- {"ccmp_64_condcmp_reg", &VISITORCLASS::VisitConditionalCompareRegister}, \
- {"csel_32_condsel", &VISITORCLASS::VisitConditionalSelect}, \
- {"csel_64_condsel", &VISITORCLASS::VisitConditionalSelect}, \
- {"csinc_32_condsel", &VISITORCLASS::VisitConditionalSelect}, \
- {"csinc_64_condsel", &VISITORCLASS::VisitConditionalSelect}, \
- {"csinv_32_condsel", &VISITORCLASS::VisitConditionalSelect}, \
- {"csinv_64_condsel", &VISITORCLASS::VisitConditionalSelect}, \
- {"csneg_32_condsel", &VISITORCLASS::VisitConditionalSelect}, \
- {"csneg_64_condsel", &VISITORCLASS::VisitConditionalSelect}, \
- {"sha1h_ss_cryptosha2", &VISITORCLASS::VisitCrypto2RegSHA}, \
- {"sha1su1_vv_cryptosha2", &VISITORCLASS::VisitCrypto2RegSHA}, \
- {"sha256su0_vv_cryptosha2", &VISITORCLASS::VisitCrypto2RegSHA}, \
- {"sha1c_qsv_cryptosha3", &VISITORCLASS::VisitCrypto3RegSHA}, \
- {"sha1m_qsv_cryptosha3", &VISITORCLASS::VisitCrypto3RegSHA}, \
- {"sha1p_qsv_cryptosha3", &VISITORCLASS::VisitCrypto3RegSHA}, \
- {"sha1su0_vvv_cryptosha3", &VISITORCLASS::VisitCrypto3RegSHA}, \
- {"sha256h2_qqv_cryptosha3", &VISITORCLASS::VisitCrypto3RegSHA}, \
- {"sha256h_qqv_cryptosha3", &VISITORCLASS::VisitCrypto3RegSHA}, \
- {"sha256su1_vvv_cryptosha3", &VISITORCLASS::VisitCrypto3RegSHA}, \
- {"aesd_b_cryptoaes", &VISITORCLASS::VisitCryptoAES}, \
- {"aese_b_cryptoaes", &VISITORCLASS::VisitCryptoAES}, \
- {"aesimc_b_cryptoaes", &VISITORCLASS::VisitCryptoAES}, \
- {"aesmc_b_cryptoaes", &VISITORCLASS::VisitCryptoAES}, \
- {"autda_64p_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"autdb_64p_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"autdza_64z_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"autdzb_64z_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"autia_64p_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"autib_64p_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"autiza_64z_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"autizb_64z_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"cls_32_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"cls_64_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"clz_32_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"clz_64_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"pacda_64p_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"pacdb_64p_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"pacdza_64z_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"pacdzb_64z_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"pacia_64p_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"pacib_64p_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"paciza_64z_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"pacizb_64z_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"rbit_32_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"rbit_64_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"rev16_32_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"rev16_64_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"rev32_64_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"rev_32_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"rev_64_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"xpacd_64z_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"xpaci_64z_dp_1src", &VISITORCLASS::VisitDataProcessing1Source}, \
- {"asrv_32_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"asrv_64_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"crc32b_32c_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"crc32cb_32c_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"crc32ch_32c_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"crc32cw_32c_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"crc32cx_64c_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"crc32h_32c_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"crc32w_32c_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"crc32x_64c_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"lslv_32_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"lslv_64_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"lsrv_32_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"lsrv_64_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"pacga_64p_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"rorv_32_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"rorv_64_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"sdiv_32_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"sdiv_64_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"udiv_32_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"udiv_64_dp_2src", &VISITORCLASS::VisitDataProcessing2Source}, \
- {"madd_32a_dp_3src", &VISITORCLASS::VisitDataProcessing3Source}, \
- {"madd_64a_dp_3src", &VISITORCLASS::VisitDataProcessing3Source}, \
- {"msub_32a_dp_3src", &VISITORCLASS::VisitDataProcessing3Source}, \
- {"msub_64a_dp_3src", &VISITORCLASS::VisitDataProcessing3Source}, \
- {"smaddl_64wa_dp_3src", &VISITORCLASS::VisitDataProcessing3Source}, \
- {"smsubl_64wa_dp_3src", &VISITORCLASS::VisitDataProcessing3Source}, \
- {"smulh_64_dp_3src", &VISITORCLASS::VisitDataProcessing3Source}, \
- {"umaddl_64wa_dp_3src", &VISITORCLASS::VisitDataProcessing3Source}, \
- {"umsubl_64wa_dp_3src", &VISITORCLASS::VisitDataProcessing3Source}, \
- {"umulh_64_dp_3src", &VISITORCLASS::VisitDataProcessing3Source}, \
- {"setf16_only_setf", &VISITORCLASS::VisitEvaluateIntoFlags}, \
- {"setf8_only_setf", &VISITORCLASS::VisitEvaluateIntoFlags}, \
- {"brk_ex_exception", &VISITORCLASS::VisitException}, \
- {"dcps1_dc_exception", &VISITORCLASS::VisitException}, \
- {"dcps2_dc_exception", &VISITORCLASS::VisitException}, \
- {"dcps3_dc_exception", &VISITORCLASS::VisitException}, \
- {"hlt_ex_exception", &VISITORCLASS::VisitException}, \
- {"hvc_ex_exception", &VISITORCLASS::VisitException}, \
- {"smc_ex_exception", &VISITORCLASS::VisitException}, \
- {"svc_ex_exception", &VISITORCLASS::VisitException}, \
- {"extr_32_extract", &VISITORCLASS::VisitExtract}, \
- {"extr_64_extract", &VISITORCLASS::VisitExtract}, \
- {"fcmpe_dz_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fcmpe_d_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fcmpe_hz_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fcmpe_h_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fcmpe_sz_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fcmpe_s_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fcmp_dz_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fcmp_d_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fcmp_hz_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fcmp_h_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fcmp_sz_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fcmp_s_floatcmp", &VISITORCLASS::VisitFPCompare}, \
- {"fccmpe_d_floatccmp", &VISITORCLASS::VisitFPConditionalCompare}, \
- {"fccmpe_h_floatccmp", &VISITORCLASS::VisitFPConditionalCompare}, \
- {"fccmpe_s_floatccmp", &VISITORCLASS::VisitFPConditionalCompare}, \
- {"fccmp_d_floatccmp", &VISITORCLASS::VisitFPConditionalCompare}, \
- {"fccmp_h_floatccmp", &VISITORCLASS::VisitFPConditionalCompare}, \
- {"fccmp_s_floatccmp", &VISITORCLASS::VisitFPConditionalCompare}, \
- {"fcsel_d_floatsel", &VISITORCLASS::VisitFPConditionalSelect}, \
- {"fcsel_h_floatsel", &VISITORCLASS::VisitFPConditionalSelect}, \
- {"fcsel_s_floatsel", &VISITORCLASS::VisitFPConditionalSelect}, \
- {"bfcvt_bs_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fabs_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fabs_h_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fabs_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fcvt_dh_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fcvt_ds_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fcvt_hd_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fcvt_hs_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fcvt_sd_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fcvt_sh_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fmov_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fmov_h_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fmov_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fneg_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fneg_h_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fneg_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frint32x_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frint32x_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frint32z_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frint32z_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frint64x_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frint64x_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frint64z_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frint64z_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frinta_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frinta_h_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frinta_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frinti_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frinti_h_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frinti_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintm_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintm_h_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintm_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintn_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintn_h_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintn_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintp_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintp_h_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintp_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintx_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintx_h_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintx_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintz_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintz_h_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"frintz_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fsqrt_d_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fsqrt_h_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fsqrt_s_floatdp1", &VISITORCLASS::VisitFPDataProcessing1Source}, \
- {"fadd_d_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fadd_h_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fadd_s_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fdiv_d_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fdiv_h_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fdiv_s_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmaxnm_d_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmaxnm_h_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmaxnm_s_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmax_d_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmax_h_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmax_s_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fminnm_d_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fminnm_h_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fminnm_s_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmin_d_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmin_h_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmin_s_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmul_d_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmul_h_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmul_s_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fnmul_d_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fnmul_h_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fnmul_s_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fsub_d_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fsub_h_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fsub_s_floatdp2", &VISITORCLASS::VisitFPDataProcessing2Source}, \
- {"fmadd_d_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fmadd_h_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fmadd_s_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fmsub_d_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fmsub_h_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fmsub_s_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fnmadd_d_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fnmadd_h_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fnmadd_s_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fnmsub_d_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fnmsub_h_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fnmsub_s_floatdp3", &VISITORCLASS::VisitFPDataProcessing3Source}, \
- {"fcvtzs_32d_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fcvtzs_32h_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fcvtzs_32s_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fcvtzs_64d_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fcvtzs_64h_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fcvtzs_64s_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fcvtzu_32d_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fcvtzu_32h_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fcvtzu_32s_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fcvtzu_64d_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fcvtzu_64h_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fcvtzu_64s_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"scvtf_d32_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"scvtf_d64_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"scvtf_h32_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"scvtf_h64_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"scvtf_s32_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"scvtf_s64_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"ucvtf_d32_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"ucvtf_d64_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"ucvtf_h32_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"ucvtf_h64_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"ucvtf_s32_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"ucvtf_s64_float2fix", &VISITORCLASS::VisitFPFixedPointConvert}, \
- {"fmov_d_floatimm", &VISITORCLASS::VisitFPImmediate}, \
- {"fmov_h_floatimm", &VISITORCLASS::VisitFPImmediate}, \
- {"fmov_s_floatimm", &VISITORCLASS::VisitFPImmediate}, \
- {"fcvtas_32d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtas_32h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtas_32s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtas_64d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtas_64h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtas_64s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtau_32d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtau_32h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtau_32s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtau_64d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtau_64h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtau_64s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtms_32d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtms_32h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtms_32s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtms_64d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtms_64h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtms_64s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtmu_32d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtmu_32h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtmu_32s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtmu_64d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtmu_64h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtmu_64s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtns_32d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtns_32h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtns_32s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtns_64d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtns_64h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtns_64s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtnu_32d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtnu_32h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtnu_32s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtnu_64d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtnu_64h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtnu_64s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtps_32d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtps_32h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtps_32s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtps_64d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtps_64h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtps_64s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtpu_32d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtpu_32h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtpu_32s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtpu_64d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtpu_64h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtpu_64s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzs_32d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzs_32h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzs_32s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzs_64d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzs_64h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzs_64s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzu_32d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzu_32h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzu_32s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzu_64d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzu_64h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fcvtzu_64s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fjcvtzs_32d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fmov_32h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fmov_32s_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fmov_64d_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fmov_64h_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fmov_64vx_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fmov_d64_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fmov_h32_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fmov_h64_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fmov_s32_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"fmov_v64i_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"scvtf_d32_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"scvtf_d64_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"scvtf_h32_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"scvtf_h64_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"scvtf_s32_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"scvtf_s64_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"ucvtf_d32_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"ucvtf_d64_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"ucvtf_h32_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"ucvtf_h64_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"ucvtf_s32_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"ucvtf_s64_float2int", &VISITORCLASS::VisitFPIntegerConvert}, \
- {"ldrsw_64_loadlit", &VISITORCLASS::VisitLoadLiteral}, \
- {"ldr_32_loadlit", &VISITORCLASS::VisitLoadLiteral}, \
- {"ldr_64_loadlit", &VISITORCLASS::VisitLoadLiteral}, \
- {"ldr_d_loadlit", &VISITORCLASS::VisitLoadLiteral}, \
- {"ldr_q_loadlit", &VISITORCLASS::VisitLoadLiteral}, \
- {"ldr_s_loadlit", &VISITORCLASS::VisitLoadLiteral}, \
- {"prfm_p_loadlit", &VISITORCLASS::VisitLoadLiteral}, \
- {"casab_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casah_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casalb_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casalh_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casal_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casal_c64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casa_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casa_c64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casb_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"cash_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"caslb_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"caslh_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casl_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casl_c64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"caspal_cp32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"caspal_cp64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"caspa_cp32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"caspa_cp64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"caspl_cp32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"caspl_cp64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casp_cp32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"casp_cp64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"cas_c32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"cas_c64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldarb_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldarh_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldar_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldar_lr64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldaxp_lp32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldaxp_lp64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldaxrb_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldaxrh_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldaxr_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldaxr_lr64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldlarb_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldlarh_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldlar_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldlar_lr64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldxp_lp32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldxp_lp64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldxrb_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldxrh_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldxr_lr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldxr_lr64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stllrb_sl32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stllrh_sl32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stllr_sl32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stllr_sl64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stlrb_sl32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stlrh_sl32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stlr_sl32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stlr_sl64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stlxp_sp32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stlxp_sp64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stlxrb_sr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stlxrh_sr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stlxr_sr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stlxr_sr64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stxp_sp32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stxp_sp64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stxrb_sr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stxrh_sr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stxr_sr32_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"stxr_sr64_ldstexcl", &VISITORCLASS::VisitLoadStoreExclusive}, \
- {"ldraa_64w_ldst_pac", &VISITORCLASS::VisitLoadStorePAC}, \
- {"ldraa_64_ldst_pac", &VISITORCLASS::VisitLoadStorePAC}, \
- {"ldrab_64w_ldst_pac", &VISITORCLASS::VisitLoadStorePAC}, \
- {"ldrab_64_ldst_pac", &VISITORCLASS::VisitLoadStorePAC}, \
- {"ldnp_32_ldstnapair_offs", \
+ {"ccmn_32_condcmp_reg"_h, \
+ &VISITORCLASS::VisitConditionalCompareRegister}, \
+ {"ccmn_64_condcmp_reg"_h, \
+ &VISITORCLASS::VisitConditionalCompareRegister}, \
+ {"ccmp_32_condcmp_reg"_h, \
+ &VISITORCLASS::VisitConditionalCompareRegister}, \
+ {"ccmp_64_condcmp_reg"_h, \
+ &VISITORCLASS::VisitConditionalCompareRegister}, \
+ {"csel_32_condsel"_h, &VISITORCLASS::VisitConditionalSelect}, \
+ {"csel_64_condsel"_h, &VISITORCLASS::VisitConditionalSelect}, \
+ {"csinc_32_condsel"_h, &VISITORCLASS::VisitConditionalSelect}, \
+ {"csinc_64_condsel"_h, &VISITORCLASS::VisitConditionalSelect}, \
+ {"csinv_32_condsel"_h, &VISITORCLASS::VisitConditionalSelect}, \
+ {"csinv_64_condsel"_h, &VISITORCLASS::VisitConditionalSelect}, \
+ {"csneg_32_condsel"_h, &VISITORCLASS::VisitConditionalSelect}, \
+ {"csneg_64_condsel"_h, &VISITORCLASS::VisitConditionalSelect}, \
+ {"sha1h_ss_cryptosha2"_h, &VISITORCLASS::VisitCrypto2RegSHA}, \
+ {"sha1su1_vv_cryptosha2"_h, &VISITORCLASS::VisitCrypto2RegSHA}, \
+ {"sha256su0_vv_cryptosha2"_h, &VISITORCLASS::VisitCrypto2RegSHA}, \
+ {"sha1c_qsv_cryptosha3"_h, &VISITORCLASS::VisitCrypto3RegSHA}, \
+ {"sha1m_qsv_cryptosha3"_h, &VISITORCLASS::VisitCrypto3RegSHA}, \
+ {"sha1p_qsv_cryptosha3"_h, &VISITORCLASS::VisitCrypto3RegSHA}, \
+ {"sha1su0_vvv_cryptosha3"_h, &VISITORCLASS::VisitCrypto3RegSHA}, \
+ {"sha256h2_qqv_cryptosha3"_h, &VISITORCLASS::VisitCrypto3RegSHA}, \
+ {"sha256h_qqv_cryptosha3"_h, &VISITORCLASS::VisitCrypto3RegSHA}, \
+ {"sha256su1_vvv_cryptosha3"_h, &VISITORCLASS::VisitCrypto3RegSHA}, \
+ {"aesd_b_cryptoaes"_h, &VISITORCLASS::VisitCryptoAES}, \
+ {"aese_b_cryptoaes"_h, &VISITORCLASS::VisitCryptoAES}, \
+ {"aesimc_b_cryptoaes"_h, &VISITORCLASS::VisitCryptoAES}, \
+ {"aesmc_b_cryptoaes"_h, &VISITORCLASS::VisitCryptoAES}, \
+ {"autda_64p_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"autdb_64p_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"autdza_64z_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"autdzb_64z_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"autia_64p_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"autib_64p_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"autiza_64z_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"autizb_64z_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"cls_32_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"cls_64_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"clz_32_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"clz_64_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"pacda_64p_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"pacdb_64p_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"pacdza_64z_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"pacdzb_64z_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"pacia_64p_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"pacib_64p_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"paciza_64z_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"pacizb_64z_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"rbit_32_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"rbit_64_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"rev16_32_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"rev16_64_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"rev32_64_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"rev_32_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"rev_64_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"xpacd_64z_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"xpaci_64z_dp_1src"_h, &VISITORCLASS::VisitDataProcessing1Source}, \
+ {"asrv_32_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"asrv_64_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"crc32b_32c_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"crc32cb_32c_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"crc32ch_32c_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"crc32cw_32c_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"crc32cx_64c_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"crc32h_32c_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"crc32w_32c_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"crc32x_64c_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"lslv_32_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"lslv_64_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"lsrv_32_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"lsrv_64_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"pacga_64p_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"rorv_32_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"rorv_64_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"sdiv_32_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"sdiv_64_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"udiv_32_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"udiv_64_dp_2src"_h, &VISITORCLASS::VisitDataProcessing2Source}, \
+ {"madd_32a_dp_3src"_h, &VISITORCLASS::VisitDataProcessing3Source}, \
+ {"madd_64a_dp_3src"_h, &VISITORCLASS::VisitDataProcessing3Source}, \
+ {"msub_32a_dp_3src"_h, &VISITORCLASS::VisitDataProcessing3Source}, \
+ {"msub_64a_dp_3src"_h, &VISITORCLASS::VisitDataProcessing3Source}, \
+ {"smaddl_64wa_dp_3src"_h, &VISITORCLASS::VisitDataProcessing3Source}, \
+ {"smsubl_64wa_dp_3src"_h, &VISITORCLASS::VisitDataProcessing3Source}, \
+ {"smulh_64_dp_3src"_h, &VISITORCLASS::VisitDataProcessing3Source}, \
+ {"umaddl_64wa_dp_3src"_h, &VISITORCLASS::VisitDataProcessing3Source}, \
+ {"umsubl_64wa_dp_3src"_h, &VISITORCLASS::VisitDataProcessing3Source}, \
+ {"umulh_64_dp_3src"_h, &VISITORCLASS::VisitDataProcessing3Source}, \
+ {"setf16_only_setf"_h, &VISITORCLASS::VisitEvaluateIntoFlags}, \
+ {"setf8_only_setf"_h, &VISITORCLASS::VisitEvaluateIntoFlags}, \
+ {"brk_ex_exception"_h, &VISITORCLASS::VisitException}, \
+ {"dcps1_dc_exception"_h, &VISITORCLASS::VisitException}, \
+ {"dcps2_dc_exception"_h, &VISITORCLASS::VisitException}, \
+ {"dcps3_dc_exception"_h, &VISITORCLASS::VisitException}, \
+ {"hlt_ex_exception"_h, &VISITORCLASS::VisitException}, \
+ {"hvc_ex_exception"_h, &VISITORCLASS::VisitException}, \
+ {"smc_ex_exception"_h, &VISITORCLASS::VisitException}, \
+ {"svc_ex_exception"_h, &VISITORCLASS::VisitException}, \
+ {"extr_32_extract"_h, &VISITORCLASS::VisitExtract}, \
+ {"extr_64_extract"_h, &VISITORCLASS::VisitExtract}, \
+ {"fcmpe_dz_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fcmpe_d_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fcmpe_hz_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fcmpe_h_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fcmpe_sz_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fcmpe_s_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fcmp_dz_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fcmp_d_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fcmp_hz_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fcmp_h_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fcmp_sz_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fcmp_s_floatcmp"_h, &VISITORCLASS::VisitFPCompare}, \
+ {"fccmpe_d_floatccmp"_h, &VISITORCLASS::VisitFPConditionalCompare}, \
+ {"fccmpe_h_floatccmp"_h, &VISITORCLASS::VisitFPConditionalCompare}, \
+ {"fccmpe_s_floatccmp"_h, &VISITORCLASS::VisitFPConditionalCompare}, \
+ {"fccmp_d_floatccmp"_h, &VISITORCLASS::VisitFPConditionalCompare}, \
+ {"fccmp_h_floatccmp"_h, &VISITORCLASS::VisitFPConditionalCompare}, \
+ {"fccmp_s_floatccmp"_h, &VISITORCLASS::VisitFPConditionalCompare}, \
+ {"fcsel_d_floatsel"_h, &VISITORCLASS::VisitFPConditionalSelect}, \
+ {"fcsel_h_floatsel"_h, &VISITORCLASS::VisitFPConditionalSelect}, \
+ {"fcsel_s_floatsel"_h, &VISITORCLASS::VisitFPConditionalSelect}, \
+ {"bfcvt_bs_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fabs_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fabs_h_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fabs_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fcvt_dh_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fcvt_ds_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fcvt_hd_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fcvt_hs_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fcvt_sd_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fcvt_sh_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fmov_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fmov_h_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fmov_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fneg_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fneg_h_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fneg_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frint32x_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frint32x_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frint32z_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frint32z_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frint64x_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frint64x_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frint64z_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frint64z_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frinta_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frinta_h_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frinta_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frinti_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frinti_h_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frinti_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintm_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintm_h_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintm_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintn_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintn_h_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintn_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintp_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintp_h_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintp_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintx_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintx_h_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintx_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintz_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintz_h_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"frintz_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fsqrt_d_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fsqrt_h_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fsqrt_s_floatdp1"_h, &VISITORCLASS::VisitFPDataProcessing1Source}, \
+ {"fadd_d_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fadd_h_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fadd_s_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fdiv_d_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fdiv_h_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fdiv_s_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmaxnm_d_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmaxnm_h_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmaxnm_s_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmax_d_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmax_h_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmax_s_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fminnm_d_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fminnm_h_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fminnm_s_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmin_d_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmin_h_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmin_s_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmul_d_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmul_h_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmul_s_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fnmul_d_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fnmul_h_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fnmul_s_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fsub_d_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fsub_h_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fsub_s_floatdp2"_h, &VISITORCLASS::VisitFPDataProcessing2Source}, \
+ {"fmadd_d_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fmadd_h_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fmadd_s_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fmsub_d_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fmsub_h_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fmsub_s_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fnmadd_d_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fnmadd_h_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fnmadd_s_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fnmsub_d_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fnmsub_h_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fnmsub_s_floatdp3"_h, &VISITORCLASS::VisitFPDataProcessing3Source}, \
+ {"fcvtzs_32d_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fcvtzs_32h_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fcvtzs_32s_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fcvtzs_64d_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fcvtzs_64h_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fcvtzs_64s_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fcvtzu_32d_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fcvtzu_32h_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fcvtzu_32s_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fcvtzu_64d_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fcvtzu_64h_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fcvtzu_64s_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"scvtf_d32_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"scvtf_d64_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"scvtf_h32_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"scvtf_h64_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"scvtf_s32_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"scvtf_s64_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"ucvtf_d32_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"ucvtf_d64_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"ucvtf_h32_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"ucvtf_h64_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"ucvtf_s32_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"ucvtf_s64_float2fix"_h, &VISITORCLASS::VisitFPFixedPointConvert}, \
+ {"fmov_d_floatimm"_h, &VISITORCLASS::VisitFPImmediate}, \
+ {"fmov_h_floatimm"_h, &VISITORCLASS::VisitFPImmediate}, \
+ {"fmov_s_floatimm"_h, &VISITORCLASS::VisitFPImmediate}, \
+ {"fcvtas_32d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtas_32h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtas_32s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtas_64d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtas_64h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtas_64s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtau_32d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtau_32h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtau_32s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtau_64d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtau_64h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtau_64s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtms_32d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtms_32h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtms_32s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtms_64d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtms_64h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtms_64s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtmu_32d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtmu_32h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtmu_32s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtmu_64d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtmu_64h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtmu_64s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtns_32d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtns_32h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtns_32s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtns_64d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtns_64h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtns_64s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtnu_32d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtnu_32h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtnu_32s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtnu_64d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtnu_64h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtnu_64s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtps_32d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtps_32h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtps_32s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtps_64d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtps_64h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtps_64s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtpu_32d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtpu_32h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtpu_32s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtpu_64d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtpu_64h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtpu_64s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzs_32d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzs_32h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzs_32s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzs_64d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzs_64h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzs_64s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzu_32d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzu_32h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzu_32s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzu_64d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzu_64h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fcvtzu_64s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fjcvtzs_32d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fmov_32h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fmov_32s_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fmov_64d_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fmov_64h_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fmov_64vx_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fmov_d64_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fmov_h32_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fmov_h64_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fmov_s32_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"fmov_v64i_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"scvtf_d32_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"scvtf_d64_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"scvtf_h32_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"scvtf_h64_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"scvtf_s32_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"scvtf_s64_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"ucvtf_d32_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"ucvtf_d64_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"ucvtf_h32_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"ucvtf_h64_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"ucvtf_s32_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"ucvtf_s64_float2int"_h, &VISITORCLASS::VisitFPIntegerConvert}, \
+ {"ldrsw_64_loadlit"_h, &VISITORCLASS::VisitLoadLiteral}, \
+ {"ldr_32_loadlit"_h, &VISITORCLASS::VisitLoadLiteral}, \
+ {"ldr_64_loadlit"_h, &VISITORCLASS::VisitLoadLiteral}, \
+ {"ldr_d_loadlit"_h, &VISITORCLASS::VisitLoadLiteral}, \
+ {"ldr_q_loadlit"_h, &VISITORCLASS::VisitLoadLiteral}, \
+ {"ldr_s_loadlit"_h, &VISITORCLASS::VisitLoadLiteral}, \
+ {"prfm_p_loadlit"_h, &VISITORCLASS::VisitLoadLiteral}, \
+ {"casab_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casah_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casalb_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casalh_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casal_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casal_c64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casa_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casa_c64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casb_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"cash_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"caslb_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"caslh_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casl_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casl_c64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"caspal_cp32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"caspal_cp64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"caspa_cp32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"caspa_cp64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"caspl_cp32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"caspl_cp64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casp_cp32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"casp_cp64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"cas_c32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"cas_c64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldarb_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldarh_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldar_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldar_lr64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldaxp_lp32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldaxp_lp64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldaxrb_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldaxrh_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldaxr_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldaxr_lr64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldlarb_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldlarh_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldlar_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldlar_lr64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldxp_lp32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldxp_lp64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldxrb_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldxrh_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldxr_lr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldxr_lr64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stllrb_sl32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stllrh_sl32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stllr_sl32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stllr_sl64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stlrb_sl32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stlrh_sl32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stlr_sl32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stlr_sl64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stlxp_sp32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stlxp_sp64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stlxrb_sr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stlxrh_sr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stlxr_sr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stlxr_sr64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stxp_sp32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stxp_sp64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stxrb_sr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stxrh_sr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stxr_sr32_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"stxr_sr64_ldstexcl"_h, &VISITORCLASS::VisitLoadStoreExclusive}, \
+ {"ldraa_64w_ldst_pac"_h, &VISITORCLASS::VisitLoadStorePAC}, \
+ {"ldraa_64_ldst_pac"_h, &VISITORCLASS::VisitLoadStorePAC}, \
+ {"ldrab_64w_ldst_pac"_h, &VISITORCLASS::VisitLoadStorePAC}, \
+ {"ldrab_64_ldst_pac"_h, &VISITORCLASS::VisitLoadStorePAC}, \
+ {"ldnp_32_ldstnapair_offs"_h, \
&VISITORCLASS::VisitLoadStorePairNonTemporal}, \
- {"ldnp_64_ldstnapair_offs", \
+ {"ldnp_64_ldstnapair_offs"_h, \
&VISITORCLASS::VisitLoadStorePairNonTemporal}, \
- {"ldnp_d_ldstnapair_offs", \
+ {"ldnp_d_ldstnapair_offs"_h, \
&VISITORCLASS::VisitLoadStorePairNonTemporal}, \
- {"ldnp_q_ldstnapair_offs", \
+ {"ldnp_q_ldstnapair_offs"_h, \
&VISITORCLASS::VisitLoadStorePairNonTemporal}, \
- {"ldnp_s_ldstnapair_offs", \
+ {"ldnp_s_ldstnapair_offs"_h, \
&VISITORCLASS::VisitLoadStorePairNonTemporal}, \
- {"stnp_32_ldstnapair_offs", \
+ {"stnp_32_ldstnapair_offs"_h, \
&VISITORCLASS::VisitLoadStorePairNonTemporal}, \
- {"stnp_64_ldstnapair_offs", \
+ {"stnp_64_ldstnapair_offs"_h, \
&VISITORCLASS::VisitLoadStorePairNonTemporal}, \
- {"stnp_d_ldstnapair_offs", \
+ {"stnp_d_ldstnapair_offs"_h, \
&VISITORCLASS::VisitLoadStorePairNonTemporal}, \
- {"stnp_q_ldstnapair_offs", \
+ {"stnp_q_ldstnapair_offs"_h, \
&VISITORCLASS::VisitLoadStorePairNonTemporal}, \
- {"stnp_s_ldstnapair_offs", \
+ {"stnp_s_ldstnapair_offs"_h, \
&VISITORCLASS::VisitLoadStorePairNonTemporal}, \
- {"ldpsw_64_ldstpair_off", &VISITORCLASS::VisitLoadStorePairOffset}, \
- {"ldp_32_ldstpair_off", &VISITORCLASS::VisitLoadStorePairOffset}, \
- {"ldp_64_ldstpair_off", &VISITORCLASS::VisitLoadStorePairOffset}, \
- {"ldp_d_ldstpair_off", &VISITORCLASS::VisitLoadStorePairOffset}, \
- {"ldp_q_ldstpair_off", &VISITORCLASS::VisitLoadStorePairOffset}, \
- {"ldp_s_ldstpair_off", &VISITORCLASS::VisitLoadStorePairOffset}, \
- {"stp_32_ldstpair_off", &VISITORCLASS::VisitLoadStorePairOffset}, \
- {"stp_64_ldstpair_off", &VISITORCLASS::VisitLoadStorePairOffset}, \
- {"stp_d_ldstpair_off", &VISITORCLASS::VisitLoadStorePairOffset}, \
- {"stp_q_ldstpair_off", &VISITORCLASS::VisitLoadStorePairOffset}, \
- {"stp_s_ldstpair_off", &VISITORCLASS::VisitLoadStorePairOffset}, \
- {"ldpsw_64_ldstpair_post", &VISITORCLASS::VisitLoadStorePairPostIndex}, \
- {"ldp_32_ldstpair_post", &VISITORCLASS::VisitLoadStorePairPostIndex}, \
- {"ldp_64_ldstpair_post", &VISITORCLASS::VisitLoadStorePairPostIndex}, \
- {"ldp_d_ldstpair_post", &VISITORCLASS::VisitLoadStorePairPostIndex}, \
- {"ldp_q_ldstpair_post", &VISITORCLASS::VisitLoadStorePairPostIndex}, \
- {"ldp_s_ldstpair_post", &VISITORCLASS::VisitLoadStorePairPostIndex}, \
- {"stp_32_ldstpair_post", &VISITORCLASS::VisitLoadStorePairPostIndex}, \
- {"stp_64_ldstpair_post", &VISITORCLASS::VisitLoadStorePairPostIndex}, \
- {"stp_d_ldstpair_post", &VISITORCLASS::VisitLoadStorePairPostIndex}, \
- {"stp_q_ldstpair_post", &VISITORCLASS::VisitLoadStorePairPostIndex}, \
- {"stp_s_ldstpair_post", &VISITORCLASS::VisitLoadStorePairPostIndex}, \
- {"ldpsw_64_ldstpair_pre", &VISITORCLASS::VisitLoadStorePairPreIndex}, \
- {"ldp_32_ldstpair_pre", &VISITORCLASS::VisitLoadStorePairPreIndex}, \
- {"ldp_64_ldstpair_pre", &VISITORCLASS::VisitLoadStorePairPreIndex}, \
- {"ldp_d_ldstpair_pre", &VISITORCLASS::VisitLoadStorePairPreIndex}, \
- {"ldp_q_ldstpair_pre", &VISITORCLASS::VisitLoadStorePairPreIndex}, \
- {"ldp_s_ldstpair_pre", &VISITORCLASS::VisitLoadStorePairPreIndex}, \
- {"stp_32_ldstpair_pre", &VISITORCLASS::VisitLoadStorePairPreIndex}, \
- {"stp_64_ldstpair_pre", &VISITORCLASS::VisitLoadStorePairPreIndex}, \
- {"stp_d_ldstpair_pre", &VISITORCLASS::VisitLoadStorePairPreIndex}, \
- {"stp_q_ldstpair_pre", &VISITORCLASS::VisitLoadStorePairPreIndex}, \
- {"stp_s_ldstpair_pre", &VISITORCLASS::VisitLoadStorePairPreIndex}, \
- {"ldrb_32_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldrh_32_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldrsb_32_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldrsb_64_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldrsh_32_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldrsh_64_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldrsw_64_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldr_32_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldr_64_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldr_b_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldr_d_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldr_h_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldr_q_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldr_s_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"strb_32_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"strh_32_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"str_32_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"str_64_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"str_b_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"str_d_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"str_h_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"str_q_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"str_s_ldst_immpost", &VISITORCLASS::VisitLoadStorePostIndex}, \
- {"ldrb_32_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldrh_32_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldrsb_32_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldrsb_64_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldrsh_32_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldrsh_64_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldrsw_64_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldr_32_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldr_64_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldr_b_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldr_d_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldr_h_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldr_q_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldr_s_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"strb_32_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"strh_32_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"str_32_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"str_64_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"str_b_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"str_d_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"str_h_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"str_q_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"str_s_ldst_immpre", &VISITORCLASS::VisitLoadStorePreIndex}, \
- {"ldapurb_32_ldapstl_unscaled", \
+ {"ldpsw_64_ldstpair_off"_h, &VISITORCLASS::VisitLoadStorePairOffset}, \
+ {"ldp_32_ldstpair_off"_h, &VISITORCLASS::VisitLoadStorePairOffset}, \
+ {"ldp_64_ldstpair_off"_h, &VISITORCLASS::VisitLoadStorePairOffset}, \
+ {"ldp_d_ldstpair_off"_h, &VISITORCLASS::VisitLoadStorePairOffset}, \
+ {"ldp_q_ldstpair_off"_h, &VISITORCLASS::VisitLoadStorePairOffset}, \
+ {"ldp_s_ldstpair_off"_h, &VISITORCLASS::VisitLoadStorePairOffset}, \
+ {"stp_32_ldstpair_off"_h, &VISITORCLASS::VisitLoadStorePairOffset}, \
+ {"stp_64_ldstpair_off"_h, &VISITORCLASS::VisitLoadStorePairOffset}, \
+ {"stp_d_ldstpair_off"_h, &VISITORCLASS::VisitLoadStorePairOffset}, \
+ {"stp_q_ldstpair_off"_h, &VISITORCLASS::VisitLoadStorePairOffset}, \
+ {"stp_s_ldstpair_off"_h, &VISITORCLASS::VisitLoadStorePairOffset}, \
+ {"ldpsw_64_ldstpair_post"_h, \
+ &VISITORCLASS::VisitLoadStorePairPostIndex}, \
+ {"ldp_32_ldstpair_post"_h, &VISITORCLASS::VisitLoadStorePairPostIndex}, \
+ {"ldp_64_ldstpair_post"_h, &VISITORCLASS::VisitLoadStorePairPostIndex}, \
+ {"ldp_d_ldstpair_post"_h, &VISITORCLASS::VisitLoadStorePairPostIndex}, \
+ {"ldp_q_ldstpair_post"_h, &VISITORCLASS::VisitLoadStorePairPostIndex}, \
+ {"ldp_s_ldstpair_post"_h, &VISITORCLASS::VisitLoadStorePairPostIndex}, \
+ {"stp_32_ldstpair_post"_h, &VISITORCLASS::VisitLoadStorePairPostIndex}, \
+ {"stp_64_ldstpair_post"_h, &VISITORCLASS::VisitLoadStorePairPostIndex}, \
+ {"stp_d_ldstpair_post"_h, &VISITORCLASS::VisitLoadStorePairPostIndex}, \
+ {"stp_q_ldstpair_post"_h, &VISITORCLASS::VisitLoadStorePairPostIndex}, \
+ {"stp_s_ldstpair_post"_h, &VISITORCLASS::VisitLoadStorePairPostIndex}, \
+ {"ldpsw_64_ldstpair_pre"_h, &VISITORCLASS::VisitLoadStorePairPreIndex}, \
+ {"ldp_32_ldstpair_pre"_h, &VISITORCLASS::VisitLoadStorePairPreIndex}, \
+ {"ldp_64_ldstpair_pre"_h, &VISITORCLASS::VisitLoadStorePairPreIndex}, \
+ {"ldp_d_ldstpair_pre"_h, &VISITORCLASS::VisitLoadStorePairPreIndex}, \
+ {"ldp_q_ldstpair_pre"_h, &VISITORCLASS::VisitLoadStorePairPreIndex}, \
+ {"ldp_s_ldstpair_pre"_h, &VISITORCLASS::VisitLoadStorePairPreIndex}, \
+ {"stp_32_ldstpair_pre"_h, &VISITORCLASS::VisitLoadStorePairPreIndex}, \
+ {"stp_64_ldstpair_pre"_h, &VISITORCLASS::VisitLoadStorePairPreIndex}, \
+ {"stp_d_ldstpair_pre"_h, &VISITORCLASS::VisitLoadStorePairPreIndex}, \
+ {"stp_q_ldstpair_pre"_h, &VISITORCLASS::VisitLoadStorePairPreIndex}, \
+ {"stp_s_ldstpair_pre"_h, &VISITORCLASS::VisitLoadStorePairPreIndex}, \
+ {"ldrb_32_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldrh_32_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldrsb_32_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldrsb_64_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldrsh_32_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldrsh_64_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldrsw_64_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldr_32_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldr_64_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldr_b_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldr_d_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldr_h_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldr_q_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldr_s_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"strb_32_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"strh_32_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"str_32_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"str_64_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"str_b_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"str_d_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"str_h_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"str_q_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"str_s_ldst_immpost"_h, &VISITORCLASS::VisitLoadStorePostIndex}, \
+ {"ldrb_32_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldrh_32_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldrsb_32_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldrsb_64_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldrsh_32_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldrsh_64_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldrsw_64_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldr_32_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldr_64_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldr_b_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldr_d_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldr_h_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldr_q_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldr_s_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"strb_32_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"strh_32_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"str_32_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"str_64_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"str_b_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"str_d_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"str_h_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"str_q_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"str_s_ldst_immpre"_h, &VISITORCLASS::VisitLoadStorePreIndex}, \
+ {"ldapurb_32_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"ldapurh_32_ldapstl_unscaled", \
+ {"ldapurh_32_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"ldapursb_32_ldapstl_unscaled", \
+ {"ldapursb_32_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"ldapursb_64_ldapstl_unscaled", \
+ {"ldapursb_64_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"ldapursh_32_ldapstl_unscaled", \
+ {"ldapursh_32_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"ldapursh_64_ldapstl_unscaled", \
+ {"ldapursh_64_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"ldapursw_64_ldapstl_unscaled", \
+ {"ldapursw_64_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"ldapur_32_ldapstl_unscaled", \
+ {"ldapur_32_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"ldapur_64_ldapstl_unscaled", \
+ {"ldapur_64_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"stlurb_32_ldapstl_unscaled", \
+ {"stlurb_32_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"stlurh_32_ldapstl_unscaled", \
+ {"stlurh_32_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"stlur_32_ldapstl_unscaled", \
+ {"stlur_32_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"stlur_64_ldapstl_unscaled", \
+ {"stlur_64_ldapstl_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreRCpcUnscaledOffset}, \
- {"ldrb_32bl_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldrb_32b_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldrh_32_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldrsb_32bl_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldrsb_32b_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldrsb_64bl_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldrsb_64b_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldrsh_32_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldrsh_64_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldrsw_64_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldr_32_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldr_64_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldr_bl_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldr_b_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldr_d_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldr_h_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldr_q_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldr_s_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"prfm_p_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"strb_32bl_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"strb_32b_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"strh_32_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"str_32_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"str_64_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"str_bl_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"str_b_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"str_d_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"str_h_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"str_q_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"str_s_ldst_regoff", &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
- {"ldurb_32_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldurh_32_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldursb_32_ldst_unscaled", \
+ {"ldrb_32bl_ldst_regoff"_h, \
+ &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldrb_32b_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldrh_32_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldrsb_32bl_ldst_regoff"_h, \
+ &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldrsb_32b_ldst_regoff"_h, \
+ &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldrsb_64bl_ldst_regoff"_h, \
+ &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldrsb_64b_ldst_regoff"_h, \
+ &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldrsh_32_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldrsh_64_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldrsw_64_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldr_32_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldr_64_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldr_bl_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldr_b_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldr_d_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldr_h_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldr_q_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldr_s_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"prfm_p_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"strb_32bl_ldst_regoff"_h, \
+ &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"strb_32b_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"strh_32_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"str_32_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"str_64_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"str_bl_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"str_b_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"str_d_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"str_h_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"str_q_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"str_s_ldst_regoff"_h, &VISITORCLASS::VisitLoadStoreRegisterOffset}, \
+ {"ldurb_32_ldst_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldursb_64_ldst_unscaled", \
+ {"ldurh_32_ldst_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldursh_32_ldst_unscaled", \
+ {"ldursb_32_ldst_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldursh_64_ldst_unscaled", \
+ {"ldursb_64_ldst_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldursw_64_ldst_unscaled", \
+ {"ldursh_32_ldst_unscaled"_h, \
&VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldur_32_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldur_64_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldur_b_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldur_d_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldur_h_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldur_q_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldur_s_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"prfum_p_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"sturb_32_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"sturh_32_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"stur_32_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"stur_64_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"stur_b_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"stur_d_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"stur_h_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"stur_q_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"stur_s_ldst_unscaled", &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
- {"ldrb_32_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldrh_32_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldrsb_32_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldrsb_64_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldrsh_32_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldrsh_64_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldrsw_64_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldr_32_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldr_64_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldr_b_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldr_d_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldr_h_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldr_q_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ldr_s_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"prfm_p_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"strb_32_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"strh_32_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"str_32_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"str_64_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"str_b_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"str_d_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"str_h_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"str_q_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"str_s_ldst_pos", &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
- {"ands_32s_log_imm", &VISITORCLASS::VisitLogicalImmediate}, \
- {"ands_64s_log_imm", &VISITORCLASS::VisitLogicalImmediate}, \
- {"and_32_log_imm", &VISITORCLASS::VisitLogicalImmediate}, \
- {"and_64_log_imm", &VISITORCLASS::VisitLogicalImmediate}, \
- {"eor_32_log_imm", &VISITORCLASS::VisitLogicalImmediate}, \
- {"eor_64_log_imm", &VISITORCLASS::VisitLogicalImmediate}, \
- {"orr_32_log_imm", &VISITORCLASS::VisitLogicalImmediate}, \
- {"orr_64_log_imm", &VISITORCLASS::VisitLogicalImmediate}, \
- {"ands_32_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"ands_64_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"and_32_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"and_64_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"bics_32_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"bics_64_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"bic_32_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"bic_64_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"eon_32_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"eon_64_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"eor_32_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"eor_64_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"orn_32_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"orn_64_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"orr_32_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"orr_64_log_shift", &VISITORCLASS::VisitLogicalShifted}, \
- {"movk_32_movewide", &VISITORCLASS::VisitMoveWideImmediate}, \
- {"movk_64_movewide", &VISITORCLASS::VisitMoveWideImmediate}, \
- {"movn_32_movewide", &VISITORCLASS::VisitMoveWideImmediate}, \
- {"movn_64_movewide", &VISITORCLASS::VisitMoveWideImmediate}, \
- {"movz_32_movewide", &VISITORCLASS::VisitMoveWideImmediate}, \
- {"movz_64_movewide", &VISITORCLASS::VisitMoveWideImmediate}, \
- {"fabs_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcmeq_asimdmiscfp16_fz", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcmge_asimdmiscfp16_fz", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcmgt_asimdmiscfp16_fz", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcmle_asimdmiscfp16_fz", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcmlt_asimdmiscfp16_fz", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcvtas_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcvtau_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcvtms_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcvtmu_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcvtns_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcvtnu_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcvtps_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcvtpu_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcvtzs_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fcvtzu_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fneg_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"frecpe_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"frinta_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"frinti_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"frintm_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"frintn_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"frintp_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"frintx_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"frintz_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"frsqrte_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"fsqrt_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"scvtf_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"ucvtf_asimdmiscfp16_r", &VISITORCLASS::VisitNEON2RegMiscFP16}, \
- {"addhn_asimddiff_n", &VISITORCLASS::VisitNEON3Different}, \
- {"pmull_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"raddhn_asimddiff_n", &VISITORCLASS::VisitNEON3Different}, \
- {"rsubhn_asimddiff_n", &VISITORCLASS::VisitNEON3Different}, \
- {"sabal_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"sabdl_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"saddl_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"saddw_asimddiff_w", &VISITORCLASS::VisitNEON3Different}, \
- {"smlal_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"smlsl_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"smull_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"sqdmlal_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"sqdmlsl_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"sqdmull_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"ssubl_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"ssubw_asimddiff_w", &VISITORCLASS::VisitNEON3Different}, \
- {"subhn_asimddiff_n", &VISITORCLASS::VisitNEON3Different}, \
- {"uabal_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"uabdl_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"uaddl_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"uaddw_asimddiff_w", &VISITORCLASS::VisitNEON3Different}, \
- {"umlal_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"umlsl_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"umull_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"usubl_asimddiff_l", &VISITORCLASS::VisitNEON3Different}, \
- {"usubw_asimddiff_w", &VISITORCLASS::VisitNEON3Different}, \
- {"addp_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"add_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"cmeq_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"cmge_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"cmgt_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"cmhi_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"cmhs_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"cmtst_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fabd_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"facge_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"facgt_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"faddp_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fadd_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fcmeq_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fcmge_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fcmgt_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fdiv_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fmaxnmp_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fmaxnm_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fmaxp_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fmax_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fminnmp_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fminnm_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fminp_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fmin_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fmla_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fmls_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fmulx_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fmul_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"frecps_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"frsqrts_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fsub_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"sqadd_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"sqdmulh_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"sqrdmulh_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"sqrshl_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"sqshl_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"sqsub_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"srshl_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"sshl_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"sub_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"uqadd_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"uqrshl_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"uqshl_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"uqsub_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"urshl_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"ushl_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fcadd_asimdsame2_c", &VISITORCLASS::VisitNEON3SameExtra}, \
- {"fcmla_asimdsame2_c", &VISITORCLASS::VisitNEON3SameExtra}, \
- {"sdot_asimdsame2_d", &VISITORCLASS::VisitNEON3SameExtra}, \
- {"sqrdmlah_asimdsame2_only", &VISITORCLASS::VisitNEON3SameExtra}, \
- {"sqrdmlsh_asimdsame2_only", &VISITORCLASS::VisitNEON3SameExtra}, \
- {"udot_asimdsame2_d", &VISITORCLASS::VisitNEON3SameExtra}, \
- {"fabd_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"facge_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"facgt_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"faddp_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fadd_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fcmeq_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fcmge_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fcmgt_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fdiv_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fmaxnmp_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fmaxnm_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fmaxp_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fmax_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fminnmp_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fminnm_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fminp_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fmin_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fmla_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fmls_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fmulx_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fmul_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"frecps_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"frsqrts_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"fsub_asimdsamefp16_only", &VISITORCLASS::VisitNEON3SameFP16}, \
- {"addv_asimdall_only", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"saddlv_asimdall_only", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"smaxv_asimdall_only", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"sminv_asimdall_only", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"uaddlv_asimdall_only", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"umaxv_asimdall_only", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"uminv_asimdall_only", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"mla_asimdelem_r", &VISITORCLASS::VisitNEONByIndexedElement}, \
- {"mls_asimdelem_r", &VISITORCLASS::VisitNEONByIndexedElement}, \
- {"mul_asimdelem_r", &VISITORCLASS::VisitNEONByIndexedElement}, \
- {"sqdmulh_asimdelem_r", &VISITORCLASS::VisitNEONByIndexedElement}, \
- {"sqrdmlah_asimdelem_r", &VISITORCLASS::VisitNEONByIndexedElement}, \
- {"sqrdmlsh_asimdelem_r", &VISITORCLASS::VisitNEONByIndexedElement}, \
- {"sqrdmulh_asimdelem_r", &VISITORCLASS::VisitNEONByIndexedElement}, \
- {"dup_asimdins_dr_r", &VISITORCLASS::VisitNEONCopy}, \
- {"dup_asimdins_dv_v", &VISITORCLASS::VisitNEONCopy}, \
- {"ins_asimdins_ir_r", &VISITORCLASS::VisitNEONCopy}, \
- {"ins_asimdins_iv_v", &VISITORCLASS::VisitNEONCopy}, \
- {"smov_asimdins_w_w", &VISITORCLASS::VisitNEONCopy}, \
- {"smov_asimdins_x_x", &VISITORCLASS::VisitNEONCopy}, \
- {"umov_asimdins_w_w", &VISITORCLASS::VisitNEONCopy}, \
- {"umov_asimdins_x_x", &VISITORCLASS::VisitNEONCopy}, \
- {"ext_asimdext_only", &VISITORCLASS::VisitNEONExtract}, \
- {"ld1_asisdlse_r1_1v", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"ld1_asisdlse_r2_2v", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"ld1_asisdlse_r3_3v", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"ld1_asisdlse_r4_4v", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"ld2_asisdlse_r2", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"ld3_asisdlse_r3", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"ld4_asisdlse_r4", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"st1_asisdlse_r1_1v", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"st1_asisdlse_r2_2v", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"st1_asisdlse_r3_3v", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"st1_asisdlse_r4_4v", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"st2_asisdlse_r2", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"st3_asisdlse_r3", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"st4_asisdlse_r4", &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
- {"ld1_asisdlsep_i1_i1", \
+ {"ldursh_64_ldst_unscaled"_h, \
+ &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"ldursw_64_ldst_unscaled"_h, \
+ &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"ldur_32_ldst_unscaled"_h, \
+ &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"ldur_64_ldst_unscaled"_h, \
+ &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"ldur_b_ldst_unscaled"_h, &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"ldur_d_ldst_unscaled"_h, &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"ldur_h_ldst_unscaled"_h, &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"ldur_q_ldst_unscaled"_h, &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"ldur_s_ldst_unscaled"_h, &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"prfum_p_ldst_unscaled"_h, \
+ &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"sturb_32_ldst_unscaled"_h, \
+ &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"sturh_32_ldst_unscaled"_h, \
+ &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"stur_32_ldst_unscaled"_h, \
+ &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"stur_64_ldst_unscaled"_h, \
+ &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"stur_b_ldst_unscaled"_h, &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"stur_d_ldst_unscaled"_h, &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"stur_h_ldst_unscaled"_h, &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"stur_q_ldst_unscaled"_h, &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"stur_s_ldst_unscaled"_h, &VISITORCLASS::VisitLoadStoreUnscaledOffset}, \
+ {"ldrb_32_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldrh_32_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldrsb_32_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldrsb_64_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldrsh_32_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldrsh_64_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldrsw_64_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldr_32_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldr_64_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldr_b_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldr_d_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldr_h_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldr_q_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ldr_s_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"prfm_p_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"strb_32_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"strh_32_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"str_32_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"str_64_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"str_b_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"str_d_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"str_h_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"str_q_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"str_s_ldst_pos"_h, &VISITORCLASS::VisitLoadStoreUnsignedOffset}, \
+ {"ands_32s_log_imm"_h, &VISITORCLASS::VisitLogicalImmediate}, \
+ {"ands_64s_log_imm"_h, &VISITORCLASS::VisitLogicalImmediate}, \
+ {"and_32_log_imm"_h, &VISITORCLASS::VisitLogicalImmediate}, \
+ {"and_64_log_imm"_h, &VISITORCLASS::VisitLogicalImmediate}, \
+ {"eor_32_log_imm"_h, &VISITORCLASS::VisitLogicalImmediate}, \
+ {"eor_64_log_imm"_h, &VISITORCLASS::VisitLogicalImmediate}, \
+ {"orr_32_log_imm"_h, &VISITORCLASS::VisitLogicalImmediate}, \
+ {"orr_64_log_imm"_h, &VISITORCLASS::VisitLogicalImmediate}, \
+ {"ands_32_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"ands_64_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"and_32_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"and_64_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"bics_32_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"bics_64_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"bic_32_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"bic_64_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"eon_32_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"eon_64_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"eor_32_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"eor_64_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"orn_32_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"orn_64_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"orr_32_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"orr_64_log_shift"_h, &VISITORCLASS::VisitLogicalShifted}, \
+ {"movk_32_movewide"_h, &VISITORCLASS::VisitMoveWideImmediate}, \
+ {"movk_64_movewide"_h, &VISITORCLASS::VisitMoveWideImmediate}, \
+ {"movn_32_movewide"_h, &VISITORCLASS::VisitMoveWideImmediate}, \
+ {"movn_64_movewide"_h, &VISITORCLASS::VisitMoveWideImmediate}, \
+ {"movz_32_movewide"_h, &VISITORCLASS::VisitMoveWideImmediate}, \
+ {"movz_64_movewide"_h, &VISITORCLASS::VisitMoveWideImmediate}, \
+ {"fabs_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcmeq_asimdmiscfp16_fz"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcmge_asimdmiscfp16_fz"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcmgt_asimdmiscfp16_fz"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcmle_asimdmiscfp16_fz"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcmlt_asimdmiscfp16_fz"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcvtas_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcvtau_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcvtms_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcvtmu_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcvtns_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcvtnu_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcvtps_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcvtpu_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcvtzs_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fcvtzu_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fneg_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"frecpe_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"frinta_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"frinti_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"frintm_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"frintn_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"frintp_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"frintx_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"frintz_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"frsqrte_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"fsqrt_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"scvtf_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"ucvtf_asimdmiscfp16_r"_h, &VISITORCLASS::VisitNEON2RegMiscFP16}, \
+ {"addhn_asimddiff_n"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"pmull_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"raddhn_asimddiff_n"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"rsubhn_asimddiff_n"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"sabal_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"sabdl_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"saddl_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"saddw_asimddiff_w"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"smlal_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"smlsl_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"smull_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"sqdmlal_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"sqdmlsl_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"sqdmull_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"ssubl_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"ssubw_asimddiff_w"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"subhn_asimddiff_n"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"uabal_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"uabdl_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"uaddl_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"uaddw_asimddiff_w"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"umlal_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"umlsl_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"umull_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"usubl_asimddiff_l"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"usubw_asimddiff_w"_h, &VISITORCLASS::VisitNEON3Different}, \
+ {"addp_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"add_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"cmeq_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"cmge_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"cmgt_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"cmhi_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"cmhs_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"cmtst_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fabd_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"facge_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"facgt_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"faddp_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fadd_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fcmeq_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fcmge_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fcmgt_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fdiv_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmaxnmp_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmaxnm_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmaxp_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmax_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fminnmp_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fminnm_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fminp_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmin_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmla_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmls_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmulx_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmul_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"frecps_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"frsqrts_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fsub_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"sqadd_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"sqdmulh_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"sqrdmulh_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"sqrshl_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"sqshl_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"sqsub_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"srshl_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"sshl_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"sub_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"uqadd_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"uqrshl_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"uqshl_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"uqsub_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"urshl_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"ushl_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fcadd_asimdsame2_c"_h, &VISITORCLASS::VisitNEON3SameExtra}, \
+ {"fcmla_asimdsame2_c"_h, &VISITORCLASS::VisitNEON3SameExtra}, \
+ {"sdot_asimdsame2_d"_h, &VISITORCLASS::VisitNEON3SameExtra}, \
+ {"sqrdmlah_asimdsame2_only"_h, &VISITORCLASS::VisitNEON3SameExtra}, \
+ {"sqrdmlsh_asimdsame2_only"_h, &VISITORCLASS::VisitNEON3SameExtra}, \
+ {"udot_asimdsame2_d"_h, &VISITORCLASS::VisitNEON3SameExtra}, \
+ {"fabd_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"facge_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"facgt_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"faddp_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fadd_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fcmeq_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fcmge_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fcmgt_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fdiv_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fmaxnmp_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fmaxnm_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fmaxp_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fmax_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fminnmp_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fminnm_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fminp_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fmin_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fmla_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fmls_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fmulx_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fmul_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"frecps_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"frsqrts_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"fsub_asimdsamefp16_only"_h, &VISITORCLASS::VisitNEON3SameFP16}, \
+ {"addv_asimdall_only"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"saddlv_asimdall_only"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"smaxv_asimdall_only"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"sminv_asimdall_only"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"uaddlv_asimdall_only"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"umaxv_asimdall_only"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"uminv_asimdall_only"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"mla_asimdelem_r"_h, &VISITORCLASS::VisitNEONByIndexedElement}, \
+ {"mls_asimdelem_r"_h, &VISITORCLASS::VisitNEONByIndexedElement}, \
+ {"mul_asimdelem_r"_h, &VISITORCLASS::VisitNEONByIndexedElement}, \
+ {"sqdmulh_asimdelem_r"_h, &VISITORCLASS::VisitNEONByIndexedElement}, \
+ {"sqrdmlah_asimdelem_r"_h, &VISITORCLASS::VisitNEONByIndexedElement}, \
+ {"sqrdmlsh_asimdelem_r"_h, &VISITORCLASS::VisitNEONByIndexedElement}, \
+ {"sqrdmulh_asimdelem_r"_h, &VISITORCLASS::VisitNEONByIndexedElement}, \
+ {"dup_asimdins_dr_r"_h, &VISITORCLASS::VisitNEONCopy}, \
+ {"dup_asimdins_dv_v"_h, &VISITORCLASS::VisitNEONCopy}, \
+ {"ins_asimdins_ir_r"_h, &VISITORCLASS::VisitNEONCopy}, \
+ {"ins_asimdins_iv_v"_h, &VISITORCLASS::VisitNEONCopy}, \
+ {"smov_asimdins_w_w"_h, &VISITORCLASS::VisitNEONCopy}, \
+ {"smov_asimdins_x_x"_h, &VISITORCLASS::VisitNEONCopy}, \
+ {"umov_asimdins_w_w"_h, &VISITORCLASS::VisitNEONCopy}, \
+ {"umov_asimdins_x_x"_h, &VISITORCLASS::VisitNEONCopy}, \
+ {"ext_asimdext_only"_h, &VISITORCLASS::VisitNEONExtract}, \
+ {"ld1_asisdlse_r1_1v"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"ld1_asisdlse_r2_2v"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"ld1_asisdlse_r3_3v"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"ld1_asisdlse_r4_4v"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"ld2_asisdlse_r2"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"ld3_asisdlse_r3"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"ld4_asisdlse_r4"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"st1_asisdlse_r1_1v"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"st1_asisdlse_r2_2v"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"st1_asisdlse_r3_3v"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"st1_asisdlse_r4_4v"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"st2_asisdlse_r2"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"st3_asisdlse_r3"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"st4_asisdlse_r4"_h, &VISITORCLASS::VisitNEONLoadStoreMultiStruct}, \
+ {"ld1_asisdlsep_i1_i1"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld1_asisdlsep_i2_i2", \
+ {"ld1_asisdlsep_i2_i2"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld1_asisdlsep_i3_i3", \
+ {"ld1_asisdlsep_i3_i3"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld1_asisdlsep_i4_i4", \
+ {"ld1_asisdlsep_i4_i4"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld1_asisdlsep_r1_r1", \
+ {"ld1_asisdlsep_r1_r1"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld1_asisdlsep_r2_r2", \
+ {"ld1_asisdlsep_r2_r2"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld1_asisdlsep_r3_r3", \
+ {"ld1_asisdlsep_r3_r3"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld1_asisdlsep_r4_r4", \
+ {"ld1_asisdlsep_r4_r4"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld2_asisdlsep_i2_i", \
+ {"ld2_asisdlsep_i2_i"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld2_asisdlsep_r2_r", \
+ {"ld2_asisdlsep_r2_r"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld3_asisdlsep_i3_i", \
+ {"ld3_asisdlsep_i3_i"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld3_asisdlsep_r3_r", \
+ {"ld3_asisdlsep_r3_r"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld4_asisdlsep_i4_i", \
+ {"ld4_asisdlsep_i4_i"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld4_asisdlsep_r4_r", \
+ {"ld4_asisdlsep_r4_r"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st1_asisdlsep_i1_i1", \
+ {"st1_asisdlsep_i1_i1"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st1_asisdlsep_i2_i2", \
+ {"st1_asisdlsep_i2_i2"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st1_asisdlsep_i3_i3", \
+ {"st1_asisdlsep_i3_i3"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st1_asisdlsep_i4_i4", \
+ {"st1_asisdlsep_i4_i4"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st1_asisdlsep_r1_r1", \
+ {"st1_asisdlsep_r1_r1"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st1_asisdlsep_r2_r2", \
+ {"st1_asisdlsep_r2_r2"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st1_asisdlsep_r3_r3", \
+ {"st1_asisdlsep_r3_r3"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st1_asisdlsep_r4_r4", \
+ {"st1_asisdlsep_r4_r4"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st2_asisdlsep_i2_i", \
+ {"st2_asisdlsep_i2_i"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st2_asisdlsep_r2_r", \
+ {"st2_asisdlsep_r2_r"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st3_asisdlsep_i3_i", \
+ {"st3_asisdlsep_i3_i"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st3_asisdlsep_r3_r", \
+ {"st3_asisdlsep_r3_r"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st4_asisdlsep_i4_i", \
+ {"st4_asisdlsep_i4_i"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"st4_asisdlsep_r4_r", \
+ {"st4_asisdlsep_r4_r"_h, \
&VISITORCLASS::VisitNEONLoadStoreMultiStructPostIndex}, \
- {"ld1r_asisdlso_r1", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld1_asisdlso_b1_1b", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld1_asisdlso_d1_1d", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld1_asisdlso_h1_1h", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld1_asisdlso_s1_1s", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld2r_asisdlso_r2", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld2_asisdlso_b2_2b", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld2_asisdlso_d2_2d", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld2_asisdlso_h2_2h", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld2_asisdlso_s2_2s", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld3r_asisdlso_r3", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld3_asisdlso_b3_3b", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld3_asisdlso_d3_3d", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld3_asisdlso_h3_3h", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld3_asisdlso_s3_3s", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld4r_asisdlso_r4", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld4_asisdlso_b4_4b", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld4_asisdlso_d4_4d", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld4_asisdlso_h4_4h", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld4_asisdlso_s4_4s", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st1_asisdlso_b1_1b", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st1_asisdlso_d1_1d", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st1_asisdlso_h1_1h", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st1_asisdlso_s1_1s", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st2_asisdlso_b2_2b", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st2_asisdlso_d2_2d", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st2_asisdlso_h2_2h", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st2_asisdlso_s2_2s", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st3_asisdlso_b3_3b", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st3_asisdlso_d3_3d", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st3_asisdlso_h3_3h", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st3_asisdlso_s3_3s", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st4_asisdlso_b4_4b", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st4_asisdlso_d4_4d", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st4_asisdlso_h4_4h", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"st4_asisdlso_s4_4s", &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
- {"ld1r_asisdlsop_r1_i", \
+ {"ld1r_asisdlso_r1"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld1_asisdlso_b1_1b"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld1_asisdlso_d1_1d"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld1_asisdlso_h1_1h"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld1_asisdlso_s1_1s"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld2r_asisdlso_r2"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld2_asisdlso_b2_2b"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld2_asisdlso_d2_2d"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld2_asisdlso_h2_2h"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld2_asisdlso_s2_2s"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld3r_asisdlso_r3"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld3_asisdlso_b3_3b"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld3_asisdlso_d3_3d"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld3_asisdlso_h3_3h"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld3_asisdlso_s3_3s"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld4r_asisdlso_r4"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld4_asisdlso_b4_4b"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld4_asisdlso_d4_4d"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld4_asisdlso_h4_4h"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld4_asisdlso_s4_4s"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st1_asisdlso_b1_1b"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st1_asisdlso_d1_1d"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st1_asisdlso_h1_1h"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st1_asisdlso_s1_1s"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st2_asisdlso_b2_2b"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st2_asisdlso_d2_2d"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st2_asisdlso_h2_2h"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st2_asisdlso_s2_2s"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st3_asisdlso_b3_3b"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st3_asisdlso_d3_3d"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st3_asisdlso_h3_3h"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st3_asisdlso_s3_3s"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st4_asisdlso_b4_4b"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st4_asisdlso_d4_4d"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st4_asisdlso_h4_4h"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"st4_asisdlso_s4_4s"_h, &VISITORCLASS::VisitNEONLoadStoreSingleStruct}, \
+ {"ld1r_asisdlsop_r1_i"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld1r_asisdlsop_rx1_r", \
+ {"ld1r_asisdlsop_rx1_r"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld1_asisdlsop_b1_i1b", \
+ {"ld1_asisdlsop_b1_i1b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld1_asisdlsop_bx1_r1b", \
+ {"ld1_asisdlsop_bx1_r1b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld1_asisdlsop_d1_i1d", \
+ {"ld1_asisdlsop_d1_i1d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld1_asisdlsop_dx1_r1d", \
+ {"ld1_asisdlsop_dx1_r1d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld1_asisdlsop_h1_i1h", \
+ {"ld1_asisdlsop_h1_i1h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld1_asisdlsop_hx1_r1h", \
+ {"ld1_asisdlsop_hx1_r1h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld1_asisdlsop_s1_i1s", \
+ {"ld1_asisdlsop_s1_i1s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld1_asisdlsop_sx1_r1s", \
+ {"ld1_asisdlsop_sx1_r1s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld2r_asisdlsop_r2_i", \
+ {"ld2r_asisdlsop_r2_i"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld2r_asisdlsop_rx2_r", \
+ {"ld2r_asisdlsop_rx2_r"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld2_asisdlsop_b2_i2b", \
+ {"ld2_asisdlsop_b2_i2b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld2_asisdlsop_bx2_r2b", \
+ {"ld2_asisdlsop_bx2_r2b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld2_asisdlsop_d2_i2d", \
+ {"ld2_asisdlsop_d2_i2d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld2_asisdlsop_dx2_r2d", \
+ {"ld2_asisdlsop_dx2_r2d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld2_asisdlsop_h2_i2h", \
+ {"ld2_asisdlsop_h2_i2h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld2_asisdlsop_hx2_r2h", \
+ {"ld2_asisdlsop_hx2_r2h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld2_asisdlsop_s2_i2s", \
+ {"ld2_asisdlsop_s2_i2s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld2_asisdlsop_sx2_r2s", \
+ {"ld2_asisdlsop_sx2_r2s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld3r_asisdlsop_r3_i", \
+ {"ld3r_asisdlsop_r3_i"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld3r_asisdlsop_rx3_r", \
+ {"ld3r_asisdlsop_rx3_r"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld3_asisdlsop_b3_i3b", \
+ {"ld3_asisdlsop_b3_i3b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld3_asisdlsop_bx3_r3b", \
+ {"ld3_asisdlsop_bx3_r3b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld3_asisdlsop_d3_i3d", \
+ {"ld3_asisdlsop_d3_i3d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld3_asisdlsop_dx3_r3d", \
+ {"ld3_asisdlsop_dx3_r3d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld3_asisdlsop_h3_i3h", \
+ {"ld3_asisdlsop_h3_i3h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld3_asisdlsop_hx3_r3h", \
+ {"ld3_asisdlsop_hx3_r3h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld3_asisdlsop_s3_i3s", \
+ {"ld3_asisdlsop_s3_i3s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld3_asisdlsop_sx3_r3s", \
+ {"ld3_asisdlsop_sx3_r3s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld4r_asisdlsop_r4_i", \
+ {"ld4r_asisdlsop_r4_i"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld4r_asisdlsop_rx4_r", \
+ {"ld4r_asisdlsop_rx4_r"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld4_asisdlsop_b4_i4b", \
+ {"ld4_asisdlsop_b4_i4b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld4_asisdlsop_bx4_r4b", \
+ {"ld4_asisdlsop_bx4_r4b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld4_asisdlsop_d4_i4d", \
+ {"ld4_asisdlsop_d4_i4d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld4_asisdlsop_dx4_r4d", \
+ {"ld4_asisdlsop_dx4_r4d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld4_asisdlsop_h4_i4h", \
+ {"ld4_asisdlsop_h4_i4h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld4_asisdlsop_hx4_r4h", \
+ {"ld4_asisdlsop_hx4_r4h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld4_asisdlsop_s4_i4s", \
+ {"ld4_asisdlsop_s4_i4s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"ld4_asisdlsop_sx4_r4s", \
+ {"ld4_asisdlsop_sx4_r4s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st1_asisdlsop_b1_i1b", \
+ {"st1_asisdlsop_b1_i1b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st1_asisdlsop_bx1_r1b", \
+ {"st1_asisdlsop_bx1_r1b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st1_asisdlsop_d1_i1d", \
+ {"st1_asisdlsop_d1_i1d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st1_asisdlsop_dx1_r1d", \
+ {"st1_asisdlsop_dx1_r1d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st1_asisdlsop_h1_i1h", \
+ {"st1_asisdlsop_h1_i1h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st1_asisdlsop_hx1_r1h", \
+ {"st1_asisdlsop_hx1_r1h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st1_asisdlsop_s1_i1s", \
+ {"st1_asisdlsop_s1_i1s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st1_asisdlsop_sx1_r1s", \
+ {"st1_asisdlsop_sx1_r1s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st2_asisdlsop_b2_i2b", \
+ {"st2_asisdlsop_b2_i2b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st2_asisdlsop_bx2_r2b", \
+ {"st2_asisdlsop_bx2_r2b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st2_asisdlsop_d2_i2d", \
+ {"st2_asisdlsop_d2_i2d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st2_asisdlsop_dx2_r2d", \
+ {"st2_asisdlsop_dx2_r2d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st2_asisdlsop_h2_i2h", \
+ {"st2_asisdlsop_h2_i2h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st2_asisdlsop_hx2_r2h", \
+ {"st2_asisdlsop_hx2_r2h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st2_asisdlsop_s2_i2s", \
+ {"st2_asisdlsop_s2_i2s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st2_asisdlsop_sx2_r2s", \
+ {"st2_asisdlsop_sx2_r2s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st3_asisdlsop_b3_i3b", \
+ {"st3_asisdlsop_b3_i3b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st3_asisdlsop_bx3_r3b", \
+ {"st3_asisdlsop_bx3_r3b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st3_asisdlsop_d3_i3d", \
+ {"st3_asisdlsop_d3_i3d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st3_asisdlsop_dx3_r3d", \
+ {"st3_asisdlsop_dx3_r3d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st3_asisdlsop_h3_i3h", \
+ {"st3_asisdlsop_h3_i3h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st3_asisdlsop_hx3_r3h", \
+ {"st3_asisdlsop_hx3_r3h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st3_asisdlsop_s3_i3s", \
+ {"st3_asisdlsop_s3_i3s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st3_asisdlsop_sx3_r3s", \
+ {"st3_asisdlsop_sx3_r3s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st4_asisdlsop_b4_i4b", \
+ {"st4_asisdlsop_b4_i4b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st4_asisdlsop_bx4_r4b", \
+ {"st4_asisdlsop_bx4_r4b"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st4_asisdlsop_d4_i4d", \
+ {"st4_asisdlsop_d4_i4d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st4_asisdlsop_dx4_r4d", \
+ {"st4_asisdlsop_dx4_r4d"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st4_asisdlsop_h4_i4h", \
+ {"st4_asisdlsop_h4_i4h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st4_asisdlsop_hx4_r4h", \
+ {"st4_asisdlsop_hx4_r4h"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st4_asisdlsop_s4_i4s", \
+ {"st4_asisdlsop_s4_i4s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"st4_asisdlsop_sx4_r4s", \
+ {"st4_asisdlsop_sx4_r4s"_h, \
&VISITORCLASS::VisitNEONLoadStoreSingleStructPostIndex}, \
- {"bic_asimdimm_l_hl", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"bic_asimdimm_l_sl", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"fmov_asimdimm_d2_d", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"fmov_asimdimm_h_h", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"fmov_asimdimm_s_s", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"movi_asimdimm_d2_d", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"movi_asimdimm_d_ds", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"movi_asimdimm_l_hl", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"movi_asimdimm_l_sl", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"movi_asimdimm_m_sm", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"movi_asimdimm_n_b", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"mvni_asimdimm_l_hl", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"mvni_asimdimm_l_sl", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"mvni_asimdimm_m_sm", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"orr_asimdimm_l_hl", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"orr_asimdimm_l_sl", &VISITORCLASS::VisitNEONModifiedImmediate}, \
- {"trn1_asimdperm_only", &VISITORCLASS::VisitNEONPerm}, \
- {"trn2_asimdperm_only", &VISITORCLASS::VisitNEONPerm}, \
- {"uzp1_asimdperm_only", &VISITORCLASS::VisitNEONPerm}, \
- {"uzp2_asimdperm_only", &VISITORCLASS::VisitNEONPerm}, \
- {"zip1_asimdperm_only", &VISITORCLASS::VisitNEONPerm}, \
- {"zip2_asimdperm_only", &VISITORCLASS::VisitNEONPerm}, \
- {"sqabs_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"sqneg_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"sqxtn_asisdmisc_n", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"sqxtun_asisdmisc_n", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"suqadd_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"uqxtn_asisdmisc_n", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"usqadd_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcmeq_asisdmiscfp16_fz", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcmge_asisdmiscfp16_fz", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcmgt_asisdmiscfp16_fz", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcmle_asisdmiscfp16_fz", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcmlt_asisdmiscfp16_fz", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcvtas_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcvtau_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcvtms_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcvtmu_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcvtns_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcvtnu_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcvtps_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcvtpu_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcvtzs_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"fcvtzu_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"frecpe_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"frecpx_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"frsqrte_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"scvtf_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"ucvtf_asisdmiscfp16_r", &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
- {"sqdmlal_asisddiff_only", &VISITORCLASS::VisitNEONScalar3Diff}, \
- {"sqdmlsl_asisddiff_only", &VISITORCLASS::VisitNEONScalar3Diff}, \
- {"sqdmull_asisddiff_only", &VISITORCLASS::VisitNEONScalar3Diff}, \
- {"sqadd_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"sqdmulh_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"sqrdmulh_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"sqrshl_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"sqshl_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"sqsub_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"srshl_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"sshl_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"uqadd_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"uqrshl_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"uqshl_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"uqsub_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"urshl_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"ushl_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"fabd_asisdsamefp16_only", &VISITORCLASS::VisitNEONScalar3SameFP16}, \
- {"facge_asisdsamefp16_only", &VISITORCLASS::VisitNEONScalar3SameFP16}, \
- {"facgt_asisdsamefp16_only", &VISITORCLASS::VisitNEONScalar3SameFP16}, \
- {"fcmeq_asisdsamefp16_only", &VISITORCLASS::VisitNEONScalar3SameFP16}, \
- {"fcmge_asisdsamefp16_only", &VISITORCLASS::VisitNEONScalar3SameFP16}, \
- {"fcmgt_asisdsamefp16_only", &VISITORCLASS::VisitNEONScalar3SameFP16}, \
- {"fmulx_asisdsamefp16_only", &VISITORCLASS::VisitNEONScalar3SameFP16}, \
- {"frecps_asisdsamefp16_only", &VISITORCLASS::VisitNEONScalar3SameFP16}, \
- {"frsqrts_asisdsamefp16_only", &VISITORCLASS::VisitNEONScalar3SameFP16}, \
- {"sqdmulh_asisdelem_r", &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"sqrdmlah_asisdelem_r", \
+ {"bic_asimdimm_l_hl"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"bic_asimdimm_l_sl"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"fmov_asimdimm_d2_d"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"fmov_asimdimm_h_h"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"fmov_asimdimm_s_s"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"movi_asimdimm_d2_d"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"movi_asimdimm_d_ds"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"movi_asimdimm_l_hl"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"movi_asimdimm_l_sl"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"movi_asimdimm_m_sm"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"movi_asimdimm_n_b"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"mvni_asimdimm_l_hl"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"mvni_asimdimm_l_sl"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"mvni_asimdimm_m_sm"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"orr_asimdimm_l_hl"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"orr_asimdimm_l_sl"_h, &VISITORCLASS::VisitNEONModifiedImmediate}, \
+ {"trn1_asimdperm_only"_h, &VISITORCLASS::VisitNEONPerm}, \
+ {"trn2_asimdperm_only"_h, &VISITORCLASS::VisitNEONPerm}, \
+ {"uzp1_asimdperm_only"_h, &VISITORCLASS::VisitNEONPerm}, \
+ {"uzp2_asimdperm_only"_h, &VISITORCLASS::VisitNEONPerm}, \
+ {"zip1_asimdperm_only"_h, &VISITORCLASS::VisitNEONPerm}, \
+ {"zip2_asimdperm_only"_h, &VISITORCLASS::VisitNEONPerm}, \
+ {"sqabs_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"sqneg_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"sqxtn_asisdmisc_n"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"sqxtun_asisdmisc_n"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"suqadd_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"uqxtn_asisdmisc_n"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"usqadd_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcmeq_asisdmiscfp16_fz"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcmge_asisdmiscfp16_fz"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcmgt_asisdmiscfp16_fz"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcmle_asisdmiscfp16_fz"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcmlt_asisdmiscfp16_fz"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcvtas_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcvtau_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcvtms_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcvtmu_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcvtns_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcvtnu_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcvtps_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcvtpu_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcvtzs_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"fcvtzu_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"frecpe_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"frecpx_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"frsqrte_asisdmiscfp16_r"_h, \
+ &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"scvtf_asisdmiscfp16_r"_h, &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"ucvtf_asisdmiscfp16_r"_h, &VISITORCLASS::VisitNEONScalar2RegMiscFP16}, \
+ {"sqdmlal_asisddiff_only"_h, &VISITORCLASS::VisitNEONScalar3Diff}, \
+ {"sqdmlsl_asisddiff_only"_h, &VISITORCLASS::VisitNEONScalar3Diff}, \
+ {"sqdmull_asisddiff_only"_h, &VISITORCLASS::VisitNEONScalar3Diff}, \
+ {"sqadd_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"sqdmulh_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"sqrdmulh_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"sqrshl_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"sqshl_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"sqsub_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"srshl_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"sshl_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"uqadd_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"uqrshl_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"uqshl_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"uqsub_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"urshl_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"ushl_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"fabd_asisdsamefp16_only"_h, &VISITORCLASS::VisitNEONScalar3SameFP16}, \
+ {"facge_asisdsamefp16_only"_h, &VISITORCLASS::VisitNEONScalar3SameFP16}, \
+ {"facgt_asisdsamefp16_only"_h, &VISITORCLASS::VisitNEONScalar3SameFP16}, \
+ {"fcmeq_asisdsamefp16_only"_h, &VISITORCLASS::VisitNEONScalar3SameFP16}, \
+ {"fcmge_asisdsamefp16_only"_h, &VISITORCLASS::VisitNEONScalar3SameFP16}, \
+ {"fcmgt_asisdsamefp16_only"_h, &VISITORCLASS::VisitNEONScalar3SameFP16}, \
+ {"fmulx_asisdsamefp16_only"_h, &VISITORCLASS::VisitNEONScalar3SameFP16}, \
+ {"frecps_asisdsamefp16_only"_h, \
+ &VISITORCLASS::VisitNEONScalar3SameFP16}, \
+ {"frsqrts_asisdsamefp16_only"_h, \
+ &VISITORCLASS::VisitNEONScalar3SameFP16}, \
+ {"sqdmulh_asisdelem_r"_h, \
&VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"sqrdmlsh_asisdelem_r", \
+ {"sqrdmlah_asisdelem_r"_h, \
&VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"sqrdmulh_asisdelem_r", \
+ {"sqrdmlsh_asisdelem_r"_h, \
&VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"dup_asisdone_only", &VISITORCLASS::VisitNEONScalarCopy}, \
- {"addp_asisdpair_only", &VISITORCLASS::VisitNEONScalarPairwise}, \
- {"faddp_asisdpair_only_h", &VISITORCLASS::VisitNEONScalarPairwise}, \
- {"faddp_asisdpair_only_sd", &VISITORCLASS::VisitNEONScalarPairwise}, \
- {"fmaxnmp_asisdpair_only_h", &VISITORCLASS::VisitNEONScalarPairwise}, \
- {"fmaxnmp_asisdpair_only_sd", &VISITORCLASS::VisitNEONScalarPairwise}, \
- {"fmaxp_asisdpair_only_h", &VISITORCLASS::VisitNEONScalarPairwise}, \
- {"fmaxp_asisdpair_only_sd", &VISITORCLASS::VisitNEONScalarPairwise}, \
- {"fminnmp_asisdpair_only_h", &VISITORCLASS::VisitNEONScalarPairwise}, \
- {"fminnmp_asisdpair_only_sd", &VISITORCLASS::VisitNEONScalarPairwise}, \
- {"fminp_asisdpair_only_h", &VISITORCLASS::VisitNEONScalarPairwise}, \
- {"fminp_asisdpair_only_sd", &VISITORCLASS::VisitNEONScalarPairwise}, \
- {"fcvtzs_asisdshf_c", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"fcvtzu_asisdshf_c", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"scvtf_asisdshf_c", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"sqshlu_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"sqshl_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"ucvtf_asisdshf_c", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"uqshl_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"sqshlu_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"sqshl_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"uqshl_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"shl_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"sli_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"tbl_asimdtbl_l1_1", &VISITORCLASS::VisitNEONTable}, \
- {"tbl_asimdtbl_l2_2", &VISITORCLASS::VisitNEONTable}, \
- {"tbl_asimdtbl_l3_3", &VISITORCLASS::VisitNEONTable}, \
- {"tbl_asimdtbl_l4_4", &VISITORCLASS::VisitNEONTable}, \
- {"tbx_asimdtbl_l1_1", &VISITORCLASS::VisitNEONTable}, \
- {"tbx_asimdtbl_l2_2", &VISITORCLASS::VisitNEONTable}, \
- {"tbx_asimdtbl_l3_3", &VISITORCLASS::VisitNEONTable}, \
- {"tbx_asimdtbl_l4_4", &VISITORCLASS::VisitNEONTable}, \
- {"adrp_only_pcreladdr", &VISITORCLASS::VisitPCRelAddressing}, \
- {"adr_only_pcreladdr", &VISITORCLASS::VisitPCRelAddressing}, \
- {"rmif_only_rmif", &VISITORCLASS::VisitRotateRightIntoFlags}, \
- {"bti_hb_hints", &VISITORCLASS::VisitSystem}, \
- {"clrex_bn_barriers", &VISITORCLASS::VisitSystem}, \
- {"dmb_bo_barriers", &VISITORCLASS::VisitSystem}, \
- {"dsb_bo_barriers", &VISITORCLASS::VisitSystem}, \
- {"hint_hm_hints", &VISITORCLASS::VisitSystem}, \
- {"mrs_rs_systemmove", &VISITORCLASS::VisitSystem}, \
- {"msr_si_pstate", &VISITORCLASS::VisitSystem}, \
- {"msr_sr_systemmove", &VISITORCLASS::VisitSystem}, \
- {"psb_hc_hints", &VISITORCLASS::VisitSystem}, \
- {"sb_only_barriers", &VISITORCLASS::VisitSystem}, \
- {"sysl_rc_systeminstrs", &VISITORCLASS::VisitSystem}, \
- {"sys_cr_systeminstrs", &VISITORCLASS::VisitSystem}, \
- {"tcommit_only_barriers", &VISITORCLASS::VisitSystem}, \
- {"tsb_hc_hints", &VISITORCLASS::VisitSystem}, \
- {"tbnz_only_testbranch", &VISITORCLASS::VisitTestBranch}, \
- {"tbz_only_testbranch", &VISITORCLASS::VisitTestBranch}, \
- {"bl_only_branch_imm", &VISITORCLASS::VisitUnconditionalBranch}, \
- {"b_only_branch_imm", &VISITORCLASS::VisitUnconditionalBranch}, \
- {"blraaz_64_branch_reg", \
+ {"sqrdmulh_asisdelem_r"_h, \
+ &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
+ {"dup_asisdone_only"_h, &VISITORCLASS::VisitNEONScalarCopy}, \
+ {"addp_asisdpair_only"_h, &VISITORCLASS::VisitNEONScalarPairwise}, \
+ {"faddp_asisdpair_only_h"_h, &VISITORCLASS::VisitNEONScalarPairwise}, \
+ {"faddp_asisdpair_only_sd"_h, &VISITORCLASS::VisitNEONScalarPairwise}, \
+ {"fmaxnmp_asisdpair_only_h"_h, &VISITORCLASS::VisitNEONScalarPairwise}, \
+ {"fmaxnmp_asisdpair_only_sd"_h, &VISITORCLASS::VisitNEONScalarPairwise}, \
+ {"fmaxp_asisdpair_only_h"_h, &VISITORCLASS::VisitNEONScalarPairwise}, \
+ {"fmaxp_asisdpair_only_sd"_h, &VISITORCLASS::VisitNEONScalarPairwise}, \
+ {"fminnmp_asisdpair_only_h"_h, &VISITORCLASS::VisitNEONScalarPairwise}, \
+ {"fminnmp_asisdpair_only_sd"_h, &VISITORCLASS::VisitNEONScalarPairwise}, \
+ {"fminp_asisdpair_only_h"_h, &VISITORCLASS::VisitNEONScalarPairwise}, \
+ {"fminp_asisdpair_only_sd"_h, &VISITORCLASS::VisitNEONScalarPairwise}, \
+ {"fcvtzs_asisdshf_c"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"fcvtzu_asisdshf_c"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"scvtf_asisdshf_c"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"sqshlu_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"sqshl_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"ucvtf_asisdshf_c"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"uqshl_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"sqshlu_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"sqshl_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"uqshl_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"shl_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"sli_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"tbl_asimdtbl_l1_1"_h, &VISITORCLASS::VisitNEONTable}, \
+ {"tbl_asimdtbl_l2_2"_h, &VISITORCLASS::VisitNEONTable}, \
+ {"tbl_asimdtbl_l3_3"_h, &VISITORCLASS::VisitNEONTable}, \
+ {"tbl_asimdtbl_l4_4"_h, &VISITORCLASS::VisitNEONTable}, \
+ {"tbx_asimdtbl_l1_1"_h, &VISITORCLASS::VisitNEONTable}, \
+ {"tbx_asimdtbl_l2_2"_h, &VISITORCLASS::VisitNEONTable}, \
+ {"tbx_asimdtbl_l3_3"_h, &VISITORCLASS::VisitNEONTable}, \
+ {"tbx_asimdtbl_l4_4"_h, &VISITORCLASS::VisitNEONTable}, \
+ {"adrp_only_pcreladdr"_h, &VISITORCLASS::VisitPCRelAddressing}, \
+ {"adr_only_pcreladdr"_h, &VISITORCLASS::VisitPCRelAddressing}, \
+ {"rmif_only_rmif"_h, &VISITORCLASS::VisitRotateRightIntoFlags}, \
+ {"bti_hb_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"clrex_bn_barriers"_h, &VISITORCLASS::VisitSystem}, \
+ {"dmb_bo_barriers"_h, &VISITORCLASS::VisitSystem}, \
+ {"dsb_bo_barriers"_h, &VISITORCLASS::VisitSystem}, \
+ {"hint_hm_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"mrs_rs_systemmove"_h, &VISITORCLASS::VisitSystem}, \
+ {"msr_si_pstate"_h, &VISITORCLASS::VisitSystem}, \
+ {"msr_sr_systemmove"_h, &VISITORCLASS::VisitSystem}, \
+ {"psb_hc_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"sb_only_barriers"_h, &VISITORCLASS::VisitSystem}, \
+ {"sysl_rc_systeminstrs"_h, &VISITORCLASS::VisitSystem}, \
+ {"sys_cr_systeminstrs"_h, &VISITORCLASS::VisitSystem}, \
+ {"tcommit_only_barriers"_h, &VISITORCLASS::VisitSystem}, \
+ {"tsb_hc_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"tbnz_only_testbranch"_h, &VISITORCLASS::VisitTestBranch}, \
+ {"tbz_only_testbranch"_h, &VISITORCLASS::VisitTestBranch}, \
+ {"bl_only_branch_imm"_h, &VISITORCLASS::VisitUnconditionalBranch}, \
+ {"b_only_branch_imm"_h, &VISITORCLASS::VisitUnconditionalBranch}, \
+ {"blraaz_64_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"blraa_64p_branch_reg", \
+ {"blraa_64p_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"blrabz_64_branch_reg", \
+ {"blrabz_64_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"blrab_64p_branch_reg", \
+ {"blrab_64p_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"blr_64_branch_reg", \
+ {"blr_64_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"braaz_64_branch_reg", \
+ {"braaz_64_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"braa_64p_branch_reg", \
+ {"braa_64p_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"brabz_64_branch_reg", \
+ {"brabz_64_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"brab_64p_branch_reg", \
+ {"brab_64p_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"br_64_branch_reg", &VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"drps_64e_branch_reg", \
+ {"br_64_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"eretaa_64e_branch_reg", \
+ {"drps_64e_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"eretab_64e_branch_reg", \
+ {"eretaa_64e_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"eret_64e_branch_reg", \
+ {"eretab_64e_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"retaa_64e_branch_reg", \
+ {"eret_64e_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"retab_64e_branch_reg", \
+ {"retaa_64e_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"ret_64r_branch_reg", \
+ {"retab_64e_branch_reg"_h, \
&VISITORCLASS::VisitUnconditionalBranchToRegister}, \
- {"bcax_vvv16_crypto4", &VISITORCLASS::VisitUnimplemented}, \
- {"bfcvtn_asimdmisc_4s", &VISITORCLASS::VisitUnimplemented}, \
- {"bfdot_asimdelem_e", &VISITORCLASS::VisitUnimplemented}, \
- {"bfdot_asimdsame2_d", &VISITORCLASS::VisitUnimplemented}, \
- {"bfmlal_asimdelem_f", &VISITORCLASS::VisitUnimplemented}, \
- {"bfmlal_asimdsame2_f_", &VISITORCLASS::VisitUnimplemented}, \
- {"bfmmla_asimdsame2_e", &VISITORCLASS::VisitUnimplemented}, \
- {"dsb_bon_barriers", &VISITORCLASS::VisitUnimplemented}, \
- {"eor3_vvv16_crypto4", &VISITORCLASS::VisitUnimplemented}, \
- {"ld64b_64l_memop", &VISITORCLASS::VisitUnimplemented}, \
- {"ldgm_64bulk_ldsttags", &VISITORCLASS::VisitUnimplemented}, \
- {"ldtrb_32_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"ldtrh_32_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"ldtrsb_32_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"ldtrsb_64_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"ldtrsh_32_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"ldtrsh_64_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"ldtrsw_64_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"ldtr_32_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"ldtr_64_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"rax1_vvv2_cryptosha512_3", &VISITORCLASS::VisitUnimplemented}, \
- {"sha512h2_qqv_cryptosha512_3", &VISITORCLASS::VisitUnimplemented}, \
- {"sha512h_qqv_cryptosha512_3", &VISITORCLASS::VisitUnimplemented}, \
- {"sha512su0_vv2_cryptosha512_2", &VISITORCLASS::VisitUnimplemented}, \
- {"sha512su1_vvv2_cryptosha512_3", &VISITORCLASS::VisitUnimplemented}, \
- {"sm3partw1_vvv4_cryptosha512_3", &VISITORCLASS::VisitUnimplemented}, \
- {"sm3partw2_vvv4_cryptosha512_3", &VISITORCLASS::VisitUnimplemented}, \
- {"sm3ss1_vvv4_crypto4", &VISITORCLASS::VisitUnimplemented}, \
- {"sm3tt1a_vvv4_crypto3_imm2", &VISITORCLASS::VisitUnimplemented}, \
- {"sm3tt1b_vvv4_crypto3_imm2", &VISITORCLASS::VisitUnimplemented}, \
- {"sm3tt2a_vvv4_crypto3_imm2", &VISITORCLASS::VisitUnimplemented}, \
- {"sm3tt2b_vvv_crypto3_imm2", &VISITORCLASS::VisitUnimplemented}, \
- {"sm4ekey_vvv4_cryptosha512_3", &VISITORCLASS::VisitUnimplemented}, \
- {"sm4e_vv4_cryptosha512_2", &VISITORCLASS::VisitUnimplemented}, \
- {"st64b_64l_memop", &VISITORCLASS::VisitUnimplemented}, \
- {"st64bv_64_memop", &VISITORCLASS::VisitUnimplemented}, \
- {"st64bv0_64_memop", &VISITORCLASS::VisitUnimplemented}, \
- {"stgm_64bulk_ldsttags", &VISITORCLASS::VisitUnimplemented}, \
- {"sttrb_32_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"sttrh_32_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"sttr_32_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"sttr_64_ldst_unpriv", &VISITORCLASS::VisitUnimplemented}, \
- {"stzgm_64bulk_ldsttags", &VISITORCLASS::VisitUnimplemented}, \
- {"tcancel_ex_exception", &VISITORCLASS::VisitUnimplemented}, \
- {"tstart_br_systemresult", &VISITORCLASS::VisitUnimplemented}, \
- {"ttest_br_systemresult", &VISITORCLASS::VisitUnimplemented}, \
- {"wfet_only_systeminstrswithreg", &VISITORCLASS::VisitUnimplemented}, \
- {"wfit_only_systeminstrswithreg", &VISITORCLASS::VisitUnimplemented}, \
- {"xar_vvv2_crypto3_imm6", &VISITORCLASS::VisitUnimplemented}, \
- {"bfcvt_z_p_z_s2bf", &VISITORCLASS::VisitUnimplemented}, \
- {"bfcvtnt_z_p_z_s2bf", &VISITORCLASS::VisitUnimplemented}, \
- {"bfdot_z_zzz_", &VISITORCLASS::VisitUnimplemented}, \
- {"bfdot_z_zzzi_", &VISITORCLASS::VisitUnimplemented}, \
- {"bfmlalb_z_zzz_", &VISITORCLASS::VisitUnimplemented}, \
- {"bfmlalb_z_zzzi_", &VISITORCLASS::VisitUnimplemented}, \
- {"bfmlalt_z_zzz_", &VISITORCLASS::VisitUnimplemented}, \
- {"bfmlalt_z_zzzi_", &VISITORCLASS::VisitUnimplemented}, \
- {"bfmmla_z_zzz_", &VISITORCLASS::VisitUnimplemented}, { \
- "Unallocated", &VISITORCLASS::VisitUnallocated \
+ {"ret_64r_branch_reg"_h, \
+ &VISITORCLASS::VisitUnconditionalBranchToRegister}, \
+ {"bcax_vvv16_crypto4"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfcvtn_asimdmisc_4s"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfdot_asimdelem_e"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfdot_asimdsame2_d"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfmlal_asimdelem_f"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfmlal_asimdsame2_f_"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfmmla_asimdsame2_e"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"dsb_bon_barriers"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"eor3_vvv16_crypto4"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ld64b_64l_memop"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ldgm_64bulk_ldsttags"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ldtrb_32_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ldtrh_32_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ldtrsb_32_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ldtrsb_64_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ldtrsh_32_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ldtrsh_64_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ldtrsw_64_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ldtr_32_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ldtr_64_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"rax1_vvv2_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sha512h2_qqv_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sha512h_qqv_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sha512su0_vv2_cryptosha512_2"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sha512su1_vvv2_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sm3partw1_vvv4_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sm3partw2_vvv4_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sm3ss1_vvv4_crypto4"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sm3tt1a_vvv4_crypto3_imm2"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sm3tt1b_vvv4_crypto3_imm2"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sm3tt2a_vvv4_crypto3_imm2"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sm3tt2b_vvv_crypto3_imm2"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sm4ekey_vvv4_cryptosha512_3"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sm4e_vv4_cryptosha512_2"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"st64b_64l_memop"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"st64bv_64_memop"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"st64bv0_64_memop"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"stgm_64bulk_ldsttags"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sttrb_32_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sttrh_32_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sttr_32_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"sttr_64_ldst_unpriv"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"stzgm_64bulk_ldsttags"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"tcancel_ex_exception"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"tstart_br_systemresult"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"ttest_br_systemresult"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"wfet_only_systeminstrswithreg"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"wfit_only_systeminstrswithreg"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"xar_vvv2_crypto3_imm6"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfcvt_z_p_z_s2bf"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfcvtnt_z_p_z_s2bf"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfdot_z_zzz_"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfdot_z_zzzi_"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfmlalb_z_zzz_"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfmlalb_z_zzzi_"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfmlalt_z_zzz_"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfmlalt_z_zzzi_"_h, &VISITORCLASS::VisitUnimplemented}, \
+ {"bfmmla_z_zzz_"_h, &VISITORCLASS::VisitUnimplemented}, { \
+ "unallocated"_h, &VISITORCLASS::VisitUnallocated \
}
#define SIM_AUD_VISITOR_MAP(VISITORCLASS) \
- {"autia1716_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"autiasp_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"autiaz_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"autib1716_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"autibsp_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"autibz_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"axflag_m_pstate", &VISITORCLASS::VisitSystem}, \
- {"cfinv_m_pstate", &VISITORCLASS::VisitSystem}, \
- {"csdb_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"dgh_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"esb_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"isb_bi_barriers", &VISITORCLASS::VisitSystem}, \
- {"nop_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"pacia1716_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"paciasp_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"paciaz_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"pacib1716_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"pacibsp_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"pacibz_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"pssbb_only_barriers", &VISITORCLASS::VisitSystem}, \
- {"sev_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"sevl_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"ssbb_only_barriers", &VISITORCLASS::VisitSystem}, \
- {"wfe_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"wfi_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"xaflag_m_pstate", &VISITORCLASS::VisitSystem}, \
- {"xpaclri_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"yield_hi_hints", &VISITORCLASS::VisitSystem}, \
- {"abs_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"cls_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"clz_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"cmeq_asimdmisc_z", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"cmge_asimdmisc_z", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"cmgt_asimdmisc_z", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"cmle_asimdmisc_z", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"cmlt_asimdmisc_z", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"cnt_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fabs_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcmeq_asimdmisc_fz", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcmge_asimdmisc_fz", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcmgt_asimdmisc_fz", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcmle_asimdmisc_fz", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcmlt_asimdmisc_fz", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtas_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtau_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtl_asimdmisc_l", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtms_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtmu_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtns_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtnu_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtn_asimdmisc_n", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtps_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtpu_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtxn_asimdmisc_n", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtzs_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fcvtzu_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fneg_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frecpe_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frint32x_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frint32z_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frint64x_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frint64z_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frinta_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frinti_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frintm_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frintn_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frintp_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frintx_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frintz_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"frsqrte_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"fsqrt_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"neg_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"not_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"rbit_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"rev16_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"rev32_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"rev64_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"sadalp_asimdmisc_p", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"saddlp_asimdmisc_p", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"scvtf_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"shll_asimdmisc_s", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"sqabs_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"sqneg_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"sqxtn_asimdmisc_n", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"sqxtun_asimdmisc_n", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"suqadd_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"uadalp_asimdmisc_p", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"uaddlp_asimdmisc_p", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"ucvtf_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"uqxtn_asimdmisc_n", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"urecpe_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"ursqrte_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"usqadd_asimdmisc_r", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"xtn_asimdmisc_n", &VISITORCLASS::VisitNEON2RegMisc}, \
- {"mla_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"mls_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"mul_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"saba_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"sabd_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"shadd_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"shsub_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"smaxp_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"smax_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"sminp_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"smin_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"srhadd_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"uaba_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"uabd_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"uhadd_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"uhsub_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"umaxp_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"umax_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"uminp_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"umin_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"urhadd_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"and_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"bic_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"bif_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"bit_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"bsl_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"eor_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"orr_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"orn_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"pmul_asimdsame_only", &VISITORCLASS::VisitNEON3Same}, \
- {"fmlal2_asimdsame_f", &VISITORCLASS::VisitNEON3Same}, \
- {"fmlal_asimdsame_f", &VISITORCLASS::VisitNEON3Same}, \
- {"fmlsl2_asimdsame_f", &VISITORCLASS::VisitNEON3Same}, \
- {"fmlsl_asimdsame_f", &VISITORCLASS::VisitNEON3Same}, \
- {"ushll_asimdshf_l", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"sshll_asimdshf_l", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"shrn_asimdshf_n", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"rshrn_asimdshf_n", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"sqshrn_asimdshf_n", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"sqrshrn_asimdshf_n", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"sqshrun_asimdshf_n", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"sqrshrun_asimdshf_n", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"uqshrn_asimdshf_n", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"uqrshrn_asimdshf_n", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"sri_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"srshr_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"srsra_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"sshr_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"ssra_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"urshr_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"ursra_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"ushr_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"usra_asimdshf_r", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"scvtf_asimdshf_c", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"ucvtf_asimdshf_c", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"fcvtzs_asimdshf_c", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"fcvtzu_asimdshf_c", &VISITORCLASS::VisitNEONShiftImmediate}, \
- {"sqdmlal_asisdelem_l", &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"sqdmlsl_asisdelem_l", &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"sqdmull_asisdelem_l", &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"fmla_asisdelem_rh_h", &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"fmla_asisdelem_r_sd", &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"fmls_asisdelem_rh_h", &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"fmls_asisdelem_r_sd", &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"fmulx_asisdelem_rh_h", \
+ {"autia1716_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"autiasp_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"autiaz_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"autib1716_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"autibsp_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"autibz_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"axflag_m_pstate"_h, &VISITORCLASS::VisitSystem}, \
+ {"cfinv_m_pstate"_h, &VISITORCLASS::VisitSystem}, \
+ {"csdb_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"dgh_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"esb_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"isb_bi_barriers"_h, &VISITORCLASS::VisitSystem}, \
+ {"nop_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"pacia1716_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"paciasp_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"paciaz_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"pacib1716_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"pacibsp_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"pacibz_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"pssbb_only_barriers"_h, &VISITORCLASS::VisitSystem}, \
+ {"sev_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"sevl_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"ssbb_only_barriers"_h, &VISITORCLASS::VisitSystem}, \
+ {"wfe_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"wfi_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"xaflag_m_pstate"_h, &VISITORCLASS::VisitSystem}, \
+ {"xpaclri_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"yield_hi_hints"_h, &VISITORCLASS::VisitSystem}, \
+ {"abs_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"cls_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"clz_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"cmeq_asimdmisc_z"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"cmge_asimdmisc_z"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"cmgt_asimdmisc_z"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"cmle_asimdmisc_z"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"cmlt_asimdmisc_z"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"cnt_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fabs_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcmeq_asimdmisc_fz"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcmge_asimdmisc_fz"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcmgt_asimdmisc_fz"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcmle_asimdmisc_fz"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcmlt_asimdmisc_fz"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtas_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtau_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtl_asimdmisc_l"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtms_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtmu_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtns_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtnu_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtn_asimdmisc_n"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtps_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtpu_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtxn_asimdmisc_n"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtzs_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fcvtzu_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fneg_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frecpe_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frint32x_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frint32z_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frint64x_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frint64z_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frinta_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frinti_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frintm_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frintn_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frintp_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frintx_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frintz_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"frsqrte_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"fsqrt_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"neg_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"not_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"rbit_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"rev16_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"rev32_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"rev64_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"sadalp_asimdmisc_p"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"saddlp_asimdmisc_p"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"scvtf_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"shll_asimdmisc_s"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"sqabs_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"sqneg_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"sqxtn_asimdmisc_n"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"sqxtun_asimdmisc_n"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"suqadd_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"uadalp_asimdmisc_p"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"uaddlp_asimdmisc_p"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"ucvtf_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"uqxtn_asimdmisc_n"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"urecpe_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"ursqrte_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"usqadd_asimdmisc_r"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"xtn_asimdmisc_n"_h, &VISITORCLASS::VisitNEON2RegMisc}, \
+ {"mla_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"mls_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"mul_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"saba_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"sabd_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"shadd_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"shsub_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"smaxp_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"smax_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"sminp_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"smin_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"srhadd_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"uaba_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"uabd_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"uhadd_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"uhsub_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"umaxp_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"umax_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"uminp_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"umin_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"urhadd_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"and_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"bic_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"bif_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"bit_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"bsl_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"eor_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"orr_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"orn_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"pmul_asimdsame_only"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmlal2_asimdsame_f"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmlal_asimdsame_f"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmlsl2_asimdsame_f"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"fmlsl_asimdsame_f"_h, &VISITORCLASS::VisitNEON3Same}, \
+ {"ushll_asimdshf_l"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"sshll_asimdshf_l"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"shrn_asimdshf_n"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"rshrn_asimdshf_n"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"sqshrn_asimdshf_n"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"sqrshrn_asimdshf_n"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"sqshrun_asimdshf_n"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"sqrshrun_asimdshf_n"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"uqshrn_asimdshf_n"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"uqrshrn_asimdshf_n"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"sri_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"srshr_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"srsra_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"sshr_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"ssra_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"urshr_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"ursra_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"ushr_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"usra_asimdshf_r"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"scvtf_asimdshf_c"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"ucvtf_asimdshf_c"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"fcvtzs_asimdshf_c"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"fcvtzu_asimdshf_c"_h, &VISITORCLASS::VisitNEONShiftImmediate}, \
+ {"sqdmlal_asisdelem_l"_h, \
&VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"fmulx_asisdelem_r_sd", \
+ {"sqdmlsl_asisdelem_l"_h, \
&VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"fmul_asisdelem_rh_h", &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"fmul_asisdelem_r_sd", &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
- {"fabd_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"facge_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"facgt_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"fcmeq_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"fcmge_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"fcmgt_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"fmulx_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"frecps_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"frsqrts_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"cmeq_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"cmge_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"cmgt_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"cmhi_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"cmhs_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"cmtst_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"add_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"sub_asisdsame_only", &VISITORCLASS::VisitNEONScalar3Same}, \
- {"sqrdmlah_asisdsame2_only", &VISITORCLASS::VisitNEONScalar3SameExtra}, \
- {"sqrdmlsh_asisdsame2_only", &VISITORCLASS::VisitNEONScalar3SameExtra}, \
- {"fmaxnmv_asimdall_only_h", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"fmaxv_asimdall_only_h", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"fminnmv_asimdall_only_h", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"fminv_asimdall_only_h", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"fmaxnmv_asimdall_only_sd", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"fminnmv_asimdall_only_sd", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"fmaxv_asimdall_only_sd", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"fminv_asimdall_only_sd", &VISITORCLASS::VisitNEONAcrossLanes}, \
- {"shl_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"sli_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"sri_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"srshr_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"srsra_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"sshr_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"ssra_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"urshr_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"ursra_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"ushr_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"usra_asisdshf_r", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"sqrshrn_asisdshf_n", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"sqrshrun_asisdshf_n", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"sqshrn_asisdshf_n", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"sqshrun_asisdshf_n", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"uqrshrn_asisdshf_n", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"uqshrn_asisdshf_n", &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
- {"cmeq_asisdmisc_z", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"cmge_asisdmisc_z", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"cmgt_asisdmisc_z", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"cmle_asisdmisc_z", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"cmlt_asisdmisc_z", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"abs_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"neg_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcmeq_asisdmisc_fz", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcmge_asisdmisc_fz", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcmgt_asisdmisc_fz", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcmle_asisdmisc_fz", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcmlt_asisdmisc_fz", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcvtas_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcvtau_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcvtms_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcvtmu_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcvtns_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcvtnu_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcvtps_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcvtpu_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcvtxn_asisdmisc_n", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcvtzs_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"fcvtzu_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"frecpe_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"frecpx_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"frsqrte_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, \
- {"scvtf_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc}, { \
- "ucvtf_asisdmisc_r", &VISITORCLASS::VisitNEONScalar2RegMisc \
+ {"sqdmull_asisdelem_l"_h, \
+ &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
+ {"fmla_asisdelem_rh_h"_h, \
+ &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
+ {"fmla_asisdelem_r_sd"_h, \
+ &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
+ {"fmls_asisdelem_rh_h"_h, \
+ &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
+ {"fmls_asisdelem_r_sd"_h, \
+ &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
+ {"fmulx_asisdelem_rh_h"_h, \
+ &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
+ {"fmulx_asisdelem_r_sd"_h, \
+ &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
+ {"fmul_asisdelem_rh_h"_h, \
+ &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
+ {"fmul_asisdelem_r_sd"_h, \
+ &VISITORCLASS::VisitNEONScalarByIndexedElement}, \
+ {"fabd_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"facge_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"facgt_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"fcmeq_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"fcmge_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"fcmgt_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"fmulx_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"frecps_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"frsqrts_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"cmeq_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"cmge_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"cmgt_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"cmhi_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"cmhs_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"cmtst_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"add_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"sub_asisdsame_only"_h, &VISITORCLASS::VisitNEONScalar3Same}, \
+ {"sqrdmlah_asisdsame2_only"_h, \
+ &VISITORCLASS::VisitNEONScalar3SameExtra}, \
+ {"sqrdmlsh_asisdsame2_only"_h, \
+ &VISITORCLASS::VisitNEONScalar3SameExtra}, \
+ {"fmaxnmv_asimdall_only_h"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"fmaxv_asimdall_only_h"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"fminnmv_asimdall_only_h"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"fminv_asimdall_only_h"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"fmaxnmv_asimdall_only_sd"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"fminnmv_asimdall_only_sd"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"fmaxv_asimdall_only_sd"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"fminv_asimdall_only_sd"_h, &VISITORCLASS::VisitNEONAcrossLanes}, \
+ {"shl_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"sli_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"sri_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"srshr_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"srsra_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"sshr_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"ssra_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"urshr_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"ursra_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"ushr_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"usra_asisdshf_r"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"sqrshrn_asisdshf_n"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"sqrshrun_asisdshf_n"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"sqshrn_asisdshf_n"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"sqshrun_asisdshf_n"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"uqrshrn_asisdshf_n"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"uqshrn_asisdshf_n"_h, &VISITORCLASS::VisitNEONScalarShiftImmediate}, \
+ {"cmeq_asisdmisc_z"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"cmge_asisdmisc_z"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"cmgt_asisdmisc_z"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"cmle_asisdmisc_z"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"cmlt_asisdmisc_z"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"abs_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"neg_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcmeq_asisdmisc_fz"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcmge_asisdmisc_fz"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcmgt_asisdmisc_fz"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcmle_asisdmisc_fz"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcmlt_asisdmisc_fz"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcvtas_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcvtau_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcvtms_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcvtmu_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcvtns_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcvtnu_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcvtps_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcvtpu_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcvtxn_asisdmisc_n"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcvtzs_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"fcvtzu_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"frecpe_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"frecpx_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"frsqrte_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, \
+ {"scvtf_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc}, { \
+ "ucvtf_asisdmisc_r"_h, &VISITORCLASS::VisitNEONScalar2RegMisc \
}
diff --git a/src/aarch64/disasm-aarch64.cc b/src/aarch64/disasm-aarch64.cc
index 0338366..3b3f7a7 100644
--- a/src/aarch64/disasm-aarch64.cc
+++ b/src/aarch64/disasm-aarch64.cc
@@ -36,636 +36,665 @@
const Disassembler::FormToVisitorFnMap *Disassembler::GetFormToVisitorFnMap() {
static const FormToVisitorFnMap form_to_visitor = {
DEFAULT_FORM_TO_VISITOR_MAP(Disassembler),
- {"autia1716_hi_hints", &Disassembler::DisassembleNoArgs},
- {"autiasp_hi_hints", &Disassembler::DisassembleNoArgs},
- {"autiaz_hi_hints", &Disassembler::DisassembleNoArgs},
- {"autib1716_hi_hints", &Disassembler::DisassembleNoArgs},
- {"autibsp_hi_hints", &Disassembler::DisassembleNoArgs},
- {"autibz_hi_hints", &Disassembler::DisassembleNoArgs},
- {"axflag_m_pstate", &Disassembler::DisassembleNoArgs},
- {"cfinv_m_pstate", &Disassembler::DisassembleNoArgs},
- {"csdb_hi_hints", &Disassembler::DisassembleNoArgs},
- {"dgh_hi_hints", &Disassembler::DisassembleNoArgs},
- {"ssbb_only_barriers", &Disassembler::DisassembleNoArgs},
- {"pssbb_only_barriers", &Disassembler::DisassembleNoArgs},
- {"esb_hi_hints", &Disassembler::DisassembleNoArgs},
- {"isb_bi_barriers", &Disassembler::DisassembleNoArgs},
- {"nop_hi_hints", &Disassembler::DisassembleNoArgs},
- {"pacia1716_hi_hints", &Disassembler::DisassembleNoArgs},
- {"paciasp_hi_hints", &Disassembler::DisassembleNoArgs},
- {"paciaz_hi_hints", &Disassembler::DisassembleNoArgs},
- {"pacib1716_hi_hints", &Disassembler::DisassembleNoArgs},
- {"pacibsp_hi_hints", &Disassembler::DisassembleNoArgs},
- {"pacibz_hi_hints", &Disassembler::DisassembleNoArgs},
- {"sev_hi_hints", &Disassembler::DisassembleNoArgs},
- {"sevl_hi_hints", &Disassembler::DisassembleNoArgs},
- {"wfe_hi_hints", &Disassembler::DisassembleNoArgs},
- {"wfi_hi_hints", &Disassembler::DisassembleNoArgs},
- {"xaflag_m_pstate", &Disassembler::DisassembleNoArgs},
- {"xpaclri_hi_hints", &Disassembler::DisassembleNoArgs},
- {"yield_hi_hints", &Disassembler::DisassembleNoArgs},
- {"abs_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"cls_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"clz_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"cnt_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"neg_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"rev16_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"rev32_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"rev64_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"sqabs_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"sqneg_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"suqadd_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"urecpe_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"ursqrte_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"usqadd_asimdmisc_r", &Disassembler::VisitNEON2RegMisc},
- {"not_asimdmisc_r", &Disassembler::DisassembleNEON2RegLogical},
- {"rbit_asimdmisc_r", &Disassembler::DisassembleNEON2RegLogical},
- {"xtn_asimdmisc_n", &Disassembler::DisassembleNEON2RegExtract},
- {"sqxtn_asimdmisc_n", &Disassembler::DisassembleNEON2RegExtract},
- {"uqxtn_asimdmisc_n", &Disassembler::DisassembleNEON2RegExtract},
- {"sqxtun_asimdmisc_n", &Disassembler::DisassembleNEON2RegExtract},
- {"shll_asimdmisc_s", &Disassembler::DisassembleNEON2RegExtract},
- {"sadalp_asimdmisc_p", &Disassembler::DisassembleNEON2RegAddlp},
- {"saddlp_asimdmisc_p", &Disassembler::DisassembleNEON2RegAddlp},
- {"uadalp_asimdmisc_p", &Disassembler::DisassembleNEON2RegAddlp},
- {"uaddlp_asimdmisc_p", &Disassembler::DisassembleNEON2RegAddlp},
- {"cmeq_asimdmisc_z", &Disassembler::DisassembleNEON2RegCompare},
- {"cmge_asimdmisc_z", &Disassembler::DisassembleNEON2RegCompare},
- {"cmgt_asimdmisc_z", &Disassembler::DisassembleNEON2RegCompare},
- {"cmle_asimdmisc_z", &Disassembler::DisassembleNEON2RegCompare},
- {"cmlt_asimdmisc_z", &Disassembler::DisassembleNEON2RegCompare},
- {"fcmeq_asimdmisc_fz", &Disassembler::DisassembleNEON2RegFPCompare},
- {"fcmge_asimdmisc_fz", &Disassembler::DisassembleNEON2RegFPCompare},
- {"fcmgt_asimdmisc_fz", &Disassembler::DisassembleNEON2RegFPCompare},
- {"fcmle_asimdmisc_fz", &Disassembler::DisassembleNEON2RegFPCompare},
- {"fcmlt_asimdmisc_fz", &Disassembler::DisassembleNEON2RegFPCompare},
- {"fcvtl_asimdmisc_l", &Disassembler::DisassembleNEON2RegFPConvert},
- {"fcvtn_asimdmisc_n", &Disassembler::DisassembleNEON2RegFPConvert},
- {"fcvtxn_asimdmisc_n", &Disassembler::DisassembleNEON2RegFPConvert},
- {"fabs_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fcvtas_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fcvtau_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fcvtms_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fcvtmu_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fcvtns_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fcvtnu_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fcvtps_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fcvtpu_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fcvtzs_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fcvtzu_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fneg_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frecpe_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frint32x_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frint32z_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frint64x_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frint64z_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frinta_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frinti_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frintm_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frintn_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frintp_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frintx_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frintz_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"frsqrte_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"fsqrt_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"scvtf_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"ucvtf_asimdmisc_r", &Disassembler::DisassembleNEON2RegFP},
- {"smlal_asimdelem_l", &Disassembler::DisassembleNEONMulByElementLong},
- {"smlsl_asimdelem_l", &Disassembler::DisassembleNEONMulByElementLong},
- {"smull_asimdelem_l", &Disassembler::DisassembleNEONMulByElementLong},
- {"umlal_asimdelem_l", &Disassembler::DisassembleNEONMulByElementLong},
- {"umlsl_asimdelem_l", &Disassembler::DisassembleNEONMulByElementLong},
- {"umull_asimdelem_l", &Disassembler::DisassembleNEONMulByElementLong},
- {"sqdmull_asimdelem_l", &Disassembler::DisassembleNEONMulByElementLong},
- {"sqdmlal_asimdelem_l", &Disassembler::DisassembleNEONMulByElementLong},
- {"sqdmlsl_asimdelem_l", &Disassembler::DisassembleNEONMulByElementLong},
- {"sdot_asimdelem_d", &Disassembler::DisassembleNEONDotProdByElement},
- {"udot_asimdelem_d", &Disassembler::DisassembleNEONDotProdByElement},
- {"usdot_asimdelem_d", &Disassembler::DisassembleNEONDotProdByElement},
- {"sudot_asimdelem_d", &Disassembler::DisassembleNEONDotProdByElement},
- {"fmlal2_asimdelem_lh", &Disassembler::DisassembleNEONFPMulByElementLong},
- {"fmlal_asimdelem_lh", &Disassembler::DisassembleNEONFPMulByElementLong},
- {"fmlsl2_asimdelem_lh", &Disassembler::DisassembleNEONFPMulByElementLong},
- {"fmlsl_asimdelem_lh", &Disassembler::DisassembleNEONFPMulByElementLong},
- {"fcmla_asimdelem_c_h",
+ {"autia1716_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"autiasp_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"autiaz_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"autib1716_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"autibsp_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"autibz_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"axflag_m_pstate"_h, &Disassembler::DisassembleNoArgs},
+ {"cfinv_m_pstate"_h, &Disassembler::DisassembleNoArgs},
+ {"csdb_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"dgh_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"ssbb_only_barriers"_h, &Disassembler::DisassembleNoArgs},
+ {"pssbb_only_barriers"_h, &Disassembler::DisassembleNoArgs},
+ {"esb_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"isb_bi_barriers"_h, &Disassembler::DisassembleNoArgs},
+ {"nop_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"pacia1716_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"paciasp_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"paciaz_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"pacib1716_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"pacibsp_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"pacibz_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"sev_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"sevl_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"wfe_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"wfi_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"xaflag_m_pstate"_h, &Disassembler::DisassembleNoArgs},
+ {"xpaclri_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"yield_hi_hints"_h, &Disassembler::DisassembleNoArgs},
+ {"abs_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"cls_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"clz_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"cnt_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"neg_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"rev16_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"rev32_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"rev64_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"sqabs_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"sqneg_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"suqadd_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"urecpe_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"ursqrte_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"usqadd_asimdmisc_r"_h, &Disassembler::VisitNEON2RegMisc},
+ {"not_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegLogical},
+ {"rbit_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegLogical},
+ {"xtn_asimdmisc_n"_h, &Disassembler::DisassembleNEON2RegExtract},
+ {"sqxtn_asimdmisc_n"_h, &Disassembler::DisassembleNEON2RegExtract},
+ {"uqxtn_asimdmisc_n"_h, &Disassembler::DisassembleNEON2RegExtract},
+ {"sqxtun_asimdmisc_n"_h, &Disassembler::DisassembleNEON2RegExtract},
+ {"shll_asimdmisc_s"_h, &Disassembler::DisassembleNEON2RegExtract},
+ {"sadalp_asimdmisc_p"_h, &Disassembler::DisassembleNEON2RegAddlp},
+ {"saddlp_asimdmisc_p"_h, &Disassembler::DisassembleNEON2RegAddlp},
+ {"uadalp_asimdmisc_p"_h, &Disassembler::DisassembleNEON2RegAddlp},
+ {"uaddlp_asimdmisc_p"_h, &Disassembler::DisassembleNEON2RegAddlp},
+ {"cmeq_asimdmisc_z"_h, &Disassembler::DisassembleNEON2RegCompare},
+ {"cmge_asimdmisc_z"_h, &Disassembler::DisassembleNEON2RegCompare},
+ {"cmgt_asimdmisc_z"_h, &Disassembler::DisassembleNEON2RegCompare},
+ {"cmle_asimdmisc_z"_h, &Disassembler::DisassembleNEON2RegCompare},
+ {"cmlt_asimdmisc_z"_h, &Disassembler::DisassembleNEON2RegCompare},
+ {"fcmeq_asimdmisc_fz"_h, &Disassembler::DisassembleNEON2RegFPCompare},
+ {"fcmge_asimdmisc_fz"_h, &Disassembler::DisassembleNEON2RegFPCompare},
+ {"fcmgt_asimdmisc_fz"_h, &Disassembler::DisassembleNEON2RegFPCompare},
+ {"fcmle_asimdmisc_fz"_h, &Disassembler::DisassembleNEON2RegFPCompare},
+ {"fcmlt_asimdmisc_fz"_h, &Disassembler::DisassembleNEON2RegFPCompare},
+ {"fcvtl_asimdmisc_l"_h, &Disassembler::DisassembleNEON2RegFPConvert},
+ {"fcvtn_asimdmisc_n"_h, &Disassembler::DisassembleNEON2RegFPConvert},
+ {"fcvtxn_asimdmisc_n"_h, &Disassembler::DisassembleNEON2RegFPConvert},
+ {"fabs_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fcvtas_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fcvtau_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fcvtms_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fcvtmu_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fcvtns_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fcvtnu_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fcvtps_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fcvtpu_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fcvtzs_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fcvtzu_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fneg_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frecpe_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frint32x_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frint32z_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frint64x_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frint64z_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frinta_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frinti_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frintm_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frintn_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frintp_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frintx_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frintz_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"frsqrte_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"fsqrt_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"scvtf_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"ucvtf_asimdmisc_r"_h, &Disassembler::DisassembleNEON2RegFP},
+ {"smlal_asimdelem_l"_h, &Disassembler::DisassembleNEONMulByElementLong},
+ {"smlsl_asimdelem_l"_h, &Disassembler::DisassembleNEONMulByElementLong},
+ {"smull_asimdelem_l"_h, &Disassembler::DisassembleNEONMulByElementLong},
+ {"umlal_asimdelem_l"_h, &Disassembler::DisassembleNEONMulByElementLong},
+ {"umlsl_asimdelem_l"_h, &Disassembler::DisassembleNEONMulByElementLong},
+ {"umull_asimdelem_l"_h, &Disassembler::DisassembleNEONMulByElementLong},
+ {"sqdmull_asimdelem_l"_h, &Disassembler::DisassembleNEONMulByElementLong},
+ {"sqdmlal_asimdelem_l"_h, &Disassembler::DisassembleNEONMulByElementLong},
+ {"sqdmlsl_asimdelem_l"_h, &Disassembler::DisassembleNEONMulByElementLong},
+ {"sdot_asimdelem_d"_h, &Disassembler::DisassembleNEONDotProdByElement},
+ {"udot_asimdelem_d"_h, &Disassembler::DisassembleNEONDotProdByElement},
+ {"usdot_asimdelem_d"_h, &Disassembler::DisassembleNEONDotProdByElement},
+ {"sudot_asimdelem_d"_h, &Disassembler::DisassembleNEONDotProdByElement},
+ {"fmlal2_asimdelem_lh"_h,
+ &Disassembler::DisassembleNEONFPMulByElementLong},
+ {"fmlal_asimdelem_lh"_h,
+ &Disassembler::DisassembleNEONFPMulByElementLong},
+ {"fmlsl2_asimdelem_lh"_h,
+ &Disassembler::DisassembleNEONFPMulByElementLong},
+ {"fmlsl_asimdelem_lh"_h,
+ &Disassembler::DisassembleNEONFPMulByElementLong},
+ {"fcmla_asimdelem_c_h"_h,
&Disassembler::DisassembleNEONComplexMulByElement},
- {"fcmla_asimdelem_c_s",
+ {"fcmla_asimdelem_c_s"_h,
&Disassembler::DisassembleNEONComplexMulByElement},
- {"fmla_asimdelem_rh_h", &Disassembler::DisassembleNEONHalfFPMulByElement},
- {"fmls_asimdelem_rh_h", &Disassembler::DisassembleNEONHalfFPMulByElement},
- {"fmulx_asimdelem_rh_h",
+ {"fmla_asimdelem_rh_h"_h,
&Disassembler::DisassembleNEONHalfFPMulByElement},
- {"fmul_asimdelem_rh_h", &Disassembler::DisassembleNEONHalfFPMulByElement},
- {"fmla_asimdelem_r_sd", &Disassembler::DisassembleNEONFPMulByElement},
- {"fmls_asimdelem_r_sd", &Disassembler::DisassembleNEONFPMulByElement},
- {"fmulx_asimdelem_r_sd", &Disassembler::DisassembleNEONFPMulByElement},
- {"fmul_asimdelem_r_sd", &Disassembler::DisassembleNEONFPMulByElement},
- {"mla_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"mls_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"mul_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"saba_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"sabd_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"shadd_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"shsub_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"smaxp_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"smax_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"sminp_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"smin_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"srhadd_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"uaba_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"uabd_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"uhadd_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"uhsub_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"umaxp_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"umax_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"uminp_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"umin_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"urhadd_asimdsame_only", &Disassembler::DisassembleNEON3SameNoD},
- {"and_asimdsame_only", &Disassembler::DisassembleNEON3SameLogical},
- {"bic_asimdsame_only", &Disassembler::DisassembleNEON3SameLogical},
- {"bif_asimdsame_only", &Disassembler::DisassembleNEON3SameLogical},
- {"bit_asimdsame_only", &Disassembler::DisassembleNEON3SameLogical},
- {"bsl_asimdsame_only", &Disassembler::DisassembleNEON3SameLogical},
- {"eor_asimdsame_only", &Disassembler::DisassembleNEON3SameLogical},
- {"orr_asimdsame_only", &Disassembler::DisassembleNEON3SameLogical},
- {"orn_asimdsame_only", &Disassembler::DisassembleNEON3SameLogical},
- {"pmul_asimdsame_only", &Disassembler::DisassembleNEON3SameLogical},
- {"fmlal2_asimdsame_f", &Disassembler::DisassembleNEON3SameFHM},
- {"fmlal_asimdsame_f", &Disassembler::DisassembleNEON3SameFHM},
- {"fmlsl2_asimdsame_f", &Disassembler::DisassembleNEON3SameFHM},
- {"fmlsl_asimdsame_f", &Disassembler::DisassembleNEON3SameFHM},
- {"sri_asimdshf_r", &Disassembler::DisassembleNEONShiftRightImm},
- {"srshr_asimdshf_r", &Disassembler::DisassembleNEONShiftRightImm},
- {"srsra_asimdshf_r", &Disassembler::DisassembleNEONShiftRightImm},
- {"sshr_asimdshf_r", &Disassembler::DisassembleNEONShiftRightImm},
- {"ssra_asimdshf_r", &Disassembler::DisassembleNEONShiftRightImm},
- {"urshr_asimdshf_r", &Disassembler::DisassembleNEONShiftRightImm},
- {"ursra_asimdshf_r", &Disassembler::DisassembleNEONShiftRightImm},
- {"ushr_asimdshf_r", &Disassembler::DisassembleNEONShiftRightImm},
- {"usra_asimdshf_r", &Disassembler::DisassembleNEONShiftRightImm},
- {"scvtf_asimdshf_c", &Disassembler::DisassembleNEONShiftRightImm},
- {"ucvtf_asimdshf_c", &Disassembler::DisassembleNEONShiftRightImm},
- {"fcvtzs_asimdshf_c", &Disassembler::DisassembleNEONShiftRightImm},
- {"fcvtzu_asimdshf_c", &Disassembler::DisassembleNEONShiftRightImm},
- {"ushll_asimdshf_l", &Disassembler::DisassembleNEONShiftLeftLongImm},
- {"sshll_asimdshf_l", &Disassembler::DisassembleNEONShiftLeftLongImm},
- {"shrn_asimdshf_n", &Disassembler::DisassembleNEONShiftRightNarrowImm},
- {"rshrn_asimdshf_n", &Disassembler::DisassembleNEONShiftRightNarrowImm},
- {"sqshrn_asimdshf_n", &Disassembler::DisassembleNEONShiftRightNarrowImm},
- {"sqrshrn_asimdshf_n", &Disassembler::DisassembleNEONShiftRightNarrowImm},
- {"sqshrun_asimdshf_n", &Disassembler::DisassembleNEONShiftRightNarrowImm},
- {"sqrshrun_asimdshf_n",
+ {"fmls_asimdelem_rh_h"_h,
+ &Disassembler::DisassembleNEONHalfFPMulByElement},
+ {"fmulx_asimdelem_rh_h"_h,
+ &Disassembler::DisassembleNEONHalfFPMulByElement},
+ {"fmul_asimdelem_rh_h"_h,
+ &Disassembler::DisassembleNEONHalfFPMulByElement},
+ {"fmla_asimdelem_r_sd"_h, &Disassembler::DisassembleNEONFPMulByElement},
+ {"fmls_asimdelem_r_sd"_h, &Disassembler::DisassembleNEONFPMulByElement},
+ {"fmulx_asimdelem_r_sd"_h, &Disassembler::DisassembleNEONFPMulByElement},
+ {"fmul_asimdelem_r_sd"_h, &Disassembler::DisassembleNEONFPMulByElement},
+ {"mla_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"mls_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"mul_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"saba_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"sabd_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"shadd_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"shsub_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"smaxp_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"smax_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"sminp_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"smin_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"srhadd_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"uaba_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"uabd_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"uhadd_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"uhsub_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"umaxp_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"umax_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"uminp_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"umin_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"urhadd_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameNoD},
+ {"and_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameLogical},
+ {"bic_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameLogical},
+ {"bif_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameLogical},
+ {"bit_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameLogical},
+ {"bsl_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameLogical},
+ {"eor_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameLogical},
+ {"orr_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameLogical},
+ {"orn_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameLogical},
+ {"pmul_asimdsame_only"_h, &Disassembler::DisassembleNEON3SameLogical},
+ {"fmlal2_asimdsame_f"_h, &Disassembler::DisassembleNEON3SameFHM},
+ {"fmlal_asimdsame_f"_h, &Disassembler::DisassembleNEON3SameFHM},
+ {"fmlsl2_asimdsame_f"_h, &Disassembler::DisassembleNEON3SameFHM},
+ {"fmlsl_asimdsame_f"_h, &Disassembler::DisassembleNEON3SameFHM},
+ {"sri_asimdshf_r"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"srshr_asimdshf_r"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"srsra_asimdshf_r"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"sshr_asimdshf_r"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"ssra_asimdshf_r"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"urshr_asimdshf_r"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"ursra_asimdshf_r"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"ushr_asimdshf_r"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"usra_asimdshf_r"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"scvtf_asimdshf_c"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"ucvtf_asimdshf_c"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"fcvtzs_asimdshf_c"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"fcvtzu_asimdshf_c"_h, &Disassembler::DisassembleNEONShiftRightImm},
+ {"ushll_asimdshf_l"_h, &Disassembler::DisassembleNEONShiftLeftLongImm},
+ {"sshll_asimdshf_l"_h, &Disassembler::DisassembleNEONShiftLeftLongImm},
+ {"shrn_asimdshf_n"_h, &Disassembler::DisassembleNEONShiftRightNarrowImm},
+ {"rshrn_asimdshf_n"_h, &Disassembler::DisassembleNEONShiftRightNarrowImm},
+ {"sqshrn_asimdshf_n"_h,
&Disassembler::DisassembleNEONShiftRightNarrowImm},
- {"uqshrn_asimdshf_n", &Disassembler::DisassembleNEONShiftRightNarrowImm},
- {"uqrshrn_asimdshf_n", &Disassembler::DisassembleNEONShiftRightNarrowImm},
- {"sqdmlal_asisdelem_l",
+ {"sqrshrn_asimdshf_n"_h,
+ &Disassembler::DisassembleNEONShiftRightNarrowImm},
+ {"sqshrun_asimdshf_n"_h,
+ &Disassembler::DisassembleNEONShiftRightNarrowImm},
+ {"sqrshrun_asimdshf_n"_h,
+ &Disassembler::DisassembleNEONShiftRightNarrowImm},
+ {"uqshrn_asimdshf_n"_h,
+ &Disassembler::DisassembleNEONShiftRightNarrowImm},
+ {"uqrshrn_asimdshf_n"_h,
+ &Disassembler::DisassembleNEONShiftRightNarrowImm},
+ {"sqdmlal_asisdelem_l"_h,
&Disassembler::DisassembleNEONScalarSatMulLongIndex},
- {"sqdmlsl_asisdelem_l",
+ {"sqdmlsl_asisdelem_l"_h,
&Disassembler::DisassembleNEONScalarSatMulLongIndex},
- {"sqdmull_asisdelem_l",
+ {"sqdmull_asisdelem_l"_h,
&Disassembler::DisassembleNEONScalarSatMulLongIndex},
- {"fmla_asisdelem_rh_h", &Disassembler::DisassembleNEONFPScalarMulIndex},
- {"fmla_asisdelem_r_sd", &Disassembler::DisassembleNEONFPScalarMulIndex},
- {"fmls_asisdelem_rh_h", &Disassembler::DisassembleNEONFPScalarMulIndex},
- {"fmls_asisdelem_r_sd", &Disassembler::DisassembleNEONFPScalarMulIndex},
- {"fmulx_asisdelem_rh_h", &Disassembler::DisassembleNEONFPScalarMulIndex},
- {"fmulx_asisdelem_r_sd", &Disassembler::DisassembleNEONFPScalarMulIndex},
- {"fmul_asisdelem_rh_h", &Disassembler::DisassembleNEONFPScalarMulIndex},
- {"fmul_asisdelem_r_sd", &Disassembler::DisassembleNEONFPScalarMulIndex},
- {"fabd_asisdsame_only", &Disassembler::DisassembleNEONFPScalar3Same},
- {"facge_asisdsame_only", &Disassembler::DisassembleNEONFPScalar3Same},
- {"facgt_asisdsame_only", &Disassembler::DisassembleNEONFPScalar3Same},
- {"fcmeq_asisdsame_only", &Disassembler::DisassembleNEONFPScalar3Same},
- {"fcmge_asisdsame_only", &Disassembler::DisassembleNEONFPScalar3Same},
- {"fcmgt_asisdsame_only", &Disassembler::DisassembleNEONFPScalar3Same},
- {"fmulx_asisdsame_only", &Disassembler::DisassembleNEONFPScalar3Same},
- {"frecps_asisdsame_only", &Disassembler::DisassembleNEONFPScalar3Same},
- {"frsqrts_asisdsame_only", &Disassembler::DisassembleNEONFPScalar3Same},
- {"sqrdmlah_asisdsame2_only", &Disassembler::VisitNEONScalar3Same},
- {"sqrdmlsh_asisdsame2_only", &Disassembler::VisitNEONScalar3Same},
- {"cmeq_asisdsame_only", &Disassembler::DisassembleNEONScalar3SameOnlyD},
- {"cmge_asisdsame_only", &Disassembler::DisassembleNEONScalar3SameOnlyD},
- {"cmgt_asisdsame_only", &Disassembler::DisassembleNEONScalar3SameOnlyD},
- {"cmhi_asisdsame_only", &Disassembler::DisassembleNEONScalar3SameOnlyD},
- {"cmhs_asisdsame_only", &Disassembler::DisassembleNEONScalar3SameOnlyD},
- {"cmtst_asisdsame_only", &Disassembler::DisassembleNEONScalar3SameOnlyD},
- {"add_asisdsame_only", &Disassembler::DisassembleNEONScalar3SameOnlyD},
- {"sub_asisdsame_only", &Disassembler::DisassembleNEONScalar3SameOnlyD},
- {"fmaxnmv_asimdall_only_h",
+ {"fmla_asisdelem_rh_h"_h, &Disassembler::DisassembleNEONFPScalarMulIndex},
+ {"fmla_asisdelem_r_sd"_h, &Disassembler::DisassembleNEONFPScalarMulIndex},
+ {"fmls_asisdelem_rh_h"_h, &Disassembler::DisassembleNEONFPScalarMulIndex},
+ {"fmls_asisdelem_r_sd"_h, &Disassembler::DisassembleNEONFPScalarMulIndex},
+ {"fmulx_asisdelem_rh_h"_h,
+ &Disassembler::DisassembleNEONFPScalarMulIndex},
+ {"fmulx_asisdelem_r_sd"_h,
+ &Disassembler::DisassembleNEONFPScalarMulIndex},
+ {"fmul_asisdelem_rh_h"_h, &Disassembler::DisassembleNEONFPScalarMulIndex},
+ {"fmul_asisdelem_r_sd"_h, &Disassembler::DisassembleNEONFPScalarMulIndex},
+ {"fabd_asisdsame_only"_h, &Disassembler::DisassembleNEONFPScalar3Same},
+ {"facge_asisdsame_only"_h, &Disassembler::DisassembleNEONFPScalar3Same},
+ {"facgt_asisdsame_only"_h, &Disassembler::DisassembleNEONFPScalar3Same},
+ {"fcmeq_asisdsame_only"_h, &Disassembler::DisassembleNEONFPScalar3Same},
+ {"fcmge_asisdsame_only"_h, &Disassembler::DisassembleNEONFPScalar3Same},
+ {"fcmgt_asisdsame_only"_h, &Disassembler::DisassembleNEONFPScalar3Same},
+ {"fmulx_asisdsame_only"_h, &Disassembler::DisassembleNEONFPScalar3Same},
+ {"frecps_asisdsame_only"_h, &Disassembler::DisassembleNEONFPScalar3Same},
+ {"frsqrts_asisdsame_only"_h, &Disassembler::DisassembleNEONFPScalar3Same},
+ {"sqrdmlah_asisdsame2_only"_h, &Disassembler::VisitNEONScalar3Same},
+ {"sqrdmlsh_asisdsame2_only"_h, &Disassembler::VisitNEONScalar3Same},
+ {"cmeq_asisdsame_only"_h, &Disassembler::DisassembleNEONScalar3SameOnlyD},
+ {"cmge_asisdsame_only"_h, &Disassembler::DisassembleNEONScalar3SameOnlyD},
+ {"cmgt_asisdsame_only"_h, &Disassembler::DisassembleNEONScalar3SameOnlyD},
+ {"cmhi_asisdsame_only"_h, &Disassembler::DisassembleNEONScalar3SameOnlyD},
+ {"cmhs_asisdsame_only"_h, &Disassembler::DisassembleNEONScalar3SameOnlyD},
+ {"cmtst_asisdsame_only"_h,
+ &Disassembler::DisassembleNEONScalar3SameOnlyD},
+ {"add_asisdsame_only"_h, &Disassembler::DisassembleNEONScalar3SameOnlyD},
+ {"sub_asisdsame_only"_h, &Disassembler::DisassembleNEONScalar3SameOnlyD},
+ {"fmaxnmv_asimdall_only_h"_h,
&Disassembler::DisassembleNEONFP16AcrossLanes},
- {"fmaxv_asimdall_only_h", &Disassembler::DisassembleNEONFP16AcrossLanes},
- {"fminnmv_asimdall_only_h",
+ {"fmaxv_asimdall_only_h"_h,
&Disassembler::DisassembleNEONFP16AcrossLanes},
- {"fminv_asimdall_only_h", &Disassembler::DisassembleNEONFP16AcrossLanes},
- {"fmaxnmv_asimdall_only_sd", &Disassembler::DisassembleNEONFPAcrossLanes},
- {"fminnmv_asimdall_only_sd", &Disassembler::DisassembleNEONFPAcrossLanes},
- {"fmaxv_asimdall_only_sd", &Disassembler::DisassembleNEONFPAcrossLanes},
- {"fminv_asimdall_only_sd", &Disassembler::DisassembleNEONFPAcrossLanes},
- {"shl_asisdshf_r", &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
- {"sli_asisdshf_r", &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
- {"sri_asisdshf_r", &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
- {"srshr_asisdshf_r", &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
- {"srsra_asisdshf_r", &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
- {"sshr_asisdshf_r", &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
- {"ssra_asisdshf_r", &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
- {"urshr_asisdshf_r", &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
- {"ursra_asisdshf_r", &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
- {"ushr_asisdshf_r", &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
- {"usra_asisdshf_r", &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
- {"sqrshrn_asisdshf_n",
+ {"fminnmv_asimdall_only_h"_h,
+ &Disassembler::DisassembleNEONFP16AcrossLanes},
+ {"fminv_asimdall_only_h"_h,
+ &Disassembler::DisassembleNEONFP16AcrossLanes},
+ {"fmaxnmv_asimdall_only_sd"_h,
+ &Disassembler::DisassembleNEONFPAcrossLanes},
+ {"fminnmv_asimdall_only_sd"_h,
+ &Disassembler::DisassembleNEONFPAcrossLanes},
+ {"fmaxv_asimdall_only_sd"_h, &Disassembler::DisassembleNEONFPAcrossLanes},
+ {"fminv_asimdall_only_sd"_h, &Disassembler::DisassembleNEONFPAcrossLanes},
+ {"shl_asisdshf_r"_h, &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
+ {"sli_asisdshf_r"_h, &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
+ {"sri_asisdshf_r"_h, &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
+ {"srshr_asisdshf_r"_h, &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
+ {"srsra_asisdshf_r"_h, &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
+ {"sshr_asisdshf_r"_h, &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
+ {"ssra_asisdshf_r"_h, &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
+ {"urshr_asisdshf_r"_h, &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
+ {"ursra_asisdshf_r"_h, &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
+ {"ushr_asisdshf_r"_h, &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
+ {"usra_asisdshf_r"_h, &Disassembler::DisassembleNEONScalarShiftImmOnlyD},
+ {"sqrshrn_asisdshf_n"_h,
&Disassembler::DisassembleNEONScalarShiftRightNarrowImm},
- {"sqrshrun_asisdshf_n",
+ {"sqrshrun_asisdshf_n"_h,
&Disassembler::DisassembleNEONScalarShiftRightNarrowImm},
- {"sqshrn_asisdshf_n",
+ {"sqshrn_asisdshf_n"_h,
&Disassembler::DisassembleNEONScalarShiftRightNarrowImm},
- {"sqshrun_asisdshf_n",
+ {"sqshrun_asisdshf_n"_h,
&Disassembler::DisassembleNEONScalarShiftRightNarrowImm},
- {"uqrshrn_asisdshf_n",
+ {"uqrshrn_asisdshf_n"_h,
&Disassembler::DisassembleNEONScalarShiftRightNarrowImm},
- {"uqshrn_asisdshf_n",
+ {"uqshrn_asisdshf_n"_h,
&Disassembler::DisassembleNEONScalarShiftRightNarrowImm},
- {"cmeq_asisdmisc_z", &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
- {"cmge_asisdmisc_z", &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
- {"cmgt_asisdmisc_z", &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
- {"cmle_asisdmisc_z", &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
- {"cmlt_asisdmisc_z", &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
- {"abs_asisdmisc_r", &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
- {"neg_asisdmisc_r", &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
- {"fcmeq_asisdmisc_fz", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcmge_asisdmisc_fz", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcmgt_asisdmisc_fz", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcmle_asisdmisc_fz", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcmlt_asisdmisc_fz", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcvtas_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcvtau_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcvtms_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcvtmu_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcvtns_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcvtnu_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcvtps_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcvtpu_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcvtxn_asisdmisc_n", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcvtzs_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"fcvtzu_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"frecpe_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"frecpx_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"frsqrte_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"scvtf_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"ucvtf_asisdmisc_r", &Disassembler::DisassembleNEONFPScalar2RegMisc},
- {"adclb_z_zzz", &Disassembler::DisassembleSVEAddSubCarry},
- {"adclt_z_zzz", &Disassembler::DisassembleSVEAddSubCarry},
- {"addhnb_z_zz", &Disassembler::DisassembleSVEAddSubHigh},
- {"addhnt_z_zz", &Disassembler::DisassembleSVEAddSubHigh},
- {"addp_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"aesd_z_zz", &Disassembler::Disassemble_ZdnB_ZdnB_ZmB},
- {"aese_z_zz", &Disassembler::Disassemble_ZdnB_ZdnB_ZmB},
- {"aesimc_z_z", &Disassembler::Disassemble_ZdnB_ZdnB},
- {"aesmc_z_z", &Disassembler::Disassemble_ZdnB_ZdnB},
- {"bcax_z_zzz", &Disassembler::DisassembleSVEBitwiseTernary},
- {"bdep_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmT},
- {"bext_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmT},
- {"bgrp_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmT},
- {"bsl1n_z_zzz", &Disassembler::DisassembleSVEBitwiseTernary},
- {"bsl2n_z_zzz", &Disassembler::DisassembleSVEBitwiseTernary},
- {"bsl_z_zzz", &Disassembler::DisassembleSVEBitwiseTernary},
- {"cadd_z_zz", &Disassembler::DisassembleSVEComplexIntAddition},
- {"cdot_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb_const},
- {"cdot_z_zzzi_d", &Disassembler::Disassemble_ZdaD_ZnH_ZmH_imm_const},
- {"cdot_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnB_ZmB_imm_const},
- {"cmla_z_zzz", &Disassembler::Disassemble_ZdaT_ZnT_ZmT_const},
- {"cmla_z_zzzi_h", &Disassembler::Disassemble_ZdaH_ZnH_ZmH_imm_const},
- {"cmla_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnS_ZmS_imm_const},
- {"eor3_z_zzz", &Disassembler::DisassembleSVEBitwiseTernary},
- {"eorbt_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmT},
- {"eortb_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmT},
- {"ext_z_zi_con", &Disassembler::Disassemble_ZdB_Zn1B_Zn2B_imm},
- {"faddp_z_p_zz", &Disassembler::DisassembleSVEFPPair},
- {"fcvtlt_z_p_z_h2s", &Disassembler::Disassemble_ZdS_PgM_ZnH},
- {"fcvtlt_z_p_z_s2d", &Disassembler::Disassemble_ZdD_PgM_ZnS},
- {"fcvtnt_z_p_z_d2s", &Disassembler::Disassemble_ZdS_PgM_ZnD},
- {"fcvtnt_z_p_z_s2h", &Disassembler::Disassemble_ZdH_PgM_ZnS},
- {"fcvtx_z_p_z_d2s", &Disassembler::Disassemble_ZdS_PgM_ZnD},
- {"fcvtxnt_z_p_z_d2s", &Disassembler::Disassemble_ZdS_PgM_ZnD},
- {"flogb_z_p_z", &Disassembler::DisassembleSVEFlogb},
- {"fmaxnmp_z_p_zz", &Disassembler::DisassembleSVEFPPair},
- {"fmaxp_z_p_zz", &Disassembler::DisassembleSVEFPPair},
- {"fminnmp_z_p_zz", &Disassembler::DisassembleSVEFPPair},
- {"fminp_z_p_zz", &Disassembler::DisassembleSVEFPPair},
- {"fmlalb_z_zzz", &Disassembler::Disassemble_ZdaS_ZnH_ZmH},
- {"fmlalb_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
- {"fmlalt_z_zzz", &Disassembler::Disassemble_ZdaS_ZnH_ZmH},
- {"fmlalt_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
- {"fmlslb_z_zzz", &Disassembler::Disassemble_ZdaS_ZnH_ZmH},
- {"fmlslb_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
- {"fmlslt_z_zzz", &Disassembler::Disassemble_ZdaS_ZnH_ZmH},
- {"fmlslt_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
- {"histcnt_z_p_zz", &Disassembler::Disassemble_ZdT_PgZ_ZnT_ZmT},
- {"histseg_z_zz", &Disassembler::Disassemble_ZdB_ZnB_ZmB},
- {"ldnt1b_z_p_ar_d_64_unscaled",
+ {"cmeq_asisdmisc_z"_h, &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
+ {"cmge_asisdmisc_z"_h, &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
+ {"cmgt_asisdmisc_z"_h, &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
+ {"cmle_asisdmisc_z"_h, &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
+ {"cmlt_asisdmisc_z"_h, &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
+ {"abs_asisdmisc_r"_h, &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
+ {"neg_asisdmisc_r"_h, &Disassembler::DisassembleNEONScalar2RegMiscOnlyD},
+ {"fcmeq_asisdmisc_fz"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcmge_asisdmisc_fz"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcmgt_asisdmisc_fz"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcmle_asisdmisc_fz"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcmlt_asisdmisc_fz"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcvtas_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcvtau_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcvtms_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcvtmu_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcvtns_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcvtnu_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcvtps_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcvtpu_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcvtxn_asisdmisc_n"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcvtzs_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"fcvtzu_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"frecpe_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"frecpx_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"frsqrte_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"scvtf_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"ucvtf_asisdmisc_r"_h, &Disassembler::DisassembleNEONFPScalar2RegMisc},
+ {"adclb_z_zzz"_h, &Disassembler::DisassembleSVEAddSubCarry},
+ {"adclt_z_zzz"_h, &Disassembler::DisassembleSVEAddSubCarry},
+ {"addhnb_z_zz"_h, &Disassembler::DisassembleSVEAddSubHigh},
+ {"addhnt_z_zz"_h, &Disassembler::DisassembleSVEAddSubHigh},
+ {"addp_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"aesd_z_zz"_h, &Disassembler::Disassemble_ZdnB_ZdnB_ZmB},
+ {"aese_z_zz"_h, &Disassembler::Disassemble_ZdnB_ZdnB_ZmB},
+ {"aesimc_z_z"_h, &Disassembler::Disassemble_ZdnB_ZdnB},
+ {"aesmc_z_z"_h, &Disassembler::Disassemble_ZdnB_ZdnB},
+ {"bcax_z_zzz"_h, &Disassembler::DisassembleSVEBitwiseTernary},
+ {"bdep_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmT},
+ {"bext_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmT},
+ {"bgrp_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmT},
+ {"bsl1n_z_zzz"_h, &Disassembler::DisassembleSVEBitwiseTernary},
+ {"bsl2n_z_zzz"_h, &Disassembler::DisassembleSVEBitwiseTernary},
+ {"bsl_z_zzz"_h, &Disassembler::DisassembleSVEBitwiseTernary},
+ {"cadd_z_zz"_h, &Disassembler::DisassembleSVEComplexIntAddition},
+ {"cdot_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb_const},
+ {"cdot_z_zzzi_d"_h, &Disassembler::Disassemble_ZdaD_ZnH_ZmH_imm_const},
+ {"cdot_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnB_ZmB_imm_const},
+ {"cmla_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnT_ZmT_const},
+ {"cmla_z_zzzi_h"_h, &Disassembler::Disassemble_ZdaH_ZnH_ZmH_imm_const},
+ {"cmla_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnS_ZmS_imm_const},
+ {"eor3_z_zzz"_h, &Disassembler::DisassembleSVEBitwiseTernary},
+ {"eorbt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmT},
+ {"eortb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmT},
+ {"ext_z_zi_con"_h, &Disassembler::Disassemble_ZdB_Zn1B_Zn2B_imm},
+ {"faddp_z_p_zz"_h, &Disassembler::DisassembleSVEFPPair},
+ {"fcvtlt_z_p_z_h2s"_h, &Disassembler::Disassemble_ZdS_PgM_ZnH},
+ {"fcvtlt_z_p_z_s2d"_h, &Disassembler::Disassemble_ZdD_PgM_ZnS},
+ {"fcvtnt_z_p_z_d2s"_h, &Disassembler::Disassemble_ZdS_PgM_ZnD},
+ {"fcvtnt_z_p_z_s2h"_h, &Disassembler::Disassemble_ZdH_PgM_ZnS},
+ {"fcvtx_z_p_z_d2s"_h, &Disassembler::Disassemble_ZdS_PgM_ZnD},
+ {"fcvtxnt_z_p_z_d2s"_h, &Disassembler::Disassemble_ZdS_PgM_ZnD},
+ {"flogb_z_p_z"_h, &Disassembler::DisassembleSVEFlogb},
+ {"fmaxnmp_z_p_zz"_h, &Disassembler::DisassembleSVEFPPair},
+ {"fmaxp_z_p_zz"_h, &Disassembler::DisassembleSVEFPPair},
+ {"fminnmp_z_p_zz"_h, &Disassembler::DisassembleSVEFPPair},
+ {"fminp_z_p_zz"_h, &Disassembler::DisassembleSVEFPPair},
+ {"fmlalb_z_zzz"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH},
+ {"fmlalb_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
+ {"fmlalt_z_zzz"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH},
+ {"fmlalt_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
+ {"fmlslb_z_zzz"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH},
+ {"fmlslb_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
+ {"fmlslt_z_zzz"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH},
+ {"fmlslt_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
+ {"histcnt_z_p_zz"_h, &Disassembler::Disassemble_ZdT_PgZ_ZnT_ZmT},
+ {"histseg_z_zz"_h, &Disassembler::Disassemble_ZdB_ZnB_ZmB},
+ {"ldnt1b_z_p_ar_d_64_unscaled"_h,
&Disassembler::Disassemble_ZtD_PgZ_ZnD_Xm},
- {"ldnt1b_z_p_ar_s_x32_unscaled",
+ {"ldnt1b_z_p_ar_s_x32_unscaled"_h,
&Disassembler::Disassemble_ZtS_PgZ_ZnS_Xm},
- {"ldnt1d_z_p_ar_d_64_unscaled",
+ {"ldnt1d_z_p_ar_d_64_unscaled"_h,
&Disassembler::Disassemble_ZtD_PgZ_ZnD_Xm},
- {"ldnt1h_z_p_ar_d_64_unscaled",
+ {"ldnt1h_z_p_ar_d_64_unscaled"_h,
&Disassembler::Disassemble_ZtD_PgZ_ZnD_Xm},
- {"ldnt1h_z_p_ar_s_x32_unscaled",
+ {"ldnt1h_z_p_ar_s_x32_unscaled"_h,
&Disassembler::Disassemble_ZtS_PgZ_ZnS_Xm},
- {"ldnt1sb_z_p_ar_d_64_unscaled",
+ {"ldnt1sb_z_p_ar_d_64_unscaled"_h,
&Disassembler::Disassemble_ZtD_PgZ_ZnD_Xm},
- {"ldnt1sb_z_p_ar_s_x32_unscaled",
+ {"ldnt1sb_z_p_ar_s_x32_unscaled"_h,
&Disassembler::Disassemble_ZtS_PgZ_ZnS_Xm},
- {"ldnt1sh_z_p_ar_d_64_unscaled",
+ {"ldnt1sh_z_p_ar_d_64_unscaled"_h,
&Disassembler::Disassemble_ZtD_PgZ_ZnD_Xm},
- {"ldnt1sh_z_p_ar_s_x32_unscaled",
+ {"ldnt1sh_z_p_ar_s_x32_unscaled"_h,
&Disassembler::Disassemble_ZtS_PgZ_ZnS_Xm},
- {"ldnt1sw_z_p_ar_d_64_unscaled",
+ {"ldnt1sw_z_p_ar_d_64_unscaled"_h,
&Disassembler::Disassemble_ZtD_PgZ_ZnD_Xm},
- {"ldnt1w_z_p_ar_d_64_unscaled",
+ {"ldnt1w_z_p_ar_d_64_unscaled"_h,
&Disassembler::Disassemble_ZtD_PgZ_ZnD_Xm},
- {"ldnt1w_z_p_ar_s_x32_unscaled",
+ {"ldnt1w_z_p_ar_s_x32_unscaled"_h,
&Disassembler::Disassemble_ZtS_PgZ_ZnS_Xm},
- {"match_p_p_zz", &Disassembler::Disassemble_PdT_PgZ_ZnT_ZmT},
- {"mla_z_zzzi_d", &Disassembler::Disassemble_ZdD_ZnD_ZmD_imm},
- {"mla_z_zzzi_h", &Disassembler::Disassemble_ZdH_ZnH_ZmH_imm},
- {"mla_z_zzzi_s", &Disassembler::Disassemble_ZdS_ZnS_ZmS_imm},
- {"mls_z_zzzi_d", &Disassembler::Disassemble_ZdD_ZnD_ZmD_imm},
- {"mls_z_zzzi_h", &Disassembler::Disassemble_ZdH_ZnH_ZmH_imm},
- {"mls_z_zzzi_s", &Disassembler::Disassemble_ZdS_ZnS_ZmS_imm},
- {"mul_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmT},
- {"mul_z_zzi_d", &Disassembler::Disassemble_ZdD_ZnD_ZmD_imm},
- {"mul_z_zzi_h", &Disassembler::Disassemble_ZdH_ZnH_ZmH_imm},
- {"mul_z_zzi_s", &Disassembler::Disassemble_ZdS_ZnS_ZmS_imm},
- {"nbsl_z_zzz", &Disassembler::DisassembleSVEBitwiseTernary},
- {"nmatch_p_p_zz", &Disassembler::Disassemble_PdT_PgZ_ZnT_ZmT},
- {"pmul_z_zz", &Disassembler::Disassemble_ZdB_ZnB_ZmB},
- {"pmullb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"pmullt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"raddhnb_z_zz", &Disassembler::DisassembleSVEAddSubHigh},
- {"raddhnt_z_zz", &Disassembler::DisassembleSVEAddSubHigh},
- {"rax1_z_zz", &Disassembler::Disassemble_ZdD_ZnD_ZmD},
- {"rshrnb_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"rshrnt_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"rsubhnb_z_zz", &Disassembler::DisassembleSVEAddSubHigh},
- {"rsubhnt_z_zz", &Disassembler::DisassembleSVEAddSubHigh},
- {"saba_z_zzz", &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
- {"sabalb_z_zzz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"sabalt_z_zzz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"sabdlb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"sabdlt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"sadalp_z_p_z", &Disassembler::Disassemble_ZdaT_PgM_ZnTb},
- {"saddlb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"saddlbt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"saddlt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"saddwb_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
- {"saddwt_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
- {"sbclb_z_zzz", &Disassembler::DisassembleSVEAddSubCarry},
- {"sbclt_z_zzz", &Disassembler::DisassembleSVEAddSubCarry},
- {"shadd_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"shrnb_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"shrnt_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"shsub_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"shsubr_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"sli_z_zzi", &Disassembler::VisitSVEBitwiseShiftUnpredicated},
- {"sm4e_z_zz", &Disassembler::Disassemble_ZdnS_ZdnS_ZmS},
- {"sm4ekey_z_zz", &Disassembler::Disassemble_ZdS_ZnS_ZmS},
- {"smaxp_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"sminp_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"smlalb_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"smlalb_z_zzzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"smlalb_z_zzzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"smlalt_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"smlalt_z_zzzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"smlalt_z_zzzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"smlslb_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"smlslb_z_zzzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"smlslb_z_zzzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"smlslt_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"smlslt_z_zzzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"smlslt_z_zzzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"smulh_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmT},
- {"smullb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"smullb_z_zzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"smullb_z_zzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"smullt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"smullt_z_zzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"smullt_z_zzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"splice_z_p_zz_con", &Disassembler::Disassemble_ZdT_Pg_Zn1T_Zn2T},
- {"sqabs_z_p_z", &Disassembler::Disassemble_ZdT_PgM_ZnT},
- {"sqadd_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"sqcadd_z_zz", &Disassembler::DisassembleSVEComplexIntAddition},
- {"sqdmlalb_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"sqdmlalb_z_zzzi_d", &Disassembler::Disassemble_ZdaD_ZnS_ZmS_imm},
- {"sqdmlalb_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
- {"sqdmlalbt_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"sqdmlalt_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"sqdmlalt_z_zzzi_d", &Disassembler::Disassemble_ZdaD_ZnS_ZmS_imm},
- {"sqdmlalt_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
- {"sqdmlslb_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"sqdmlslb_z_zzzi_d", &Disassembler::Disassemble_ZdaD_ZnS_ZmS_imm},
- {"sqdmlslb_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
- {"sqdmlslbt_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"sqdmlslt_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"sqdmlslt_z_zzzi_d", &Disassembler::Disassemble_ZdaD_ZnS_ZmS_imm},
- {"sqdmlslt_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
- {"sqdmulh_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmT},
- {"sqdmulh_z_zzi_d", &Disassembler::Disassemble_ZdD_ZnD_ZmD_imm},
- {"sqdmulh_z_zzi_h", &Disassembler::Disassemble_ZdH_ZnH_ZmH_imm},
- {"sqdmulh_z_zzi_s", &Disassembler::Disassemble_ZdS_ZnS_ZmS_imm},
- {"sqdmullb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"sqdmullb_z_zzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"sqdmullb_z_zzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"sqdmullt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"sqdmullt_z_zzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"sqdmullt_z_zzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"sqneg_z_p_z", &Disassembler::Disassemble_ZdT_PgM_ZnT},
- {"sqrdcmlah_z_zzz", &Disassembler::Disassemble_ZdaT_ZnT_ZmT_const},
- {"sqrdcmlah_z_zzzi_h", &Disassembler::Disassemble_ZdaH_ZnH_ZmH_imm_const},
- {"sqrdcmlah_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnS_ZmS_imm_const},
- {"sqrdmlah_z_zzz", &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
- {"sqrdmlah_z_zzzi_d", &Disassembler::Disassemble_ZdaD_ZnD_ZmD_imm},
- {"sqrdmlah_z_zzzi_h", &Disassembler::Disassemble_ZdaH_ZnH_ZmH_imm},
- {"sqrdmlah_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnS_ZmS_imm},
- {"sqrdmlsh_z_zzz", &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
- {"sqrdmlsh_z_zzzi_d", &Disassembler::Disassemble_ZdaD_ZnD_ZmD_imm},
- {"sqrdmlsh_z_zzzi_h", &Disassembler::Disassemble_ZdaH_ZnH_ZmH_imm},
- {"sqrdmlsh_z_zzzi_s", &Disassembler::Disassemble_ZdaS_ZnS_ZmS_imm},
- {"sqrdmulh_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmT},
- {"sqrdmulh_z_zzi_d", &Disassembler::Disassemble_ZdD_ZnD_ZmD_imm},
- {"sqrdmulh_z_zzi_h", &Disassembler::Disassemble_ZdH_ZnH_ZmH_imm},
- {"sqrdmulh_z_zzi_s", &Disassembler::Disassemble_ZdS_ZnS_ZmS_imm},
- {"sqrshl_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"sqrshlr_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"sqrshrnb_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"sqrshrnt_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"sqrshrunb_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"sqrshrunt_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"sqshl_z_p_zi", &Disassembler::VisitSVEBitwiseShiftByImm_Predicated},
- {"sqshl_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"sqshlr_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"sqshlu_z_p_zi", &Disassembler::VisitSVEBitwiseShiftByImm_Predicated},
- {"sqshrnb_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"sqshrnt_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"sqshrunb_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"sqshrunt_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"sqsub_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"sqsubr_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"sqxtnb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb},
- {"sqxtnt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb},
- {"sqxtunb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb},
- {"sqxtunt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb},
- {"srhadd_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"sri_z_zzi", &Disassembler::VisitSVEBitwiseShiftUnpredicated},
- {"srshl_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"srshlr_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"srshr_z_p_zi", &Disassembler::VisitSVEBitwiseShiftByImm_Predicated},
- {"srsra_z_zi", &Disassembler::VisitSVEBitwiseShiftUnpredicated},
- {"sshllb_z_zi", &Disassembler::DisassembleSVEShiftLeftImm},
- {"sshllt_z_zi", &Disassembler::DisassembleSVEShiftLeftImm},
- {"ssra_z_zi", &Disassembler::VisitSVEBitwiseShiftUnpredicated},
- {"ssublb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"ssublbt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"ssublt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"ssubltb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"ssubwb_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
- {"ssubwt_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
- {"stnt1b_z_p_ar_d_64_unscaled", &Disassembler::Disassemble_ZtD_Pg_ZnD_Xm},
- {"stnt1b_z_p_ar_s_x32_unscaled",
+ {"match_p_p_zz"_h, &Disassembler::Disassemble_PdT_PgZ_ZnT_ZmT},
+ {"mla_z_zzzi_d"_h, &Disassembler::Disassemble_ZdD_ZnD_ZmD_imm},
+ {"mla_z_zzzi_h"_h, &Disassembler::Disassemble_ZdH_ZnH_ZmH_imm},
+ {"mla_z_zzzi_s"_h, &Disassembler::Disassemble_ZdS_ZnS_ZmS_imm},
+ {"mls_z_zzzi_d"_h, &Disassembler::Disassemble_ZdD_ZnD_ZmD_imm},
+ {"mls_z_zzzi_h"_h, &Disassembler::Disassemble_ZdH_ZnH_ZmH_imm},
+ {"mls_z_zzzi_s"_h, &Disassembler::Disassemble_ZdS_ZnS_ZmS_imm},
+ {"mul_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmT},
+ {"mul_z_zzi_d"_h, &Disassembler::Disassemble_ZdD_ZnD_ZmD_imm},
+ {"mul_z_zzi_h"_h, &Disassembler::Disassemble_ZdH_ZnH_ZmH_imm},
+ {"mul_z_zzi_s"_h, &Disassembler::Disassemble_ZdS_ZnS_ZmS_imm},
+ {"nbsl_z_zzz"_h, &Disassembler::DisassembleSVEBitwiseTernary},
+ {"nmatch_p_p_zz"_h, &Disassembler::Disassemble_PdT_PgZ_ZnT_ZmT},
+ {"pmul_z_zz"_h, &Disassembler::Disassemble_ZdB_ZnB_ZmB},
+ {"pmullb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"pmullt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"raddhnb_z_zz"_h, &Disassembler::DisassembleSVEAddSubHigh},
+ {"raddhnt_z_zz"_h, &Disassembler::DisassembleSVEAddSubHigh},
+ {"rax1_z_zz"_h, &Disassembler::Disassemble_ZdD_ZnD_ZmD},
+ {"rshrnb_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"rshrnt_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"rsubhnb_z_zz"_h, &Disassembler::DisassembleSVEAddSubHigh},
+ {"rsubhnt_z_zz"_h, &Disassembler::DisassembleSVEAddSubHigh},
+ {"saba_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
+ {"sabalb_z_zzz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"sabalt_z_zzz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"sabdlb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"sabdlt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"sadalp_z_p_z"_h, &Disassembler::Disassemble_ZdaT_PgM_ZnTb},
+ {"saddlb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"saddlbt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"saddlt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"saddwb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
+ {"saddwt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
+ {"sbclb_z_zzz"_h, &Disassembler::DisassembleSVEAddSubCarry},
+ {"sbclt_z_zzz"_h, &Disassembler::DisassembleSVEAddSubCarry},
+ {"shadd_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"shrnb_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"shrnt_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"shsub_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"shsubr_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"sli_z_zzi"_h, &Disassembler::VisitSVEBitwiseShiftUnpredicated},
+ {"sm4e_z_zz"_h, &Disassembler::Disassemble_ZdnS_ZdnS_ZmS},
+ {"sm4ekey_z_zz"_h, &Disassembler::Disassemble_ZdS_ZnS_ZmS},
+ {"smaxp_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"sminp_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"smlalb_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"smlalb_z_zzzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"smlalb_z_zzzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"smlalt_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"smlalt_z_zzzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"smlalt_z_zzzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"smlslb_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"smlslb_z_zzzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"smlslb_z_zzzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"smlslt_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"smlslt_z_zzzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"smlslt_z_zzzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"smulh_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmT},
+ {"smullb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"smullb_z_zzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"smullb_z_zzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"smullt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"smullt_z_zzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"smullt_z_zzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"splice_z_p_zz_con"_h, &Disassembler::Disassemble_ZdT_Pg_Zn1T_Zn2T},
+ {"sqabs_z_p_z"_h, &Disassembler::Disassemble_ZdT_PgM_ZnT},
+ {"sqadd_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"sqcadd_z_zz"_h, &Disassembler::DisassembleSVEComplexIntAddition},
+ {"sqdmlalb_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"sqdmlalb_z_zzzi_d"_h, &Disassembler::Disassemble_ZdaD_ZnS_ZmS_imm},
+ {"sqdmlalb_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
+ {"sqdmlalbt_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"sqdmlalt_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"sqdmlalt_z_zzzi_d"_h, &Disassembler::Disassemble_ZdaD_ZnS_ZmS_imm},
+ {"sqdmlalt_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
+ {"sqdmlslb_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"sqdmlslb_z_zzzi_d"_h, &Disassembler::Disassemble_ZdaD_ZnS_ZmS_imm},
+ {"sqdmlslb_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
+ {"sqdmlslbt_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"sqdmlslt_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"sqdmlslt_z_zzzi_d"_h, &Disassembler::Disassemble_ZdaD_ZnS_ZmS_imm},
+ {"sqdmlslt_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnH_ZmH_imm},
+ {"sqdmulh_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmT},
+ {"sqdmulh_z_zzi_d"_h, &Disassembler::Disassemble_ZdD_ZnD_ZmD_imm},
+ {"sqdmulh_z_zzi_h"_h, &Disassembler::Disassemble_ZdH_ZnH_ZmH_imm},
+ {"sqdmulh_z_zzi_s"_h, &Disassembler::Disassemble_ZdS_ZnS_ZmS_imm},
+ {"sqdmullb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"sqdmullb_z_zzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"sqdmullb_z_zzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"sqdmullt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"sqdmullt_z_zzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"sqdmullt_z_zzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"sqneg_z_p_z"_h, &Disassembler::Disassemble_ZdT_PgM_ZnT},
+ {"sqrdcmlah_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnT_ZmT_const},
+ {"sqrdcmlah_z_zzzi_h"_h,
+ &Disassembler::Disassemble_ZdaH_ZnH_ZmH_imm_const},
+ {"sqrdcmlah_z_zzzi_s"_h,
+ &Disassembler::Disassemble_ZdaS_ZnS_ZmS_imm_const},
+ {"sqrdmlah_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
+ {"sqrdmlah_z_zzzi_d"_h, &Disassembler::Disassemble_ZdaD_ZnD_ZmD_imm},
+ {"sqrdmlah_z_zzzi_h"_h, &Disassembler::Disassemble_ZdaH_ZnH_ZmH_imm},
+ {"sqrdmlah_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnS_ZmS_imm},
+ {"sqrdmlsh_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
+ {"sqrdmlsh_z_zzzi_d"_h, &Disassembler::Disassemble_ZdaD_ZnD_ZmD_imm},
+ {"sqrdmlsh_z_zzzi_h"_h, &Disassembler::Disassemble_ZdaH_ZnH_ZmH_imm},
+ {"sqrdmlsh_z_zzzi_s"_h, &Disassembler::Disassemble_ZdaS_ZnS_ZmS_imm},
+ {"sqrdmulh_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmT},
+ {"sqrdmulh_z_zzi_d"_h, &Disassembler::Disassemble_ZdD_ZnD_ZmD_imm},
+ {"sqrdmulh_z_zzi_h"_h, &Disassembler::Disassemble_ZdH_ZnH_ZmH_imm},
+ {"sqrdmulh_z_zzi_s"_h, &Disassembler::Disassemble_ZdS_ZnS_ZmS_imm},
+ {"sqrshl_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"sqrshlr_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"sqrshrnb_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"sqrshrnt_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"sqrshrunb_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"sqrshrunt_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"sqshl_z_p_zi"_h, &Disassembler::VisitSVEBitwiseShiftByImm_Predicated},
+ {"sqshl_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"sqshlr_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"sqshlu_z_p_zi"_h, &Disassembler::VisitSVEBitwiseShiftByImm_Predicated},
+ {"sqshrnb_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"sqshrnt_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"sqshrunb_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"sqshrunt_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"sqsub_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"sqsubr_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"sqxtnb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb},
+ {"sqxtnt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb},
+ {"sqxtunb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb},
+ {"sqxtunt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb},
+ {"srhadd_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"sri_z_zzi"_h, &Disassembler::VisitSVEBitwiseShiftUnpredicated},
+ {"srshl_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"srshlr_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"srshr_z_p_zi"_h, &Disassembler::VisitSVEBitwiseShiftByImm_Predicated},
+ {"srsra_z_zi"_h, &Disassembler::VisitSVEBitwiseShiftUnpredicated},
+ {"sshllb_z_zi"_h, &Disassembler::DisassembleSVEShiftLeftImm},
+ {"sshllt_z_zi"_h, &Disassembler::DisassembleSVEShiftLeftImm},
+ {"ssra_z_zi"_h, &Disassembler::VisitSVEBitwiseShiftUnpredicated},
+ {"ssublb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"ssublbt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"ssublt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"ssubltb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"ssubwb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
+ {"ssubwt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
+ {"stnt1b_z_p_ar_d_64_unscaled"_h,
+ &Disassembler::Disassemble_ZtD_Pg_ZnD_Xm},
+ {"stnt1b_z_p_ar_s_x32_unscaled"_h,
&Disassembler::Disassemble_ZtS_Pg_ZnS_Xm},
- {"stnt1d_z_p_ar_d_64_unscaled", &Disassembler::Disassemble_ZtD_Pg_ZnD_Xm},
- {"stnt1h_z_p_ar_d_64_unscaled", &Disassembler::Disassemble_ZtD_Pg_ZnD_Xm},
- {"stnt1h_z_p_ar_s_x32_unscaled",
+ {"stnt1d_z_p_ar_d_64_unscaled"_h,
+ &Disassembler::Disassemble_ZtD_Pg_ZnD_Xm},
+ {"stnt1h_z_p_ar_d_64_unscaled"_h,
+ &Disassembler::Disassemble_ZtD_Pg_ZnD_Xm},
+ {"stnt1h_z_p_ar_s_x32_unscaled"_h,
&Disassembler::Disassemble_ZtS_Pg_ZnS_Xm},
- {"stnt1w_z_p_ar_d_64_unscaled", &Disassembler::Disassemble_ZtD_Pg_ZnD_Xm},
- {"stnt1w_z_p_ar_s_x32_unscaled",
+ {"stnt1w_z_p_ar_d_64_unscaled"_h,
+ &Disassembler::Disassemble_ZtD_Pg_ZnD_Xm},
+ {"stnt1w_z_p_ar_s_x32_unscaled"_h,
&Disassembler::Disassemble_ZtS_Pg_ZnS_Xm},
- {"subhnb_z_zz", &Disassembler::DisassembleSVEAddSubHigh},
- {"subhnt_z_zz", &Disassembler::DisassembleSVEAddSubHigh},
- {"suqadd_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"tbl_z_zz_2", &Disassembler::Disassemble_ZdT_Zn1T_Zn2T_ZmT},
- {"tbx_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmT},
- {"uaba_z_zzz", &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
- {"uabalb_z_zzz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"uabalt_z_zzz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"uabdlb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"uabdlt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"uadalp_z_p_z", &Disassembler::Disassemble_ZdaT_PgM_ZnTb},
- {"uaddlb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"uaddlt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"uaddwb_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
- {"uaddwt_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
- {"uhadd_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"uhsub_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"uhsubr_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"umaxp_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"uminp_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"umlalb_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"umlalb_z_zzzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"umlalb_z_zzzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"umlalt_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"umlalt_z_zzzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"umlalt_z_zzzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"umlslb_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"umlslb_z_zzzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"umlslb_z_zzzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"umlslt_z_zzz", &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
- {"umlslt_z_zzzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"umlslt_z_zzzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"umulh_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmT},
- {"umullb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"umullb_z_zzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"umullb_z_zzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"umullt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"umullt_z_zzi_d", &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
- {"umullt_z_zzi_s", &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
- {"uqadd_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"uqrshl_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"uqrshlr_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"uqrshrnb_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"uqrshrnt_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"uqshl_z_p_zi", &Disassembler::VisitSVEBitwiseShiftByImm_Predicated},
- {"uqshl_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"uqshlr_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"uqshrnb_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"uqshrnt_z_zi", &Disassembler::DisassembleSVEShiftRightImm},
- {"uqsub_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"uqsubr_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"uqxtnb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb},
- {"uqxtnt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb},
- {"urecpe_z_p_z", &Disassembler::Disassemble_ZdS_PgM_ZnS},
- {"urhadd_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"urshl_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"urshlr_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"urshr_z_p_zi", &Disassembler::VisitSVEBitwiseShiftByImm_Predicated},
- {"ursqrte_z_p_z", &Disassembler::Disassemble_ZdS_PgM_ZnS},
- {"ursra_z_zi", &Disassembler::VisitSVEBitwiseShiftUnpredicated},
- {"ushllb_z_zi", &Disassembler::DisassembleSVEShiftLeftImm},
- {"ushllt_z_zi", &Disassembler::DisassembleSVEShiftLeftImm},
- {"usqadd_z_p_zz", &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
- {"usra_z_zi", &Disassembler::VisitSVEBitwiseShiftUnpredicated},
- {"usublb_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"usublt_z_zz", &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
- {"usubwb_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
- {"usubwt_z_zz", &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
- {"whilege_p_p_rr", &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
- {"whilegt_p_p_rr", &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
- {"whilehi_p_p_rr", &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
- {"whilehs_p_p_rr", &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
- {"whilerw_p_rr", &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
- {"whilewr_p_rr", &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
- {"xar_z_zzi", &Disassembler::Disassemble_ZdnT_ZdnT_ZmT_const},
- {"fmmla_z_zzz_s", &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
- {"fmmla_z_zzz_d", &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
- {"smmla_z_zzz", &Disassembler::Disassemble_ZdaS_ZnB_ZmB},
- {"ummla_z_zzz", &Disassembler::Disassemble_ZdaS_ZnB_ZmB},
- {"usmmla_z_zzz", &Disassembler::Disassemble_ZdaS_ZnB_ZmB},
- {"usdot_z_zzz_s", &Disassembler::Disassemble_ZdaS_ZnB_ZmB},
- {"smmla_asimdsame2_g", &Disassembler::Disassemble_Vd4S_Vn16B_Vm16B},
- {"ummla_asimdsame2_g", &Disassembler::Disassemble_Vd4S_Vn16B_Vm16B},
- {"usmmla_asimdsame2_g", &Disassembler::Disassemble_Vd4S_Vn16B_Vm16B},
- {"ld1row_z_p_bi_u32",
+ {"subhnb_z_zz"_h, &Disassembler::DisassembleSVEAddSubHigh},
+ {"subhnt_z_zz"_h, &Disassembler::DisassembleSVEAddSubHigh},
+ {"suqadd_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"tbl_z_zz_2"_h, &Disassembler::Disassemble_ZdT_Zn1T_Zn2T_ZmT},
+ {"tbx_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmT},
+ {"uaba_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
+ {"uabalb_z_zzz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"uabalt_z_zzz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"uabdlb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"uabdlt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"uadalp_z_p_z"_h, &Disassembler::Disassemble_ZdaT_PgM_ZnTb},
+ {"uaddlb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"uaddlt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"uaddwb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
+ {"uaddwt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
+ {"uhadd_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"uhsub_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"uhsubr_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"umaxp_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"uminp_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"umlalb_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"umlalb_z_zzzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"umlalb_z_zzzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"umlalt_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"umlalt_z_zzzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"umlalt_z_zzzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"umlslb_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"umlslb_z_zzzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"umlslb_z_zzzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"umlslt_z_zzz"_h, &Disassembler::Disassemble_ZdaT_ZnTb_ZmTb},
+ {"umlslt_z_zzzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"umlslt_z_zzzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"umulh_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmT},
+ {"umullb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"umullb_z_zzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"umullb_z_zzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"umullt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"umullt_z_zzi_d"_h, &Disassembler::Disassemble_ZdD_ZnS_ZmS_imm},
+ {"umullt_z_zzi_s"_h, &Disassembler::Disassemble_ZdS_ZnH_ZmH_imm},
+ {"uqadd_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"uqrshl_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"uqrshlr_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"uqrshrnb_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"uqrshrnt_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"uqshl_z_p_zi"_h, &Disassembler::VisitSVEBitwiseShiftByImm_Predicated},
+ {"uqshl_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"uqshlr_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"uqshrnb_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"uqshrnt_z_zi"_h, &Disassembler::DisassembleSVEShiftRightImm},
+ {"uqsub_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"uqsubr_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"uqxtnb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb},
+ {"uqxtnt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb},
+ {"urecpe_z_p_z"_h, &Disassembler::Disassemble_ZdS_PgM_ZnS},
+ {"urhadd_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"urshl_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"urshlr_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"urshr_z_p_zi"_h, &Disassembler::VisitSVEBitwiseShiftByImm_Predicated},
+ {"ursqrte_z_p_z"_h, &Disassembler::Disassemble_ZdS_PgM_ZnS},
+ {"ursra_z_zi"_h, &Disassembler::VisitSVEBitwiseShiftUnpredicated},
+ {"ushllb_z_zi"_h, &Disassembler::DisassembleSVEShiftLeftImm},
+ {"ushllt_z_zi"_h, &Disassembler::DisassembleSVEShiftLeftImm},
+ {"usqadd_z_p_zz"_h, &Disassembler::Disassemble_ZdnT_PgM_ZdnT_ZmT},
+ {"usra_z_zi"_h, &Disassembler::VisitSVEBitwiseShiftUnpredicated},
+ {"usublb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"usublt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnTb_ZmTb},
+ {"usubwb_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
+ {"usubwt_z_zz"_h, &Disassembler::Disassemble_ZdT_ZnT_ZmTb},
+ {"whilege_p_p_rr"_h,
+ &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
+ {"whilegt_p_p_rr"_h,
+ &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
+ {"whilehi_p_p_rr"_h,
+ &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
+ {"whilehs_p_p_rr"_h,
+ &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
+ {"whilerw_p_rr"_h, &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
+ {"whilewr_p_rr"_h, &Disassembler::VisitSVEIntCompareScalarCountAndLimit},
+ {"xar_z_zzi"_h, &Disassembler::Disassemble_ZdnT_ZdnT_ZmT_const},
+ {"fmmla_z_zzz_s"_h, &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
+ {"fmmla_z_zzz_d"_h, &Disassembler::Disassemble_ZdaT_ZnT_ZmT},
+ {"smmla_z_zzz"_h, &Disassembler::Disassemble_ZdaS_ZnB_ZmB},
+ {"ummla_z_zzz"_h, &Disassembler::Disassemble_ZdaS_ZnB_ZmB},
+ {"usmmla_z_zzz"_h, &Disassembler::Disassemble_ZdaS_ZnB_ZmB},
+ {"usdot_z_zzz_s"_h, &Disassembler::Disassemble_ZdaS_ZnB_ZmB},
+ {"smmla_asimdsame2_g"_h, &Disassembler::Disassemble_Vd4S_Vn16B_Vm16B},
+ {"ummla_asimdsame2_g"_h, &Disassembler::Disassemble_Vd4S_Vn16B_Vm16B},
+ {"usmmla_asimdsame2_g"_h, &Disassembler::Disassemble_Vd4S_Vn16B_Vm16B},
+ {"ld1row_z_p_bi_u32"_h,
&Disassembler::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
- {"ld1row_z_p_br_contiguous",
+ {"ld1row_z_p_br_contiguous"_h,
&Disassembler::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
- {"ld1rod_z_p_bi_u64",
+ {"ld1rod_z_p_bi_u64"_h,
&Disassembler::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
- {"ld1rod_z_p_br_contiguous",
+ {"ld1rod_z_p_br_contiguous"_h,
&Disassembler::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
- {"ld1rob_z_p_bi_u8",
+ {"ld1rob_z_p_bi_u8"_h,
&Disassembler::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
- {"ld1rob_z_p_br_contiguous",
+ {"ld1rob_z_p_br_contiguous"_h,
&Disassembler::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
- {"ld1roh_z_p_bi_u16",
+ {"ld1roh_z_p_bi_u16"_h,
&Disassembler::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
- {"ld1roh_z_p_br_contiguous",
+ {"ld1roh_z_p_br_contiguous"_h,
&Disassembler::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
- {"usdot_z_zzzi_s", &Disassembler::VisitSVEMulIndex},
- {"sudot_z_zzzi_s", &Disassembler::VisitSVEMulIndex},
- {"usdot_asimdsame2_d", &Disassembler::VisitNEON3SameExtra},
- {"addg_64_addsub_immtags",
+ {"usdot_z_zzzi_s"_h, &Disassembler::VisitSVEMulIndex},
+ {"sudot_z_zzzi_s"_h, &Disassembler::VisitSVEMulIndex},
+ {"usdot_asimdsame2_d"_h, &Disassembler::VisitNEON3SameExtra},
+ {"addg_64_addsub_immtags"_h,
&Disassembler::Disassemble_XdSP_XnSP_uimm6_uimm4},
- {"gmi_64g_dp_2src", &Disassembler::Disassemble_Xd_XnSP_Xm},
- {"irg_64i_dp_2src", &Disassembler::Disassemble_XdSP_XnSP_Xm},
- {"ldg_64loffset_ldsttags", &Disassembler::DisassembleMTELoadTag},
- {"st2g_64soffset_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"st2g_64spost_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"st2g_64spre_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"stgp_64_ldstpair_off", &Disassembler::DisassembleMTEStoreTagPair},
- {"stgp_64_ldstpair_post", &Disassembler::DisassembleMTEStoreTagPair},
- {"stgp_64_ldstpair_pre", &Disassembler::DisassembleMTEStoreTagPair},
- {"stg_64soffset_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"stg_64spost_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"stg_64spre_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"stz2g_64soffset_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"stz2g_64spost_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"stz2g_64spre_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"stzg_64soffset_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"stzg_64spost_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"stzg_64spre_ldsttags", &Disassembler::DisassembleMTEStoreTag},
- {"subg_64_addsub_immtags",
+ {"gmi_64g_dp_2src"_h, &Disassembler::Disassemble_Xd_XnSP_Xm},
+ {"irg_64i_dp_2src"_h, &Disassembler::Disassemble_XdSP_XnSP_Xm},
+ {"ldg_64loffset_ldsttags"_h, &Disassembler::DisassembleMTELoadTag},
+ {"st2g_64soffset_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"st2g_64spost_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"st2g_64spre_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"stgp_64_ldstpair_off"_h, &Disassembler::DisassembleMTEStoreTagPair},
+ {"stgp_64_ldstpair_post"_h, &Disassembler::DisassembleMTEStoreTagPair},
+ {"stgp_64_ldstpair_pre"_h, &Disassembler::DisassembleMTEStoreTagPair},
+ {"stg_64soffset_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"stg_64spost_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"stg_64spre_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"stz2g_64soffset_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"stz2g_64spost_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"stz2g_64spre_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"stzg_64soffset_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"stzg_64spost_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"stzg_64spre_ldsttags"_h, &Disassembler::DisassembleMTEStoreTag},
+ {"subg_64_addsub_immtags"_h,
&Disassembler::Disassemble_XdSP_XnSP_uimm6_uimm4},
- {"subps_64s_dp_2src", &Disassembler::Disassemble_Xd_XnSP_XmSP},
- {"subp_64s_dp_2src", &Disassembler::Disassemble_Xd_XnSP_XmSP},
+ {"subps_64s_dp_2src"_h, &Disassembler::Disassemble_Xd_XnSP_XmSP},
+ {"subp_64s_dp_2src"_h, &Disassembler::Disassemble_Xd_XnSP_XmSP},
};
return &form_to_visitor;
} // NOLINT(readability/fn_size)
@@ -699,45 +728,33 @@
bool stack_op =
(rd_is_zr || RnIsZROrSP(instr)) && (instr->GetImmAddSub() == 0) ? true
: false;
- const char *mnemonic = "";
+ const char *mnemonic = mnemonic_.c_str();
const char *form = "'Rds, 'Rns, 'IAddSub";
const char *form_cmp = "'Rns, 'IAddSub";
const char *form_mov = "'Rds, 'Rns";
- switch (instr->Mask(AddSubImmediateMask)) {
- case ADD_w_imm:
- case ADD_x_imm: {
- mnemonic = "add";
+ switch (form_hash_) {
+ case "add_32_addsub_imm"_h:
+ case "add_64_addsub_imm"_h:
if (stack_op) {
mnemonic = "mov";
form = form_mov;
}
break;
- }
- case ADDS_w_imm:
- case ADDS_x_imm: {
- mnemonic = "adds";
+ case "adds_32s_addsub_imm"_h:
+ case "adds_64s_addsub_imm"_h:
if (rd_is_zr) {
mnemonic = "cmn";
form = form_cmp;
}
break;
- }
- case SUB_w_imm:
- case SUB_x_imm:
- mnemonic = "sub";
- break;
- case SUBS_w_imm:
- case SUBS_x_imm: {
- mnemonic = "subs";
+ case "subs_32s_addsub_imm"_h:
+ case "subs_64s_addsub_imm"_h:
if (rd_is_zr) {
mnemonic = "cmp";
form = form_cmp;
}
break;
- }
- default:
- VIXL_UNREACHABLE();
}
Format(instr, mnemonic, form);
}
@@ -746,37 +763,28 @@
void Disassembler::VisitAddSubShifted(const Instruction *instr) {
bool rd_is_zr = RdIsZROrSP(instr);
bool rn_is_zr = RnIsZROrSP(instr);
- const char *mnemonic = "";
+ const char *mnemonic = mnemonic_.c_str();
const char *form = "'Rd, 'Rn, 'Rm'NDP";
const char *form_cmp = "'Rn, 'Rm'NDP";
const char *form_neg = "'Rd, 'Rm'NDP";
- switch (instr->Mask(AddSubShiftedMask)) {
- case ADD_w_shift:
- case ADD_x_shift:
- mnemonic = "add";
- break;
- case ADDS_w_shift:
- case ADDS_x_shift: {
- mnemonic = "adds";
+ switch (form_hash_) {
+ case "adds_32_addsub_shift"_h:
+ case "adds_64_addsub_shift"_h:
if (rd_is_zr) {
mnemonic = "cmn";
form = form_cmp;
}
break;
- }
- case SUB_w_shift:
- case SUB_x_shift: {
- mnemonic = "sub";
+ case "sub_32_addsub_shift"_h:
+ case "sub_64_addsub_shift"_h:
if (rn_is_zr) {
mnemonic = "neg";
form = form_neg;
}
break;
- }
- case SUBS_w_shift:
- case SUBS_x_shift: {
- mnemonic = "subs";
+ case "subs_32_addsub_shift"_h:
+ case "subs_64_addsub_shift"_h:
if (rd_is_zr) {
mnemonic = "cmp";
form = form_cmp;
@@ -784,10 +792,6 @@
mnemonic = "negs";
form = form_neg;
}
- break;
- }
- default:
- VIXL_UNREACHABLE();
}
Format(instr, mnemonic, form);
}
@@ -877,40 +881,12 @@
void Disassembler::VisitRotateRightIntoFlags(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(RotateRightIntoFlags)";
-
- switch (instr->Mask(RotateRightIntoFlagsMask)) {
- case RMIF:
- mnemonic = "rmif";
- form = "'Xn, 'IRr, 'INzcv";
- break;
- default:
- VIXL_UNREACHABLE();
- }
-
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Xn, 'IRr, 'INzcv");
}
void Disassembler::VisitEvaluateIntoFlags(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(EvaluateIntoFlags)";
-
- switch (instr->Mask(EvaluateIntoFlagsMask)) {
- case SETF8:
- mnemonic = "setf8";
- form = "'Wn";
- break;
- case SETF16:
- mnemonic = "setf16";
- form = "'Wn";
- break;
- default:
- VIXL_UNREACHABLE();
- }
-
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Wn");
}
@@ -993,60 +969,32 @@
void Disassembler::VisitLogicalShifted(const Instruction *instr) {
bool rd_is_zr = RdIsZROrSP(instr);
bool rn_is_zr = RnIsZROrSP(instr);
- const char *mnemonic = "";
+ const char *mnemonic = mnemonic_.c_str();
const char *form = "'Rd, 'Rn, 'Rm'NLo";
- switch (instr->Mask(LogicalShiftedMask)) {
- case AND_w:
- case AND_x:
- mnemonic = "and";
- break;
- case BIC_w:
- case BIC_x:
- mnemonic = "bic";
- break;
- case EOR_w:
- case EOR_x:
- mnemonic = "eor";
- break;
- case EON_w:
- case EON_x:
- mnemonic = "eon";
- break;
- case BICS_w:
- case BICS_x:
- mnemonic = "bics";
- break;
- case ANDS_w:
- case ANDS_x: {
- mnemonic = "ands";
+ switch (form_hash_) {
+ case "ands_32_log_shift"_h:
+ case "ands_64_log_shift"_h:
if (rd_is_zr) {
mnemonic = "tst";
form = "'Rn, 'Rm'NLo";
}
break;
- }
- case ORR_w:
- case ORR_x: {
- mnemonic = "orr";
+ case "orr_32_log_shift"_h:
+ case "orr_64_log_shift"_h:
if (rn_is_zr && (instr->GetImmDPShift() == 0) &&
(instr->GetShiftDP() == LSL)) {
mnemonic = "mov";
form = "'Rd, 'Rm";
}
break;
- }
- case ORN_w:
- case ORN_x: {
- mnemonic = "orn";
+ case "orn_32_log_shift"_h:
+ case "orn_64_log_shift"_h:
if (rn_is_zr) {
mnemonic = "mvn";
form = "'Rd, 'Rm'NLo";
}
break;
- }
- default:
- VIXL_UNREACHABLE();
}
Format(instr, mnemonic, form);
@@ -1054,42 +1002,12 @@
void Disassembler::VisitConditionalCompareRegister(const Instruction *instr) {
- const char *mnemonic = "";
- const char *form = "'Rn, 'Rm, 'INzcv, 'Cond";
-
- switch (instr->Mask(ConditionalCompareRegisterMask)) {
- case CCMN_w:
- case CCMN_x:
- mnemonic = "ccmn";
- break;
- case CCMP_w:
- case CCMP_x:
- mnemonic = "ccmp";
- break;
- default:
- VIXL_UNREACHABLE();
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Rn, 'Rm, 'INzcv, 'Cond");
}
void Disassembler::VisitConditionalCompareImmediate(const Instruction *instr) {
- const char *mnemonic = "";
- const char *form = "'Rn, 'IP, 'INzcv, 'Cond";
-
- switch (instr->Mask(ConditionalCompareImmediateMask)) {
- case CCMN_w_imm:
- case CCMN_x_imm:
- mnemonic = "ccmn";
- break;
- case CCMP_w_imm:
- case CCMP_x_imm:
- mnemonic = "ccmp";
- break;
- default:
- VIXL_UNREACHABLE();
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Rn, 'IP, 'INzcv, 'Cond");
}
@@ -1280,174 +1198,102 @@
void Disassembler::VisitConditionalBranch(const Instruction *instr) {
- switch (instr->Mask(ConditionalBranchMask)) {
- case B_cond:
- Format(instr, "b.'CBrn", "'TImmCond");
- break;
- default:
- VIXL_UNREACHABLE();
- }
+ // We can't use the mnemonic directly here, as there's no space between it and
+ // the condition. Assert that we have the correct mnemonic, then use "b"
+ // explicitly for formatting the output.
+ VIXL_ASSERT(form_hash_ == "b_only_condbranch"_h);
+ Format(instr, "b.'CBrn", "'TImmCond");
}
void Disassembler::VisitUnconditionalBranchToRegister(
const Instruction *instr) {
- const char *mnemonic = mnemonic_.c_str();
const char *form = "'Xn";
switch (form_hash_) {
- case Hash("ret_64r_branch_reg"):
+ case "ret_64r_branch_reg"_h:
if (instr->GetRn() == kLinkRegCode) {
form = "";
}
break;
- case Hash("retaa_64e_branch_reg"):
- case Hash("retab_64e_branch_reg"):
+ case "retaa_64e_branch_reg"_h:
+ case "retab_64e_branch_reg"_h:
form = "";
break;
- case Hash("braa_64p_branch_reg"):
- case Hash("brab_64p_branch_reg"):
- case Hash("blraa_64p_branch_reg"):
- case Hash("blrab_64p_branch_reg"):
+ case "braa_64p_branch_reg"_h:
+ case "brab_64p_branch_reg"_h:
+ case "blraa_64p_branch_reg"_h:
+ case "blrab_64p_branch_reg"_h:
form = "'Xn, 'Xds";
break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitUnconditionalBranch(const Instruction *instr) {
- const char *mnemonic = "";
- const char *form = "'TImmUncn";
-
- switch (instr->Mask(UnconditionalBranchMask)) {
- case B:
- mnemonic = "b";
- break;
- case BL:
- mnemonic = "bl";
- break;
- default:
- VIXL_UNREACHABLE();
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'TImmUncn");
}
void Disassembler::VisitDataProcessing1Source(const Instruction *instr) {
- const char *mnemonic = "";
const char *form = "'Rd, 'Rn";
- switch (instr->Mask(DataProcessing1SourceMask)) {
-#define FORMAT(A, B) \
- case A##_w: \
- case A##_x: \
- mnemonic = B; \
- break;
- FORMAT(RBIT, "rbit");
- FORMAT(REV16, "rev16");
- FORMAT(REV, "rev");
- FORMAT(CLZ, "clz");
- FORMAT(CLS, "cls");
-#undef FORMAT
-
-#define PAUTH_VARIATIONS(V) \
- V(PACI, "paci") \
- V(PACD, "pacd") \
- V(AUTI, "auti") \
- V(AUTD, "autd")
-#define PAUTH_CASE(NAME, MN) \
- case NAME##A: \
- mnemonic = MN "a"; \
- form = "'Xd, 'Xns"; \
- break; \
- case NAME##ZA: \
- mnemonic = MN "za"; \
- form = "'Xd"; \
- break; \
- case NAME##B: \
- mnemonic = MN "b"; \
- form = "'Xd, 'Xns"; \
- break; \
- case NAME##ZB: \
- mnemonic = MN "zb"; \
- form = "'Xd"; \
- break;
-
- PAUTH_VARIATIONS(PAUTH_CASE)
-#undef PAUTH_CASE
-
- case XPACI:
- mnemonic = "xpaci";
+ switch (form_hash_) {
+ case "pacia_64p_dp_1src"_h:
+ case "pacda_64p_dp_1src"_h:
+ case "autia_64p_dp_1src"_h:
+ case "autda_64p_dp_1src"_h:
+ case "pacib_64p_dp_1src"_h:
+ case "pacdb_64p_dp_1src"_h:
+ case "autib_64p_dp_1src"_h:
+ case "autdb_64p_dp_1src"_h:
+ form = "'Xd, 'Xns";
+ break;
+ case "paciza_64z_dp_1src"_h:
+ case "pacdza_64z_dp_1src"_h:
+ case "autiza_64z_dp_1src"_h:
+ case "autdza_64z_dp_1src"_h:
+ case "pacizb_64z_dp_1src"_h:
+ case "pacdzb_64z_dp_1src"_h:
+ case "autizb_64z_dp_1src"_h:
+ case "autdzb_64z_dp_1src"_h:
+ case "xpacd_64z_dp_1src"_h:
+ case "xpaci_64z_dp_1src"_h:
form = "'Xd";
break;
- case XPACD:
- mnemonic = "xpacd";
- form = "'Xd";
- break;
- case REV32_x:
- mnemonic = "rev32";
- break;
- default:
- VIXL_UNREACHABLE();
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitDataProcessing2Source(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
+ std::string mnemonic = mnemonic_;
const char *form = "'Rd, 'Rn, 'Rm";
- const char *form_wwx = "'Wd, 'Wn, 'Xm";
- switch (instr->Mask(DataProcessing2SourceMask)) {
-#define FORMAT(A, B) \
- case A##_w: \
- case A##_x: \
- mnemonic = B; \
- break;
- FORMAT(UDIV, "udiv");
- FORMAT(SDIV, "sdiv");
- FORMAT(LSLV, "lsl");
- FORMAT(LSRV, "lsr");
- FORMAT(ASRV, "asr");
- FORMAT(RORV, "ror");
-#undef FORMAT
- case PACGA:
- mnemonic = "pacga";
+ switch (form_hash_) {
+ case "asrv_32_dp_2src"_h:
+ case "asrv_64_dp_2src"_h:
+ case "lslv_32_dp_2src"_h:
+ case "lslv_64_dp_2src"_h:
+ case "lsrv_32_dp_2src"_h:
+ case "lsrv_64_dp_2src"_h:
+ case "rorv_32_dp_2src"_h:
+ case "rorv_64_dp_2src"_h:
+ // Drop the last 'v' character.
+ VIXL_ASSERT(mnemonic[3] == 'v');
+ mnemonic.pop_back();
+ break;
+ case "pacga_64p_dp_2src"_h:
form = "'Xd, 'Xn, 'Xms";
break;
- case CRC32B:
- mnemonic = "crc32b";
+ case "crc32x_64c_dp_2src"_h:
+ case "crc32cx_64c_dp_2src"_h:
+ form = "'Wd, 'Wn, 'Xm";
break;
- case CRC32H:
- mnemonic = "crc32h";
- break;
- case CRC32W:
- mnemonic = "crc32w";
- break;
- case CRC32X:
- mnemonic = "crc32x";
- form = form_wwx;
- break;
- case CRC32CB:
- mnemonic = "crc32cb";
- break;
- case CRC32CH:
- mnemonic = "crc32ch";
- break;
- case CRC32CW:
- mnemonic = "crc32cw";
- break;
- case CRC32CX:
- mnemonic = "crc32cx";
- form = form_wwx;
- break;
- default:
- form = "(DataProcessing2Source)";
}
- Format(instr, mnemonic, form);
+ Format(instr, mnemonic.c_str(), form);
}
@@ -1531,44 +1377,16 @@
void Disassembler::VisitCompareBranch(const Instruction *instr) {
- const char *mnemonic = "";
- const char *form = "'Rt, 'TImmCmpa";
-
- switch (instr->Mask(CompareBranchMask)) {
- case CBZ_w:
- case CBZ_x:
- mnemonic = "cbz";
- break;
- case CBNZ_w:
- case CBNZ_x:
- mnemonic = "cbnz";
- break;
- default:
- VIXL_UNREACHABLE();
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Rt, 'TImmCmpa");
}
void Disassembler::VisitTestBranch(const Instruction *instr) {
- const char *mnemonic = "";
// If the top bit of the immediate is clear, the tested register is
// disassembled as Wt, otherwise Xt. As the top bit of the immediate is
// encoded in bit 31 of the instruction, we can reuse the Rt form, which
// uses bit 31 (normally "sf") to choose the register size.
- const char *form = "'Rt, 'It, 'TImmTest";
-
- switch (instr->Mask(TestBranchMask)) {
- case TBZ:
- mnemonic = "tbz";
- break;
- case TBNZ:
- mnemonic = "tbnz";
- break;
- default:
- VIXL_UNREACHABLE();
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Rt, 'It, 'TImmTest");
}
@@ -1613,138 +1431,94 @@
}
-#define LOAD_STORE_LIST(V) \
- V(STRB_w, "strb", "'Wt") \
- V(STRH_w, "strh", "'Wt") \
- V(STR_w, "str", "'Wt") \
- V(STR_x, "str", "'Xt") \
- V(LDRB_w, "ldrb", "'Wt") \
- V(LDRH_w, "ldrh", "'Wt") \
- V(LDR_w, "ldr", "'Wt") \
- V(LDR_x, "ldr", "'Xt") \
- V(LDRSB_x, "ldrsb", "'Xt") \
- V(LDRSH_x, "ldrsh", "'Xt") \
- V(LDRSW_x, "ldrsw", "'Xt") \
- V(LDRSB_w, "ldrsb", "'Wt") \
- V(LDRSH_w, "ldrsh", "'Wt") \
- V(STR_b, "str", "'Bt") \
- V(STR_h, "str", "'Ht") \
- V(STR_s, "str", "'St") \
- V(STR_d, "str", "'Dt") \
- V(LDR_b, "ldr", "'Bt") \
- V(LDR_h, "ldr", "'Ht") \
- V(LDR_s, "ldr", "'St") \
- V(LDR_d, "ldr", "'Dt") \
- V(STR_q, "str", "'Qt") \
- V(LDR_q, "ldr", "'Qt")
+#define LOAD_STORE_LIST(V) \
+ V(STRB_w, "'Wt") \
+ V(STRH_w, "'Wt") \
+ V(STR_w, "'Wt") \
+ V(STR_x, "'Xt") \
+ V(LDRB_w, "'Wt") \
+ V(LDRH_w, "'Wt") \
+ V(LDR_w, "'Wt") \
+ V(LDR_x, "'Xt") \
+ V(LDRSB_x, "'Xt") \
+ V(LDRSH_x, "'Xt") \
+ V(LDRSW_x, "'Xt") \
+ V(LDRSB_w, "'Wt") \
+ V(LDRSH_w, "'Wt") \
+ V(STR_b, "'Bt") \
+ V(STR_h, "'Ht") \
+ V(STR_s, "'St") \
+ V(STR_d, "'Dt") \
+ V(LDR_b, "'Bt") \
+ V(LDR_h, "'Ht") \
+ V(LDR_s, "'St") \
+ V(LDR_d, "'Dt") \
+ V(STR_q, "'Qt") \
+ V(LDR_q, "'Qt")
void Disassembler::VisitLoadStorePreIndex(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "(LoadStorePreIndex)";
+ const char *suffix = ", ['Xns'ILSi]!";
switch (instr->Mask(LoadStorePreIndexMask)) {
-#define LS_PREINDEX(A, B, C) \
- case A##_pre: \
- mnemonic = B; \
- form = C ", ['Xns'ILSi]!"; \
+#define LS_PREINDEX(A, B) \
+ case A##_pre: \
+ form = B; \
break;
LOAD_STORE_LIST(LS_PREINDEX)
#undef LS_PREINDEX
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitLoadStorePostIndex(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "(LoadStorePostIndex)";
+ const char *suffix = ", ['Xns]'ILSi";
switch (instr->Mask(LoadStorePostIndexMask)) {
-#define LS_POSTINDEX(A, B, C) \
- case A##_post: \
- mnemonic = B; \
- form = C ", ['Xns]'ILSi"; \
+#define LS_POSTINDEX(A, B) \
+ case A##_post: \
+ form = B; \
break;
LOAD_STORE_LIST(LS_POSTINDEX)
#undef LS_POSTINDEX
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitLoadStoreUnsignedOffset(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "(LoadStoreUnsignedOffset)";
+ const char *suffix = ", ['Xns'ILU]";
switch (instr->Mask(LoadStoreUnsignedOffsetMask)) {
-#define LS_UNSIGNEDOFFSET(A, B, C) \
- case A##_unsigned: \
- mnemonic = B; \
- form = C ", ['Xns'ILU]"; \
+#define LS_UNSIGNEDOFFSET(A, B) \
+ case A##_unsigned: \
+ form = B; \
break;
LOAD_STORE_LIST(LS_UNSIGNEDOFFSET)
#undef LS_UNSIGNEDOFFSET
case PRFM_unsigned:
- mnemonic = "prfm";
- form = "'prefOp, ['Xns'ILU]";
+ form = "'prefOp";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitLoadStoreRCpcUnscaledOffset(const Instruction *instr) {
- const char *mnemonic;
+ const char *mnemonic = mnemonic_.c_str();
const char *form = "'Wt, ['Xns'ILS]";
const char *form_x = "'Xt, ['Xns'ILS]";
- switch (instr->Mask(LoadStoreRCpcUnscaledOffsetMask)) {
- case STLURB:
- mnemonic = "stlurb";
- break;
- case LDAPURB:
- mnemonic = "ldapurb";
- break;
- case LDAPURSB_w:
- mnemonic = "ldapursb";
- break;
- case LDAPURSB_x:
- mnemonic = "ldapursb";
+ switch (form_hash_) {
+ case "ldapursb_64_ldapstl_unscaled"_h:
+ case "ldapursh_64_ldapstl_unscaled"_h:
+ case "ldapursw_64_ldapstl_unscaled"_h:
+ case "ldapur_64_ldapstl_unscaled"_h:
+ case "stlur_64_ldapstl_unscaled"_h:
form = form_x;
break;
- case STLURH:
- mnemonic = "stlurh";
- break;
- case LDAPURH:
- mnemonic = "ldapurh";
- break;
- case LDAPURSH_w:
- mnemonic = "ldapursh";
- break;
- case LDAPURSH_x:
- mnemonic = "ldapursh";
- form = form_x;
- break;
- case STLUR_w:
- mnemonic = "stlur";
- break;
- case LDAPUR_w:
- mnemonic = "ldapur";
- break;
- case LDAPURSW:
- mnemonic = "ldapursw";
- form = form_x;
- break;
- case STLUR_x:
- mnemonic = "stlur";
- form = form_x;
- break;
- case LDAPUR_x:
- mnemonic = "ldapur";
- form = form_x;
- break;
- default:
- mnemonic = "unimplemented";
- form = "(LoadStoreRCpcUnscaledOffset)";
}
Format(instr, mnemonic, form);
@@ -1752,365 +1526,233 @@
void Disassembler::VisitLoadStoreRegisterOffset(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "(LoadStoreRegisterOffset)";
+ const char *suffix = ", ['Xns, 'Offsetreg]";
switch (instr->Mask(LoadStoreRegisterOffsetMask)) {
-#define LS_REGISTEROFFSET(A, B, C) \
- case A##_reg: \
- mnemonic = B; \
- form = C ", ['Xns, 'Offsetreg]"; \
+#define LS_REGISTEROFFSET(A, B) \
+ case A##_reg: \
+ form = B; \
break;
LOAD_STORE_LIST(LS_REGISTEROFFSET)
#undef LS_REGISTEROFFSET
case PRFM_reg:
- mnemonic = "prfm";
- form = "'prefOp, ['Xns, 'Offsetreg]";
+ form = "'prefOp";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitLoadStoreUnscaledOffset(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Wt, ['Xns'ILS]";
- const char *form_x = "'Xt, ['Xns'ILS]";
- const char *form_b = "'Bt, ['Xns'ILS]";
- const char *form_h = "'Ht, ['Xns'ILS]";
- const char *form_s = "'St, ['Xns'ILS]";
- const char *form_d = "'Dt, ['Xns'ILS]";
- const char *form_q = "'Qt, ['Xns'ILS]";
- const char *form_prefetch = "'prefOp, ['Xns'ILS]";
+ const char *form = "'Wt";
+ const char *suffix = ", ['Xns'ILS]";
- switch (instr->Mask(LoadStoreUnscaledOffsetMask)) {
- case STURB_w:
- mnemonic = "sturb";
+ switch (form_hash_) {
+ case "ldur_64_ldst_unscaled"_h:
+ case "ldursb_64_ldst_unscaled"_h:
+ case "ldursh_64_ldst_unscaled"_h:
+ case "ldursw_64_ldst_unscaled"_h:
+ case "stur_64_ldst_unscaled"_h:
+ form = "'Xt";
break;
- case STURH_w:
- mnemonic = "sturh";
+ case "ldur_b_ldst_unscaled"_h:
+ case "stur_b_ldst_unscaled"_h:
+ form = "'Bt";
break;
- case STUR_w:
- mnemonic = "stur";
+ case "ldur_h_ldst_unscaled"_h:
+ case "stur_h_ldst_unscaled"_h:
+ form = "'Ht";
break;
- case STUR_x:
- mnemonic = "stur";
- form = form_x;
+ case "ldur_s_ldst_unscaled"_h:
+ case "stur_s_ldst_unscaled"_h:
+ form = "'St";
break;
- case STUR_b:
- mnemonic = "stur";
- form = form_b;
+ case "ldur_d_ldst_unscaled"_h:
+ case "stur_d_ldst_unscaled"_h:
+ form = "'Dt";
break;
- case STUR_h:
- mnemonic = "stur";
- form = form_h;
+ case "ldur_q_ldst_unscaled"_h:
+ case "stur_q_ldst_unscaled"_h:
+ form = "'Qt";
break;
- case STUR_s:
- mnemonic = "stur";
- form = form_s;
+ case "prfum_p_ldst_unscaled"_h:
+ form = "'prefOp";
break;
- case STUR_d:
- mnemonic = "stur";
- form = form_d;
- break;
- case STUR_q:
- mnemonic = "stur";
- form = form_q;
- break;
- case LDURB_w:
- mnemonic = "ldurb";
- break;
- case LDURH_w:
- mnemonic = "ldurh";
- break;
- case LDUR_w:
- mnemonic = "ldur";
- break;
- case LDUR_x:
- mnemonic = "ldur";
- form = form_x;
- break;
- case LDUR_b:
- mnemonic = "ldur";
- form = form_b;
- break;
- case LDUR_h:
- mnemonic = "ldur";
- form = form_h;
- break;
- case LDUR_s:
- mnemonic = "ldur";
- form = form_s;
- break;
- case LDUR_d:
- mnemonic = "ldur";
- form = form_d;
- break;
- case LDUR_q:
- mnemonic = "ldur";
- form = form_q;
- break;
- case LDURSB_x:
- form = form_x;
- VIXL_FALLTHROUGH();
- case LDURSB_w:
- mnemonic = "ldursb";
- break;
- case LDURSH_x:
- form = form_x;
- VIXL_FALLTHROUGH();
- case LDURSH_w:
- mnemonic = "ldursh";
- break;
- case LDURSW_x:
- mnemonic = "ldursw";
- form = form_x;
- break;
- case PRFUM:
- mnemonic = "prfum";
- form = form_prefetch;
- break;
- default:
- form = "(LoadStoreUnscaledOffset)";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitLoadLiteral(const Instruction *instr) {
- const char *mnemonic = "ldr";
- const char *form = "(LoadLiteral)";
+ const char *form = "'Wt";
+ const char *suffix = ", 'ILLiteral 'LValue";
- switch (instr->Mask(LoadLiteralMask)) {
- case LDR_w_lit:
- form = "'Wt, 'ILLiteral 'LValue";
+ switch (form_hash_) {
+ case "ldr_64_loadlit"_h:
+ case "ldrsw_64_loadlit"_h:
+ form = "'Xt";
break;
- case LDR_x_lit:
- form = "'Xt, 'ILLiteral 'LValue";
+ case "ldr_s_loadlit"_h:
+ form = "'St";
break;
- case LDR_s_lit:
- form = "'St, 'ILLiteral 'LValue";
+ case "ldr_d_loadlit"_h:
+ form = "'Dt";
break;
- case LDR_d_lit:
- form = "'Dt, 'ILLiteral 'LValue";
+ case "ldr_q_loadlit"_h:
+ form = "'Qt";
break;
- case LDR_q_lit:
- form = "'Qt, 'ILLiteral 'LValue";
+ case "prfm_p_loadlit"_h:
+ form = "'prefOp";
break;
- case LDRSW_x_lit: {
- mnemonic = "ldrsw";
- form = "'Xt, 'ILLiteral 'LValue";
- break;
- }
- case PRFM_lit: {
- mnemonic = "prfm";
- form = "'prefOp, 'ILLiteral 'LValue";
- break;
- }
- default:
- mnemonic = "unimplemented";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
-#define LOAD_STORE_PAIR_LIST(V) \
- V(STP_w, "stp", "'Wt, 'Wt2", "2") \
- V(LDP_w, "ldp", "'Wt, 'Wt2", "2") \
- V(LDPSW_x, "ldpsw", "'Xt, 'Xt2", "2") \
- V(STP_x, "stp", "'Xt, 'Xt2", "3") \
- V(LDP_x, "ldp", "'Xt, 'Xt2", "3") \
- V(STP_s, "stp", "'St, 'St2", "2") \
- V(LDP_s, "ldp", "'St, 'St2", "2") \
- V(STP_d, "stp", "'Dt, 'Dt2", "3") \
- V(LDP_d, "ldp", "'Dt, 'Dt2", "3") \
- V(LDP_q, "ldp", "'Qt, 'Qt2", "4") \
- V(STP_q, "stp", "'Qt, 'Qt2", "4")
+#define LOAD_STORE_PAIR_LIST(V) \
+ V(STP_w, "'Wt, 'Wt2", "2") \
+ V(LDP_w, "'Wt, 'Wt2", "2") \
+ V(LDPSW_x, "'Xt, 'Xt2", "2") \
+ V(STP_x, "'Xt, 'Xt2", "3") \
+ V(LDP_x, "'Xt, 'Xt2", "3") \
+ V(STP_s, "'St, 'St2", "2") \
+ V(LDP_s, "'St, 'St2", "2") \
+ V(STP_d, "'Dt, 'Dt2", "3") \
+ V(LDP_d, "'Dt, 'Dt2", "3") \
+ V(LDP_q, "'Qt, 'Qt2", "4") \
+ V(STP_q, "'Qt, 'Qt2", "4")
void Disassembler::VisitLoadStorePairPostIndex(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "(LoadStorePairPostIndex)";
switch (instr->Mask(LoadStorePairPostIndexMask)) {
-#define LSP_POSTINDEX(A, B, C, D) \
+#define LSP_POSTINDEX(A, B, C) \
case A##_post: \
- mnemonic = B; \
- form = C ", ['Xns]'ILP" D "i"; \
+ form = B ", ['Xns]'ILP" C "i"; \
break;
LOAD_STORE_PAIR_LIST(LSP_POSTINDEX)
#undef LSP_POSTINDEX
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitLoadStorePairPreIndex(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "(LoadStorePairPreIndex)";
switch (instr->Mask(LoadStorePairPreIndexMask)) {
-#define LSP_PREINDEX(A, B, C, D) \
+#define LSP_PREINDEX(A, B, C) \
case A##_pre: \
- mnemonic = B; \
- form = C ", ['Xns'ILP" D "i]!"; \
+ form = B ", ['Xns'ILP" C "i]!"; \
break;
LOAD_STORE_PAIR_LIST(LSP_PREINDEX)
#undef LSP_PREINDEX
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitLoadStorePairOffset(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "(LoadStorePairOffset)";
switch (instr->Mask(LoadStorePairOffsetMask)) {
-#define LSP_OFFSET(A, B, C, D) \
+#define LSP_OFFSET(A, B, C) \
case A##_off: \
- mnemonic = B; \
- form = C ", ['Xns'ILP" D "]"; \
+ form = B ", ['Xns'ILP" C "]"; \
break;
LOAD_STORE_PAIR_LIST(LSP_OFFSET)
#undef LSP_OFFSET
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitLoadStorePairNonTemporal(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form;
+ const char *form = "'Wt, 'Wt2, ['Xns'ILP2]";
- switch (instr->Mask(LoadStorePairNonTemporalMask)) {
- case STNP_w:
- mnemonic = "stnp";
- form = "'Wt, 'Wt2, ['Xns'ILP2]";
- break;
- case LDNP_w:
- mnemonic = "ldnp";
- form = "'Wt, 'Wt2, ['Xns'ILP2]";
- break;
- case STNP_x:
- mnemonic = "stnp";
+ switch (form_hash_) {
+ case "ldnp_64_ldstnapair_offs"_h:
+ case "stnp_64_ldstnapair_offs"_h:
form = "'Xt, 'Xt2, ['Xns'ILP3]";
break;
- case LDNP_x:
- mnemonic = "ldnp";
- form = "'Xt, 'Xt2, ['Xns'ILP3]";
- break;
- case STNP_s:
- mnemonic = "stnp";
+ case "ldnp_s_ldstnapair_offs"_h:
+ case "stnp_s_ldstnapair_offs"_h:
form = "'St, 'St2, ['Xns'ILP2]";
break;
- case LDNP_s:
- mnemonic = "ldnp";
- form = "'St, 'St2, ['Xns'ILP2]";
- break;
- case STNP_d:
- mnemonic = "stnp";
+ case "ldnp_d_ldstnapair_offs"_h:
+ case "stnp_d_ldstnapair_offs"_h:
form = "'Dt, 'Dt2, ['Xns'ILP3]";
break;
- case LDNP_d:
- mnemonic = "ldnp";
- form = "'Dt, 'Dt2, ['Xns'ILP3]";
- break;
- case STNP_q:
- mnemonic = "stnp";
+ case "ldnp_q_ldstnapair_offs"_h:
+ case "stnp_q_ldstnapair_offs"_h:
form = "'Qt, 'Qt2, ['Xns'ILP4]";
break;
- case LDNP_q:
- mnemonic = "ldnp";
- form = "'Qt, 'Qt2, ['Xns'ILP4]";
- break;
- default:
- form = "(LoadStorePairNonTemporal)";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
// clang-format off
-#define LOAD_STORE_EXCLUSIVE_LIST(V) \
- V(STXRB_w, "stxrb", "'Ws, 'Wt") \
- V(STXRH_w, "stxrh", "'Ws, 'Wt") \
- V(STXR_w, "stxr", "'Ws, 'Wt") \
- V(STXR_x, "stxr", "'Ws, 'Xt") \
- V(LDXRB_w, "ldxrb", "'Wt") \
- V(LDXRH_w, "ldxrh", "'Wt") \
- V(LDXR_w, "ldxr", "'Wt") \
- V(LDXR_x, "ldxr", "'Xt") \
- V(STXP_w, "stxp", "'Ws, 'Wt, 'Wt2") \
- V(STXP_x, "stxp", "'Ws, 'Xt, 'Xt2") \
- V(LDXP_w, "ldxp", "'Wt, 'Wt2") \
- V(LDXP_x, "ldxp", "'Xt, 'Xt2") \
- V(STLXRB_w, "stlxrb", "'Ws, 'Wt") \
- V(STLXRH_w, "stlxrh", "'Ws, 'Wt") \
- V(STLXR_w, "stlxr", "'Ws, 'Wt") \
- V(STLXR_x, "stlxr", "'Ws, 'Xt") \
- V(LDAXRB_w, "ldaxrb", "'Wt") \
- V(LDAXRH_w, "ldaxrh", "'Wt") \
- V(LDAXR_w, "ldaxr", "'Wt") \
- V(LDAXR_x, "ldaxr", "'Xt") \
- V(STLXP_w, "stlxp", "'Ws, 'Wt, 'Wt2") \
- V(STLXP_x, "stlxp", "'Ws, 'Xt, 'Xt2") \
- V(LDAXP_w, "ldaxp", "'Wt, 'Wt2") \
- V(LDAXP_x, "ldaxp", "'Xt, 'Xt2") \
- V(STLRB_w, "stlrb", "'Wt") \
- V(STLRH_w, "stlrh", "'Wt") \
- V(STLR_w, "stlr", "'Wt") \
- V(STLR_x, "stlr", "'Xt") \
- V(LDARB_w, "ldarb", "'Wt") \
- V(LDARH_w, "ldarh", "'Wt") \
- V(LDAR_w, "ldar", "'Wt") \
- V(LDAR_x, "ldar", "'Xt") \
- V(STLLRB, "stllrb", "'Wt") \
- V(STLLRH, "stllrh", "'Wt") \
- V(STLLR_w, "stllr", "'Wt") \
- V(STLLR_x, "stllr", "'Xt") \
- V(LDLARB, "ldlarb", "'Wt") \
- V(LDLARH, "ldlarh", "'Wt") \
- V(LDLAR_w, "ldlar", "'Wt") \
- V(LDLAR_x, "ldlar", "'Xt") \
- V(CAS_w, "cas", "'Ws, 'Wt") \
- V(CAS_x, "cas", "'Xs, 'Xt") \
- V(CASA_w, "casa", "'Ws, 'Wt") \
- V(CASA_x, "casa", "'Xs, 'Xt") \
- V(CASL_w, "casl", "'Ws, 'Wt") \
- V(CASL_x, "casl", "'Xs, 'Xt") \
- V(CASAL_w, "casal", "'Ws, 'Wt") \
- V(CASAL_x, "casal", "'Xs, 'Xt") \
- V(CASB, "casb", "'Ws, 'Wt") \
- V(CASAB, "casab", "'Ws, 'Wt") \
- V(CASLB, "caslb", "'Ws, 'Wt") \
- V(CASALB, "casalb", "'Ws, 'Wt") \
- V(CASH, "cash", "'Ws, 'Wt") \
- V(CASAH, "casah", "'Ws, 'Wt") \
- V(CASLH, "caslh", "'Ws, 'Wt") \
- V(CASALH, "casalh", "'Ws, 'Wt") \
- V(CASP_w, "casp", "'Ws, 'Ws+, 'Wt, 'Wt+") \
- V(CASP_x, "casp", "'Xs, 'Xs+, 'Xt, 'Xt+") \
- V(CASPA_w, "caspa", "'Ws, 'Ws+, 'Wt, 'Wt+") \
- V(CASPA_x, "caspa", "'Xs, 'Xs+, 'Xt, 'Xt+") \
- V(CASPL_w, "caspl", "'Ws, 'Ws+, 'Wt, 'Wt+") \
- V(CASPL_x, "caspl", "'Xs, 'Xs+, 'Xt, 'Xt+") \
- V(CASPAL_w, "caspal", "'Ws, 'Ws+, 'Wt, 'Wt+") \
- V(CASPAL_x, "caspal", "'Xs, 'Xs+, 'Xt, 'Xt+")
+#define LOAD_STORE_EXCLUSIVE_LIST(V) \
+ V(STXRB_w, "'Ws, 'Wt") \
+ V(STXRH_w, "'Ws, 'Wt") \
+ V(STXR_w, "'Ws, 'Wt") \
+ V(STXR_x, "'Ws, 'Xt") \
+ V(LDXR_x, "'Xt") \
+ V(STXP_w, "'Ws, 'Wt, 'Wt2") \
+ V(STXP_x, "'Ws, 'Xt, 'Xt2") \
+ V(LDXP_w, "'Wt, 'Wt2") \
+ V(LDXP_x, "'Xt, 'Xt2") \
+ V(STLXRB_w, "'Ws, 'Wt") \
+ V(STLXRH_w, "'Ws, 'Wt") \
+ V(STLXR_w, "'Ws, 'Wt") \
+ V(STLXR_x, "'Ws, 'Xt") \
+ V(LDAXR_x, "'Xt") \
+ V(STLXP_w, "'Ws, 'Wt, 'Wt2") \
+ V(STLXP_x, "'Ws, 'Xt, 'Xt2") \
+ V(LDAXP_w, "'Wt, 'Wt2") \
+ V(LDAXP_x, "'Xt, 'Xt2") \
+ V(STLR_x, "'Xt") \
+ V(LDAR_x, "'Xt") \
+ V(STLLR_x, "'Xt") \
+ V(LDLAR_x, "'Xt") \
+ V(CAS_w, "'Ws, 'Wt") \
+ V(CAS_x, "'Xs, 'Xt") \
+ V(CASA_w, "'Ws, 'Wt") \
+ V(CASA_x, "'Xs, 'Xt") \
+ V(CASL_w, "'Ws, 'Wt") \
+ V(CASL_x, "'Xs, 'Xt") \
+ V(CASAL_w, "'Ws, 'Wt") \
+ V(CASAL_x, "'Xs, 'Xt") \
+ V(CASB, "'Ws, 'Wt") \
+ V(CASAB, "'Ws, 'Wt") \
+ V(CASLB, "'Ws, 'Wt") \
+ V(CASALB, "'Ws, 'Wt") \
+ V(CASH, "'Ws, 'Wt") \
+ V(CASAH, "'Ws, 'Wt") \
+ V(CASLH, "'Ws, 'Wt") \
+ V(CASALH, "'Ws, 'Wt") \
+ V(CASP_w, "'Ws, 'Ws+, 'Wt, 'Wt+") \
+ V(CASP_x, "'Xs, 'Xs+, 'Xt, 'Xt+") \
+ V(CASPA_w, "'Ws, 'Ws+, 'Wt, 'Wt+") \
+ V(CASPA_x, "'Xs, 'Xs+, 'Xt, 'Xt+") \
+ V(CASPL_w, "'Ws, 'Ws+, 'Wt, 'Wt+") \
+ V(CASPL_x, "'Xs, 'Xs+, 'Xt, 'Xt+") \
+ V(CASPAL_w, "'Ws, 'Ws+, 'Wt, 'Wt+") \
+ V(CASPAL_x, "'Xs, 'Xs+, 'Xt, 'Xt+")
// clang-format on
void Disassembler::VisitLoadStoreExclusive(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form;
+ const char *form = "'Wt";
+ const char *suffix = ", ['Xns]";
switch (instr->Mask(LoadStoreExclusiveMask)) {
-#define LSX(A, B, C) \
- case A: \
- mnemonic = B; \
- form = C ", ['Xns]"; \
+#define LSX(A, B) \
+ case A: \
+ form = B; \
break;
LOAD_STORE_EXCLUSIVE_LIST(LSX)
#undef LSX
- default:
- form = "(LoadStoreExclusive)";
}
switch (instr->Mask(LoadStoreExclusiveMask)) {
@@ -2123,588 +1765,183 @@
case CASPAL_w:
case CASPAL_x:
if ((instr->GetRs() % 2 == 1) || (instr->GetRt() % 2 == 1)) {
- mnemonic = "unallocated";
- form = "(LoadStoreExclusive)";
+ VisitUnallocated(instr);
+ return;
}
break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitLoadStorePAC(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(LoadStorePAC)";
-
- switch (instr->Mask(LoadStorePACMask)) {
- case LDRAA:
- mnemonic = "ldraa";
- form = "'Xt, ['Xns'ILA]";
- break;
- case LDRAB:
- mnemonic = "ldrab";
- form = "'Xt, ['Xns'ILA]";
- break;
- case LDRAA_pre:
- mnemonic = "ldraa";
- form = "'Xt, ['Xns'ILA]!";
- break;
- case LDRAB_pre:
- mnemonic = "ldrab";
- form = "'Xt, ['Xns'ILA]!";
+ const char *form = "'Xt, ['Xns'ILA]";
+ const char *suffix = "";
+ switch (form_hash_) {
+ case "ldraa_64w_ldst_pac"_h:
+ case "ldrab_64w_ldst_pac"_h:
+ suffix = "!";
break;
}
-
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
-#define ATOMIC_MEMORY_SIMPLE_LIST(V) \
- V(LDADD, "add") \
- V(LDCLR, "clr") \
- V(LDEOR, "eor") \
- V(LDSET, "set") \
- V(LDSMAX, "smax") \
- V(LDSMIN, "smin") \
- V(LDUMAX, "umax") \
- V(LDUMIN, "umin")
-
void Disassembler::VisitAtomicMemory(const Instruction *instr) {
- const int kMaxAtomicOpMnemonicLength = 16;
- const char *mnemonic;
- const char *form = "'Ws, 'Wt, ['Xns]";
+ bool is_x = (instr->ExtractBits(31, 30) == 3);
+ const char *form = is_x ? "'Xs, 'Xt" : "'Ws, 'Wt";
+ const char *suffix = ", ['Xns]";
- switch (instr->Mask(AtomicMemoryMask)) {
-#define AMS(A, MN) \
- case A##B: \
- mnemonic = MN "b"; \
- break; \
- case A##AB: \
- mnemonic = MN "ab"; \
- break; \
- case A##LB: \
- mnemonic = MN "lb"; \
- break; \
- case A##ALB: \
- mnemonic = MN "alb"; \
- break; \
- case A##H: \
- mnemonic = MN "h"; \
- break; \
- case A##AH: \
- mnemonic = MN "ah"; \
- break; \
- case A##LH: \
- mnemonic = MN "lh"; \
- break; \
- case A##ALH: \
- mnemonic = MN "alh"; \
- break; \
- case A##_w: \
- mnemonic = MN; \
- break; \
- case A##A_w: \
- mnemonic = MN "a"; \
- break; \
- case A##L_w: \
- mnemonic = MN "l"; \
- break; \
- case A##AL_w: \
- mnemonic = MN "al"; \
- break; \
- case A##_x: \
- mnemonic = MN; \
- form = "'Xs, 'Xt, ['Xns]"; \
- break; \
- case A##A_x: \
- mnemonic = MN "a"; \
- form = "'Xs, 'Xt, ['Xns]"; \
- break; \
- case A##L_x: \
- mnemonic = MN "l"; \
- form = "'Xs, 'Xt, ['Xns]"; \
- break; \
- case A##AL_x: \
- mnemonic = MN "al"; \
- form = "'Xs, 'Xt, ['Xns]"; \
- break;
- ATOMIC_MEMORY_SIMPLE_LIST(AMS)
+ std::string mnemonic = mnemonic_;
- // SWP has the same semantics as ldadd etc but without the store aliases.
- AMS(SWP, "swp")
-#undef AMS
-
- case LDAPRB:
- mnemonic = "ldaprb";
- form = "'Wt, ['Xns]";
+ switch (form_hash_) {
+ case "ldaprb_32l_memop"_h:
+ case "ldaprh_32l_memop"_h:
+ case "ldapr_32l_memop"_h:
+ form = "'Wt";
break;
- case LDAPRH:
- mnemonic = "ldaprh";
- form = "'Wt, ['Xns]";
- break;
- case LDAPR_w:
- mnemonic = "ldapr";
- form = "'Wt, ['Xns]";
- break;
- case LDAPR_x:
- mnemonic = "ldapr";
- form = "'Xt, ['Xns]";
+ case "ldapr_64l_memop"_h:
+ form = "'Xt";
break;
default:
- mnemonic = "unimplemented";
- form = "(AtomicMemory)";
+ // Zero register implies a store instruction.
+ if (instr->GetRt() == kZeroRegCode) {
+ mnemonic.replace(0, 2, "st");
+ form = is_x ? "'Xs" : "'Ws";
+ }
}
-
- const char *prefix = "";
- switch (instr->Mask(AtomicMemoryMask)) {
-#define AMS(A, MN) \
- case A##AB: \
- case A##ALB: \
- case A##AH: \
- case A##ALH: \
- case A##A_w: \
- case A##AL_w: \
- case A##A_x: \
- case A##AL_x: \
- prefix = "ld"; \
- break; \
- case A##B: \
- case A##LB: \
- case A##H: \
- case A##LH: \
- case A##_w: \
- case A##L_w: { \
- prefix = "ld"; \
- unsigned rt = instr->GetRt(); \
- if (Register(rt, 32).IsZero()) { \
- prefix = "st"; \
- form = "'Ws, ['Xns]"; \
- } \
- break; \
- } \
- case A##_x: \
- case A##L_x: { \
- prefix = "ld"; \
- unsigned rt = instr->GetRt(); \
- if (Register(rt, 64).IsZero()) { \
- prefix = "st"; \
- form = "'Xs, ['Xns]"; \
- } \
- break; \
- }
- ATOMIC_MEMORY_SIMPLE_LIST(AMS)
-#undef AMS
- }
-
- char buffer[kMaxAtomicOpMnemonicLength];
- if (strlen(prefix) > 0) {
- snprintf(buffer, kMaxAtomicOpMnemonicLength, "%s%s", prefix, mnemonic);
- mnemonic = buffer;
- }
-
- Format(instr, mnemonic, form);
+ Format(instr, mnemonic.c_str(), form, suffix);
}
void Disassembler::VisitFPCompare(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "'Fn, 'Fm";
- const char *form_zero = "'Fn, #0.0";
-
- switch (instr->Mask(FPCompareMask)) {
- case FCMP_h_zero:
- case FCMP_s_zero:
- case FCMP_d_zero:
- form = form_zero;
- VIXL_FALLTHROUGH();
- case FCMP_h:
- case FCMP_s:
- case FCMP_d:
- mnemonic = "fcmp";
- break;
- case FCMPE_h_zero:
- case FCMPE_s_zero:
- case FCMPE_d_zero:
- form = form_zero;
- VIXL_FALLTHROUGH();
- case FCMPE_h:
- case FCMPE_s:
- case FCMPE_d:
- mnemonic = "fcmpe";
- break;
- default:
- form = "(FPCompare)";
+ switch (form_hash_) {
+ case "fcmpe_dz_floatcmp"_h:
+ case "fcmpe_hz_floatcmp"_h:
+ case "fcmpe_sz_floatcmp"_h:
+ case "fcmp_dz_floatcmp"_h:
+ case "fcmp_hz_floatcmp"_h:
+ case "fcmp_sz_floatcmp"_h:
+ form = "'Fn, #0.0";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitFPConditionalCompare(const Instruction *instr) {
- const char *mnemonic = "unmplemented";
- const char *form = "'Fn, 'Fm, 'INzcv, 'Cond";
-
- switch (instr->Mask(FPConditionalCompareMask)) {
- case FCCMP_h:
- case FCCMP_s:
- case FCCMP_d:
- mnemonic = "fccmp";
- break;
- case FCCMPE_h:
- case FCCMPE_s:
- case FCCMPE_d:
- mnemonic = "fccmpe";
- break;
- default:
- form = "(FPConditionalCompare)";
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Fn, 'Fm, 'INzcv, 'Cond");
}
void Disassembler::VisitFPConditionalSelect(const Instruction *instr) {
- const char *mnemonic = "";
- const char *form = "'Fd, 'Fn, 'Fm, 'Cond";
-
- switch (instr->Mask(FPConditionalSelectMask)) {
- case FCSEL_h:
- case FCSEL_s:
- case FCSEL_d:
- mnemonic = "fcsel";
- break;
- default:
- VIXL_UNREACHABLE();
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Fd, 'Fn, 'Fm, 'Cond");
}
void Disassembler::VisitFPDataProcessing1Source(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "'Fd, 'Fn";
-
- switch (instr->Mask(FPDataProcessing1SourceMask)) {
-#define FORMAT(A, B) \
- case A##_h: \
- case A##_s: \
- case A##_d: \
- mnemonic = B; \
- break;
- FORMAT(FMOV, "fmov");
- FORMAT(FABS, "fabs");
- FORMAT(FNEG, "fneg");
- FORMAT(FSQRT, "fsqrt");
- FORMAT(FRINTN, "frintn");
- FORMAT(FRINTP, "frintp");
- FORMAT(FRINTM, "frintm");
- FORMAT(FRINTZ, "frintz");
- FORMAT(FRINTA, "frinta");
- FORMAT(FRINTX, "frintx");
- FORMAT(FRINTI, "frinti");
-#undef FORMAT
-#define FORMAT(A, B) \
- case A##_s: \
- case A##_d: \
- mnemonic = B; \
- break;
- FORMAT(FRINT32X, "frint32x");
- FORMAT(FRINT32Z, "frint32z");
- FORMAT(FRINT64X, "frint64x");
- FORMAT(FRINT64Z, "frint64z");
-#undef FORMAT
- case FCVT_ds:
- mnemonic = "fcvt";
+ switch (form_hash_) {
+ case "fcvt_ds_floatdp1"_h:
form = "'Dd, 'Sn";
break;
- case FCVT_sd:
- mnemonic = "fcvt";
+ case "fcvt_sd_floatdp1"_h:
form = "'Sd, 'Dn";
break;
- case FCVT_hs:
- mnemonic = "fcvt";
+ case "fcvt_hs_floatdp1"_h:
form = "'Hd, 'Sn";
break;
- case FCVT_sh:
- mnemonic = "fcvt";
+ case "fcvt_sh_floatdp1"_h:
form = "'Sd, 'Hn";
break;
- case FCVT_dh:
- mnemonic = "fcvt";
+ case "fcvt_dh_floatdp1"_h:
form = "'Dd, 'Hn";
break;
- case FCVT_hd:
- mnemonic = "fcvt";
+ case "fcvt_hd_floatdp1"_h:
form = "'Hd, 'Dn";
break;
- default:
- form = "(FPDataProcessing1Source)";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitFPDataProcessing2Source(const Instruction *instr) {
- const char *mnemonic = "";
- const char *form = "'Fd, 'Fn, 'Fm";
-
- switch (instr->Mask(FPDataProcessing2SourceMask)) {
-#define FORMAT(A, B) \
- case A##_h: \
- case A##_s: \
- case A##_d: \
- mnemonic = B; \
- break;
- FORMAT(FADD, "fadd");
- FORMAT(FSUB, "fsub");
- FORMAT(FMUL, "fmul");
- FORMAT(FDIV, "fdiv");
- FORMAT(FMAX, "fmax");
- FORMAT(FMIN, "fmin");
- FORMAT(FMAXNM, "fmaxnm");
- FORMAT(FMINNM, "fminnm");
- FORMAT(FNMUL, "fnmul");
-#undef FORMAT
- default:
- VIXL_UNREACHABLE();
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Fd, 'Fn, 'Fm");
}
void Disassembler::VisitFPDataProcessing3Source(const Instruction *instr) {
- const char *mnemonic = "";
- const char *form = "'Fd, 'Fn, 'Fm, 'Fa";
-
- switch (instr->Mask(FPDataProcessing3SourceMask)) {
-#define FORMAT(A, B) \
- case A##_h: \
- case A##_s: \
- case A##_d: \
- mnemonic = B; \
- break;
- FORMAT(FMADD, "fmadd");
- FORMAT(FMSUB, "fmsub");
- FORMAT(FNMADD, "fnmadd");
- FORMAT(FNMSUB, "fnmsub");
-#undef FORMAT
- default:
- VIXL_UNREACHABLE();
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Fd, 'Fn, 'Fm, 'Fa");
}
void Disassembler::VisitFPImmediate(const Instruction *instr) {
- const char *mnemonic = "";
- const char *form = "(FPImmediate)";
- switch (instr->Mask(FPImmediateMask)) {
- case FMOV_h_imm:
- mnemonic = "fmov";
- form = "'Hd, 'IFP";
+ const char *form = "'Hd";
+ const char *suffix = ", 'IFP";
+ switch (form_hash_) {
+ case "fmov_s_floatimm"_h:
+ form = "'Sd";
break;
- case FMOV_s_imm:
- mnemonic = "fmov";
- form = "'Sd, 'IFP";
+ case "fmov_d_floatimm"_h:
+ form = "'Dd";
break;
- case FMOV_d_imm:
- mnemonic = "fmov";
- form = "'Dd, 'IFP";
- break;
- default:
- VIXL_UNREACHABLE();
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitFPIntegerConvert(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(FPIntegerConvert)";
- const char *form_rf = "'Rd, 'Fn";
- const char *form_fr = "'Fd, 'Rn";
-
- switch (instr->Mask(FPIntegerConvertMask)) {
- case FMOV_wh:
- case FMOV_xh:
- case FMOV_ws:
- case FMOV_xd:
- mnemonic = "fmov";
- form = form_rf;
+ const char *form = "'Rd, 'Fn";
+ switch (form_hash_) {
+ case "fmov_h32_float2int"_h:
+ case "fmov_h64_float2int"_h:
+ case "fmov_s32_float2int"_h:
+ case "fmov_d64_float2int"_h:
+ case "scvtf_d32_float2int"_h:
+ case "scvtf_d64_float2int"_h:
+ case "scvtf_h32_float2int"_h:
+ case "scvtf_h64_float2int"_h:
+ case "scvtf_s32_float2int"_h:
+ case "scvtf_s64_float2int"_h:
+ case "ucvtf_d32_float2int"_h:
+ case "ucvtf_d64_float2int"_h:
+ case "ucvtf_h32_float2int"_h:
+ case "ucvtf_h64_float2int"_h:
+ case "ucvtf_s32_float2int"_h:
+ case "ucvtf_s64_float2int"_h:
+ form = "'Fd, 'Rn";
break;
- case FMOV_hw:
- case FMOV_hx:
- case FMOV_sw:
- case FMOV_dx:
- mnemonic = "fmov";
- form = form_fr;
- break;
- case FMOV_d1_x:
- mnemonic = "fmov";
+ case "fmov_v64i_float2int"_h:
form = "'Vd.D[1], 'Rn";
break;
- case FMOV_x_d1:
- mnemonic = "fmov";
+ case "fmov_64vx_float2int"_h:
form = "'Rd, 'Vn.D[1]";
break;
- case FCVTAS_wh:
- case FCVTAS_xh:
- case FCVTAS_ws:
- case FCVTAS_xs:
- case FCVTAS_wd:
- case FCVTAS_xd:
- mnemonic = "fcvtas";
- form = form_rf;
- break;
- case FCVTAU_wh:
- case FCVTAU_xh:
- case FCVTAU_ws:
- case FCVTAU_xs:
- case FCVTAU_wd:
- case FCVTAU_xd:
- mnemonic = "fcvtau";
- form = form_rf;
- break;
- case FCVTMS_wh:
- case FCVTMS_xh:
- case FCVTMS_ws:
- case FCVTMS_xs:
- case FCVTMS_wd:
- case FCVTMS_xd:
- mnemonic = "fcvtms";
- form = form_rf;
- break;
- case FCVTMU_wh:
- case FCVTMU_xh:
- case FCVTMU_ws:
- case FCVTMU_xs:
- case FCVTMU_wd:
- case FCVTMU_xd:
- mnemonic = "fcvtmu";
- form = form_rf;
- break;
- case FCVTNS_wh:
- case FCVTNS_xh:
- case FCVTNS_ws:
- case FCVTNS_xs:
- case FCVTNS_wd:
- case FCVTNS_xd:
- mnemonic = "fcvtns";
- form = form_rf;
- break;
- case FCVTNU_wh:
- case FCVTNU_xh:
- case FCVTNU_ws:
- case FCVTNU_xs:
- case FCVTNU_wd:
- case FCVTNU_xd:
- mnemonic = "fcvtnu";
- form = form_rf;
- break;
- case FCVTZU_wh:
- case FCVTZU_xh:
- case FCVTZU_ws:
- case FCVTZU_xs:
- case FCVTZU_wd:
- case FCVTZU_xd:
- mnemonic = "fcvtzu";
- form = form_rf;
- break;
- case FCVTZS_wh:
- case FCVTZS_xh:
- case FCVTZS_ws:
- case FCVTZS_xs:
- case FCVTZS_wd:
- case FCVTZS_xd:
- mnemonic = "fcvtzs";
- form = form_rf;
- break;
- case FCVTPU_wh:
- case FCVTPU_xh:
- case FCVTPU_xs:
- case FCVTPU_wd:
- case FCVTPU_ws:
- case FCVTPU_xd:
- mnemonic = "fcvtpu";
- form = form_rf;
- break;
- case FCVTPS_wh:
- case FCVTPS_xh:
- case FCVTPS_ws:
- case FCVTPS_xs:
- case FCVTPS_wd:
- case FCVTPS_xd:
- mnemonic = "fcvtps";
- form = form_rf;
- break;
- case SCVTF_hw:
- case SCVTF_hx:
- case SCVTF_sw:
- case SCVTF_sx:
- case SCVTF_dw:
- case SCVTF_dx:
- mnemonic = "scvtf";
- form = form_fr;
- break;
- case UCVTF_hw:
- case UCVTF_hx:
- case UCVTF_sw:
- case UCVTF_sx:
- case UCVTF_dw:
- case UCVTF_dx:
- mnemonic = "ucvtf";
- form = form_fr;
- break;
- case FJCVTZS:
- mnemonic = "fjcvtzs";
- form = form_rf;
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitFPFixedPointConvert(const Instruction *instr) {
- const char *mnemonic = "";
- const char *form = "'Rd, 'Fn, 'IFPFBits";
- const char *form_fr = "'Fd, 'Rn, 'IFPFBits";
+ const char *form = "'Rd, 'Fn";
+ const char *suffix = ", 'IFPFBits";
- switch (instr->Mask(FPFixedPointConvertMask)) {
- case FCVTZS_wh_fixed:
- case FCVTZS_xh_fixed:
- case FCVTZS_ws_fixed:
- case FCVTZS_xs_fixed:
- case FCVTZS_wd_fixed:
- case FCVTZS_xd_fixed:
- mnemonic = "fcvtzs";
+ switch (form_hash_) {
+ case "scvtf_d32_float2fix"_h:
+ case "scvtf_d64_float2fix"_h:
+ case "scvtf_h32_float2fix"_h:
+ case "scvtf_h64_float2fix"_h:
+ case "scvtf_s32_float2fix"_h:
+ case "scvtf_s64_float2fix"_h:
+ case "ucvtf_d32_float2fix"_h:
+ case "ucvtf_d64_float2fix"_h:
+ case "ucvtf_h32_float2fix"_h:
+ case "ucvtf_h64_float2fix"_h:
+ case "ucvtf_s32_float2fix"_h:
+ case "ucvtf_s64_float2fix"_h:
+ form = "'Fd, 'Rn";
break;
- case FCVTZU_wh_fixed:
- case FCVTZU_xh_fixed:
- case FCVTZU_ws_fixed:
- case FCVTZU_xs_fixed:
- case FCVTZU_wd_fixed:
- case FCVTZU_xd_fixed:
- mnemonic = "fcvtzu";
- break;
- case SCVTF_hw_fixed:
- case SCVTF_hx_fixed:
- case SCVTF_sw_fixed:
- case SCVTF_sx_fixed:
- case SCVTF_dw_fixed:
- case SCVTF_dx_fixed:
- mnemonic = "scvtf";
- form = form_fr;
- break;
- case UCVTF_hw_fixed:
- case UCVTF_hx_fixed:
- case UCVTF_sw_fixed:
- case UCVTF_sx_fixed:
- case UCVTF_dw_fixed:
- case UCVTF_dx_fixed:
- mnemonic = "ucvtf";
- form = form_fr;
- break;
- default:
- VIXL_UNREACHABLE();
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::DisassembleNoArgs(const Instruction *instr) {
@@ -2717,17 +1954,17 @@
const char *suffix = NULL;
switch (form_hash_) {
- case Hash("clrex_bn_barriers"):
+ case "clrex_bn_barriers"_h:
form = (instr->GetCRm() == 0xf) ? "" : "'IX";
break;
- case Hash("mrs_rs_systemmove"):
+ case "mrs_rs_systemmove"_h:
form = "'Xt, 'IY";
break;
- case Hash("msr_si_pstate"):
- case Hash("msr_sr_systemmove"):
+ case "msr_si_pstate"_h:
+ case "msr_sr_systemmove"_h:
form = "'IY, 'Xt";
break;
- case Hash("bti_hb_hints"):
+ case "bti_hb_hints"_h:
switch (instr->ExtractBits(7, 6)) {
case 0:
form = "";
@@ -2743,14 +1980,14 @@
break;
}
break;
- case Hash("hint_hm_hints"):
+ case "hint_hm_hints"_h:
form = "'IH";
break;
- case Hash("dmb_bo_barriers"):
- case Hash("dsb_bo_barriers"):
+ case "dmb_bo_barriers"_h:
+ case "dsb_bo_barriers"_h:
form = "'M";
break;
- case Hash("sys_cr_systeminstrs"): {
+ case "sys_cr_systeminstrs"_h: {
mnemonic = "dc";
suffix = ", 'Xt";
@@ -2881,10 +2118,10 @@
VectorFormat vform_dst = nfd.GetVectorFormat(0);
switch (form_hash_) {
- case Hash("fcvtl_asimdmisc_l"):
+ case "fcvtl_asimdmisc_l"_h:
nfd.SetFormatMaps(&map_cvt_ta, &map_cvt_tb);
break;
- case Hash("fcvtxn_asimdmisc_n"):
+ case "fcvtxn_asimdmisc_n"_h:
if ((vform_dst != kFormat2S) && (vform_dst != kFormat4S)) {
mnemonic = NULL;
}
@@ -2904,7 +2141,7 @@
const char *mnemonic = mnemonic_.c_str();
const char *form = "'Vd.%s, 'Vn.%s";
NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
- if (form_hash_ == Hash("not_asimdmisc_r")) {
+ if (form_hash_ == "not_asimdmisc_r"_h) {
mnemonic = "mvn";
}
Format(instr, mnemonic, nfd.Substitute(form));
@@ -2918,7 +2155,7 @@
NEONFormatDecoder::IntegerFormatMap(),
NEONFormatDecoder::LongIntegerFormatMap());
- if (form_hash_ == Hash("shll_asimdmisc_s")) {
+ if (form_hash_ == "shll_asimdmisc_s"_h) {
nfd.SetFormatMaps(nfd.LongIntegerFormatMap(), nfd.IntegerFormatMap());
switch (instr->GetNEONSize()) {
case 0:
@@ -2944,27 +2181,27 @@
if (vform_dst != kFormatUndefined) {
uint32_t ls_dst = LaneSizeInBitsFromFormat(vform_dst);
switch (form_hash_) {
- case Hash("cnt_asimdmisc_r"):
- case Hash("rev16_asimdmisc_r"):
+ case "cnt_asimdmisc_r"_h:
+ case "rev16_asimdmisc_r"_h:
if (ls_dst != kBRegSize) {
mnemonic = NULL;
}
break;
- case Hash("rev32_asimdmisc_r"):
+ case "rev32_asimdmisc_r"_h:
if ((ls_dst == kDRegSize) || (ls_dst == kSRegSize)) {
mnemonic = NULL;
}
break;
- case Hash("urecpe_asimdmisc_r"):
- case Hash("ursqrte_asimdmisc_r"):
+ case "urecpe_asimdmisc_r"_h:
+ case "ursqrte_asimdmisc_r"_h:
// For urecpe and ursqrte, only S-sized elements are supported. The MSB
// of the size field is always set by the instruction (0b1x) so we need
// only check and discard D-sized elements here.
VIXL_ASSERT((ls_dst == kSRegSize) || (ls_dst == kDRegSize));
VIXL_FALLTHROUGH();
- case Hash("clz_asimdmisc_r"):
- case Hash("cls_asimdmisc_r"):
- case Hash("rev64_asimdmisc_r"):
+ case "clz_asimdmisc_r"_h:
+ case "cls_asimdmisc_r"_h:
+ case "rev64_asimdmisc_r"_h:
if (ls_dst == kDRegSize) {
mnemonic = NULL;
}
@@ -2981,11 +2218,11 @@
const char *suffix = NULL;
switch (form_hash_) {
- case Hash("fcmeq_asimdmiscfp16_fz"):
- case Hash("fcmge_asimdmiscfp16_fz"):
- case Hash("fcmgt_asimdmiscfp16_fz"):
- case Hash("fcmle_asimdmiscfp16_fz"):
- case Hash("fcmlt_asimdmiscfp16_fz"):
+ case "fcmeq_asimdmiscfp16_fz"_h:
+ case "fcmge_asimdmiscfp16_fz"_h:
+ case "fcmgt_asimdmiscfp16_fz"_h:
+ case "fcmle_asimdmiscfp16_fz"_h:
+ case "fcmlt_asimdmiscfp16_fz"_h:
suffix = ", #0.0";
}
Format(instr, mnemonic, form, suffix);
@@ -2997,13 +2234,13 @@
NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
switch (form_hash_) {
- case Hash("orr_asimdsame_only"):
+ case "orr_asimdsame_only"_h:
if (instr->GetRm() == instr->GetRn()) {
mnemonic = "mov";
form = "'Vd.%s, 'Vn.%s";
}
break;
- case Hash("pmul_asimdsame_only"):
+ case "pmul_asimdsame_only"_h:
if (instr->GetNEONSize() != 0) {
mnemonic = NULL;
}
@@ -3012,9 +2249,7 @@
}
void Disassembler::DisassembleNEON3SameFHM(const Instruction *instr) {
- const char *mnemonic = mnemonic_.c_str();
- const char *form = "'Vd.'?30:42s, 'Vn.'?30:42h, 'Vm.'?30:42h";
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Vd.'?30:42s, 'Vn.'?30:42h, 'Vm.'?30:42h");
}
void Disassembler::DisassembleNEON3SameNoD(const Instruction *instr) {
@@ -3040,8 +2275,8 @@
if (vform_dst != kFormatUndefined) {
uint32_t ls_dst = LaneSizeInBitsFromFormat(vform_dst);
switch (form_hash_) {
- case Hash("sqdmulh_asimdsame_only"):
- case Hash("sqrdmulh_asimdsame_only"):
+ case "sqdmulh_asimdsame_only"_h:
+ case "sqrdmulh_asimdsame_only"_h:
if ((ls_dst == kBRegSize) || (ls_dst == kDRegSize)) {
mnemonic = NULL;
}
@@ -3069,16 +2304,16 @@
NEONFormatDecoder nfd(instr);
switch (form_hash_) {
- case Hash("fcmla_asimdsame2_c"):
+ case "fcmla_asimdsame2_c"_h:
suffix = ", #'u1211*90";
break;
- case Hash("fcadd_asimdsame2_c"):
+ case "fcadd_asimdsame2_c"_h:
// Bit 10 is always set, so this gives 90 * 1 or 3.
suffix = ", #'u1212:1010*90";
break;
- case Hash("sdot_asimdsame2_d"):
- case Hash("udot_asimdsame2_d"):
- case Hash("usdot_asimdsame2_d"):
+ case "sdot_asimdsame2_d"_h:
+ case "udot_asimdsame2_d"_h:
+ case "usdot_asimdsame2_d"_h:
nfd.SetFormatMap(1, &map_usdot);
nfd.SetFormatMap(2, &map_usdot);
break;
@@ -3099,27 +2334,27 @@
nfd.SetFormatMap(0, nfd.LongIntegerFormatMap());
switch (form_hash_) {
- case Hash("saddw_asimddiff_w"):
- case Hash("ssubw_asimddiff_w"):
- case Hash("uaddw_asimddiff_w"):
- case Hash("usubw_asimddiff_w"):
+ case "saddw_asimddiff_w"_h:
+ case "ssubw_asimddiff_w"_h:
+ case "uaddw_asimddiff_w"_h:
+ case "usubw_asimddiff_w"_h:
nfd.SetFormatMap(1, nfd.LongIntegerFormatMap());
break;
- case Hash("addhn_asimddiff_n"):
- case Hash("raddhn_asimddiff_n"):
- case Hash("rsubhn_asimddiff_n"):
- case Hash("subhn_asimddiff_n"):
+ case "addhn_asimddiff_n"_h:
+ case "raddhn_asimddiff_n"_h:
+ case "rsubhn_asimddiff_n"_h:
+ case "subhn_asimddiff_n"_h:
nfd.SetFormatMaps(nfd.LongIntegerFormatMap());
nfd.SetFormatMap(0, nfd.IntegerFormatMap());
break;
- case Hash("pmull_asimddiff_l"):
+ case "pmull_asimddiff_l"_h:
if (nfd.GetVectorFormat(0) != kFormat8H) {
mnemonic = NULL;
}
break;
- case Hash("sqdmlal_asimddiff_l"):
- case Hash("sqdmlsl_asimddiff_l"):
- case Hash("sqdmull_asimddiff_l"):
+ case "sqdmlal_asimddiff_l"_h:
+ case "sqdmlsl_asimddiff_l"_h:
+ case "sqdmull_asimddiff_l"_h:
if (nfd.GetVectorFormat(0) == kFormat8H) {
mnemonic = NULL;
}
@@ -3138,9 +2373,7 @@
}
void Disassembler::DisassembleNEONFP16AcrossLanes(const Instruction *instr) {
- const char *mnemonic = mnemonic_.c_str();
- const char *form = "'Hd, 'Vn.'?30:84h";
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Hd, 'Vn.'?30:84h");
}
void Disassembler::VisitNEONAcrossLanes(const Instruction *instr) {
@@ -3152,8 +2385,8 @@
NEONFormatDecoder::IntegerFormatMap());
switch (form_hash_) {
- case Hash("saddlv_asimdall_only"):
- case Hash("uaddlv_asimdall_only"):
+ case "saddlv_asimdall_only"_h:
+ case "uaddlv_asimdall_only"_h:
nfd.SetFormatMap(0, nfd.LongScalarFormatMap());
}
@@ -3207,13 +2440,15 @@
}
void Disassembler::DisassembleNEONHalfFPMulByElement(const Instruction *instr) {
- const char *form = "'Vd.'?30:84h, 'Vn.'?30:84h, 'Ve.h['IVByElemIndex]";
- Format(instr, mnemonic_.c_str(), form);
+ FormatWithDecodedMnemonic(instr,
+ "'Vd.'?30:84h, 'Vn.'?30:84h, "
+ "'Ve.h['IVByElemIndex]");
}
void Disassembler::DisassembleNEONFPMulByElementLong(const Instruction *instr) {
- const char *form = "'Vd.'?30:42s, 'Vn.'?30:42h, 'Ve.h['IVByElemIndexFHM]";
- Format(instr, mnemonic_.c_str(), form);
+ FormatWithDecodedMnemonic(instr,
+ "'Vd.'?30:42s, 'Vn.'?30:42h, "
+ "'Ve.h['IVByElemIndexFHM]");
}
void Disassembler::DisassembleNEONComplexMulByElement(
@@ -3239,12 +2474,12 @@
NEONFormatDecoder::TriangularScalarFormatMap());
switch (form_hash_) {
- case Hash("ins_asimdins_iv_v"):
+ case "ins_asimdins_iv_v"_h:
mnemonic = "mov";
nfd.SetFormatMap(0, nfd.TriangularScalarFormatMap());
form = "'Vd.%s['IVInsIndex1], 'Vn.%s['IVInsIndex2]";
break;
- case Hash("ins_asimdins_ir_r"):
+ case "ins_asimdins_ir_r"_h:
mnemonic = "mov";
nfd.SetFormatMap(0, nfd.TriangularScalarFormatMap());
if (nfd.GetVectorFormat() == kFormatD) {
@@ -3253,8 +2488,8 @@
form = "'Vd.%s['IVInsIndex1], 'Wn";
}
break;
- case Hash("umov_asimdins_w_w"):
- case Hash("umov_asimdins_x_x"):
+ case "umov_asimdins_w_w"_h:
+ case "umov_asimdins_x_x"_h:
if (instr->Mask(NEON_Q) || ((instr->GetImmNEON5() & 7) == 4)) {
mnemonic = "mov";
}
@@ -3265,8 +2500,8 @@
form = "'Wd, 'Vn.%s['IVInsIndex1]";
}
break;
- case Hash("smov_asimdins_w_w"):
- case Hash("smov_asimdins_x_x"): {
+ case "smov_asimdins_w_w"_h:
+ case "smov_asimdins_x_x"_h: {
nfd.SetFormatMap(0, nfd.TriangularScalarFormatMap());
VectorFormat vform = nfd.GetVectorFormat();
if ((vform == kFormatD) ||
@@ -3276,10 +2511,10 @@
form = "'R30d, 'Vn.%s['IVInsIndex1]";
break;
}
- case Hash("dup_asimdins_dv_v"):
+ case "dup_asimdins_dv_v"_h:
form = "'Vd.%s, 'Vn.%s['IVInsIndex1]";
break;
- case Hash("dup_asimdins_dr_r"):
+ case "dup_asimdins_dr_r"_h:
if (nfd.GetVectorFormat() == kFormat2D) {
form = "'Vd.%s, 'Xn";
} else {
@@ -3832,40 +3067,40 @@
NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
switch (form_hash_) {
- case Hash("movi_asimdimm_n_b"):
+ case "movi_asimdimm_n_b"_h:
form = "'Vt.%s, 'IVMIImm8";
break;
- case Hash("bic_asimdimm_l_hl"):
- case Hash("movi_asimdimm_l_hl"):
- case Hash("mvni_asimdimm_l_hl"):
- case Hash("orr_asimdimm_l_hl"):
+ case "bic_asimdimm_l_hl"_h:
+ case "movi_asimdimm_l_hl"_h:
+ case "mvni_asimdimm_l_hl"_h:
+ case "orr_asimdimm_l_hl"_h:
nfd.SetFormatMap(0, &map_h);
break;
- case Hash("movi_asimdimm_m_sm"):
- case Hash("mvni_asimdimm_m_sm"):
+ case "movi_asimdimm_m_sm"_h:
+ case "mvni_asimdimm_m_sm"_h:
form = "'Vt.%s, 'IVMIImm8, msl 'IVMIShiftAmt2";
VIXL_FALLTHROUGH();
- case Hash("bic_asimdimm_l_sl"):
- case Hash("movi_asimdimm_l_sl"):
- case Hash("mvni_asimdimm_l_sl"):
- case Hash("orr_asimdimm_l_sl"):
+ case "bic_asimdimm_l_sl"_h:
+ case "movi_asimdimm_l_sl"_h:
+ case "mvni_asimdimm_l_sl"_h:
+ case "orr_asimdimm_l_sl"_h:
nfd.SetFormatMap(0, &map_s);
break;
- case Hash("movi_asimdimm_d_ds"):
+ case "movi_asimdimm_d_ds"_h:
form = "'Dd, 'IVMIImm";
break;
- case Hash("movi_asimdimm_d2_d"):
+ case "movi_asimdimm_d2_d"_h:
form = "'Vt.2d, 'IVMIImm";
break;
- case Hash("fmov_asimdimm_h_h"):
+ case "fmov_asimdimm_h_h"_h:
form = "'Vt.%s, 'IFPNeon";
nfd.SetFormatMap(0, &map_h);
break;
- case Hash("fmov_asimdimm_s_s"):
+ case "fmov_asimdimm_s_s"_h:
form = "'Vt.%s, 'IFPNeon";
nfd.SetFormatMap(0, &map_s);
break;
- case Hash("fmov_asimdimm_d2_d"):
+ case "fmov_asimdimm_d2_d"_h:
form = "'Vt.2d, 'IFPNeon";
break;
}
@@ -3882,8 +3117,8 @@
mnemonic = NULL;
}
switch (form_hash_) {
- case Hash("abs_asisdmisc_r"):
- case Hash("neg_asisdmisc_r"):
+ case "abs_asisdmisc_r"_h:
+ case "neg_asisdmisc_r"_h:
suffix = NULL;
}
Format(instr, mnemonic, form, suffix);
@@ -3895,14 +3130,14 @@
const char *suffix = NULL;
NEONFormatDecoder nfd(instr, NEONFormatDecoder::FPScalarFormatMap());
switch (form_hash_) {
- case Hash("fcmeq_asisdmisc_fz"):
- case Hash("fcmge_asisdmisc_fz"):
- case Hash("fcmgt_asisdmisc_fz"):
- case Hash("fcmle_asisdmisc_fz"):
- case Hash("fcmlt_asisdmisc_fz"):
+ case "fcmeq_asisdmisc_fz"_h:
+ case "fcmge_asisdmisc_fz"_h:
+ case "fcmgt_asisdmisc_fz"_h:
+ case "fcmle_asisdmisc_fz"_h:
+ case "fcmlt_asisdmisc_fz"_h:
suffix = ", #0.0";
break;
- case Hash("fcvtxn_asisdmisc_n"):
+ case "fcvtxn_asisdmisc_n"_h:
if (nfd.GetVectorFormat(0) == kFormatS) { // Source format.
mnemonic = NULL;
}
@@ -3916,9 +3151,9 @@
const char *form = "%sd, %sn";
NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
switch (form_hash_) {
- case Hash("sqxtn_asisdmisc_n"):
- case Hash("sqxtun_asisdmisc_n"):
- case Hash("uqxtn_asisdmisc_n"):
+ case "sqxtn_asisdmisc_n"_h:
+ case "sqxtun_asisdmisc_n"_h:
+ case "uqxtn_asisdmisc_n"_h:
nfd.SetFormatMap(1, nfd.LongScalarFormatMap());
}
Format(instr, mnemonic, nfd.SubstitutePlaceholders(form));
@@ -3930,11 +3165,11 @@
const char *suffix = NULL;
switch (form_hash_) {
- case Hash("fcmeq_asisdmiscfp16_fz"):
- case Hash("fcmge_asisdmiscfp16_fz"):
- case Hash("fcmgt_asisdmiscfp16_fz"):
- case Hash("fcmle_asisdmiscfp16_fz"):
- case Hash("fcmlt_asisdmiscfp16_fz"):
+ case "fcmeq_asisdmiscfp16_fz"_h:
+ case "fcmge_asisdmiscfp16_fz"_h:
+ case "fcmgt_asisdmiscfp16_fz"_h:
+ case "fcmle_asisdmiscfp16_fz"_h:
+ case "fcmlt_asisdmiscfp16_fz"_h:
suffix = ", #0.0";
}
Format(instr, mnemonic, form, suffix);
@@ -3975,16 +3210,16 @@
NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
VectorFormat vform = nfd.GetVectorFormat(0);
switch (form_hash_) {
- case Hash("srshl_asisdsame_only"):
- case Hash("urshl_asisdsame_only"):
- case Hash("sshl_asisdsame_only"):
- case Hash("ushl_asisdsame_only"):
+ case "srshl_asisdsame_only"_h:
+ case "urshl_asisdsame_only"_h:
+ case "sshl_asisdsame_only"_h:
+ case "ushl_asisdsame_only"_h:
if (vform != kFormatD) {
mnemonic = NULL;
}
break;
- case Hash("sqdmulh_asisdsame_only"):
- case Hash("sqrdmulh_asisdsame_only"):
+ case "sqdmulh_asisdsame_only"_h:
+ case "sqrdmulh_asisdsame_only"_h:
if ((vform == kFormatB) || (vform == kFormatD)) {
mnemonic = NULL;
}
@@ -3993,9 +3228,7 @@
}
void Disassembler::VisitNEONScalar3SameFP16(const Instruction *instr) {
- const char *mnemonic = mnemonic_.c_str();
- const char *form = "'Hd, 'Hn, 'Hm";
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Hd, 'Hn, 'Hm");
}
void Disassembler::VisitNEONScalar3SameExtra(const Instruction *instr) {
@@ -4060,7 +3293,7 @@
void Disassembler::VisitNEONScalarPairwise(const Instruction *instr) {
const char *mnemonic = mnemonic_.c_str();
- if (form_hash_ == Hash("addp_asisdpair_only")) {
+ if (form_hash_ == "addp_asisdpair_only"_h) {
// All pairwise operations except ADDP use bit U to differentiate FP16
// from FP32/FP64 variations.
if (instr->GetNEONSize() != 3) {
@@ -4092,8 +3325,8 @@
}
switch (form_hash_) {
- case Hash("shl_asisdshf_r"):
- case Hash("sli_asisdshf_r"):
+ case "shl_asisdshf_r"_h:
+ case "sli_asisdshf_r"_h:
suffix = "'IsL";
}
@@ -4126,9 +3359,9 @@
// clang-format on
NEONFormatDecoder nfd(instr, &map);
switch (form_hash_) {
- case Hash("sqshlu_asisdshf_r"):
- case Hash("sqshl_asisdshf_r"):
- case Hash("uqshl_asisdshf_r"):
+ case "sqshlu_asisdshf_r"_h:
+ case "sqshl_asisdshf_r"_h:
+ case "uqshl_asisdshf_r"_h:
suffix = "'IsL";
break;
default:
@@ -4150,9 +3383,9 @@
if (instr->GetImmNEONImmb() == 0 &&
CountSetBits(instr->GetImmNEONImmh(), 32) == 1) { // xtl variant.
- VIXL_ASSERT((form_hash_ == Hash("sshll_asimdshf_l")) ||
- (form_hash_ == Hash("ushll_asimdshf_l")));
- mnemonic = (form_hash_ == Hash("sshll_asimdshf_l")) ? "sxtl" : "uxtl";
+ VIXL_ASSERT((form_hash_ == "sshll_asimdshf_l"_h) ||
+ (form_hash_ == "ushll_asimdshf_l"_h));
+ mnemonic = (form_hash_ == "sshll_asimdshf_l"_h) ? "sxtl" : "uxtl";
suffix = NULL;
}
Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form), suffix);
@@ -4167,10 +3400,10 @@
if (vform_dst != kFormatUndefined) {
uint32_t ls_dst = LaneSizeInBitsFromFormat(vform_dst);
switch (form_hash_) {
- case Hash("scvtf_asimdshf_c"):
- case Hash("ucvtf_asimdshf_c"):
- case Hash("fcvtzs_asimdshf_c"):
- case Hash("fcvtzu_asimdshf_c"):
+ case "scvtf_asimdshf_c"_h:
+ case "ucvtf_asimdshf_c"_h:
+ case "fcvtzs_asimdshf_c"_h:
+ case "fcvtzu_asimdshf_c"_h:
if (ls_dst == kBRegSize) {
mnemonic = NULL;
}
@@ -4211,16 +3444,16 @@
NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
switch (form_hash_) {
- case Hash("tbl_asimdtbl_l2_2"):
- case Hash("tbx_asimdtbl_l2_2"):
+ case "tbl_asimdtbl_l2_2"_h:
+ case "tbx_asimdtbl_l2_2"_h:
form = form_2v;
break;
- case Hash("tbl_asimdtbl_l3_3"):
- case Hash("tbx_asimdtbl_l3_3"):
+ case "tbl_asimdtbl_l3_3"_h:
+ case "tbx_asimdtbl_l3_3"_h:
form = form_3v;
break;
- case Hash("tbl_asimdtbl_l4_4"):
- case Hash("tbx_asimdtbl_l4_4"):
+ case "tbl_asimdtbl_l4_4"_h:
+ case "tbx_asimdtbl_l4_4"_h:
form = form_4v;
break;
}
@@ -4240,161 +3473,52 @@
void Disassembler::VisitNEONPerm(const Instruction *instr) {
- const char *mnemonic = mnemonic_.c_str();
- const char *form = "'Vd.%s, 'Vn.%s, 'Vm.%s";
NEONFormatDecoder nfd(instr);
- Format(instr, mnemonic, nfd.Substitute(form));
+ FormatWithDecodedMnemonic(instr, nfd.Substitute("'Vd.%s, 'Vn.%s, 'Vm.%s"));
}
void Disassembler::Disassemble_Vd4S_Vn16B_Vm16B(const Instruction *instr) {
- const char *form = "'Vd.4s, 'Vn.16b, 'Vm.16b";
- Format(instr, mnemonic_.c_str(), form);
+ FormatWithDecodedMnemonic(instr, "'Vd.4s, 'Vn.16b, 'Vm.16b");
}
void Disassembler::
VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.s}, 'Pgl/z, ['Xns, 'Zm.s, '?22:suxtw #1]";
-
- switch (instr->Mask(
- SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsMask)) {
- case LD1H_z_p_bz_s_x32_scaled:
- mnemonic = "ld1h";
- break;
- case LD1SH_z_p_bz_s_x32_scaled:
- mnemonic = "ld1sh";
- break;
- case LDFF1H_z_p_bz_s_x32_scaled:
- mnemonic = "ldff1h";
- break;
- case LDFF1SH_z_p_bz_s_x32_scaled:
- mnemonic = "ldff1sh";
- break;
- default:
- form = "(SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr,
+ "{'Zt.s}, 'Pgl/z, ['Xns, 'Zm.s, '?22:suxtw #1]");
}
void Disassembler::VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.s}, 'Pgl/z, ['Xns, 'Zm.s, '?22:suxtw #2]";
-
- switch (
- instr->Mask(SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask)) {
- case LD1W_z_p_bz_s_x32_scaled:
- mnemonic = "ld1w";
- break;
- case LDFF1W_z_p_bz_s_x32_scaled:
- mnemonic = "ldff1w";
- break;
- default:
- form = "(SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr,
+ "{'Zt.s}, 'Pgl/z, ['Xns, 'Zm.s, '?22:suxtw #2]");
}
void Disassembler::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets(
const Instruction *instr) {
- const char *form = "{'Zt.s}, 'Pgl/z, ['Xns, 'Zm.s, '?22:suxtw]";
-
- const char *mnemonic = "unimplemented";
- switch (instr->Mask(SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask)) {
- case LD1B_z_p_bz_s_x32_unscaled:
- mnemonic = "ld1b";
- break;
- case LD1H_z_p_bz_s_x32_unscaled:
- mnemonic = "ld1h";
- break;
- case LD1SB_z_p_bz_s_x32_unscaled:
- mnemonic = "ld1sb";
- break;
- case LD1SH_z_p_bz_s_x32_unscaled:
- mnemonic = "ld1sh";
- break;
- case LD1W_z_p_bz_s_x32_unscaled:
- mnemonic = "ld1w";
- break;
- case LDFF1B_z_p_bz_s_x32_unscaled:
- mnemonic = "ldff1b";
- break;
- case LDFF1H_z_p_bz_s_x32_unscaled:
- mnemonic = "ldff1h";
- break;
- case LDFF1SB_z_p_bz_s_x32_unscaled:
- mnemonic = "ldff1sb";
- break;
- case LDFF1SH_z_p_bz_s_x32_unscaled:
- mnemonic = "ldff1sh";
- break;
- case LDFF1W_z_p_bz_s_x32_unscaled:
- mnemonic = "ldff1w";
- break;
- default:
- form = "(SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr,
+ "{'Zt.s}, 'Pgl/z, ['Xns, 'Zm.s, '?22:suxtw]");
}
void Disassembler::VisitSVE32BitGatherLoad_VectorPlusImm(
const Instruction *instr) {
const char *form = "{'Zt.s}, 'Pgl/z, ['Zn.s]";
- const char *form_imm_b = "{'Zt.s}, 'Pgl/z, ['Zn.s, #'u2016]";
+ const char *form_imm = "{'Zt.s}, 'Pgl/z, ['Zn.s, #'u2016]";
const char *form_imm_h = "{'Zt.s}, 'Pgl/z, ['Zn.s, #'u2016*2]";
const char *form_imm_w = "{'Zt.s}, 'Pgl/z, ['Zn.s, #'u2016*4]";
- const char *form_imm;
- const char *mnemonic = "unimplemented";
- switch (instr->Mask(SVE32BitGatherLoad_VectorPlusImmMask)) {
- case LD1B_z_p_ai_s:
- mnemonic = "ld1b";
- form_imm = form_imm_b;
- break;
- case LD1H_z_p_ai_s:
- mnemonic = "ld1h";
+ const char *mnemonic = mnemonic_.c_str();
+ switch (form_hash_) {
+ case "ld1h_z_p_ai_s"_h:
+ case "ld1sh_z_p_ai_s"_h:
+ case "ldff1h_z_p_ai_s"_h:
+ case "ldff1sh_z_p_ai_s"_h:
form_imm = form_imm_h;
break;
- case LD1SB_z_p_ai_s:
- mnemonic = "ld1sb";
- form_imm = form_imm_b;
- break;
- case LD1SH_z_p_ai_s:
- mnemonic = "ld1sh";
- form_imm = form_imm_h;
- break;
- case LD1W_z_p_ai_s:
- mnemonic = "ld1w";
+ case "ld1w_z_p_ai_s"_h:
+ case "ldff1w_z_p_ai_s"_h:
form_imm = form_imm_w;
break;
- case LDFF1B_z_p_ai_s:
- mnemonic = "ldff1b";
- form_imm = form_imm_b;
- break;
- case LDFF1H_z_p_ai_s:
- mnemonic = "ldff1h";
- form_imm = form_imm_h;
- break;
- case LDFF1SB_z_p_ai_s:
- mnemonic = "ldff1sb";
- form_imm = form_imm_b;
- break;
- case LDFF1SH_z_p_ai_s:
- mnemonic = "ldff1sh";
- form_imm = form_imm_h;
- break;
- case LDFF1W_z_p_ai_s:
- mnemonic = "ldff1w";
- form_imm = form_imm_w;
- break;
- default:
- form = "(SVE32BitGatherLoad_VectorPlusImm)";
- form_imm = form;
- break;
}
if (instr->ExtractBits(20, 16) != 0) form = form_imm;
@@ -4434,70 +3558,21 @@
void Disassembler::VisitSVE32BitGatherPrefetch_VectorPlusImm(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = (instr->ExtractBits(20, 16) != 0)
? "'prefSVEOp, 'Pgl, ['Zn.s, #'u2016]"
: "'prefSVEOp, 'Pgl, ['Zn.s]";
-
- switch (instr->Mask(SVE32BitGatherPrefetch_VectorPlusImmMask)) {
- case PRFB_i_p_ai_s:
- mnemonic = "prfb";
- break;
- case PRFD_i_p_ai_s:
- mnemonic = "prfd";
- break;
- case PRFH_i_p_ai_s:
- mnemonic = "prfh";
- break;
- case PRFW_i_p_ai_s:
- mnemonic = "prfw";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.s}, 'Pgl, ['Xns, 'Zm.s, '?14:suxtw #'u2423]";
-
- switch (instr->Mask(SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask)) {
- case ST1H_z_p_bz_s_x32_scaled:
- mnemonic = "st1h";
- break;
- case ST1W_z_p_bz_s_x32_scaled:
- mnemonic = "st1w";
- break;
- default:
- form = "(SVE32BitScatterStore_ScalarPlus32BitScaledOffsets)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr,
+ "{'Zt.s}, 'Pgl, ['Xns, 'Zm.s, '?14:suxtw #'u2423]");
}
void Disassembler::VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.s}, 'Pgl, ['Xns, 'Zm.s, '?14:suxtw]";
-
- switch (
- instr->Mask(SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask)) {
- case ST1B_z_p_bz_s_x32_unscaled:
- mnemonic = "st1b";
- break;
- case ST1H_z_p_bz_s_x32_unscaled:
- mnemonic = "st1h";
- break;
- case ST1W_z_p_bz_s_x32_unscaled:
- mnemonic = "st1w";
- break;
- default:
- form = "(SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "{'Zt.s}, 'Pgl, ['Xns, 'Zm.s, '?14:suxtw]");
}
void Disassembler::VisitSVE32BitScatterStore_VectorPlusImm(
@@ -4530,200 +3605,27 @@
void Disassembler::VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d, '?22:suxtw #'u2423]";
-
- switch (instr->Mask(
- SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask)) {
- case LD1D_z_p_bz_d_x32_scaled:
- mnemonic = "ld1d";
- break;
- case LD1H_z_p_bz_d_x32_scaled:
- mnemonic = "ld1h";
- break;
- case LD1SH_z_p_bz_d_x32_scaled:
- mnemonic = "ld1sh";
- break;
- case LD1SW_z_p_bz_d_x32_scaled:
- mnemonic = "ld1sw";
- break;
- case LD1W_z_p_bz_d_x32_scaled:
- mnemonic = "ld1w";
- break;
- case LDFF1D_z_p_bz_d_x32_scaled:
- mnemonic = "ldff1d";
- break;
- case LDFF1H_z_p_bz_d_x32_scaled:
- mnemonic = "ldff1h";
- break;
- case LDFF1SH_z_p_bz_d_x32_scaled:
- mnemonic = "ldff1sh";
- break;
- case LDFF1SW_z_p_bz_d_x32_scaled:
- mnemonic = "ldff1sw";
- break;
- case LDFF1W_z_p_bz_d_x32_scaled:
- mnemonic = "ldff1w";
- break;
- default:
- form = "(SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr,
+ "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d, '?22:suxtw "
+ "#'u2423]");
}
void Disassembler::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d, lsl #'u2423]";
-
- switch (instr->Mask(SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask)) {
- case LD1D_z_p_bz_d_64_scaled:
- mnemonic = "ld1d";
- break;
- case LD1H_z_p_bz_d_64_scaled:
- mnemonic = "ld1h";
- break;
- case LD1SH_z_p_bz_d_64_scaled:
- mnemonic = "ld1sh";
- break;
- case LD1SW_z_p_bz_d_64_scaled:
- mnemonic = "ld1sw";
- break;
- case LD1W_z_p_bz_d_64_scaled:
- mnemonic = "ld1w";
- break;
- case LDFF1D_z_p_bz_d_64_scaled:
- mnemonic = "ldff1d";
- break;
- case LDFF1H_z_p_bz_d_64_scaled:
- mnemonic = "ldff1h";
- break;
- case LDFF1SH_z_p_bz_d_64_scaled:
- mnemonic = "ldff1sh";
- break;
- case LDFF1SW_z_p_bz_d_64_scaled:
- mnemonic = "ldff1sw";
- break;
- case LDFF1W_z_p_bz_d_64_scaled:
- mnemonic = "ldff1w";
- break;
- default:
- form = "(SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr,
+ "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d, lsl #'u2423]");
}
void Disassembler::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d]";
-
- switch (instr->Mask(SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask)) {
- case LD1B_z_p_bz_d_64_unscaled:
- mnemonic = "ld1b";
- break;
- case LD1D_z_p_bz_d_64_unscaled:
- mnemonic = "ld1d";
- break;
- case LD1H_z_p_bz_d_64_unscaled:
- mnemonic = "ld1h";
- break;
- case LD1SB_z_p_bz_d_64_unscaled:
- mnemonic = "ld1sb";
- break;
- case LD1SH_z_p_bz_d_64_unscaled:
- mnemonic = "ld1sh";
- break;
- case LD1SW_z_p_bz_d_64_unscaled:
- mnemonic = "ld1sw";
- break;
- case LD1W_z_p_bz_d_64_unscaled:
- mnemonic = "ld1w";
- break;
- case LDFF1B_z_p_bz_d_64_unscaled:
- mnemonic = "ldff1b";
- break;
- case LDFF1D_z_p_bz_d_64_unscaled:
- mnemonic = "ldff1d";
- break;
- case LDFF1H_z_p_bz_d_64_unscaled:
- mnemonic = "ldff1h";
- break;
- case LDFF1SB_z_p_bz_d_64_unscaled:
- mnemonic = "ldff1sb";
- break;
- case LDFF1SH_z_p_bz_d_64_unscaled:
- mnemonic = "ldff1sh";
- break;
- case LDFF1SW_z_p_bz_d_64_unscaled:
- mnemonic = "ldff1sw";
- break;
- case LDFF1W_z_p_bz_d_64_unscaled:
- mnemonic = "ldff1w";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d]");
}
void Disassembler::
VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d, '?22:suxtw]";
-
- switch (instr->Mask(
- SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask)) {
- case LD1B_z_p_bz_d_x32_unscaled:
- mnemonic = "ld1b";
- break;
- case LD1D_z_p_bz_d_x32_unscaled:
- mnemonic = "ld1d";
- break;
- case LD1H_z_p_bz_d_x32_unscaled:
- mnemonic = "ld1h";
- break;
- case LD1SB_z_p_bz_d_x32_unscaled:
- mnemonic = "ld1sb";
- break;
- case LD1SH_z_p_bz_d_x32_unscaled:
- mnemonic = "ld1sh";
- break;
- case LD1SW_z_p_bz_d_x32_unscaled:
- mnemonic = "ld1sw";
- break;
- case LD1W_z_p_bz_d_x32_unscaled:
- mnemonic = "ld1w";
- break;
- case LDFF1B_z_p_bz_d_x32_unscaled:
- mnemonic = "ldff1b";
- break;
- case LDFF1D_z_p_bz_d_x32_unscaled:
- mnemonic = "ldff1d";
- break;
- case LDFF1H_z_p_bz_d_x32_unscaled:
- mnemonic = "ldff1h";
- break;
- case LDFF1SB_z_p_bz_d_x32_unscaled:
- mnemonic = "ldff1sb";
- break;
- case LDFF1SH_z_p_bz_d_x32_unscaled:
- mnemonic = "ldff1sh";
- break;
- case LDFF1SW_z_p_bz_d_x32_unscaled:
- mnemonic = "ldff1sw";
- break;
- case LDFF1W_z_p_bz_d_x32_unscaled:
- mnemonic = "ldff1w";
- break;
- default:
- form = "(SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr,
+ "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d, '?22:suxtw]");
}
void Disassembler::VisitSVE64BitGatherLoad_VectorPlusImm(
@@ -4745,322 +3647,116 @@
}
}
- const char *mnemonic = "unimplemented";
- switch (instr->Mask(SVE64BitGatherLoad_VectorPlusImmMask)) {
- case LD1B_z_p_ai_d:
- mnemonic = "ld1b";
- break;
- case LD1D_z_p_ai_d:
- mnemonic = "ld1d";
- break;
- case LD1H_z_p_ai_d:
- mnemonic = "ld1h";
- break;
- case LD1SB_z_p_ai_d:
- mnemonic = "ld1sb";
- break;
- case LD1SH_z_p_ai_d:
- mnemonic = "ld1sh";
- break;
- case LD1SW_z_p_ai_d:
- mnemonic = "ld1sw";
- break;
- case LD1W_z_p_ai_d:
- mnemonic = "ld1w";
- break;
- case LDFF1B_z_p_ai_d:
- mnemonic = "ldff1b";
- break;
- case LDFF1D_z_p_ai_d:
- mnemonic = "ldff1d";
- break;
- case LDFF1H_z_p_ai_d:
- mnemonic = "ldff1h";
- break;
- case LDFF1SB_z_p_ai_d:
- mnemonic = "ldff1sb";
- break;
- case LDFF1SH_z_p_ai_d:
- mnemonic = "ldff1sh";
- break;
- case LDFF1SW_z_p_ai_d:
- mnemonic = "ldff1sw";
- break;
- case LDFF1W_z_p_ai_d:
- mnemonic = "ldff1w";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets)";
+ const char *form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d";
+ const char *suffix = "]";
- switch (
- instr->Mask(SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask)) {
- case PRFB_i_p_bz_d_64_scaled:
- mnemonic = "prfb";
- form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d]";
+ switch (form_hash_) {
+ case "prfh_i_p_bz_d_64_scaled"_h:
+ suffix = ", lsl #1]";
break;
- case PRFD_i_p_bz_d_64_scaled:
- mnemonic = "prfd";
- form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d, lsl #3]";
+ case "prfs_i_p_bz_d_64_scaled"_h:
+ suffix = ", lsl #2]";
break;
- case PRFH_i_p_bz_d_64_scaled:
- mnemonic = "prfh";
- form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d, lsl #1]";
- break;
- case PRFW_i_p_bz_d_64_scaled:
- mnemonic = "prfw";
- form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d, lsl #2]";
- break;
- default:
+ case "prfd_i_p_bz_d_64_scaled"_h:
+ suffix = ", lsl #3]";
break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::
VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d, '?22:suxtw";
- const char *suffix = NULL;
+ const char *form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d, '?22:suxtw ";
+ const char *suffix = "]";
- switch (instr->Mask(
- SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsMask)) {
- case PRFB_i_p_bz_d_x32_scaled:
- mnemonic = "prfb";
- suffix = " ]";
+ switch (form_hash_) {
+ case "prfh_i_p_bz_d_x32_scaled"_h:
+ suffix = "#1]";
break;
- case PRFD_i_p_bz_d_x32_scaled:
- mnemonic = "prfd";
- suffix = " #3]";
+ case "prfs_i_p_bz_d_x32_scaled"_h:
+ suffix = "#2]";
break;
- case PRFH_i_p_bz_d_x32_scaled:
- mnemonic = "prfh";
- suffix = " #1]";
- break;
- case PRFW_i_p_bz_d_x32_scaled:
- mnemonic = "prfw";
- suffix = " #2]";
- break;
- default:
- form = "(SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets)";
+ case "prfd_i_p_bz_d_x32_scaled"_h:
+ suffix = "#3]";
break;
}
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVE64BitGatherPrefetch_VectorPlusImm(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = (instr->ExtractBits(20, 16) != 0)
? "'prefSVEOp, 'Pgl, ['Zn.d, #'u2016]"
: "'prefSVEOp, 'Pgl, ['Zn.d]";
- switch (instr->Mask(SVE64BitGatherPrefetch_VectorPlusImmMask)) {
- case PRFB_i_p_ai_d:
- mnemonic = "prfb";
- break;
- case PRFD_i_p_ai_d:
- mnemonic = "prfd";
- break;
- case PRFH_i_p_ai_d:
- mnemonic = "prfh";
- break;
- case PRFW_i_p_ai_d:
- mnemonic = "prfw";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d, lsl #'u2423]";
-
- switch (instr->Mask(SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask)) {
- case ST1D_z_p_bz_d_64_scaled:
- mnemonic = "st1d";
- break;
- case ST1H_z_p_bz_d_64_scaled:
- mnemonic = "st1h";
- break;
- case ST1W_z_p_bz_d_64_scaled:
- mnemonic = "st1w";
- break;
- default:
- form = "(SVE64BitScatterStore_ScalarPlus64BitScaledOffsets)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d, lsl #'u2423]");
}
void Disassembler::VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d]";
-
- switch (
- instr->Mask(SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask)) {
- case ST1B_z_p_bz_d_64_unscaled:
- mnemonic = "st1b";
- break;
- case ST1D_z_p_bz_d_64_unscaled:
- mnemonic = "st1d";
- break;
- case ST1H_z_p_bz_d_64_unscaled:
- mnemonic = "st1h";
- break;
- case ST1W_z_p_bz_d_64_unscaled:
- mnemonic = "st1w";
- break;
- default:
- form = "(SVE64BitScatterStore_ScalarPlus64BitUnscaledOffset)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d]");
}
void Disassembler::
VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d, '?14:suxtw #'u2423]";
-
- switch (instr->Mask(
- SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsMask)) {
- case ST1D_z_p_bz_d_x32_scaled:
- mnemonic = "st1d";
- break;
- case ST1H_z_p_bz_d_x32_scaled:
- mnemonic = "st1h";
- break;
- case ST1W_z_p_bz_d_x32_scaled:
- mnemonic = "st1w";
- break;
- default:
- form = "(SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr,
+ "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d, '?14:suxtw #'u2423]");
}
void Disassembler::
VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d, '?14:suxtw]";
-
- switch (instr->Mask(
- SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsMask)) {
- case ST1B_z_p_bz_d_x32_unscaled:
- mnemonic = "st1b";
- break;
- case ST1D_z_p_bz_d_x32_unscaled:
- mnemonic = "st1d";
- break;
- case ST1H_z_p_bz_d_x32_unscaled:
- mnemonic = "st1h";
- break;
- case ST1W_z_p_bz_d_x32_unscaled:
- mnemonic = "st1w";
- break;
- default:
- form = "(SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d, '?14:suxtw]");
}
void Disassembler::VisitSVE64BitScatterStore_VectorPlusImm(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "{'Zt.d}, 'Pgl, ['Zn.d";
- const char *suffix = NULL;
+ const char *suffix = "]";
- bool is_zero = instr->ExtractBits(20, 16) == 0;
-
- switch (instr->Mask(SVE64BitScatterStore_VectorPlusImmMask)) {
- case ST1B_z_p_ai_d:
- mnemonic = "st1b";
- suffix = is_zero ? "]" : ", #'u2016]";
- break;
- case ST1D_z_p_ai_d:
- mnemonic = "st1d";
- suffix = is_zero ? "]" : ", #'u2016*8]";
- break;
- case ST1H_z_p_ai_d:
- mnemonic = "st1h";
- suffix = is_zero ? "]" : ", #'u2016*2]";
- break;
- case ST1W_z_p_ai_d:
- mnemonic = "st1w";
- suffix = is_zero ? "]" : ", #'u2016*4]";
- break;
- default:
- form = "(SVE64BitScatterStore_VectorPlusImm)";
- break;
+ if (instr->ExtractBits(20, 16) != 0) {
+ switch (form_hash_) {
+ case "st1b_z_p_ai_d"_h:
+ suffix = ", #'u2016]";
+ break;
+ case "st1h_z_p_ai_d"_h:
+ suffix = ", #'u2016*2]";
+ break;
+ case "st1w_z_p_ai_d"_h:
+ suffix = ", #'u2016*4]";
+ break;
+ case "st1d_z_p_ai_d"_h:
+ suffix = ", #'u2016*8]";
+ break;
+ }
}
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEBitwiseLogicalWithImm_Unpredicated(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'tl, 'Zd.'tl, 'ITriSvel";
-
if (instr->GetSVEImmLogical() == 0) {
// The immediate encoded in the instruction is not in the expected format.
Format(instr, "unallocated", "(SVEBitwiseImm)");
- return;
+ } else {
+ FormatWithDecodedMnemonic(instr, "'Zd.'tl, 'Zd.'tl, 'ITriSvel");
}
-
- switch (instr->Mask(SVEBitwiseLogicalWithImm_UnpredicatedMask)) {
- case AND_z_zi:
- mnemonic = "and";
- break;
- case EOR_z_zi:
- mnemonic = "eor";
- break;
- case ORR_z_zi:
- mnemonic = "orr";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEBitwiseLogical_Predicated(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
-
- switch (instr->Mask(SVEBitwiseLogical_PredicatedMask)) {
- case AND_z_p_zz:
- mnemonic = "and";
- break;
- case BIC_z_p_zz:
- mnemonic = "bic";
- break;
- case EOR_z_p_zz:
- mnemonic = "eor";
- break;
- case ORR_z_p_zz:
- mnemonic = "orr";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
}
void Disassembler::VisitSVEBitwiseShiftByImm_Predicated(
@@ -5075,17 +3771,17 @@
form = "(SVEBitwiseShiftByImm_Predicated)";
} else {
switch (form_hash_) {
- case Hash("lsl_z_p_zi"):
- case Hash("sqshl_z_p_zi"):
- case Hash("sqshlu_z_p_zi"):
- case Hash("uqshl_z_p_zi"):
+ case "lsl_z_p_zi"_h:
+ case "sqshl_z_p_zi"_h:
+ case "sqshlu_z_p_zi"_h:
+ case "uqshl_z_p_zi"_h:
suffix = "'ITriSvep";
break;
- case Hash("asrd_z_p_zi"):
- case Hash("asr_z_p_zi"):
- case Hash("lsr_z_p_zi"):
- case Hash("srshr_z_p_zi"):
- case Hash("urshr_z_p_zi"):
+ case "asrd_z_p_zi"_h:
+ case "asr_z_p_zi"_h:
+ case "lsr_z_p_zi"_h:
+ case "srshr_z_p_zi"_h:
+ case "urshr_z_p_zi"_h:
suffix = "'ITriSveq";
break;
default:
@@ -5099,59 +3795,16 @@
void Disassembler::VisitSVEBitwiseShiftByVector_Predicated(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
-
- switch (instr->Mask(SVEBitwiseShiftByVector_PredicatedMask)) {
- case ASRR_z_p_zz:
- mnemonic = "asrr";
- break;
- case ASR_z_p_zz:
- mnemonic = "asr";
- break;
- case LSLR_z_p_zz:
- mnemonic = "lslr";
- break;
- case LSL_z_p_zz:
- mnemonic = "lsl";
- break;
- case LSRR_z_p_zz:
- mnemonic = "lsrr";
- break;
- case LSR_z_p_zz:
- mnemonic = "lsr";
- break;
- default:
- form = "(SVEBitwiseShiftByVector_Predicated)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
}
void Disassembler::VisitSVEBitwiseShiftByWideElements_Predicated(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.d";
-
if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
- form = "(SVEBitwiseShiftByWideElements_Predicated)";
+ Format(instr, "unallocated", "(SVEBitwiseShiftByWideElements_Predicated)");
} else {
- switch (instr->Mask(SVEBitwiseShiftByWideElements_PredicatedMask)) {
- case ASR_z_p_zw:
- mnemonic = "asr";
- break;
- case LSL_z_p_zw:
- mnemonic = "lsl";
- break;
- case LSR_z_p_zw:
- mnemonic = "lsr";
- break;
- default:
- form = "(SVEBitwiseShiftByWideElements_Predicated)";
- break;
- }
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.d");
}
- Format(instr, mnemonic, form);
}
static bool SVEMoveMaskPreferred(uint64_t value, int lane_bytes_log2) {
@@ -5346,304 +3999,145 @@
}
void Disassembler::VisitSVECompressActiveElements(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVECompressActiveElements)";
-
- switch (instr->Mask(SVECompressActiveElementsMask)) {
- case COMPACT_z_p_z:
- // The top bit of size is always set for compact, so 't can only be
- // substituted with types S and D.
- VIXL_ASSERT(instr->ExtractBit(23) == 1);
- mnemonic = "compact";
- form = "'Zd.'t, 'Pgl, 'Zn.'t";
- break;
- default:
- break;
+ // The top bit of size is always set for compact, so 't can only be
+ // substituted with types S and D.
+ if (instr->ExtractBit(23) == 1) {
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl, 'Zn.'t");
+ } else {
+ VisitUnallocated(instr);
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEConditionallyBroadcastElementToVector(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl, 'Zd.'t, 'Zn.'t";
-
- switch (instr->Mask(SVEConditionallyBroadcastElementToVectorMask)) {
- case CLASTA_z_p_zz:
- mnemonic = "clasta";
- break;
- case CLASTB_z_p_zz:
- mnemonic = "clastb";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl, 'Zd.'t, 'Zn.'t");
}
void Disassembler::VisitSVEConditionallyExtractElementToGeneralRegister(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "'Wd, 'Pgl, 'Wd, 'Zn.'t";
if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
form = "'Xd, p'u1210, 'Xd, 'Zn.'t";
}
-
- switch (instr->Mask(SVEConditionallyExtractElementToGeneralRegisterMask)) {
- case CLASTA_r_p_z:
- mnemonic = "clasta";
- break;
- case CLASTB_r_p_z:
- mnemonic = "clastb";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEConditionallyExtractElementToSIMDFPScalar(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'t'u0400, 'Pgl, 't'u0400, 'Zn.'t";
-
- switch (instr->Mask(SVEConditionallyExtractElementToSIMDFPScalarMask)) {
- case CLASTA_v_p_z:
- mnemonic = "clasta";
- break;
- case CLASTB_v_p_z:
- mnemonic = "clastb";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'t'u0400, 'Pgl, 't'u0400, 'Zn.'t");
}
void Disassembler::VisitSVEConditionallyTerminateScalars(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = (instr->ExtractBit(22) == 0) ? "'Wn, 'Wm" : "'Xn, 'Xm";
-
- switch (instr->Mask(SVEConditionallyTerminateScalarsMask)) {
- case CTERMEQ_rr:
- mnemonic = "ctermeq";
- break;
- case CTERMNE_rr:
- mnemonic = "ctermne";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEConstructivePrefix_Unpredicated(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEConstructivePrefix_Unpredicated)";
-
- switch (instr->Mask(SVEConstructivePrefix_UnpredicatedMask)) {
- case MOVPRFX_z_z:
- mnemonic = "movprfx";
- form = "'Zd, 'Zn";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd, 'Zn");
}
void Disassembler::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
-
- bool rm_is_zr = instr->GetRm() == kZeroRegCode;
-
const char *form = "{'Zt.'tlss}, 'Pgl/z, ['Xns";
- const char *suffix = NULL;
+ const char *suffix = "]";
- switch (instr->Mask(SVEContiguousFirstFaultLoad_ScalarPlusScalarMask)) {
- case LDFF1B_z_p_br_u16:
- case LDFF1B_z_p_br_u32:
- case LDFF1B_z_p_br_u64:
- case LDFF1B_z_p_br_u8:
- mnemonic = "ldff1b";
- suffix = rm_is_zr ? "]" : ", 'Xm]";
- break;
- case LDFF1D_z_p_br_u64:
- mnemonic = "ldff1d";
- suffix = rm_is_zr ? "]" : ", 'Xm, lsl #3]";
- break;
- case LDFF1H_z_p_br_u16:
- case LDFF1H_z_p_br_u32:
- case LDFF1H_z_p_br_u64:
- mnemonic = "ldff1h";
- suffix = rm_is_zr ? "]" : ", 'Xm, lsl #1]";
- break;
- case LDFF1SB_z_p_br_s16:
- case LDFF1SB_z_p_br_s32:
- case LDFF1SB_z_p_br_s64:
- mnemonic = "ldff1sb";
- suffix = rm_is_zr ? "]" : ", 'Xm]";
- break;
- case LDFF1SH_z_p_br_s32:
- case LDFF1SH_z_p_br_s64:
- mnemonic = "ldff1sh";
- suffix = rm_is_zr ? "]" : ", 'Xm, lsl #1]";
- break;
- case LDFF1SW_z_p_br_s64:
- mnemonic = "ldff1sw";
- suffix = rm_is_zr ? "]" : ", 'Xm, lsl #2]";
- break;
- case LDFF1W_z_p_br_u32:
- case LDFF1W_z_p_br_u64:
- mnemonic = "ldff1w";
- suffix = rm_is_zr ? "]" : ", 'Xm, lsl #2]";
- break;
- default:
- form = "(SVEContiguousFirstFaultLoad_ScalarPlusScalar)";
- break;
+ if (instr->GetRm() != kZeroRegCode) {
+ switch (form_hash_) {
+ case "ldff1b_z_p_br_u8"_h:
+ case "ldff1b_z_p_br_u16"_h:
+ case "ldff1b_z_p_br_u32"_h:
+ case "ldff1b_z_p_br_u64"_h:
+ case "ldff1sb_z_p_br_s16"_h:
+ case "ldff1sb_z_p_br_s32"_h:
+ case "ldff1sb_z_p_br_s64"_h:
+ suffix = ", 'Xm]";
+ break;
+ case "ldff1h_z_p_br_u16"_h:
+ case "ldff1h_z_p_br_u32"_h:
+ case "ldff1h_z_p_br_u64"_h:
+ case "ldff1sh_z_p_br_s32"_h:
+ case "ldff1sh_z_p_br_s64"_h:
+ suffix = ", 'Xm, lsl #1]";
+ break;
+ case "ldff1w_z_p_br_u32"_h:
+ case "ldff1w_z_p_br_u64"_h:
+ case "ldff1sw_z_p_br_s64"_h:
+ suffix = ", 'Xm, lsl #2]";
+ break;
+ case "ldff1d_z_p_br_u64"_h:
+ suffix = ", 'Xm, lsl #3]";
+ break;
+ }
}
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEContiguousNonFaultLoad_ScalarPlusImm(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "{'Zt.'tlss}, 'Pgl/z, ['Xns";
const char *suffix =
(instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
-
- switch (instr->Mask(SVEContiguousNonFaultLoad_ScalarPlusImmMask)) {
- case LDNF1B_z_p_bi_u16:
- case LDNF1B_z_p_bi_u32:
- case LDNF1B_z_p_bi_u64:
- case LDNF1B_z_p_bi_u8:
- mnemonic = "ldnf1b";
- break;
- case LDNF1D_z_p_bi_u64:
- mnemonic = "ldnf1d";
- break;
- case LDNF1H_z_p_bi_u16:
- case LDNF1H_z_p_bi_u32:
- case LDNF1H_z_p_bi_u64:
- mnemonic = "ldnf1h";
- break;
- case LDNF1SB_z_p_bi_s16:
- case LDNF1SB_z_p_bi_s32:
- case LDNF1SB_z_p_bi_s64:
- mnemonic = "ldnf1sb";
- break;
- case LDNF1SH_z_p_bi_s32:
- case LDNF1SH_z_p_bi_s64:
- mnemonic = "ldnf1sh";
- break;
- case LDNF1SW_z_p_bi_s64:
- mnemonic = "ldnf1sw";
- break;
- case LDNF1W_z_p_bi_u32:
- case LDNF1W_z_p_bi_u64:
- mnemonic = "ldnf1w";
- break;
- default:
- form = "(SVEContiguousNonFaultLoad_ScalarPlusImm)";
- suffix = NULL;
- break;
- }
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEContiguousNonTemporalLoad_ScalarPlusImm)";
-
+ const char *form = "{'Zt.b}, 'Pgl/z, ['Xns";
const char *suffix =
(instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
- switch (instr->Mask(SVEContiguousNonTemporalLoad_ScalarPlusImmMask)) {
- case LDNT1B_z_p_bi_contiguous:
- mnemonic = "ldnt1b";
- form = "{'Zt.b}, 'Pgl/z, ['Xns";
- break;
- case LDNT1D_z_p_bi_contiguous:
- mnemonic = "ldnt1d";
+ switch (form_hash_) {
+ case "ldnt1d_z_p_bi_contiguous"_h:
form = "{'Zt.d}, 'Pgl/z, ['Xns";
break;
- case LDNT1H_z_p_bi_contiguous:
- mnemonic = "ldnt1h";
+ case "ldnt1h_z_p_bi_contiguous"_h:
form = "{'Zt.h}, 'Pgl/z, ['Xns";
break;
- case LDNT1W_z_p_bi_contiguous:
- mnemonic = "ldnt1w";
+ case "ldnt1w_z_p_bi_contiguous"_h:
form = "{'Zt.s}, 'Pgl/z, ['Xns";
break;
- default:
- suffix = NULL;
- break;
}
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEContiguousNonTemporalLoad_ScalarPlusScalar)";
-
- switch (instr->Mask(SVEContiguousNonTemporalLoad_ScalarPlusScalarMask)) {
- case LDNT1B_z_p_br_contiguous:
- mnemonic = "ldnt1b";
- form = "{'Zt.b}, 'Pgl/z, ['Xns, 'Rm]";
- break;
- case LDNT1D_z_p_br_contiguous:
- mnemonic = "ldnt1d";
+ const char *form = "{'Zt.b}, 'Pgl/z, ['Xns, 'Rm]";
+ switch (form_hash_) {
+ case "ldnt1d_z_p_br_contiguous"_h:
form = "{'Zt.d}, 'Pgl/z, ['Xns, 'Rm, lsl #3]";
break;
- case LDNT1H_z_p_br_contiguous:
- mnemonic = "ldnt1h";
+ case "ldnt1h_z_p_br_contiguous"_h:
form = "{'Zt.h}, 'Pgl/z, ['Xns, 'Rm, lsl #1]";
break;
- case LDNT1W_z_p_br_contiguous:
- mnemonic = "ldnt1w";
+ case "ldnt1w_z_p_br_contiguous"_h:
form = "{'Zt.s}, 'Pgl/z, ['Xns, 'Rm, lsl #2]";
break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEContiguousNonTemporalStore_ScalarPlusImm(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEContiguousNonTemporalStore_ScalarPlusImm)";
-
+ const char *form = "{'Zt.b}, 'Pgl, ['Xns";
const char *suffix =
(instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
- switch (instr->Mask(SVEContiguousNonTemporalStore_ScalarPlusImmMask)) {
- case STNT1B_z_p_bi_contiguous:
- mnemonic = "stnt1b";
- form = "{'Zt.b}, 'Pgl, ['Xns";
- break;
- case STNT1D_z_p_bi_contiguous:
- mnemonic = "stnt1d";
+
+ switch (form_hash_) {
+ case "stnt1d_z_p_bi_contiguous"_h:
form = "{'Zt.d}, 'Pgl, ['Xns";
break;
- case STNT1H_z_p_bi_contiguous:
- mnemonic = "stnt1h";
+ case "stnt1h_z_p_bi_contiguous"_h:
form = "{'Zt.h}, 'Pgl, ['Xns";
break;
- case STNT1W_z_p_bi_contiguous:
- mnemonic = "stnt1w";
+ case "stnt1w_z_p_bi_contiguous"_h:
form = "{'Zt.s}, 'Pgl, ['Xns";
break;
- default:
- suffix = NULL;
- break;
}
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar(
@@ -5676,28 +4170,10 @@
void Disassembler::VisitSVEContiguousPrefetch_ScalarPlusImm(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = (instr->ExtractBits(21, 16) != 0)
? "'prefSVEOp, 'Pgl, ['Xns, #'s2116, mul vl]"
: "'prefSVEOp, 'Pgl, ['Xns]";
-
- switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusImmMask)) {
- case PRFB_i_p_bi_s:
- mnemonic = "prfb";
- break;
- case PRFD_i_p_bi_s:
- mnemonic = "prfd";
- break;
- case PRFH_i_p_bi_s:
- mnemonic = "prfh";
- break;
- case PRFW_i_p_bi_s:
- mnemonic = "prfw";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEContiguousPrefetch_ScalarPlusScalar(
@@ -5732,57 +4208,18 @@
void Disassembler::VisitSVEContiguousStore_ScalarPlusImm(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
-
// The 'size' field isn't in the usual place here.
const char *form = "{'Zt.'tls}, 'Pgl, ['Xns, #'s1916, mul vl]";
if (instr->ExtractBits(19, 16) == 0) {
form = "{'Zt.'tls}, 'Pgl, ['Xns]";
}
-
- switch (instr->Mask(SVEContiguousStore_ScalarPlusImmMask)) {
- case ST1B_z_p_bi:
- mnemonic = "st1b";
- break;
- case ST1D_z_p_bi:
- mnemonic = "st1d";
- break;
- case ST1H_z_p_bi:
- mnemonic = "st1h";
- break;
- case ST1W_z_p_bi:
- mnemonic = "st1w";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEContiguousStore_ScalarPlusScalar(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
-
// The 'size' field isn't in the usual place here.
- const char *form = "{'Zt.'tls}, 'Pgl, ['Xns, 'Xm'NSveS]";
-
- switch (instr->Mask(SVEContiguousStore_ScalarPlusScalarMask)) {
- case ST1B_z_p_br:
- mnemonic = "st1b";
- break;
- case ST1D_z_p_br:
- mnemonic = "st1d";
- break;
- case ST1H_z_p_br:
- mnemonic = "st1h";
- break;
- case ST1W_z_p_br:
- mnemonic = "st1w";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "{'Zt.'tls}, 'Pgl, ['Xns, 'Xm'NSveS]");
}
void Disassembler::VisitSVECopyFPImm_Predicated(const Instruction *instr) {
@@ -5861,393 +4298,168 @@
void Disassembler::VisitSVEExtractElementToGeneralRegister(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "'Wd, 'Pgl, 'Zn.'t";
-
if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
form = "'Xd, p'u1210, 'Zn.'t";
}
-
- switch (instr->Mask(SVEExtractElementToGeneralRegisterMask)) {
- case LASTA_r_p_z:
- mnemonic = "lasta";
- break;
- case LASTB_r_p_z:
- mnemonic = "lastb";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEExtractElementToSIMDFPScalarRegister(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'t'u0400, 'Pgl, 'Zn.'t";
-
- switch (instr->Mask(SVEExtractElementToSIMDFPScalarRegisterMask)) {
- case LASTA_v_p_z:
- mnemonic = "lasta";
- break;
- case LASTB_v_p_z:
- mnemonic = "lastb";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'t'u0400, 'Pgl, 'Zn.'t");
}
void Disassembler::VisitSVEFFRInitialise(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFFRInitialise)";
-
- switch (instr->Mask(SVEFFRInitialiseMask)) {
- case SETFFR_f:
- mnemonic = "setffr";
- form = " ";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ DisassembleNoArgs(instr);
}
void Disassembler::VisitSVEFFRWriteFromPredicate(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFFRWriteFromPredicate)";
-
- switch (instr->Mask(SVEFFRWriteFromPredicateMask)) {
- case WRFFR_f_p:
- mnemonic = "wrffr";
- form = "'Pn.b";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pn.b");
}
void Disassembler::VisitSVEFPArithmeticWithImm_Predicated(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form00 = "'Zd.'t, 'Pgl/m, 'Zd.'t, #0.0";
- const char *form05 = "'Zd.'t, 'Pgl/m, 'Zd.'t, #0.5";
- const char *form10 = "'Zd.'t, 'Pgl/m, 'Zd.'t, #1.0";
- const char *form20 = "'Zd.'t, 'Pgl/m, 'Zd.'t, #2.0";
+ const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, #";
+ const char *suffix00 = "0.0";
+ const char *suffix05 = "0.5";
+ const char *suffix10 = "1.0";
+ const char *suffix20 = "2.0";
int i1 = instr->ExtractBit(5);
- const char *form = i1 ? form10 : form00;
+ const char *suffix = i1 ? suffix10 : suffix00;
if (instr->GetSVEVectorFormat() == kFormatVnB) {
- form = "(SVEFPArithmeticWithImm_Predicated)";
- } else {
- switch (instr->Mask(SVEFPArithmeticWithImm_PredicatedMask)) {
- case FADD_z_p_zs:
- mnemonic = "fadd";
- form = i1 ? form10 : form05;
- break;
- case FMAXNM_z_p_zs:
- mnemonic = "fmaxnm";
- break;
- case FMAX_z_p_zs:
- mnemonic = "fmax";
- break;
- case FMINNM_z_p_zs:
- mnemonic = "fminnm";
- break;
- case FMIN_z_p_zs:
- mnemonic = "fmin";
- break;
- case FMUL_z_p_zs:
- mnemonic = "fmul";
- form = i1 ? form20 : form05;
- break;
- case FSUBR_z_p_zs:
- mnemonic = "fsubr";
- form = i1 ? form10 : form05;
- break;
- case FSUB_z_p_zs:
- mnemonic = "fsub";
- form = i1 ? form10 : form05;
- break;
- default:
- form = "(SVEFPArithmeticWithImm_Predicated)";
- break;
- }
+ VisitUnallocated(instr);
+ return;
}
- Format(instr, mnemonic, form);
+
+ switch (form_hash_) {
+ case "fadd_z_p_zs"_h:
+ case "fsubr_z_p_zs"_h:
+ case "fsub_z_p_zs"_h:
+ suffix = i1 ? suffix10 : suffix05;
+ break;
+ case "fmul_z_p_zs"_h:
+ suffix = i1 ? suffix20 : suffix05;
+ break;
+ }
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEFPArithmetic_Predicated(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
-
if (instr->GetSVEVectorFormat() == kFormatVnB) {
- form = "(SVEFPArithmetic_Predicated)";
+ VisitUnallocated(instr);
} else {
- switch (instr->Mask(SVEFPArithmetic_PredicatedMask)) {
- case FABD_z_p_zz:
- mnemonic = "fabd";
- break;
- case FADD_z_p_zz:
- mnemonic = "fadd";
- break;
- case FDIVR_z_p_zz:
- mnemonic = "fdivr";
- break;
- case FDIV_z_p_zz:
- mnemonic = "fdiv";
- break;
- case FMAXNM_z_p_zz:
- mnemonic = "fmaxnm";
- break;
- case FMAX_z_p_zz:
- mnemonic = "fmax";
- break;
- case FMINNM_z_p_zz:
- mnemonic = "fminnm";
- break;
- case FMIN_z_p_zz:
- mnemonic = "fmin";
- break;
- case FMULX_z_p_zz:
- mnemonic = "fmulx";
- break;
- case FMUL_z_p_zz:
- mnemonic = "fmul";
- break;
- case FSCALE_z_p_zz:
- mnemonic = "fscale";
- break;
- case FSUBR_z_p_zz:
- mnemonic = "fsubr";
- break;
- case FSUB_z_p_zz:
- mnemonic = "fsub";
- break;
- default:
- break;
- }
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPConvertPrecision(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFPConvertPrecision)";
+ const char *form = NULL;
- switch (instr->Mask(SVEFPConvertPrecisionMask)) {
- case FCVT_z_p_z_d2h:
- mnemonic = "fcvt";
+ switch (form_hash_) {
+ case "fcvt_z_p_z_d2h"_h:
form = "'Zd.h, 'Pgl/m, 'Zn.d";
break;
- case FCVT_z_p_z_d2s:
- mnemonic = "fcvt";
+ case "fcvt_z_p_z_d2s"_h:
form = "'Zd.s, 'Pgl/m, 'Zn.d";
break;
- case FCVT_z_p_z_h2d:
- mnemonic = "fcvt";
+ case "fcvt_z_p_z_h2d"_h:
form = "'Zd.d, 'Pgl/m, 'Zn.h";
break;
- case FCVT_z_p_z_h2s:
- mnemonic = "fcvt";
+ case "fcvt_z_p_z_h2s"_h:
form = "'Zd.s, 'Pgl/m, 'Zn.h";
break;
- case FCVT_z_p_z_s2d:
- mnemonic = "fcvt";
+ case "fcvt_z_p_z_s2d"_h:
form = "'Zd.d, 'Pgl/m, 'Zn.s";
break;
- case FCVT_z_p_z_s2h:
- mnemonic = "fcvt";
+ case "fcvt_z_p_z_s2h"_h:
form = "'Zd.h, 'Pgl/m, 'Zn.s";
break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEFPConvertToInt(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFPConvertToInt)";
+ const char *form = NULL;
- switch (instr->Mask(SVEFPConvertToIntMask)) {
- case FCVTZS_z_p_z_d2w:
- mnemonic = "fcvtzs";
+ switch (form_hash_) {
+ case "fcvtzs_z_p_z_d2w"_h:
+ case "fcvtzu_z_p_z_d2w"_h:
form = "'Zd.s, 'Pgl/m, 'Zn.d";
break;
- case FCVTZS_z_p_z_d2x:
- mnemonic = "fcvtzs";
+ case "fcvtzs_z_p_z_d2x"_h:
+ case "fcvtzu_z_p_z_d2x"_h:
form = "'Zd.d, 'Pgl/m, 'Zn.d";
break;
- case FCVTZS_z_p_z_fp162h:
- mnemonic = "fcvtzs";
+ case "fcvtzs_z_p_z_fp162h"_h:
+ case "fcvtzu_z_p_z_fp162h"_h:
form = "'Zd.h, 'Pgl/m, 'Zn.h";
break;
- case FCVTZS_z_p_z_fp162w:
- mnemonic = "fcvtzs";
+ case "fcvtzs_z_p_z_fp162w"_h:
+ case "fcvtzu_z_p_z_fp162w"_h:
form = "'Zd.s, 'Pgl/m, 'Zn.h";
break;
- case FCVTZS_z_p_z_fp162x:
- mnemonic = "fcvtzs";
+ case "fcvtzs_z_p_z_fp162x"_h:
+ case "fcvtzu_z_p_z_fp162x"_h:
form = "'Zd.d, 'Pgl/m, 'Zn.h";
break;
- case FCVTZS_z_p_z_s2w:
- mnemonic = "fcvtzs";
+ case "fcvtzs_z_p_z_s2w"_h:
+ case "fcvtzu_z_p_z_s2w"_h:
form = "'Zd.s, 'Pgl/m, 'Zn.s";
break;
- case FCVTZS_z_p_z_s2x:
- mnemonic = "fcvtzs";
+ case "fcvtzs_z_p_z_s2x"_h:
+ case "fcvtzu_z_p_z_s2x"_h:
form = "'Zd.d, 'Pgl/m, 'Zn.s";
break;
- case FCVTZU_z_p_z_d2w:
- mnemonic = "fcvtzu";
- form = "'Zd.s, 'Pgl/m, 'Zn.d";
- break;
- case FCVTZU_z_p_z_d2x:
- mnemonic = "fcvtzu";
- form = "'Zd.d, 'Pgl/m, 'Zn.d";
- break;
- case FCVTZU_z_p_z_fp162h:
- mnemonic = "fcvtzu";
- form = "'Zd.h, 'Pgl/m, 'Zn.h";
- break;
- case FCVTZU_z_p_z_fp162w:
- mnemonic = "fcvtzu";
- form = "'Zd.s, 'Pgl/m, 'Zn.h";
- break;
- case FCVTZU_z_p_z_fp162x:
- mnemonic = "fcvtzu";
- form = "'Zd.d, 'Pgl/m, 'Zn.h";
- break;
- case FCVTZU_z_p_z_s2w:
- mnemonic = "fcvtzu";
- form = "'Zd.s, 'Pgl/m, 'Zn.s";
- break;
- case FCVTZU_z_p_z_s2x:
- mnemonic = "fcvtzu";
- form = "'Zd.d, 'Pgl/m, 'Zn.s";
- break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEFPExponentialAccelerator(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFPExponentialAccelerator)";
-
unsigned size = instr->GetSVESize();
- switch (instr->Mask(SVEFPExponentialAcceleratorMask)) {
- case FEXPA_z_z:
- if ((size == kHRegSizeInBytesLog2) || (size == kSRegSizeInBytesLog2) ||
- (size == kDRegSizeInBytesLog2)) {
- mnemonic = "fexpa";
- form = "'Zd.'t, 'Zn.'t";
- }
- break;
- default:
- break;
+ if ((size == kHRegSizeInBytesLog2) || (size == kSRegSizeInBytesLog2) ||
+ (size == kDRegSizeInBytesLog2)) {
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t");
+ } else {
+ VisitUnallocated(instr);
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPRoundToIntegralValue(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl/m, 'Zn.'t";
-
if (instr->GetSVEVectorFormat() == kFormatVnB) {
- form = "(SVEFPRoundToIntegralValue)";
+ VisitUnallocated(instr);
} else {
- switch (instr->Mask(SVEFPRoundToIntegralValueMask)) {
- case FRINTA_z_p_z:
- mnemonic = "frinta";
- break;
- case FRINTI_z_p_z:
- mnemonic = "frinti";
- break;
- case FRINTM_z_p_z:
- mnemonic = "frintm";
- break;
- case FRINTN_z_p_z:
- mnemonic = "frintn";
- break;
- case FRINTP_z_p_z:
- mnemonic = "frintp";
- break;
- case FRINTX_z_p_z:
- mnemonic = "frintx";
- break;
- case FRINTZ_z_p_z:
- mnemonic = "frintz";
- break;
- default:
- break;
- }
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zn.'t");
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPTrigMulAddCoefficient(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFPTrigMulAddCoefficient)";
-
unsigned size = instr->GetSVESize();
- switch (instr->Mask(SVEFPTrigMulAddCoefficientMask)) {
- case FTMAD_z_zzi:
- if ((size == kHRegSizeInBytesLog2) || (size == kSRegSizeInBytesLog2) ||
- (size == kDRegSizeInBytesLog2)) {
- mnemonic = "ftmad";
- form = "'Zd.'t, 'Zd.'t, 'Zn.'t, #'u1816";
- }
- break;
- default:
- break;
+ if ((size == kHRegSizeInBytesLog2) || (size == kSRegSizeInBytesLog2) ||
+ (size == kDRegSizeInBytesLog2)) {
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zd.'t, 'Zn.'t, #'u1816");
+ } else {
+ VisitUnallocated(instr);
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPTrigSelectCoefficient(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFPTrigSelectCoefficient)";
-
unsigned size = instr->GetSVESize();
- switch (instr->Mask(SVEFPTrigSelectCoefficientMask)) {
- case FTSSEL_z_zz:
- if ((size == kHRegSizeInBytesLog2) || (size == kSRegSizeInBytesLog2) ||
- (size == kDRegSizeInBytesLog2)) {
- mnemonic = "ftssel";
- form = "'Zd.'t, 'Zn.'t, 'Zm.'t";
- }
- break;
- default:
- break;
+ if ((size == kHRegSizeInBytesLog2) || (size == kSRegSizeInBytesLog2) ||
+ (size == kDRegSizeInBytesLog2)) {
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t, 'Zm.'t");
+ } else {
+ VisitUnallocated(instr);
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPUnaryOp(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl/m, 'Zn.'t";
-
if (instr->GetSVESize() == kBRegSizeInBytesLog2) {
- form = "(SVEFPUnaryOp)";
+ VisitUnallocated(instr);
} else {
- switch (instr->Mask(SVEFPUnaryOpMask)) {
- case FRECPX_z_p_z:
- mnemonic = "frecpx";
- break;
- case FSQRT_z_p_z:
- mnemonic = "fsqrt";
- break;
- default:
- form = "(SVEFPUnaryOp)";
- break;
- }
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zn.'t");
}
- Format(instr, mnemonic, form);
}
static const char *IncDecFormHelper(const Instruction *instr,
@@ -6268,381 +4480,125 @@
void Disassembler::VisitSVEIncDecRegisterByElementCount(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form =
IncDecFormHelper(instr, "'Xd, 'Ipc, mul #'u1916+1", "'Xd, 'Ipc", "'Xd");
-
- switch (instr->Mask(SVEIncDecRegisterByElementCountMask)) {
- case DECB_r_rs:
- mnemonic = "decb";
- break;
- case DECD_r_rs:
- mnemonic = "decd";
- break;
- case DECH_r_rs:
- mnemonic = "dech";
- break;
- case DECW_r_rs:
- mnemonic = "decw";
- break;
- case INCB_r_rs:
- mnemonic = "incb";
- break;
- case INCD_r_rs:
- mnemonic = "incd";
- break;
- case INCH_r_rs:
- mnemonic = "inch";
- break;
- case INCW_r_rs:
- mnemonic = "incw";
- break;
- default:
- form = "(SVEIncDecRegisterByElementCount)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEIncDecVectorByElementCount(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = IncDecFormHelper(instr,
"'Zd.'t, 'Ipc, mul #'u1916+1",
"'Zd.'t, 'Ipc",
"'Zd.'t");
-
- switch (instr->Mask(SVEIncDecVectorByElementCountMask)) {
- case DECD_z_zs:
- mnemonic = "decd";
- break;
- case DECH_z_zs:
- mnemonic = "dech";
- break;
- case DECW_z_zs:
- mnemonic = "decw";
- break;
- case INCD_z_zs:
- mnemonic = "incd";
- break;
- case INCH_z_zs:
- mnemonic = "inch";
- break;
- case INCW_z_zs:
- mnemonic = "incw";
- break;
- default:
- form = "(SVEIncDecVectorByElementCount)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEInsertGeneralRegister(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEInsertGeneralRegister)";
-
- switch (instr->Mask(SVEInsertGeneralRegisterMask)) {
- case INSR_z_r:
- mnemonic = "insr";
- if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
- form = "'Zd.'t, 'Xn";
- } else {
- form = "'Zd.'t, 'Wn";
- }
- break;
- default:
- break;
+ const char *form = "'Zd.'t, 'Wn";
+ if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
+ form = "'Zd.'t, 'Xn";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEInsertSIMDFPScalarRegister(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEInsertSIMDFPScalarRegister)";
-
- switch (instr->Mask(SVEInsertSIMDFPScalarRegisterMask)) {
- case INSR_z_v:
- mnemonic = "insr";
- form = "'Zd.'t, 'Vnv";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Vnv");
}
void Disassembler::VisitSVEIntAddSubtractImm_Unpredicated(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = (instr->ExtractBit(13) == 0)
? "'Zd.'t, 'Zd.'t, #'u1205"
: "'Zd.'t, 'Zd.'t, #'u1205, lsl #8";
-
- switch (instr->Mask(SVEIntAddSubtractImm_UnpredicatedMask)) {
- case ADD_z_zi:
- mnemonic = "add";
- break;
- case SQADD_z_zi:
- mnemonic = "sqadd";
- break;
- case SQSUB_z_zi:
- mnemonic = "sqsub";
- break;
- case SUBR_z_zi:
- mnemonic = "subr";
- break;
- case SUB_z_zi:
- mnemonic = "sub";
- break;
- case UQADD_z_zi:
- mnemonic = "uqadd";
- break;
- case UQSUB_z_zi:
- mnemonic = "uqsub";
- break;
- default:
- form = "(SVEIntAddSubtractImm_Unpredicated)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEIntAddSubtractVectors_Predicated(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
-
- switch (instr->Mask(SVEIntAddSubtractVectors_PredicatedMask)) {
- case ADD_z_p_zz:
- mnemonic = "add";
- break;
- case SUBR_z_p_zz:
- mnemonic = "subr";
- break;
- case SUB_z_p_zz:
- mnemonic = "sub";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
}
void Disassembler::VisitSVEIntCompareScalarCountAndLimit(
const Instruction *instr) {
const char *form =
(instr->ExtractBit(12) == 0) ? "'Pd.'t, 'Wn, 'Wm" : "'Pd.'t, 'Xn, 'Xm";
- Format(instr, mnemonic_.c_str(), form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEIntConvertToFP(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEIntConvertToFP)";
-
- switch (instr->Mask(SVEIntConvertToFPMask)) {
- case SCVTF_z_p_z_h2fp16:
- mnemonic = "scvtf";
+ const char *form = NULL;
+ switch (form_hash_) {
+ case "scvtf_z_p_z_h2fp16"_h:
+ case "ucvtf_z_p_z_h2fp16"_h:
form = "'Zd.h, 'Pgl/m, 'Zn.h";
break;
- case SCVTF_z_p_z_w2d:
- mnemonic = "scvtf";
+ case "scvtf_z_p_z_w2d"_h:
+ case "ucvtf_z_p_z_w2d"_h:
form = "'Zd.d, 'Pgl/m, 'Zn.s";
break;
- case SCVTF_z_p_z_w2fp16:
- mnemonic = "scvtf";
+ case "scvtf_z_p_z_w2fp16"_h:
+ case "ucvtf_z_p_z_w2fp16"_h:
form = "'Zd.h, 'Pgl/m, 'Zn.s";
break;
- case SCVTF_z_p_z_w2s:
- mnemonic = "scvtf";
+ case "scvtf_z_p_z_w2s"_h:
+ case "ucvtf_z_p_z_w2s"_h:
form = "'Zd.s, 'Pgl/m, 'Zn.s";
break;
- case SCVTF_z_p_z_x2d:
- mnemonic = "scvtf";
+ case "scvtf_z_p_z_x2d"_h:
+ case "ucvtf_z_p_z_x2d"_h:
form = "'Zd.d, 'Pgl/m, 'Zn.d";
break;
- case SCVTF_z_p_z_x2fp16:
- mnemonic = "scvtf";
+ case "scvtf_z_p_z_x2fp16"_h:
+ case "ucvtf_z_p_z_x2fp16"_h:
form = "'Zd.h, 'Pgl/m, 'Zn.d";
break;
- case SCVTF_z_p_z_x2s:
- mnemonic = "scvtf";
+ case "scvtf_z_p_z_x2s"_h:
+ case "ucvtf_z_p_z_x2s"_h:
form = "'Zd.s, 'Pgl/m, 'Zn.d";
break;
- case UCVTF_z_p_z_h2fp16:
- mnemonic = "ucvtf";
- form = "'Zd.h, 'Pgl/m, 'Zn.h";
- break;
- case UCVTF_z_p_z_w2d:
- mnemonic = "ucvtf";
- form = "'Zd.d, 'Pgl/m, 'Zn.s";
- break;
- case UCVTF_z_p_z_w2fp16:
- mnemonic = "ucvtf";
- form = "'Zd.h, 'Pgl/m, 'Zn.s";
- break;
- case UCVTF_z_p_z_w2s:
- mnemonic = "ucvtf";
- form = "'Zd.s, 'Pgl/m, 'Zn.s";
- break;
- case UCVTF_z_p_z_x2d:
- mnemonic = "ucvtf";
- form = "'Zd.d, 'Pgl/m, 'Zn.d";
- break;
- case UCVTF_z_p_z_x2fp16:
- mnemonic = "ucvtf";
- form = "'Zd.h, 'Pgl/m, 'Zn.d";
- break;
- case UCVTF_z_p_z_x2s:
- mnemonic = "ucvtf";
- form = "'Zd.s, 'Pgl/m, 'Zn.d";
- break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEIntDivideVectors_Predicated(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
-
- switch (instr->Mask(SVEIntDivideVectors_PredicatedMask)) {
- case SDIVR_z_p_zz:
- mnemonic = "sdivr";
- break;
- case SDIV_z_p_zz:
- mnemonic = "sdiv";
- break;
- case UDIVR_z_p_zz:
- mnemonic = "udivr";
- break;
- case UDIV_z_p_zz:
- mnemonic = "udiv";
- break;
- default:
- break;
+ unsigned size = instr->GetSVESize();
+ if ((size == kSRegSizeInBytesLog2) || (size == kDRegSizeInBytesLog2)) {
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
+ } else {
+ VisitUnallocated(instr);
}
-
- switch (instr->Mask(SVEIntDivideVectors_PredicatedMask)) {
- case SDIVR_z_p_zz:
- case SDIV_z_p_zz:
- case UDIVR_z_p_zz:
- case UDIV_z_p_zz:
- switch (instr->GetSVESize()) {
- case kBRegSizeInBytesLog2:
- case kHRegSizeInBytesLog2:
- mnemonic = "unimplemented";
- form = "(SVEIntBinaryArithmeticPredicated)";
- break;
- case kSRegSizeInBytesLog2:
- case kDRegSizeInBytesLog2:
- // The default form works for these instructions.
- break;
- default:
- // GetSVESize() should never return other values.
- VIXL_UNREACHABLE();
- break;
- }
- }
-
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEIntMinMaxDifference_Predicated(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
-
- switch (instr->Mask(SVEIntMinMaxDifference_PredicatedMask)) {
- case SABD_z_p_zz:
- mnemonic = "sabd";
- break;
- case SMAX_z_p_zz:
- mnemonic = "smax";
- break;
- case SMIN_z_p_zz:
- mnemonic = "smin";
- break;
- case UABD_z_p_zz:
- mnemonic = "uabd";
- break;
- case UMAX_z_p_zz:
- mnemonic = "umax";
- break;
- case UMIN_z_p_zz:
- mnemonic = "umin";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
}
void Disassembler::VisitSVEIntMinMaxImm_Unpredicated(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Zd.'t, #'u1205";
+ const char *form = "'Zd.'t, 'Zd.'t, #";
+ const char *suffix = "'u1205";
- switch (instr->Mask(SVEIntMinMaxImm_UnpredicatedMask)) {
- case SMAX_z_zi:
- mnemonic = "smax";
- form = "'Zd.'t, 'Zd.'t, #'s1205";
- break;
- case SMIN_z_zi:
- mnemonic = "smin";
- form = "'Zd.'t, 'Zd.'t, #'s1205";
- break;
- case UMAX_z_zi:
- mnemonic = "umax";
- break;
- case UMIN_z_zi:
- mnemonic = "umin";
- break;
- default:
+ switch (form_hash_) {
+ case "smax_z_zi"_h:
+ case "smin_z_zi"_h:
+ suffix = "'s1205";
break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEIntMulImm_Unpredicated(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEIntMulImm_Unpredicated)";
-
- switch (instr->Mask(SVEIntMulImm_UnpredicatedMask)) {
- case MUL_z_zi:
- mnemonic = "mul";
- form = "'Zd.'t, 'Zd.'t, #'s1205";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zd.'t, #'s1205");
}
void Disassembler::VisitSVEIntMulVectors_Predicated(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
-
- switch (instr->Mask(SVEIntMulVectors_PredicatedMask)) {
- case MUL_z_p_zz:
- mnemonic = "mul";
- break;
- case SMULH_z_p_zz:
- mnemonic = "smulh";
- break;
- case UMULH_z_p_zz:
- mnemonic = "umulh";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t");
}
void Disassembler::VisitSVELoadAndBroadcastElement(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "(SVELoadAndBroadcastElement)";
const char *suffix_b = ", #'u2116]";
const char *suffix_h = ", #'u2116*2]";
@@ -6650,89 +4606,53 @@
const char *suffix_d = ", #'u2116*8]";
const char *suffix = NULL;
- switch (instr->Mask(SVELoadAndBroadcastElementMask)) {
- case LD1RB_z_p_bi_u16:
- mnemonic = "ld1rb";
- form = "{'Zt.h}, 'Pgl/z, ['Xns";
- suffix = suffix_b;
- break;
- case LD1RB_z_p_bi_u32:
- mnemonic = "ld1rb";
- form = "{'Zt.s}, 'Pgl/z, ['Xns";
- suffix = suffix_b;
- break;
- case LD1RB_z_p_bi_u64:
- mnemonic = "ld1rb";
- form = "{'Zt.d}, 'Pgl/z, ['Xns";
- suffix = suffix_b;
- break;
- case LD1RB_z_p_bi_u8:
- mnemonic = "ld1rb";
+ switch (form_hash_) {
+ case "ld1rb_z_p_bi_u8"_h:
form = "{'Zt.b}, 'Pgl/z, ['Xns";
suffix = suffix_b;
break;
- case LD1RD_z_p_bi_u64:
- mnemonic = "ld1rd";
+ case "ld1rb_z_p_bi_u16"_h:
+ case "ld1rsb_z_p_bi_s16"_h:
+ form = "{'Zt.h}, 'Pgl/z, ['Xns";
+ suffix = suffix_b;
+ break;
+ case "ld1rb_z_p_bi_u32"_h:
+ case "ld1rsb_z_p_bi_s32"_h:
+ form = "{'Zt.s}, 'Pgl/z, ['Xns";
+ suffix = suffix_b;
+ break;
+ case "ld1rb_z_p_bi_u64"_h:
+ case "ld1rsb_z_p_bi_s64"_h:
+ form = "{'Zt.d}, 'Pgl/z, ['Xns";
+ suffix = suffix_b;
+ break;
+ case "ld1rh_z_p_bi_u16"_h:
+ form = "{'Zt.h}, 'Pgl/z, ['Xns";
+ suffix = suffix_h;
+ break;
+ case "ld1rh_z_p_bi_u32"_h:
+ case "ld1rsh_z_p_bi_s32"_h:
+ form = "{'Zt.s}, 'Pgl/z, ['Xns";
+ suffix = suffix_h;
+ break;
+ case "ld1rh_z_p_bi_u64"_h:
+ case "ld1rsh_z_p_bi_s64"_h:
+ form = "{'Zt.d}, 'Pgl/z, ['Xns";
+ suffix = suffix_h;
+ break;
+ case "ld1rw_z_p_bi_u32"_h:
+ form = "{'Zt.s}, 'Pgl/z, ['Xns";
+ suffix = suffix_w;
+ break;
+ case "ld1rsw_z_p_bi_s64"_h:
+ case "ld1rw_z_p_bi_u64"_h:
+ form = "{'Zt.d}, 'Pgl/z, ['Xns";
+ suffix = suffix_w;
+ break;
+ case "ld1rd_z_p_bi_u64"_h:
form = "{'Zt.d}, 'Pgl/z, ['Xns";
suffix = suffix_d;
break;
- case LD1RH_z_p_bi_u16:
- mnemonic = "ld1rh";
- form = "{'Zt.h}, 'Pgl/z, ['Xns";
- suffix = suffix_h;
- break;
- case LD1RH_z_p_bi_u32:
- mnemonic = "ld1rh";
- form = "{'Zt.s}, 'Pgl/z, ['Xns";
- suffix = suffix_h;
- break;
- case LD1RH_z_p_bi_u64:
- mnemonic = "ld1rh";
- form = "{'Zt.d}, 'Pgl/z, ['Xns";
- suffix = suffix_h;
- break;
- case LD1RSB_z_p_bi_s16:
- mnemonic = "ld1rsb";
- form = "{'Zt.h}, 'Pgl/z, ['Xns";
- suffix = suffix_b;
- break;
- case LD1RSB_z_p_bi_s32:
- mnemonic = "ld1rsb";
- form = "{'Zt.s}, 'Pgl/z, ['Xns";
- suffix = suffix_b;
- break;
- case LD1RSB_z_p_bi_s64:
- mnemonic = "ld1rsb";
- form = "{'Zt.d}, 'Pgl/z, ['Xns";
- suffix = suffix_b;
- break;
- case LD1RSH_z_p_bi_s32:
- mnemonic = "ld1rsh";
- form = "{'Zt.s}, 'Pgl/z, ['Xns";
- suffix = suffix_h;
- break;
- case LD1RSH_z_p_bi_s64:
- mnemonic = "ld1rsh";
- form = "{'Zt.d}, 'Pgl/z, ['Xns";
- suffix = suffix_h;
- break;
- case LD1RSW_z_p_bi_s64:
- mnemonic = "ld1rsw";
- form = "{'Zt.d}, 'Pgl/z, ['Xns";
- suffix = suffix_w;
- break;
- case LD1RW_z_p_bi_u32:
- mnemonic = "ld1rw";
- form = "{'Zt.s}, 'Pgl/z, ['Xns";
- suffix = suffix_w;
- break;
- case LD1RW_z_p_bi_u64:
- mnemonic = "ld1rw";
- form = "{'Zt.d}, 'Pgl/z, ['Xns";
- suffix = suffix_w;
- break;
- default:
- break;
}
// Hide curly brackets if immediate is zero.
@@ -6740,395 +4660,141 @@
suffix = "]";
}
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm(
const Instruction *instr) {
- const char *mnemonic = mnemonic_.c_str();
const char *form = "{'Zt.'tmsz}, 'Pgl/z, ['Xns";
const char *suffix = ", #'s1916*16]";
switch (form_hash_) {
- case Hash("ld1rqb_z_p_bi_u8"):
- case Hash("ld1rqd_z_p_bi_u64"):
- case Hash("ld1rqh_z_p_bi_u16"):
- case Hash("ld1rqw_z_p_bi_u32"):
- // Nothing to do.
- break;
- case Hash("ld1rob_z_p_bi_u8"):
- case Hash("ld1rod_z_p_bi_u64"):
- case Hash("ld1roh_z_p_bi_u16"):
- case Hash("ld1row_z_p_bi_u32"):
+ case "ld1rob_z_p_bi_u8"_h:
+ case "ld1rod_z_p_bi_u64"_h:
+ case "ld1roh_z_p_bi_u16"_h:
+ case "ld1row_z_p_bi_u32"_h:
suffix = ", #'s1916*32]";
break;
- default:
- VIXL_UNREACHABLE();
- break;
}
if (instr->ExtractBits(19, 16) == 0) suffix = "]";
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar(
const Instruction *instr) {
- const char *mnemonic = mnemonic_.c_str();
const char *form = "{'Zt.'tmsz}, 'Pgl/z, ['Xns, ";
const char *suffix = "'Rm, lsl #'u2423]";
switch (form_hash_) {
- case Hash("ld1rqb_z_p_br_contiguous"):
- case Hash("ld1rob_z_p_br_contiguous"):
+ case "ld1rqb_z_p_br_contiguous"_h:
+ case "ld1rob_z_p_br_contiguous"_h:
suffix = "'Rm]";
break;
- case Hash("ld1rqd_z_p_br_contiguous"):
- case Hash("ld1rod_z_p_br_contiguous"):
- case Hash("ld1rqh_z_p_br_contiguous"):
- case Hash("ld1roh_z_p_br_contiguous"):
- case Hash("ld1rqw_z_p_br_contiguous"):
- case Hash("ld1row_z_p_br_contiguous"):
- // Nothing to do.
- break;
- default:
- VIXL_UNREACHABLE();
- break;
}
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVELoadMultipleStructures_ScalarPlusImm(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVELoadMultipleStructures_ScalarPlusImm)";
+ const char *form = "{'Zt.'tmsz, 'Zt2.'tmsz}";
+ const char *form_3 = "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}";
+ const char *form_4 = "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}";
+ const char *suffix = ", 'Pgl/z, ['Xns'ISveSvl]";
- const char *form_2 = "{'Zt.'tmsz, 'Zt2.'tmsz}, 'Pgl/z, ['Xns'ISveSvl]";
- const char *form_3 =
- "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}, 'Pgl/z, ['Xns'ISveSvl]";
- const char *form_4 =
- "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}, "
- "'Pgl/z, ['Xns'ISveSvl]";
-
- switch (instr->Mask(SVELoadMultipleStructures_ScalarPlusImmMask)) {
- case LD2B_z_p_bi_contiguous:
- mnemonic = "ld2b";
- form = form_2;
- break;
- case LD2D_z_p_bi_contiguous:
- mnemonic = "ld2d";
- form = form_2;
- break;
- case LD2H_z_p_bi_contiguous:
- mnemonic = "ld2h";
- form = form_2;
- break;
- case LD2W_z_p_bi_contiguous:
- mnemonic = "ld2w";
- form = form_2;
- break;
- case LD3B_z_p_bi_contiguous:
- mnemonic = "ld3b";
+ switch (form_hash_) {
+ case "ld3b_z_p_bi_contiguous"_h:
+ case "ld3d_z_p_bi_contiguous"_h:
+ case "ld3h_z_p_bi_contiguous"_h:
+ case "ld3w_z_p_bi_contiguous"_h:
form = form_3;
break;
- case LD3D_z_p_bi_contiguous:
- mnemonic = "ld3d";
- form = form_3;
- break;
- case LD3H_z_p_bi_contiguous:
- mnemonic = "ld3h";
- form = form_3;
- break;
- case LD3W_z_p_bi_contiguous:
- mnemonic = "ld3w";
- form = form_3;
- break;
- case LD4B_z_p_bi_contiguous:
- mnemonic = "ld4b";
+ case "ld4b_z_p_bi_contiguous"_h:
+ case "ld4d_z_p_bi_contiguous"_h:
+ case "ld4h_z_p_bi_contiguous"_h:
+ case "ld4w_z_p_bi_contiguous"_h:
form = form_4;
break;
- case LD4D_z_p_bi_contiguous:
- mnemonic = "ld4d";
- form = form_4;
- break;
- case LD4H_z_p_bi_contiguous:
- mnemonic = "ld4h";
- form = form_4;
- break;
- case LD4W_z_p_bi_contiguous:
- mnemonic = "ld4w";
- form = form_4;
- break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVELoadMultipleStructures_ScalarPlusScalar(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVELoadMultipleStructures_ScalarPlusScalar)";
+ const char *form = "{'Zt.'tmsz, 'Zt2.'tmsz}";
+ const char *form_3 = "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}";
+ const char *form_4 = "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}";
+ const char *suffix = ", 'Pgl/z, ['Xns, 'Xm'NSveS]";
- const char *form_2 = "{'Zt.'tmsz, 'Zt2.'tmsz}, 'Pgl/z, ['Xns, 'Xm'NSveS]";
- const char *form_3 =
- "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}, 'Pgl/z, ['Xns, 'Xm'NSveS]";
- const char *form_4 =
- "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}, "
- "'Pgl/z, ['Xns, 'Xm'NSveS]";
-
- switch (instr->Mask(SVELoadMultipleStructures_ScalarPlusScalarMask)) {
- case LD2B_z_p_br_contiguous:
- mnemonic = "ld2b";
- form = form_2;
- break;
- case LD2D_z_p_br_contiguous:
- mnemonic = "ld2d";
- form = form_2;
- break;
- case LD2H_z_p_br_contiguous:
- mnemonic = "ld2h";
- form = form_2;
- break;
- case LD2W_z_p_br_contiguous:
- mnemonic = "ld2w";
- form = form_2;
- break;
- case LD3B_z_p_br_contiguous:
- mnemonic = "ld3b";
+ switch (form_hash_) {
+ case "ld3b_z_p_br_contiguous"_h:
+ case "ld3d_z_p_br_contiguous"_h:
+ case "ld3h_z_p_br_contiguous"_h:
+ case "ld3w_z_p_br_contiguous"_h:
form = form_3;
break;
- case LD3D_z_p_br_contiguous:
- mnemonic = "ld3d";
- form = form_3;
- break;
- case LD3H_z_p_br_contiguous:
- mnemonic = "ld3h";
- form = form_3;
- break;
- case LD3W_z_p_br_contiguous:
- mnemonic = "ld3w";
- form = form_3;
- break;
- case LD4B_z_p_br_contiguous:
- mnemonic = "ld4b";
+ case "ld4b_z_p_br_contiguous"_h:
+ case "ld4d_z_p_br_contiguous"_h:
+ case "ld4h_z_p_br_contiguous"_h:
+ case "ld4w_z_p_br_contiguous"_h:
form = form_4;
break;
- case LD4D_z_p_br_contiguous:
- mnemonic = "ld4d";
- form = form_4;
- break;
- case LD4H_z_p_br_contiguous:
- mnemonic = "ld4h";
- form = form_4;
- break;
- case LD4W_z_p_br_contiguous:
- mnemonic = "ld4w";
- form = form_4;
- break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVELoadPredicateRegister(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVELoadPredicateRegister)";
-
- switch (instr->Mask(SVELoadPredicateRegisterMask)) {
- case LDR_p_bi:
- mnemonic = "ldr";
- if (instr->Mask(0x003f1c00) == 0) {
- form = "'Pd, ['Xns]";
- } else {
- form = "'Pd, ['Xns, #'s2116:1210, mul vl]";
- }
- break;
- default:
- break;
+ const char *form = "'Pd, ['Xns, #'s2116:1210, mul vl]";
+ if (instr->Mask(0x003f1c00) == 0) {
+ form = "'Pd, ['Xns]";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVELoadVectorRegister(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVELoadVectorRegister)";
-
- switch (instr->Mask(SVELoadVectorRegisterMask)) {
- case LDR_z_bi:
- mnemonic = "ldr";
- if (instr->Mask(0x003f1c00) == 0) {
- form = "'Zd, ['Xns]";
- } else {
- form = "'Zt, ['Xns, #'s2116:1210, mul vl]";
- }
- break;
- default:
- break;
+ const char *form = "'Zt, ['Xns, #'s2116:1210, mul vl]";
+ if (instr->Mask(0x003f1c00) == 0) {
+ form = "'Zd, ['Xns]";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEPartitionBreakCondition(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Pd.b, p'u1310/'?04:mz, 'Pn.b";
-
- switch (instr->Mask(SVEPartitionBreakConditionMask)) {
- case BRKAS_p_p_p_z:
- mnemonic = "brkas";
- break;
- case BRKA_p_p_p:
- mnemonic = "brka";
- break;
- case BRKBS_p_p_p_z:
- mnemonic = "brkbs";
- break;
- case BRKB_p_p_p:
- mnemonic = "brkb";
- break;
- default:
- form = "(SVEPartitionBreakCondition)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.b, p'u1310/'?04:mz, 'Pn.b");
}
void Disassembler::VisitSVEPermutePredicateElements(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Pd.'t, 'Pn.'t, 'Pm.'t";
-
- switch (instr->Mask(SVEPermutePredicateElementsMask)) {
- case TRN1_p_pp:
- mnemonic = "trn1";
- break;
- case TRN2_p_pp:
- mnemonic = "trn2";
- break;
- case UZP1_p_pp:
- mnemonic = "uzp1";
- break;
- case UZP2_p_pp:
- mnemonic = "uzp2";
- break;
- case ZIP1_p_pp:
- mnemonic = "zip1";
- break;
- case ZIP2_p_pp:
- mnemonic = "zip2";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pn.'t, 'Pm.'t");
}
void Disassembler::VisitSVEPredicateFirstActive(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEPredicateFirstActive)";
-
- switch (instr->Mask(SVEPredicateFirstActiveMask)) {
- case PFIRST_p_p_p:
- mnemonic = "pfirst";
- form = "'Pd.b, 'Pn, 'Pd.b";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.b, 'Pn, 'Pd.b");
}
void Disassembler::VisitSVEPredicateReadFromFFR_Unpredicated(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEPredicateReadFromFFR_Unpredicated)";
-
- switch (instr->Mask(SVEPredicateReadFromFFR_UnpredicatedMask)) {
- case RDFFR_p_f:
- mnemonic = "rdffr";
- form = "'Pd.b";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.b");
}
void Disassembler::VisitSVEPredicateTest(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEPredicateTest)";
-
- switch (instr->Mask(SVEPredicateTestMask)) {
- case PTEST_p_p:
- mnemonic = "ptest";
- form = "p'u1310, 'Pn.b";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "p'u1310, 'Pn.b");
}
void Disassembler::VisitSVEPredicateZero(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEPredicateZero)";
-
- switch (instr->Mask(SVEPredicateZeroMask)) {
- case PFALSE_p:
- mnemonic = "pfalse";
- form = "'Pd.b";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.b");
}
void Disassembler::VisitSVEPropagateBreakToNextPartition(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Pd.b, p'u1310/z, 'Pn.b, 'Pd.b";
-
- switch (instr->Mask(SVEPropagateBreakToNextPartitionMask)) {
- case BRKNS_p_p_pp:
- mnemonic = "brkns";
- break;
- case BRKN_p_p_pp:
- mnemonic = "brkn";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.b, p'u1310/z, 'Pn.b, 'Pd.b");
}
void Disassembler::VisitSVEReversePredicateElements(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEReversePredicateElements)";
-
- switch (instr->Mask(SVEReversePredicateElementsMask)) {
- case REV_p_p:
- mnemonic = "rev";
- form = "'Pd.'t, 'Pn.'t";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pn.'t");
}
void Disassembler::VisitSVEReverseVectorElements(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEReverseVectorElements)";
-
- switch (instr->Mask(SVEReverseVectorElementsMask)) {
- case REV_z_z:
- mnemonic = "rev";
- form = "'Zd.'t, 'Zn.'t";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t");
}
void Disassembler::VisitSVEReverseWithinElements(const Instruction *instr) {
@@ -7170,7 +4836,6 @@
void Disassembler::VisitSVESaturatingIncDecRegisterByElementCount(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = IncDecFormHelper(instr,
"'R20d, 'Ipc, mul #'u1916+1",
"'R20d, 'Ipc",
@@ -7180,399 +4845,113 @@
"'Xd, 'Wd, 'Ipc",
"'Xd, 'Wd");
- switch (instr->Mask(SVESaturatingIncDecRegisterByElementCountMask)) {
- case SQDECB_r_rs_sx:
- mnemonic = "sqdecb";
+ switch (form_hash_) {
+ case "sqdecb_r_rs_sx"_h:
+ case "sqdecd_r_rs_sx"_h:
+ case "sqdech_r_rs_sx"_h:
+ case "sqdecw_r_rs_sx"_h:
+ case "sqincb_r_rs_sx"_h:
+ case "sqincd_r_rs_sx"_h:
+ case "sqinch_r_rs_sx"_h:
+ case "sqincw_r_rs_sx"_h:
form = form_sx;
break;
- case SQDECD_r_rs_sx:
- mnemonic = "sqdecd";
- form = form_sx;
- break;
- case SQDECH_r_rs_sx:
- mnemonic = "sqdech";
- form = form_sx;
- break;
- case SQDECW_r_rs_sx:
- mnemonic = "sqdecw";
- form = form_sx;
- break;
- case SQINCB_r_rs_sx:
- mnemonic = "sqincb";
- form = form_sx;
- break;
- case SQINCD_r_rs_sx:
- mnemonic = "sqincd";
- form = form_sx;
- break;
- case SQINCH_r_rs_sx:
- mnemonic = "sqinch";
- form = form_sx;
- break;
- case SQINCW_r_rs_sx:
- mnemonic = "sqincw";
- form = form_sx;
- break;
- case SQDECB_r_rs_x:
- mnemonic = "sqdecb";
- break;
- case SQDECD_r_rs_x:
- mnemonic = "sqdecd";
- break;
- case SQDECH_r_rs_x:
- mnemonic = "sqdech";
- break;
- case SQDECW_r_rs_x:
- mnemonic = "sqdecw";
- break;
- case SQINCB_r_rs_x:
- mnemonic = "sqincb";
- break;
- case SQINCD_r_rs_x:
- mnemonic = "sqincd";
- break;
- case SQINCH_r_rs_x:
- mnemonic = "sqinch";
- break;
- case SQINCW_r_rs_x:
- mnemonic = "sqincw";
- break;
- case UQDECB_r_rs_uw:
- case UQDECB_r_rs_x:
- mnemonic = "uqdecb";
- break;
- case UQDECD_r_rs_uw:
- case UQDECD_r_rs_x:
- mnemonic = "uqdecd";
- break;
- case UQDECH_r_rs_uw:
- case UQDECH_r_rs_x:
- mnemonic = "uqdech";
- break;
- case UQDECW_r_rs_uw:
- case UQDECW_r_rs_x:
- mnemonic = "uqdecw";
- break;
- case UQINCB_r_rs_uw:
- case UQINCB_r_rs_x:
- mnemonic = "uqincb";
- break;
- case UQINCD_r_rs_uw:
- case UQINCD_r_rs_x:
- mnemonic = "uqincd";
- break;
- case UQINCH_r_rs_uw:
- case UQINCH_r_rs_x:
- mnemonic = "uqinch";
- break;
- case UQINCW_r_rs_uw:
- case UQINCW_r_rs_x:
- mnemonic = "uqincw";
- break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVESaturatingIncDecVectorByElementCount(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = IncDecFormHelper(instr,
"'Zd.'t, 'Ipc, mul #'u1916+1",
"'Zd.'t, 'Ipc",
"'Zd.'t");
-
- switch (instr->Mask(SVESaturatingIncDecVectorByElementCountMask)) {
- case SQDECD_z_zs:
- mnemonic = "sqdecd";
- break;
- case SQDECH_z_zs:
- mnemonic = "sqdech";
- break;
- case SQDECW_z_zs:
- mnemonic = "sqdecw";
- break;
- case SQINCD_z_zs:
- mnemonic = "sqincd";
- break;
- case SQINCH_z_zs:
- mnemonic = "sqinch";
- break;
- case SQINCW_z_zs:
- mnemonic = "sqincw";
- break;
- case UQDECD_z_zs:
- mnemonic = "uqdecd";
- break;
- case UQDECH_z_zs:
- mnemonic = "uqdech";
- break;
- case UQDECW_z_zs:
- mnemonic = "uqdecw";
- break;
- case UQINCD_z_zs:
- mnemonic = "uqincd";
- break;
- case UQINCH_z_zs:
- mnemonic = "uqinch";
- break;
- case UQINCW_z_zs:
- mnemonic = "uqincw";
- break;
- default:
- form = "(SVEElementCount)";
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEStoreMultipleStructures_ScalarPlusImm(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEStoreMultipleStructures_ScalarPlusImm)";
+ const char *form = "{'Zt.'tmsz, 'Zt2.'tmsz}";
+ const char *form_3 = "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}";
+ const char *form_4 = "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}";
+ const char *suffix = ", 'Pgl, ['Xns'ISveSvl]";
- const char *form_2 = "{'Zt.'tmsz, 'Zt2.'tmsz}, 'Pgl, ['Xns'ISveSvl]";
- const char *form_3 =
- "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}, 'Pgl, ['Xns'ISveSvl]";
- const char *form_4 =
- "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}, "
- "'Pgl, ['Xns'ISveSvl]";
-
- switch (instr->Mask(SVEStoreMultipleStructures_ScalarPlusImmMask)) {
- case ST2B_z_p_bi_contiguous:
- mnemonic = "st2b";
- form = form_2;
- break;
- case ST2H_z_p_bi_contiguous:
- mnemonic = "st2h";
- form = form_2;
- break;
- case ST2W_z_p_bi_contiguous:
- mnemonic = "st2w";
- form = form_2;
- break;
- case ST2D_z_p_bi_contiguous:
- mnemonic = "st2d";
- form = form_2;
- break;
- case ST3B_z_p_bi_contiguous:
- mnemonic = "st3b";
+ switch (form_hash_) {
+ case "st3b_z_p_bi_contiguous"_h:
+ case "st3h_z_p_bi_contiguous"_h:
+ case "st3w_z_p_bi_contiguous"_h:
+ case "st3d_z_p_bi_contiguous"_h:
form = form_3;
break;
- case ST3H_z_p_bi_contiguous:
- mnemonic = "st3h";
- form = form_3;
- break;
- case ST3W_z_p_bi_contiguous:
- mnemonic = "st3w";
- form = form_3;
- break;
- case ST3D_z_p_bi_contiguous:
- mnemonic = "st3d";
- form = form_3;
- break;
- case ST4B_z_p_bi_contiguous:
- mnemonic = "st4b";
+ case "st4b_z_p_bi_contiguous"_h:
+ case "st4h_z_p_bi_contiguous"_h:
+ case "st4w_z_p_bi_contiguous"_h:
+ case "st4d_z_p_bi_contiguous"_h:
form = form_4;
break;
- case ST4H_z_p_bi_contiguous:
- mnemonic = "st4h";
- form = form_4;
- break;
- case ST4W_z_p_bi_contiguous:
- mnemonic = "st4w";
- form = form_4;
- break;
- case ST4D_z_p_bi_contiguous:
- mnemonic = "st4d";
- form = form_4;
- break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEStoreMultipleStructures_ScalarPlusScalar(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEStoreMultipleStructures_ScalarPlusScalar)";
+ const char *form = "{'Zt.'tmsz, 'Zt2.'tmsz}";
+ const char *form_3 = "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}";
+ const char *form_4 = "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}";
+ const char *suffix = ", 'Pgl, ['Xns, 'Xm'NSveS]";
- const char *form_2 = "{'Zt.'tmsz, 'Zt2.'tmsz}, 'Pgl, ['Xns, 'Xm'NSveS]";
- const char *form_3 =
- "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}, 'Pgl, ['Xns, 'Xm'NSveS]";
- const char *form_4 =
- "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}, "
- "'Pgl, ['Xns, 'Xm'NSveS]";
-
- switch (instr->Mask(SVEStoreMultipleStructures_ScalarPlusScalarMask)) {
- case ST2B_z_p_br_contiguous:
- mnemonic = "st2b";
- form = form_2;
- break;
- case ST2D_z_p_br_contiguous:
- mnemonic = "st2d";
- form = form_2;
- break;
- case ST2H_z_p_br_contiguous:
- mnemonic = "st2h";
- form = form_2;
- break;
- case ST2W_z_p_br_contiguous:
- mnemonic = "st2w";
- form = form_2;
- break;
- case ST3B_z_p_br_contiguous:
- mnemonic = "st3b";
+ switch (form_hash_) {
+ case "st3b_z_p_br_contiguous"_h:
+ case "st3d_z_p_br_contiguous"_h:
+ case "st3h_z_p_br_contiguous"_h:
+ case "st3w_z_p_br_contiguous"_h:
form = form_3;
break;
- case ST3D_z_p_br_contiguous:
- mnemonic = "st3d";
- form = form_3;
- break;
- case ST3H_z_p_br_contiguous:
- mnemonic = "st3h";
- form = form_3;
- break;
- case ST3W_z_p_br_contiguous:
- mnemonic = "st3w";
- form = form_3;
- break;
- case ST4B_z_p_br_contiguous:
- mnemonic = "st4b";
+ case "st4b_z_p_br_contiguous"_h:
+ case "st4d_z_p_br_contiguous"_h:
+ case "st4h_z_p_br_contiguous"_h:
+ case "st4w_z_p_br_contiguous"_h:
form = form_4;
break;
- case ST4D_z_p_br_contiguous:
- mnemonic = "st4d";
- form = form_4;
- break;
- case ST4H_z_p_br_contiguous:
- mnemonic = "st4h";
- form = form_4;
- break;
- case ST4W_z_p_br_contiguous:
- mnemonic = "st4w";
- form = form_4;
- break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEStorePredicateRegister(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEStorePredicateRegister)";
-
- switch (instr->Mask(SVEStorePredicateRegisterMask)) {
- case STR_p_bi:
- mnemonic = "str";
- if (instr->Mask(0x003f1c00) == 0) {
- form = "'Pd, ['Xns]";
- } else {
- form = "'Pd, ['Xns, #'s2116:1210, mul vl]";
- }
- break;
- default:
- break;
+ const char *form = "'Pd, ['Xns, #'s2116:1210, mul vl]";
+ if (instr->Mask(0x003f1c00) == 0) {
+ form = "'Pd, ['Xns]";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEStoreVectorRegister(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEStoreVectorRegister)";
-
- switch (instr->Mask(SVEStoreVectorRegisterMask)) {
- case STR_z_bi:
- mnemonic = "str";
- if (instr->Mask(0x003f1c00) == 0) {
- form = "'Zd, ['Xns]";
- } else {
- form = "'Zt, ['Xns, #'s2116:1210, mul vl]";
- }
- break;
- default:
- break;
+ const char *form = "'Zt, ['Xns, #'s2116:1210, mul vl]";
+ if (instr->Mask(0x003f1c00) == 0) {
+ form = "'Zd, ['Xns]";
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVETableLookup(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVETableLookup)";
-
- switch (instr->Mask(SVETableLookupMask)) {
- case TBL_z_zz_1:
- mnemonic = "tbl";
- form = "'Zd.'t, {'Zn.'t}, 'Zm.'t";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, {'Zn.'t}, 'Zm.'t");
}
void Disassembler::VisitSVEUnpackPredicateElements(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Pd.h, 'Pn.b";
-
- switch (instr->Mask(SVEUnpackPredicateElementsMask)) {
- case PUNPKHI_p_p:
- mnemonic = "punpkhi";
- break;
- case PUNPKLO_p_p:
- mnemonic = "punpklo";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.h, 'Pn.b");
}
void Disassembler::VisitSVEUnpackVectorElements(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Zn.'th";
-
if (instr->GetSVESize() == 0) {
// The lowest lane size of the destination vector is H-sized lane.
- Format(instr, "unallocated", "(SVEUnpackVectorElements)");
- return;
+ VisitUnallocated(instr);
+ } else {
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'th");
}
-
- switch (instr->Mask(SVEUnpackVectorElementsMask)) {
- case SUNPKHI_z_z:
- mnemonic = "sunpkhi";
- break;
- case SUNPKLO_z_z:
- mnemonic = "sunpklo";
- break;
- case UUNPKHI_z_z:
- mnemonic = "uunpkhi";
- break;
- case UUNPKLO_z_z:
- mnemonic = "uunpklo";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEVectorSplice(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEVectorSplice)";
-
- switch (instr->Mask(SVEVectorSpliceMask)) {
- case SPLICE_z_p_zz_des:
- mnemonic = "splice";
- form = "'Zd.'t, 'Pgl, 'Zd.'t, 'Zn.'t";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl, 'Zd.'t, 'Zn.'t");
}
void Disassembler::VisitSVEAddressGeneration(const Instruction *instr) {
@@ -7641,13 +5020,13 @@
const char *form_i = "'Zd.'tszs, 'Zn.'tszs, ";
switch (form_hash_) {
- case Hash("asr_z_zi"):
- case Hash("lsr_z_zi"):
- case Hash("sri_z_zzi"):
- case Hash("srsra_z_zi"):
- case Hash("ssra_z_zi"):
- case Hash("ursra_z_zi"):
- case Hash("usra_z_zi"):
+ case "asr_z_zi"_h:
+ case "lsr_z_zi"_h:
+ case "sri_z_zzi"_h:
+ case "srsra_z_zi"_h:
+ case "ssra_z_zi"_h:
+ case "ursra_z_zi"_h:
+ case "usra_z_zi"_h:
if (tsize != 0) {
// The tsz field must not be zero.
mnemonic = mnemonic_.c_str();
@@ -7655,8 +5034,8 @@
suffix = "'ITriSves";
}
break;
- case Hash("lsl_z_zi"):
- case Hash("sli_z_zzi"):
+ case "lsl_z_zi"_h:
+ case "sli_z_zzi"_h:
if (tsize != 0) {
// The tsz field must not be zero.
mnemonic = mnemonic_.c_str();
@@ -7664,9 +5043,9 @@
suffix = "'ITriSver";
}
break;
- case Hash("asr_z_zw"):
- case Hash("lsl_z_zw"):
- case Hash("lsr_z_zw"):
+ case "asr_z_zw"_h:
+ case "lsl_z_zw"_h:
+ case "lsr_z_zw"_h:
if (lane_size <= kSRegSizeInBytesLog2) {
mnemonic = mnemonic_.c_str();
form = "'Zd.'t, 'Zn.'t, 'Zm.d";
@@ -7680,748 +5059,259 @@
}
void Disassembler::VisitSVEElementCount(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form =
IncDecFormHelper(instr, "'Xd, 'Ipc, mul #'u1916+1", "'Xd, 'Ipc", "'Xd");
-
- switch (instr->Mask(SVEElementCountMask)) {
- case CNTB_r_s:
- mnemonic = "cntb";
- break;
- case CNTD_r_s:
- mnemonic = "cntd";
- break;
- case CNTH_r_s:
- mnemonic = "cnth";
- break;
- case CNTW_r_s:
- mnemonic = "cntw";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEFPAccumulatingReduction(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFPAccumulatingReduction)";
-
- if (instr->GetSVEVectorFormat() != kFormatVnB) {
- switch (instr->Mask(SVEFPAccumulatingReductionMask)) {
- case FADDA_v_p_z:
- mnemonic = "fadda";
- form = "'t'u0400, 'Pgl, 't'u0400, 'Zn.'t";
- break;
- default:
- break;
- }
+ if (instr->GetSVEVectorFormat() == kFormatVnB) {
+ VisitUnallocated(instr);
+ } else {
+ FormatWithDecodedMnemonic(instr, "'t'u0400, 'Pgl, 't'u0400, 'Zn.'t");
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPArithmeticUnpredicated(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Zn.'t, 'Zm.'t";
-
if (instr->GetSVEVectorFormat() == kFormatVnB) {
- form = ("(SVEFPArithmeticUnpredicated)");
+ VisitUnallocated(instr);
} else {
- switch (instr->Mask(SVEFPArithmeticUnpredicatedMask)) {
- case FADD_z_zz:
- mnemonic = "fadd";
- break;
- case FMUL_z_zz:
- mnemonic = "fmul";
- break;
- case FRECPS_z_zz:
- mnemonic = "frecps";
- break;
- case FRSQRTS_z_zz:
- mnemonic = "frsqrts";
- break;
- case FSUB_z_zz:
- mnemonic = "fsub";
- break;
- case FTSMUL_z_zz:
- mnemonic = "ftsmul";
- break;
- default:
- break;
- }
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t, 'Zm.'t");
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPCompareVectors(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
-
if (instr->GetSVEVectorFormat() == kFormatVnB) {
- form = "(SVEFPCompareVectors)";
+ VisitUnallocated(instr);
} else {
- switch (instr->Mask(SVEFPCompareVectorsMask)) {
- case FACGE_p_p_zz:
- mnemonic = "facge";
- break;
- case FACGT_p_p_zz:
- mnemonic = "facgt";
- break;
- case FCMEQ_p_p_zz:
- mnemonic = "fcmeq";
- break;
- case FCMGE_p_p_zz:
- mnemonic = "fcmge";
- break;
- case FCMGT_p_p_zz:
- mnemonic = "fcmgt";
- break;
- case FCMNE_p_p_zz:
- mnemonic = "fcmne";
- break;
- case FCMUO_p_p_zz:
- mnemonic = "fcmuo";
- break;
- default:
- break;
- }
+ FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t");
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPCompareWithZero(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Pd.'t, 'Pgl/z, 'Zn.'t, #0.0";
-
if (instr->GetSVEVectorFormat() == kFormatVnB) {
- form = "(SVEFPCompareWithZero)";
+ VisitUnallocated(instr);
} else {
- switch (instr->Mask(SVEFPCompareWithZeroMask)) {
- case FCMEQ_p_p_z0:
- mnemonic = "fcmeq";
- break;
- case FCMGE_p_p_z0:
- mnemonic = "fcmge";
- break;
- case FCMGT_p_p_z0:
- mnemonic = "fcmgt";
- break;
- case FCMLE_p_p_z0:
- mnemonic = "fcmle";
- break;
- case FCMLT_p_p_z0:
- mnemonic = "fcmlt";
- break;
- case FCMNE_p_p_z0:
- mnemonic = "fcmne";
- break;
- default:
- break;
- }
+ FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pgl/z, 'Zn.'t, #0.0");
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPComplexAddition(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFPComplexAddition)";
-
- if (instr->GetSVEVectorFormat() != kFormatVnB) {
- switch (instr->Mask(SVEFPComplexAdditionMask)) {
- case FCADD_z_p_zz:
- mnemonic = "fcadd";
- if (instr->ExtractBit(16) == 0) {
- form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t, #90";
- } else {
- form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t, #270";
- }
- break;
- default:
- break;
- }
+ // Bit 15 is always set, so this gives 90 * 1 or 3.
+ const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t, #'u1615*90";
+ if (instr->GetSVEVectorFormat() == kFormatVnB) {
+ VisitUnallocated(instr);
+ } else {
+ FormatWithDecodedMnemonic(instr, form);
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPComplexMulAdd(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFPComplexMulAdd)";
- const char *suffix = NULL;
-
- const char *fcmla_constants[] = {"0", "90", "180", "270"};
-
- if (instr->GetSVEVectorFormat() != kFormatVnB) {
- switch (instr->Mask(SVEFPComplexMulAddMask)) {
- case FCMLA_z_p_zzz:
- mnemonic = "fcmla";
- form = "'Zd.'t, 'Pgl/m, 'Zn.'t, 'Zm.'t, #";
- suffix = fcmla_constants[instr->ExtractBits(14, 13)];
- break;
- default:
- break;
- }
+ const char *form = "'Zd.'t, 'Pgl/m, 'Zn.'t, 'Zm.'t, #'u1413*90";
+ if (instr->GetSVEVectorFormat() == kFormatVnB) {
+ VisitUnallocated(instr);
+ } else {
+ FormatWithDecodedMnemonic(instr, form);
}
- Format(instr, mnemonic, form, suffix);
}
void Disassembler::VisitSVEFPComplexMulAddIndex(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFPComplexMulAddIndex)";
-
- const char *fcmla_constants[] = {"0", "90", "180", "270"};
- const char *suffix = fcmla_constants[instr->ExtractBits(11, 10)];
-
- switch (instr->Mask(SVEFPComplexMulAddIndexMask)) {
- case FCMLA_z_zzzi_h:
- mnemonic = "fcmla";
- form = "'Zd.h, 'Zn.h, z'u1816.h['u2019], #";
- break;
- case FCMLA_z_zzzi_s:
- mnemonic = "fcmla";
- form = "'Zd.s, 'Zn.s, z'u1916.s['u2020], #";
- break;
- default:
- suffix = NULL;
+ const char *form = "'Zd.h, 'Zn.h, z'u1816.h['u2019]";
+ const char *suffix = ", #'u1110*90";
+ switch (form_hash_) {
+ case "fcmla_z_zzzi_s"_h:
+ form = "'Zd.s, 'Zn.s, z'u1916.s['u2020]";
break;
}
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEFPFastReduction(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'t'u0400, 'Pgl, 'Zn.'t";
-
if (instr->GetSVEVectorFormat() == kFormatVnB) {
- form = "(SVEFPFastReduction)";
+ VisitUnallocated(instr);
} else {
- switch (instr->Mask(SVEFPFastReductionMask)) {
- case FADDV_v_p_z:
- mnemonic = "faddv";
- break;
- case FMAXNMV_v_p_z:
- mnemonic = "fmaxnmv";
- break;
- case FMAXV_v_p_z:
- mnemonic = "fmaxv";
- break;
- case FMINNMV_v_p_z:
- mnemonic = "fminnmv";
- break;
- case FMINV_v_p_z:
- mnemonic = "fminv";
- break;
- default:
- break;
- }
+ FormatWithDecodedMnemonic(instr, "'t'u0400, 'Pgl, 'Zn.'t");
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPMulIndex(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFPMulIndex)";
-
- switch (instr->Mask(SVEFPMulIndexMask)) {
- case FMUL_z_zzi_d:
- mnemonic = "fmul";
+ const char *form = "'Zd.h, 'Zn.h, z'u1816.h['u2222:2019]";
+ switch (form_hash_) {
+ case "fmul_z_zzi_d"_h:
form = "'Zd.d, 'Zn.d, z'u1916.d['u2020]";
break;
- case FMUL_z_zzi_h:
- case FMUL_z_zzi_h_i3h:
- mnemonic = "fmul";
- form = "'Zd.h, 'Zn.h, z'u1816.h['u2222:2019]";
- break;
- case FMUL_z_zzi_s:
- mnemonic = "fmul";
+ case "fmul_z_zzi_s"_h:
form = "'Zd.s, 'Zn.s, z'u1816.s['u2019]";
break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEFPMulAdd(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Pgl/m, 'Zn.'t, 'Zm.'t";
-
if (instr->GetSVEVectorFormat() == kFormatVnB) {
- form = "(SVEFPMulAdd)";
+ VisitUnallocated(instr);
} else {
- switch (instr->Mask(SVEFPMulAddMask)) {
- case FMAD_z_p_zzz:
- mnemonic = "fmad";
- break;
- case FMLA_z_p_zzz:
- mnemonic = "fmla";
- break;
- case FMLS_z_p_zzz:
- mnemonic = "fmls";
- break;
- case FMSB_z_p_zzz:
- mnemonic = "fmsb";
- break;
- case FNMAD_z_p_zzz:
- mnemonic = "fnmad";
- break;
- case FNMLA_z_p_zzz:
- mnemonic = "fnmla";
- break;
- case FNMLS_z_p_zzz:
- mnemonic = "fnmls";
- break;
- case FNMSB_z_p_zzz:
- mnemonic = "fnmsb";
- break;
- default:
- break;
- }
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zn.'t, 'Zm.'t");
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEFPMulAddIndex(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEFPMulAddIndex)";
-
- switch (instr->Mask(SVEFPMulAddIndexMask)) {
- case FMLA_z_zzzi_d:
- mnemonic = "fmla";
- form = "'Zd.d, 'Zn.d, z'u1916.d['u2020]";
- break;
- case FMLA_z_zzzi_s:
- mnemonic = "fmla";
+ const char *form = "'Zd.h, 'Zn.h, z'u1816.h['u2222:2019]";
+ switch (form_hash_) {
+ case "fmla_z_zzzi_s"_h:
+ case "fmls_z_zzzi_s"_h:
form = "'Zd.s, 'Zn.s, z'u1816.s['u2019]";
break;
- case FMLS_z_zzzi_d:
- mnemonic = "fmls";
+ case "fmla_z_zzzi_d"_h:
+ case "fmls_z_zzzi_d"_h:
form = "'Zd.d, 'Zn.d, z'u1916.d['u2020]";
break;
- case FMLS_z_zzzi_s:
- mnemonic = "fmls";
- form = "'Zd.s, 'Zn.s, z'u1816.s['u2019]";
- break;
- case FMLA_z_zzzi_h:
- case FMLA_z_zzzi_h_i3h:
- mnemonic = "fmla";
- form = "'Zd.h, 'Zn.h, z'u1816.h['u2222:2019]";
- break;
- case FMLS_z_zzzi_h:
- case FMLS_z_zzzi_h_i3h:
- mnemonic = "fmls";
- form = "'Zd.h, 'Zn.h, z'u1816.h['u2222:2019]";
- break;
- default:
- break;
}
-
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEFPUnaryOpUnpredicated(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Zn.'t";
-
if (instr->GetSVEVectorFormat() == kFormatVnB) {
- form = "(SVEFPUnaryOpUnpredicated)";
+ VisitUnallocated(instr);
} else {
- switch (instr->Mask(SVEFPUnaryOpUnpredicatedMask)) {
- case FRECPE_z_z:
- mnemonic = "frecpe";
- break;
- case FRSQRTE_z_z:
- mnemonic = "frsqrte";
- break;
- default:
- break;
- }
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t");
}
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEIncDecByPredicateCount(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEIncDecByPredicateCount)";
-
- switch (instr->Mask(SVEIncDecByPredicateCountMask)) {
- case DECP_r_p_r:
- case DECP_z_p_z:
- mnemonic = "decp";
- break;
- case INCP_r_p_r:
- case INCP_z_p_z:
- mnemonic = "incp";
- break;
- case SQDECP_r_p_r_sx:
- case SQDECP_r_p_r_x:
- case SQDECP_z_p_z:
- mnemonic = "sqdecp";
- break;
- case SQINCP_r_p_r_sx:
- case SQINCP_r_p_r_x:
- case SQINCP_z_p_z:
- mnemonic = "sqincp";
- break;
- case UQDECP_r_p_r_uw:
- case UQDECP_r_p_r_x:
- case UQDECP_z_p_z:
- mnemonic = "uqdecp";
- break;
- case UQINCP_r_p_r_uw:
- case UQINCP_r_p_r_x:
- case UQINCP_z_p_z:
- mnemonic = "uqincp";
- break;
- default:
- break;
- }
-
- switch (instr->Mask(SVEIncDecByPredicateCountMask)) {
+ const char *form = "'Zd.'t, 'Pn";
+ switch (form_hash_) {
// <Xdn>, <Pg>.<T>
- case DECP_r_p_r:
- case INCP_r_p_r:
+ case "decp_r_p_r"_h:
+ case "incp_r_p_r"_h:
form = "'Xd, 'Pn.'t";
break;
- // <Zdn>.<T>, <Pg>
- case DECP_z_p_z:
- case INCP_z_p_z:
- case SQDECP_z_p_z:
- case SQINCP_z_p_z:
- case UQDECP_z_p_z:
- case UQINCP_z_p_z:
- form = "'Zd.'t, 'Pn";
- break;
// <Xdn>, <Pg>.<T>, <Wdn>
- case SQDECP_r_p_r_sx:
- case SQINCP_r_p_r_sx:
+ case "sqdecp_r_p_r_sx"_h:
+ case "sqincp_r_p_r_sx"_h:
form = "'Xd, 'Pn.'t, 'Wd";
break;
// <Xdn>, <Pg>.<T>
- case SQDECP_r_p_r_x:
- case SQINCP_r_p_r_x:
- case UQDECP_r_p_r_x:
- case UQINCP_r_p_r_x:
+ case "sqdecp_r_p_r_x"_h:
+ case "sqincp_r_p_r_x"_h:
+ case "uqdecp_r_p_r_x"_h:
+ case "uqincp_r_p_r_x"_h:
form = "'Xd, 'Pn.'t";
break;
// <Wdn>, <Pg>.<T>
- case UQDECP_r_p_r_uw:
- case UQINCP_r_p_r_uw:
+ case "uqdecp_r_p_r_uw"_h:
+ case "uqincp_r_p_r_uw"_h:
form = "'Wd, 'Pn.'t";
break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEIndexGeneration(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEIndexGeneration)";
-
+ const char *form = "'Zd.'t, #'s0905, #'s2016";
bool w_inputs =
static_cast<unsigned>(instr->GetSVESize()) <= kWRegSizeInBytesLog2;
- switch (instr->Mask(SVEIndexGenerationMask)) {
- case INDEX_z_ii:
- mnemonic = "index";
- form = "'Zd.'t, #'s0905, #'s2016";
- break;
- case INDEX_z_ir:
- mnemonic = "index";
+ switch (form_hash_) {
+ case "index_z_ir"_h:
form = w_inputs ? "'Zd.'t, #'s0905, 'Wm" : "'Zd.'t, #'s0905, 'Xm";
break;
- case INDEX_z_ri:
- mnemonic = "index";
+ case "index_z_ri"_h:
form = w_inputs ? "'Zd.'t, 'Wn, #'s2016" : "'Zd.'t, 'Xn, #'s2016";
break;
- case INDEX_z_rr:
- mnemonic = "index";
+ case "index_z_rr"_h:
form = w_inputs ? "'Zd.'t, 'Wn, 'Wm" : "'Zd.'t, 'Xn, 'Xm";
break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEIntArithmeticUnpredicated(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Zn.'t, 'Zm.'t";
-
- switch (instr->Mask(SVEIntArithmeticUnpredicatedMask)) {
- case ADD_z_zz:
- mnemonic = "add";
- break;
- case SQADD_z_zz:
- mnemonic = "sqadd";
- break;
- case SQSUB_z_zz:
- mnemonic = "sqsub";
- break;
- case SUB_z_zz:
- mnemonic = "sub";
- break;
- case UQADD_z_zz:
- mnemonic = "uqadd";
- break;
- case UQSUB_z_zz:
- mnemonic = "uqsub";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t, 'Zm.'t");
}
void Disassembler::VisitSVEIntCompareSignedImm(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Pd.'t, 'Pgl/z, 'Zn.'t, #'s2016";
-
- switch (instr->Mask(SVEIntCompareSignedImmMask)) {
- case CMPEQ_p_p_zi:
- mnemonic = "cmpeq";
- break;
- case CMPGE_p_p_zi:
- mnemonic = "cmpge";
- break;
- case CMPGT_p_p_zi:
- mnemonic = "cmpgt";
- break;
- case CMPLE_p_p_zi:
- mnemonic = "cmple";
- break;
- case CMPLT_p_p_zi:
- mnemonic = "cmplt";
- break;
- case CMPNE_p_p_zi:
- mnemonic = "cmpne";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pgl/z, 'Zn.'t, #'s2016");
}
void Disassembler::VisitSVEIntCompareUnsignedImm(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Pd.'t, 'Pgl/z, 'Zn.'t, #'u2014";
-
- switch (instr->Mask(SVEIntCompareUnsignedImmMask)) {
- case CMPHI_p_p_zi:
- mnemonic = "cmphi";
- break;
- case CMPHS_p_p_zi:
- mnemonic = "cmphs";
- break;
- case CMPLO_p_p_zi:
- mnemonic = "cmplo";
- break;
- case CMPLS_p_p_zi:
- mnemonic = "cmpls";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pgl/z, 'Zn.'t, #'u2014");
}
void Disassembler::VisitSVEIntCompareVectors(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.d";
-
- switch (instr->Mask(SVEIntCompareVectorsMask)) {
- case CMPEQ_p_p_zw:
- mnemonic = "cmpeq";
- break;
- case CMPEQ_p_p_zz:
- mnemonic = "cmpeq";
- form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
- break;
- case CMPGE_p_p_zw:
- mnemonic = "cmpge";
- break;
- case CMPGE_p_p_zz:
- mnemonic = "cmpge";
- form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
- break;
- case CMPGT_p_p_zw:
- mnemonic = "cmpgt";
- break;
- case CMPGT_p_p_zz:
- mnemonic = "cmpgt";
- form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
- break;
- case CMPHI_p_p_zw:
- mnemonic = "cmphi";
- break;
- case CMPHI_p_p_zz:
- mnemonic = "cmphi";
- form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
- break;
- case CMPHS_p_p_zw:
- mnemonic = "cmphs";
- break;
- case CMPHS_p_p_zz:
- mnemonic = "cmphs";
- form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
- break;
- case CMPLE_p_p_zw:
- mnemonic = "cmple";
- break;
- case CMPLO_p_p_zw:
- mnemonic = "cmplo";
- break;
- case CMPLS_p_p_zw:
- mnemonic = "cmpls";
- break;
- case CMPLT_p_p_zw:
- mnemonic = "cmplt";
- break;
- case CMPNE_p_p_zw:
- mnemonic = "cmpne";
- break;
- case CMPNE_p_p_zz:
- mnemonic = "cmpne";
- form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
- break;
- default:
+ const char *form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.";
+ const char *suffix = "d";
+ switch (form_hash_) {
+ case "cmpeq_p_p_zz"_h:
+ case "cmpge_p_p_zz"_h:
+ case "cmpgt_p_p_zz"_h:
+ case "cmphi_p_p_zz"_h:
+ case "cmphs_p_p_zz"_h:
+ case "cmpne_p_p_zz"_h:
+ suffix = "'t";
break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEIntMulAddPredicated(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEIntMulAddPredicated)";
-
- switch (instr->Mask(SVEIntMulAddPredicatedMask)) {
- case MAD_z_p_zzz:
- mnemonic = "mad";
- form = "'Zd.'t, 'Pgl/m, 'Zm.'t, 'Zn.'t";
- break;
- case MLA_z_p_zzz:
- mnemonic = "mla";
- form = "'Zd.'t, 'Pgl/m, 'Zn.'t, 'Zm.'t";
- break;
- case MLS_z_p_zzz:
- mnemonic = "mls";
- form = "'Zd.'t, 'Pgl/m, 'Zn.'t, 'Zm.'t";
- break;
- case MSB_z_p_zzz:
- mnemonic = "msb";
- form = "'Zd.'t, 'Pgl/m, 'Zm.'t, 'Zn.'t";
- break;
- default:
+ const char *form = "'Zd.'t, 'Pgl/m, ";
+ const char *suffix = "'Zn.'t, 'Zm.'t";
+ switch (form_hash_) {
+ case "mad_z_p_zzz"_h:
+ case "msb_z_p_zzz"_h:
+ suffix = "'Zm.'t, 'Zn.'t";
break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEIntMulAddUnpredicated(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEIntMulAddUnpredicated)";
-
if (static_cast<unsigned>(instr->GetSVESize()) >= kSRegSizeInBytesLog2) {
- form = "'Zd.'t, 'Zn.'tq, 'Zm.'tq";
- switch (instr->Mask(SVEIntMulAddUnpredicatedMask)) {
- case SDOT_z_zzz:
- mnemonic = "sdot";
- break;
- case UDOT_z_zzz:
- mnemonic = "udot";
- break;
- default:
- break;
- }
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'tq, 'Zm.'tq");
+ } else {
+ VisitUnallocated(instr);
}
-
- Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEMovprfx(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEMovprfx)";
-
- if (instr->Mask(SVEMovprfxMask) == MOVPRFX_z_p_z) {
- mnemonic = "movprfx";
- form = "'Zd.'t, 'Pgl/'?16:mz, 'Zn.'t";
- }
-
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/'?16:mz, 'Zn.'t");
}
void Disassembler::VisitSVEIntReduction(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "'Vdv, 'Pgl, 'Zn.'t";
-
- if (instr->Mask(SVEIntReductionLogicalFMask) == SVEIntReductionLogicalFixed) {
- switch (instr->Mask(SVEIntReductionLogicalMask)) {
- case ANDV_r_p_z:
- mnemonic = "andv";
- break;
- case EORV_r_p_z:
- mnemonic = "eorv";
- break;
- case ORV_r_p_z:
- mnemonic = "orv";
- break;
- default:
- break;
- }
- } else {
- switch (instr->Mask(SVEIntReductionMask)) {
- case SADDV_r_p_z:
- mnemonic = "saddv";
- form = "'Dd, 'Pgl, 'Zn.'t";
- break;
- case SMAXV_r_p_z:
- mnemonic = "smaxv";
- break;
- case SMINV_r_p_z:
- mnemonic = "sminv";
- break;
- case UADDV_r_p_z:
- mnemonic = "uaddv";
- form = "'Dd, 'Pgl, 'Zn.'t";
- break;
- case UMAXV_r_p_z:
- mnemonic = "umaxv";
- break;
- case UMINV_r_p_z:
- mnemonic = "uminv";
- break;
- default:
- break;
- }
+ switch (form_hash_) {
+ case "saddv_r_p_z"_h:
+ case "uaddv_r_p_z"_h:
+ form = "'Dd, 'Pgl, 'Zn.'t";
+ break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEIntUnaryArithmeticPredicated(
const Instruction *instr) {
- const char *mnemonic = mnemonic_.c_str();
- const char *form = "'Zd.'t, 'Pgl/m, 'Zn.'t";
VectorFormat vform = instr->GetSVEVectorFormat();
switch (form_hash_) {
- case Hash("sxtw_z_p_z"):
- case Hash("uxtw_z_p_z"):
+ case "sxtw_z_p_z"_h:
+ case "uxtw_z_p_z"_h:
if (vform == kFormatVnS) {
VisitUnallocated(instr);
return;
}
VIXL_FALLTHROUGH();
- case Hash("sxth_z_p_z"):
- case Hash("uxth_z_p_z"):
+ case "sxth_z_p_z"_h:
+ case "uxth_z_p_z"_h:
if (vform == kFormatVnH) {
VisitUnallocated(instr);
return;
}
VIXL_FALLTHROUGH();
- case Hash("sxtb_z_p_z"):
- case Hash("uxtb_z_p_z"):
- case Hash("fabs_z_p_z"):
- case Hash("fneg_z_p_z"):
+ case "sxtb_z_p_z"_h:
+ case "uxtb_z_p_z"_h:
+ case "fabs_z_p_z"_h:
+ case "fneg_z_p_z"_h:
if (vform == kFormatVnB) {
VisitUnallocated(instr);
return;
@@ -8429,91 +5319,36 @@
break;
}
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Pgl/m, 'Zn.'t");
}
void Disassembler::VisitSVEMulIndex(const Instruction *instr) {
- const char *mnemonic = mnemonic_.c_str();
- const char *form = "(SVEMulIndex)";
+ const char *form = "'Zd.s, 'Zn.b, z'u1816.b['u2019]";
switch (form_hash_) {
- case Hash("sdot_z_zzzi_d"):
- case Hash("udot_z_zzzi_d"):
+ case "sdot_z_zzzi_d"_h:
+ case "udot_z_zzzi_d"_h:
form = "'Zd.d, 'Zn.h, z'u1916.h['u2020]";
break;
- case Hash("sdot_z_zzzi_s"):
- case Hash("sudot_z_zzzi_s"):
- case Hash("udot_z_zzzi_s"):
- case Hash("usdot_z_zzzi_s"):
- form = "'Zd.s, 'Zn.b, z'u1816.b['u2019]";
- break;
- default:
- break;
}
- Format(instr, mnemonic, form);
+
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEPermuteVectorExtract(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEPermuteVectorExtract)";
-
- switch (instr->Mask(SVEPermuteVectorExtractMask)) {
- case EXT_z_zi_des:
- mnemonic = "ext";
- form = "'Zd.b, 'Zd.b, 'Zn.b, #'u2016:1210";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.b, 'Zd.b, 'Zn.b, #'u2016:1210");
}
void Disassembler::VisitSVEPermuteVectorInterleaving(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Zd.'t, 'Zn.'t, 'Zm.'t";
-
- switch (instr->Mask(SVEPermuteVectorInterleavingMask)) {
- case TRN1_z_zz:
- mnemonic = "trn1";
- break;
- case TRN2_z_zz:
- mnemonic = "trn2";
- break;
- case UZP1_z_zz:
- mnemonic = "uzp1";
- break;
- case UZP2_z_zz:
- mnemonic = "uzp2";
- break;
- case ZIP1_z_zz:
- mnemonic = "zip1";
- break;
- case ZIP2_z_zz:
- mnemonic = "zip2";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Zd.'t, 'Zn.'t, 'Zm.'t");
}
void Disassembler::VisitSVEPredicateCount(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEPredicateCount)";
-
- switch (instr->Mask(SVEPredicateCountMask)) {
- case CNTP_r_p_p:
- mnemonic = "cntp";
- form = "'Xd, p'u1310, 'Pn.'t";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Xd, p'u1310, 'Pn.'t");
}
void Disassembler::VisitSVEPredicateLogical(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
+ const char *mnemonic = mnemonic_.c_str();
const char *form = "'Pd.b, p'u1310/z, 'Pn.b, 'Pm.b";
int pd = instr->GetPd();
@@ -8521,304 +5356,127 @@
int pm = instr->GetPm();
int pg = instr->ExtractBits(13, 10);
- switch (instr->Mask(SVEPredicateLogicalMask)) {
- case ANDS_p_p_pp_z:
- mnemonic = "ands";
+ switch (form_hash_) {
+ case "ands_p_p_pp_z"_h:
if (pn == pm) {
mnemonic = "movs";
form = "'Pd.b, p'u1310/z, 'Pn.b";
}
break;
- case AND_p_p_pp_z:
- mnemonic = "and";
+ case "and_p_p_pp_z"_h:
if (pn == pm) {
mnemonic = "mov";
form = "'Pd.b, p'u1310/z, 'Pn.b";
}
break;
- case BICS_p_p_pp_z:
- mnemonic = "bics";
- break;
- case BIC_p_p_pp_z:
- mnemonic = "bic";
- break;
- case EORS_p_p_pp_z:
- mnemonic = "eors";
+ case "eors_p_p_pp_z"_h:
if (pm == pg) {
mnemonic = "nots";
form = "'Pd.b, 'Pm/z, 'Pn.b";
}
break;
- case EOR_p_p_pp_z:
- mnemonic = "eor";
+ case "eor_p_p_pp_z"_h:
if (pm == pg) {
mnemonic = "not";
form = "'Pd.b, 'Pm/z, 'Pn.b";
}
break;
- case NANDS_p_p_pp_z:
- mnemonic = "nands";
- break;
- case NAND_p_p_pp_z:
- mnemonic = "nand";
- break;
- case NORS_p_p_pp_z:
- mnemonic = "nors";
- break;
- case NOR_p_p_pp_z:
- mnemonic = "nor";
- break;
- case ORNS_p_p_pp_z:
- mnemonic = "orns";
- break;
- case ORN_p_p_pp_z:
- mnemonic = "orn";
- break;
- case ORRS_p_p_pp_z:
- mnemonic = "orrs";
+ case "orrs_p_p_pp_z"_h:
if ((pn == pm) && (pn == pg)) {
mnemonic = "movs";
form = "'Pd.b, 'Pn.b";
}
break;
- case ORR_p_p_pp_z:
- mnemonic = "orr";
+ case "orr_p_p_pp_z"_h:
if ((pn == pm) && (pn == pg)) {
mnemonic = "mov";
form = "'Pd.b, 'Pn.b";
}
break;
- case SEL_p_p_pp:
+ case "sel_p_p_pp"_h:
if (pd == pm) {
mnemonic = "mov";
form = "'Pd.b, p'u1310/m, 'Pn.b";
} else {
- mnemonic = "sel";
form = "'Pd.b, p'u1310, 'Pn.b, 'Pm.b";
}
break;
- default:
- form = "(SVEPredicateLogical)";
- break;
}
Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEPredicateInitialize(const Instruction *instr) {
- // This group only contains PTRUE{S}, and there are no unallocated encodings.
- VIXL_STATIC_ASSERT(
- SVEPredicateInitializeMask ==
- (SVEPredicateInitializeFMask | SVEPredicateInitializeSetFlagsBit));
- VIXL_ASSERT((instr->Mask(SVEPredicateInitializeMask) == PTRUE_p_s) ||
- (instr->Mask(SVEPredicateInitializeMask) == PTRUES_p_s));
-
- const char *mnemonic = instr->ExtractBit(16) ? "ptrues" : "ptrue";
const char *form = "'Pd.'t, 'Ipc";
// Omit the pattern if it is the default ('ALL').
if (instr->ExtractBits(9, 5) == SVE_ALL) form = "'Pd.'t";
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, form);
}
void Disassembler::VisitSVEPredicateNextActive(const Instruction *instr) {
- // This group only contains PNEXT, and there are no unallocated encodings.
- VIXL_STATIC_ASSERT(SVEPredicateNextActiveFMask == SVEPredicateNextActiveMask);
- VIXL_ASSERT(instr->Mask(SVEPredicateNextActiveMask) == PNEXT_p_p_p);
-
- Format(instr, "pnext", "'Pd.'t, 'Pn, 'Pd.'t");
+ FormatWithDecodedMnemonic(instr, "'Pd.'t, 'Pn, 'Pd.'t");
}
void Disassembler::VisitSVEPredicateReadFromFFR_Predicated(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEPredicateReadFromFFR_Predicated)";
- switch (instr->Mask(SVEPredicateReadFromFFR_PredicatedMask)) {
- case RDFFR_p_p_f:
- case RDFFRS_p_p_f:
- mnemonic = instr->ExtractBit(22) ? "rdffrs" : "rdffr";
- form = "'Pd.b, 'Pn/z";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.b, 'Pn/z");
}
void Disassembler::VisitSVEPropagateBreak(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Pd.b, p'u1310/z, 'Pn.b, 'Pm.b";
-
- switch (instr->Mask(SVEPropagateBreakMask)) {
- case BRKPAS_p_p_pp:
- mnemonic = "brkpas";
- break;
- case BRKPA_p_p_pp:
- mnemonic = "brkpa";
- break;
- case BRKPBS_p_p_pp:
- mnemonic = "brkpbs";
- break;
- case BRKPB_p_p_pp:
- mnemonic = "brkpb";
- break;
- default:
- break;
- }
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Pd.b, p'u1310/z, 'Pn.b, 'Pm.b");
}
void Disassembler::VisitSVEStackFrameAdjustment(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "'Xds, 'Xms, #'s1005";
-
- switch (instr->Mask(SVEStackFrameAdjustmentMask)) {
- case ADDPL_r_ri:
- mnemonic = "addpl";
- break;
- case ADDVL_r_ri:
- mnemonic = "addvl";
- break;
- default:
- form = "(SVEStackFrameAdjustment)";
- break;
- }
-
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Xds, 'Xms, #'s1005");
}
void Disassembler::VisitSVEStackFrameSize(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEStackFrameSize)";
-
- switch (instr->Mask(SVEStackFrameSizeMask)) {
- case RDVL_r_i:
- mnemonic = "rdvl";
- form = "'Xd, #'s1005";
- break;
- default:
- break;
- }
-
- Format(instr, mnemonic, form);
+ FormatWithDecodedMnemonic(instr, "'Xd, #'s1005");
}
void Disassembler::VisitSVEVectorSelect(const Instruction *instr) {
- const char *mnemonic = "unimplemented";
- const char *form = "(SVEVectorSelect)";
+ const char *mnemonic = mnemonic_.c_str();
+ const char *form = "'Zd.'t, p'u1310, 'Zn.'t, 'Zm.'t";
- switch (instr->Mask(SVEVectorSelectMask)) {
- case SEL_z_p_zz:
- if (instr->GetRd() == instr->GetRm()) {
- mnemonic = "mov";
- form = "'Zd.'t, p'u1310/m, 'Zn.'t";
- } else {
- mnemonic = "sel";
- form = "'Zd.'t, p'u1310, 'Zn.'t, 'Zm.'t";
- }
- break;
- default:
- break;
+ if (instr->GetRd() == instr->GetRm()) {
+ mnemonic = "mov";
+ form = "'Zd.'t, p'u1310/m, 'Zn.'t";
}
+
Format(instr, mnemonic, form);
}
void Disassembler::VisitSVEContiguousLoad_ScalarPlusImm(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "{'Zt.'tlss}, 'Pgl/z, ['Xns";
const char *suffix =
(instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
-
- switch (instr->Mask(SVEContiguousLoad_ScalarPlusImmMask)) {
- case LD1B_z_p_bi_u16:
- case LD1B_z_p_bi_u32:
- case LD1B_z_p_bi_u64:
- case LD1B_z_p_bi_u8:
- mnemonic = "ld1b";
- break;
- case LD1D_z_p_bi_u64:
- mnemonic = "ld1d";
- break;
- case LD1H_z_p_bi_u16:
- case LD1H_z_p_bi_u32:
- case LD1H_z_p_bi_u64:
- mnemonic = "ld1h";
- break;
- case LD1SB_z_p_bi_s16:
- case LD1SB_z_p_bi_s32:
- case LD1SB_z_p_bi_s64:
- mnemonic = "ld1sb";
- break;
- case LD1SH_z_p_bi_s32:
- case LD1SH_z_p_bi_s64:
- mnemonic = "ld1sh";
- break;
- case LD1SW_z_p_bi_s64:
- mnemonic = "ld1sw";
- break;
- case LD1W_z_p_bi_u32:
- case LD1W_z_p_bi_u64:
- mnemonic = "ld1w";
- break;
- default:
- form = "(SVEContiguousLoad_ScalarPlusImm)";
- suffix = NULL;
- break;
- }
-
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitSVEContiguousLoad_ScalarPlusScalar(
const Instruction *instr) {
- const char *mnemonic = "unimplemented";
const char *form = "{'Zt.'tlss}, 'Pgl/z, ['Xns, 'Xm";
- const char *suffix = NULL;
+ const char *suffix = "]";
- switch (instr->Mask(SVEContiguousLoad_ScalarPlusScalarMask)) {
- case LD1B_z_p_br_u16:
- case LD1B_z_p_br_u32:
- case LD1B_z_p_br_u64:
- case LD1B_z_p_br_u8:
- mnemonic = "ld1b";
- suffix = "]";
- break;
- case LD1D_z_p_br_u64:
- mnemonic = "ld1d";
+ switch (form_hash_) {
+ case "ld1h_z_p_br_u16"_h:
+ case "ld1h_z_p_br_u32"_h:
+ case "ld1h_z_p_br_u64"_h:
+ case "ld1w_z_p_br_u32"_h:
+ case "ld1w_z_p_br_u64"_h:
+ case "ld1d_z_p_br_u64"_h:
suffix = ", lsl #'u2423]";
break;
- case LD1H_z_p_br_u16:
- case LD1H_z_p_br_u32:
- case LD1H_z_p_br_u64:
- mnemonic = "ld1h";
- suffix = ", lsl #'u2423]";
- break;
- case LD1SB_z_p_br_s16:
- case LD1SB_z_p_br_s32:
- case LD1SB_z_p_br_s64:
- mnemonic = "ld1sb";
- suffix = "]";
- break;
- case LD1SH_z_p_br_s32:
- case LD1SH_z_p_br_s64:
- mnemonic = "ld1sh";
+ case "ld1sh_z_p_br_s32"_h:
+ case "ld1sh_z_p_br_s64"_h:
suffix = ", lsl #1]";
break;
- case LD1SW_z_p_br_s64:
- mnemonic = "ld1sw";
+ case "ld1sw_z_p_br_s64"_h:
suffix = ", lsl #2]";
break;
- case LD1W_z_p_br_u32:
- case LD1W_z_p_br_u64:
- mnemonic = "ld1w";
- suffix = ", lsl #'u2423]";
- break;
- default:
- form = "(SVEContiguousLoad_ScalarPlusScalar)";
- suffix = NULL;
- break;
}
- Format(instr, mnemonic, form, suffix);
+ FormatWithDecodedMnemonic(instr, form, suffix);
}
void Disassembler::VisitReserved(const Instruction *instr) {
@@ -8839,13 +5497,14 @@
void Disassembler::Visit(Metadata *metadata, const Instruction *instr) {
VIXL_ASSERT(metadata->count("form") > 0);
const std::string &form = (*metadata)["form"];
+ form_hash_ = Hash(form.c_str());
const FormToVisitorFnMap *fv = Disassembler::GetFormToVisitorFnMap();
- if ((fv->count(form) > 0) && fv->at(form)) {
- form_hash_ = Hash(form.c_str());
- SetMnemonicFromForm(form);
- fv->at(form)(this, instr);
- } else {
+ FormToVisitorFnMap::const_iterator it = fv->find(form_hash_);
+ if (it == fv->end()) {
VisitUnimplemented(instr);
+ } else {
+ SetMnemonicFromForm(form);
+ (it->second)(this, instr);
}
}
@@ -9461,6 +6120,11 @@
}
}
+void Disassembler::FormatWithDecodedMnemonic(const Instruction *instr,
+ const char *format0,
+ const char *format1) {
+ Format(instr, mnemonic_.c_str(), format0, format1);
+}
void Disassembler::Substitute(const Instruction *instr, const char *string) {
char chr = *string++;
diff --git a/src/aarch64/disasm-aarch64.h b/src/aarch64/disasm-aarch64.h
index 5888456..3af4f11 100644
--- a/src/aarch64/disasm-aarch64.h
+++ b/src/aarch64/disasm-aarch64.h
@@ -118,7 +118,7 @@
#undef DECLARE
using FormToVisitorFnMap = std::unordered_map<
- std::string,
+ uint32_t,
std::function<void(Disassembler*, const Instruction*)>>;
static const FormToVisitorFnMap* GetFormToVisitorFnMap();
@@ -126,7 +126,7 @@
uint32_t form_hash_;
void SetMnemonicFromForm(const std::string& form) {
- if (form != "Unallocated") {
+ if (form != "unallocated") {
VIXL_ASSERT(form.find_first_of('_') != std::string::npos);
mnemonic_ = form.substr(0, form.find_first_of('_'));
}
@@ -238,6 +238,10 @@
const char* mnemonic,
const char* format0,
const char* format1 = NULL);
+ void FormatWithDecodedMnemonic(const Instruction* instr,
+ const char* format0,
+ const char* format1 = NULL);
+
void Substitute(const Instruction* instr, const char* string);
int SubstituteField(const Instruction* instr, const char* format);
int SubstituteRegisterField(const Instruction* instr, const char* format);
diff --git a/src/aarch64/instructions-aarch64.cc b/src/aarch64/instructions-aarch64.cc
index 2adf24a..4718e2d 100644
--- a/src/aarch64/instructions-aarch64.cc
+++ b/src/aarch64/instructions-aarch64.cc
@@ -68,197 +68,197 @@
bool zd_isnt_zm = movprfx_zd != GetRm();
switch (form_hash) {
- case Hash("cdot_z_zzzi_s"):
- case Hash("sdot_z_zzzi_s"):
- case Hash("sudot_z_zzzi_s"):
- case Hash("udot_z_zzzi_s"):
- case Hash("usdot_z_zzzi_s"):
+ case "cdot_z_zzzi_s"_h:
+ case "sdot_z_zzzi_s"_h:
+ case "sudot_z_zzzi_s"_h:
+ case "udot_z_zzzi_s"_h:
+ case "usdot_z_zzzi_s"_h:
return (GetRd() != static_cast<int>(ExtractBits(18, 16))) &&
movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
- case Hash("cdot_z_zzzi_d"):
- case Hash("sdot_z_zzzi_d"):
- case Hash("udot_z_zzzi_d"):
+ case "cdot_z_zzzi_d"_h:
+ case "sdot_z_zzzi_d"_h:
+ case "udot_z_zzzi_d"_h:
return (GetRd() != static_cast<int>(ExtractBits(19, 16))) &&
movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
- case Hash("fmlalb_z_zzzi_s"):
- case Hash("fmlalt_z_zzzi_s"):
- case Hash("fmlslb_z_zzzi_s"):
- case Hash("fmlslt_z_zzzi_s"):
- case Hash("smlalb_z_zzzi_d"):
- case Hash("smlalb_z_zzzi_s"):
- case Hash("smlalt_z_zzzi_d"):
- case Hash("smlalt_z_zzzi_s"):
- case Hash("smlslb_z_zzzi_d"):
- case Hash("smlslb_z_zzzi_s"):
- case Hash("smlslt_z_zzzi_d"):
- case Hash("smlslt_z_zzzi_s"):
- case Hash("sqdmlalb_z_zzzi_d"):
- case Hash("sqdmlalb_z_zzzi_s"):
- case Hash("sqdmlalt_z_zzzi_d"):
- case Hash("sqdmlalt_z_zzzi_s"):
- case Hash("sqdmlslb_z_zzzi_d"):
- case Hash("sqdmlslb_z_zzzi_s"):
- case Hash("sqdmlslt_z_zzzi_d"):
- case Hash("sqdmlslt_z_zzzi_s"):
- case Hash("umlalb_z_zzzi_d"):
- case Hash("umlalb_z_zzzi_s"):
- case Hash("umlalt_z_zzzi_d"):
- case Hash("umlalt_z_zzzi_s"):
- case Hash("umlslb_z_zzzi_d"):
- case Hash("umlslb_z_zzzi_s"):
- case Hash("umlslt_z_zzzi_d"):
- case Hash("umlslt_z_zzzi_s"):
+ case "fmlalb_z_zzzi_s"_h:
+ case "fmlalt_z_zzzi_s"_h:
+ case "fmlslb_z_zzzi_s"_h:
+ case "fmlslt_z_zzzi_s"_h:
+ case "smlalb_z_zzzi_d"_h:
+ case "smlalb_z_zzzi_s"_h:
+ case "smlalt_z_zzzi_d"_h:
+ case "smlalt_z_zzzi_s"_h:
+ case "smlslb_z_zzzi_d"_h:
+ case "smlslb_z_zzzi_s"_h:
+ case "smlslt_z_zzzi_d"_h:
+ case "smlslt_z_zzzi_s"_h:
+ case "sqdmlalb_z_zzzi_d"_h:
+ case "sqdmlalb_z_zzzi_s"_h:
+ case "sqdmlalt_z_zzzi_d"_h:
+ case "sqdmlalt_z_zzzi_s"_h:
+ case "sqdmlslb_z_zzzi_d"_h:
+ case "sqdmlslb_z_zzzi_s"_h:
+ case "sqdmlslt_z_zzzi_d"_h:
+ case "sqdmlslt_z_zzzi_s"_h:
+ case "umlalb_z_zzzi_d"_h:
+ case "umlalb_z_zzzi_s"_h:
+ case "umlalt_z_zzzi_d"_h:
+ case "umlalt_z_zzzi_s"_h:
+ case "umlslb_z_zzzi_d"_h:
+ case "umlslb_z_zzzi_s"_h:
+ case "umlslt_z_zzzi_d"_h:
+ case "umlslt_z_zzzi_s"_h:
return (GetRd() != GetSVEMulLongZmAndIndex().first) &&
movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
- case Hash("cmla_z_zzzi_h"):
- case Hash("cmla_z_zzzi_s"):
- case Hash("fcmla_z_zzzi_h"):
- case Hash("fcmla_z_zzzi_s"):
- case Hash("fmla_z_zzzi_d"):
- case Hash("fmla_z_zzzi_h"):
- case Hash("fmla_z_zzzi_s"):
- case Hash("fmls_z_zzzi_d"):
- case Hash("fmls_z_zzzi_h"):
- case Hash("fmls_z_zzzi_s"):
- case Hash("mla_z_zzzi_d"):
- case Hash("mla_z_zzzi_h"):
- case Hash("mla_z_zzzi_s"):
- case Hash("mls_z_zzzi_d"):
- case Hash("mls_z_zzzi_h"):
- case Hash("mls_z_zzzi_s"):
- case Hash("sqrdcmlah_z_zzzi_h"):
- case Hash("sqrdcmlah_z_zzzi_s"):
- case Hash("sqrdmlah_z_zzzi_d"):
- case Hash("sqrdmlah_z_zzzi_h"):
- case Hash("sqrdmlah_z_zzzi_s"):
- case Hash("sqrdmlsh_z_zzzi_d"):
- case Hash("sqrdmlsh_z_zzzi_h"):
- case Hash("sqrdmlsh_z_zzzi_s"):
+ case "cmla_z_zzzi_h"_h:
+ case "cmla_z_zzzi_s"_h:
+ case "fcmla_z_zzzi_h"_h:
+ case "fcmla_z_zzzi_s"_h:
+ case "fmla_z_zzzi_d"_h:
+ case "fmla_z_zzzi_h"_h:
+ case "fmla_z_zzzi_s"_h:
+ case "fmls_z_zzzi_d"_h:
+ case "fmls_z_zzzi_h"_h:
+ case "fmls_z_zzzi_s"_h:
+ case "mla_z_zzzi_d"_h:
+ case "mla_z_zzzi_h"_h:
+ case "mla_z_zzzi_s"_h:
+ case "mls_z_zzzi_d"_h:
+ case "mls_z_zzzi_h"_h:
+ case "mls_z_zzzi_s"_h:
+ case "sqrdcmlah_z_zzzi_h"_h:
+ case "sqrdcmlah_z_zzzi_s"_h:
+ case "sqrdmlah_z_zzzi_d"_h:
+ case "sqrdmlah_z_zzzi_h"_h:
+ case "sqrdmlah_z_zzzi_s"_h:
+ case "sqrdmlsh_z_zzzi_d"_h:
+ case "sqrdmlsh_z_zzzi_h"_h:
+ case "sqrdmlsh_z_zzzi_s"_h:
return (GetRd() != GetSVEMulZmAndIndex().first) &&
movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
- case Hash("adclb_z_zzz"):
- case Hash("adclt_z_zzz"):
- case Hash("bcax_z_zzz"):
- case Hash("bsl1n_z_zzz"):
- case Hash("bsl2n_z_zzz"):
- case Hash("bsl_z_zzz"):
- case Hash("cdot_z_zzz"):
- case Hash("cmla_z_zzz"):
- case Hash("eor3_z_zzz"):
- case Hash("eorbt_z_zz"):
- case Hash("eortb_z_zz"):
- case Hash("fmlalb_z_zzz"):
- case Hash("fmlalt_z_zzz"):
- case Hash("fmlslb_z_zzz"):
- case Hash("fmlslt_z_zzz"):
- case Hash("nbsl_z_zzz"):
- case Hash("saba_z_zzz"):
- case Hash("sabalb_z_zzz"):
- case Hash("sabalt_z_zzz"):
- case Hash("sbclb_z_zzz"):
- case Hash("sbclt_z_zzz"):
- case Hash("sdot_z_zzz"):
- case Hash("smlalb_z_zzz"):
- case Hash("smlalt_z_zzz"):
- case Hash("smlslb_z_zzz"):
- case Hash("smlslt_z_zzz"):
- case Hash("sqdmlalb_z_zzz"):
- case Hash("sqdmlalbt_z_zzz"):
- case Hash("sqdmlalt_z_zzz"):
- case Hash("sqdmlslb_z_zzz"):
- case Hash("sqdmlslbt_z_zzz"):
- case Hash("sqdmlslt_z_zzz"):
- case Hash("sqrdcmlah_z_zzz"):
- case Hash("sqrdmlah_z_zzz"):
- case Hash("sqrdmlsh_z_zzz"):
- case Hash("uaba_z_zzz"):
- case Hash("uabalb_z_zzz"):
- case Hash("uabalt_z_zzz"):
- case Hash("udot_z_zzz"):
- case Hash("umlalb_z_zzz"):
- case Hash("umlalt_z_zzz"):
- case Hash("umlslb_z_zzz"):
- case Hash("umlslt_z_zzz"):
- case Hash("usdot_z_zzz_s"):
- case Hash("fmmla_z_zzz_s"):
- case Hash("fmmla_z_zzz_d"):
- case Hash("smmla_z_zzz"):
- case Hash("ummla_z_zzz"):
- case Hash("usmmla_z_zzz"):
+ case "adclb_z_zzz"_h:
+ case "adclt_z_zzz"_h:
+ case "bcax_z_zzz"_h:
+ case "bsl1n_z_zzz"_h:
+ case "bsl2n_z_zzz"_h:
+ case "bsl_z_zzz"_h:
+ case "cdot_z_zzz"_h:
+ case "cmla_z_zzz"_h:
+ case "eor3_z_zzz"_h:
+ case "eorbt_z_zz"_h:
+ case "eortb_z_zz"_h:
+ case "fmlalb_z_zzz"_h:
+ case "fmlalt_z_zzz"_h:
+ case "fmlslb_z_zzz"_h:
+ case "fmlslt_z_zzz"_h:
+ case "nbsl_z_zzz"_h:
+ case "saba_z_zzz"_h:
+ case "sabalb_z_zzz"_h:
+ case "sabalt_z_zzz"_h:
+ case "sbclb_z_zzz"_h:
+ case "sbclt_z_zzz"_h:
+ case "sdot_z_zzz"_h:
+ case "smlalb_z_zzz"_h:
+ case "smlalt_z_zzz"_h:
+ case "smlslb_z_zzz"_h:
+ case "smlslt_z_zzz"_h:
+ case "sqdmlalb_z_zzz"_h:
+ case "sqdmlalbt_z_zzz"_h:
+ case "sqdmlalt_z_zzz"_h:
+ case "sqdmlslb_z_zzz"_h:
+ case "sqdmlslbt_z_zzz"_h:
+ case "sqdmlslt_z_zzz"_h:
+ case "sqrdcmlah_z_zzz"_h:
+ case "sqrdmlah_z_zzz"_h:
+ case "sqrdmlsh_z_zzz"_h:
+ case "uaba_z_zzz"_h:
+ case "uabalb_z_zzz"_h:
+ case "uabalt_z_zzz"_h:
+ case "udot_z_zzz"_h:
+ case "umlalb_z_zzz"_h:
+ case "umlalt_z_zzz"_h:
+ case "umlslb_z_zzz"_h:
+ case "umlslt_z_zzz"_h:
+ case "usdot_z_zzz_s"_h:
+ case "fmmla_z_zzz_s"_h:
+ case "fmmla_z_zzz_d"_h:
+ case "smmla_z_zzz"_h:
+ case "ummla_z_zzz"_h:
+ case "usmmla_z_zzz"_h:
return movprfx_is_unpredicated && zd_isnt_zm && zd_isnt_zn && zd_matches;
- case Hash("addp_z_p_zz"):
- case Hash("cadd_z_zz"):
- case Hash("clasta_z_p_zz"):
- case Hash("clastb_z_p_zz"):
- case Hash("decd_z_zs"):
- case Hash("dech_z_zs"):
- case Hash("decw_z_zs"):
- case Hash("faddp_z_p_zz"):
- case Hash("fmaxnmp_z_p_zz"):
- case Hash("fmaxp_z_p_zz"):
- case Hash("fminnmp_z_p_zz"):
- case Hash("fminp_z_p_zz"):
- case Hash("ftmad_z_zzi"):
- case Hash("incd_z_zs"):
- case Hash("inch_z_zs"):
- case Hash("incw_z_zs"):
- case Hash("insr_z_v"):
- case Hash("smaxp_z_p_zz"):
- case Hash("sminp_z_p_zz"):
- case Hash("splice_z_p_zz_con"):
- case Hash("splice_z_p_zz_des"):
- case Hash("sqcadd_z_zz"):
- case Hash("sqdecd_z_zs"):
- case Hash("sqdech_z_zs"):
- case Hash("sqdecw_z_zs"):
- case Hash("sqincd_z_zs"):
- case Hash("sqinch_z_zs"):
- case Hash("sqincw_z_zs"):
- case Hash("srsra_z_zi"):
- case Hash("ssra_z_zi"):
- case Hash("umaxp_z_p_zz"):
- case Hash("uminp_z_p_zz"):
- case Hash("uqdecd_z_zs"):
- case Hash("uqdech_z_zs"):
- case Hash("uqdecw_z_zs"):
- case Hash("uqincd_z_zs"):
- case Hash("uqinch_z_zs"):
- case Hash("uqincw_z_zs"):
- case Hash("ursra_z_zi"):
- case Hash("usra_z_zi"):
- case Hash("xar_z_zzi"):
+ case "addp_z_p_zz"_h:
+ case "cadd_z_zz"_h:
+ case "clasta_z_p_zz"_h:
+ case "clastb_z_p_zz"_h:
+ case "decd_z_zs"_h:
+ case "dech_z_zs"_h:
+ case "decw_z_zs"_h:
+ case "faddp_z_p_zz"_h:
+ case "fmaxnmp_z_p_zz"_h:
+ case "fmaxp_z_p_zz"_h:
+ case "fminnmp_z_p_zz"_h:
+ case "fminp_z_p_zz"_h:
+ case "ftmad_z_zzi"_h:
+ case "incd_z_zs"_h:
+ case "inch_z_zs"_h:
+ case "incw_z_zs"_h:
+ case "insr_z_v"_h:
+ case "smaxp_z_p_zz"_h:
+ case "sminp_z_p_zz"_h:
+ case "splice_z_p_zz_con"_h:
+ case "splice_z_p_zz_des"_h:
+ case "sqcadd_z_zz"_h:
+ case "sqdecd_z_zs"_h:
+ case "sqdech_z_zs"_h:
+ case "sqdecw_z_zs"_h:
+ case "sqincd_z_zs"_h:
+ case "sqinch_z_zs"_h:
+ case "sqincw_z_zs"_h:
+ case "srsra_z_zi"_h:
+ case "ssra_z_zi"_h:
+ case "umaxp_z_p_zz"_h:
+ case "uminp_z_p_zz"_h:
+ case "uqdecd_z_zs"_h:
+ case "uqdech_z_zs"_h:
+ case "uqdecw_z_zs"_h:
+ case "uqincd_z_zs"_h:
+ case "uqinch_z_zs"_h:
+ case "uqincw_z_zs"_h:
+ case "ursra_z_zi"_h:
+ case "usra_z_zi"_h:
+ case "xar_z_zzi"_h:
return movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
- case Hash("add_z_zi"):
- case Hash("and_z_zi"):
- case Hash("decp_z_p_z"):
- case Hash("eor_z_zi"):
- case Hash("incp_z_p_z"):
- case Hash("insr_z_r"):
- case Hash("mul_z_zi"):
- case Hash("orr_z_zi"):
- case Hash("smax_z_zi"):
- case Hash("smin_z_zi"):
- case Hash("sqadd_z_zi"):
- case Hash("sqdecp_z_p_z"):
- case Hash("sqincp_z_p_z"):
- case Hash("sqsub_z_zi"):
- case Hash("sub_z_zi"):
- case Hash("subr_z_zi"):
- case Hash("umax_z_zi"):
- case Hash("umin_z_zi"):
- case Hash("uqadd_z_zi"):
- case Hash("uqdecp_z_p_z"):
- case Hash("uqincp_z_p_z"):
- case Hash("uqsub_z_zi"):
+ case "add_z_zi"_h:
+ case "and_z_zi"_h:
+ case "decp_z_p_z"_h:
+ case "eor_z_zi"_h:
+ case "incp_z_p_z"_h:
+ case "insr_z_r"_h:
+ case "mul_z_zi"_h:
+ case "orr_z_zi"_h:
+ case "smax_z_zi"_h:
+ case "smin_z_zi"_h:
+ case "sqadd_z_zi"_h:
+ case "sqdecp_z_p_z"_h:
+ case "sqincp_z_p_z"_h:
+ case "sqsub_z_zi"_h:
+ case "sub_z_zi"_h:
+ case "subr_z_zi"_h:
+ case "umax_z_zi"_h:
+ case "umin_z_zi"_h:
+ case "uqadd_z_zi"_h:
+ case "uqdecp_z_p_z"_h:
+ case "uqincp_z_p_z"_h:
+ case "uqsub_z_zi"_h:
return movprfx_is_unpredicated && zd_matches;
- case Hash("cpy_z_p_i"):
+ case "cpy_z_p_i"_h:
if (movprfx_is_predicated) {
if (!vform_matches) return false;
if (movprfx_pg != GetRx<19, 16>()) return false;
@@ -267,25 +267,25 @@
if (ExtractBit(14) == 0) return false;
return zd_matches;
- case Hash("fcpy_z_p_i"):
+ case "fcpy_z_p_i"_h:
return (movprfx_is_unpredicated ||
((movprfx_pg == GetRx<19, 16>()) && vform_matches)) &&
zd_matches;
- case Hash("flogb_z_p_z"):
+ case "flogb_z_p_z"_h:
return (movprfx_is_unpredicated ||
((movprfx_vform == GetSVEVectorFormat(17)) && pg_matches_low8)) &&
zd_isnt_zn && zd_matches;
- case Hash("asr_z_p_zi"):
- case Hash("asrd_z_p_zi"):
- case Hash("lsl_z_p_zi"):
- case Hash("lsr_z_p_zi"):
- case Hash("sqshl_z_p_zi"):
- case Hash("sqshlu_z_p_zi"):
- case Hash("srshr_z_p_zi"):
- case Hash("uqshl_z_p_zi"):
- case Hash("urshr_z_p_zi"):
+ case "asr_z_p_zi"_h:
+ case "asrd_z_p_zi"_h:
+ case "lsl_z_p_zi"_h:
+ case "lsr_z_p_zi"_h:
+ case "sqshl_z_p_zi"_h:
+ case "sqshlu_z_p_zi"_h:
+ case "srshr_z_p_zi"_h:
+ case "uqshl_z_p_zi"_h:
+ case "urshr_z_p_zi"_h:
return (movprfx_is_unpredicated ||
((movprfx_vform ==
SVEFormatFromLaneSizeInBytesLog2(
@@ -293,187 +293,187 @@
pg_matches_low8)) &&
zd_matches;
- case Hash("fcvt_z_p_z_d2h"):
- case Hash("fcvt_z_p_z_d2s"):
- case Hash("fcvt_z_p_z_h2d"):
- case Hash("fcvt_z_p_z_s2d"):
- case Hash("fcvtx_z_p_z_d2s"):
- case Hash("fcvtzs_z_p_z_d2w"):
- case Hash("fcvtzs_z_p_z_d2x"):
- case Hash("fcvtzs_z_p_z_fp162x"):
- case Hash("fcvtzs_z_p_z_s2x"):
- case Hash("fcvtzu_z_p_z_d2w"):
- case Hash("fcvtzu_z_p_z_d2x"):
- case Hash("fcvtzu_z_p_z_fp162x"):
- case Hash("fcvtzu_z_p_z_s2x"):
- case Hash("scvtf_z_p_z_w2d"):
- case Hash("scvtf_z_p_z_x2d"):
- case Hash("scvtf_z_p_z_x2fp16"):
- case Hash("scvtf_z_p_z_x2s"):
- case Hash("ucvtf_z_p_z_w2d"):
- case Hash("ucvtf_z_p_z_x2d"):
- case Hash("ucvtf_z_p_z_x2fp16"):
- case Hash("ucvtf_z_p_z_x2s"):
+ case "fcvt_z_p_z_d2h"_h:
+ case "fcvt_z_p_z_d2s"_h:
+ case "fcvt_z_p_z_h2d"_h:
+ case "fcvt_z_p_z_s2d"_h:
+ case "fcvtx_z_p_z_d2s"_h:
+ case "fcvtzs_z_p_z_d2w"_h:
+ case "fcvtzs_z_p_z_d2x"_h:
+ case "fcvtzs_z_p_z_fp162x"_h:
+ case "fcvtzs_z_p_z_s2x"_h:
+ case "fcvtzu_z_p_z_d2w"_h:
+ case "fcvtzu_z_p_z_d2x"_h:
+ case "fcvtzu_z_p_z_fp162x"_h:
+ case "fcvtzu_z_p_z_s2x"_h:
+ case "scvtf_z_p_z_w2d"_h:
+ case "scvtf_z_p_z_x2d"_h:
+ case "scvtf_z_p_z_x2fp16"_h:
+ case "scvtf_z_p_z_x2s"_h:
+ case "ucvtf_z_p_z_w2d"_h:
+ case "ucvtf_z_p_z_x2d"_h:
+ case "ucvtf_z_p_z_x2fp16"_h:
+ case "ucvtf_z_p_z_x2s"_h:
return (movprfx_is_unpredicated ||
((movprfx_vform == kFormatVnD) && pg_matches_low8)) &&
zd_isnt_zn && zd_matches;
- case Hash("fcvtzs_z_p_z_fp162h"):
- case Hash("fcvtzu_z_p_z_fp162h"):
- case Hash("scvtf_z_p_z_h2fp16"):
- case Hash("ucvtf_z_p_z_h2fp16"):
+ case "fcvtzs_z_p_z_fp162h"_h:
+ case "fcvtzu_z_p_z_fp162h"_h:
+ case "scvtf_z_p_z_h2fp16"_h:
+ case "ucvtf_z_p_z_h2fp16"_h:
return (movprfx_is_unpredicated ||
((movprfx_vform == kFormatVnH) && pg_matches_low8)) &&
zd_isnt_zn && zd_matches;
- case Hash("fcvt_z_p_z_h2s"):
- case Hash("fcvt_z_p_z_s2h"):
- case Hash("fcvtzs_z_p_z_fp162w"):
- case Hash("fcvtzs_z_p_z_s2w"):
- case Hash("fcvtzu_z_p_z_fp162w"):
- case Hash("fcvtzu_z_p_z_s2w"):
- case Hash("scvtf_z_p_z_w2fp16"):
- case Hash("scvtf_z_p_z_w2s"):
- case Hash("ucvtf_z_p_z_w2fp16"):
- case Hash("ucvtf_z_p_z_w2s"):
+ case "fcvt_z_p_z_h2s"_h:
+ case "fcvt_z_p_z_s2h"_h:
+ case "fcvtzs_z_p_z_fp162w"_h:
+ case "fcvtzs_z_p_z_s2w"_h:
+ case "fcvtzu_z_p_z_fp162w"_h:
+ case "fcvtzu_z_p_z_s2w"_h:
+ case "scvtf_z_p_z_w2fp16"_h:
+ case "scvtf_z_p_z_w2s"_h:
+ case "ucvtf_z_p_z_w2fp16"_h:
+ case "ucvtf_z_p_z_w2s"_h:
return (movprfx_is_unpredicated ||
((movprfx_vform == kFormatVnS) && pg_matches_low8)) &&
zd_isnt_zn && zd_matches;
- case Hash("fcmla_z_p_zzz"):
- case Hash("fmad_z_p_zzz"):
- case Hash("fmla_z_p_zzz"):
- case Hash("fmls_z_p_zzz"):
- case Hash("fmsb_z_p_zzz"):
- case Hash("fnmad_z_p_zzz"):
- case Hash("fnmla_z_p_zzz"):
- case Hash("fnmls_z_p_zzz"):
- case Hash("fnmsb_z_p_zzz"):
- case Hash("mad_z_p_zzz"):
- case Hash("mla_z_p_zzz"):
- case Hash("mls_z_p_zzz"):
- case Hash("msb_z_p_zzz"):
+ case "fcmla_z_p_zzz"_h:
+ case "fmad_z_p_zzz"_h:
+ case "fmla_z_p_zzz"_h:
+ case "fmls_z_p_zzz"_h:
+ case "fmsb_z_p_zzz"_h:
+ case "fnmad_z_p_zzz"_h:
+ case "fnmla_z_p_zzz"_h:
+ case "fnmls_z_p_zzz"_h:
+ case "fnmsb_z_p_zzz"_h:
+ case "mad_z_p_zzz"_h:
+ case "mla_z_p_zzz"_h:
+ case "mls_z_p_zzz"_h:
+ case "msb_z_p_zzz"_h:
return (movprfx_is_unpredicated || (pg_matches_low8 && vform_matches)) &&
zd_isnt_zm && zd_isnt_zn && zd_matches;
- case Hash("abs_z_p_z"):
- case Hash("add_z_p_zz"):
- case Hash("and_z_p_zz"):
- case Hash("asr_z_p_zw"):
- case Hash("asr_z_p_zz"):
- case Hash("asrr_z_p_zz"):
- case Hash("bic_z_p_zz"):
- case Hash("cls_z_p_z"):
- case Hash("clz_z_p_z"):
- case Hash("cnot_z_p_z"):
- case Hash("cnt_z_p_z"):
- case Hash("cpy_z_p_v"):
- case Hash("eor_z_p_zz"):
- case Hash("fabd_z_p_zz"):
- case Hash("fabs_z_p_z"):
- case Hash("fadd_z_p_zz"):
- case Hash("fcadd_z_p_zz"):
- case Hash("fdiv_z_p_zz"):
- case Hash("fdivr_z_p_zz"):
- case Hash("fmax_z_p_zz"):
- case Hash("fmaxnm_z_p_zz"):
- case Hash("fmin_z_p_zz"):
- case Hash("fminnm_z_p_zz"):
- case Hash("fmul_z_p_zz"):
- case Hash("fmulx_z_p_zz"):
- case Hash("fneg_z_p_z"):
- case Hash("frecpx_z_p_z"):
- case Hash("frinta_z_p_z"):
- case Hash("frinti_z_p_z"):
- case Hash("frintm_z_p_z"):
- case Hash("frintn_z_p_z"):
- case Hash("frintp_z_p_z"):
- case Hash("frintx_z_p_z"):
- case Hash("frintz_z_p_z"):
- case Hash("fscale_z_p_zz"):
- case Hash("fsqrt_z_p_z"):
- case Hash("fsub_z_p_zz"):
- case Hash("fsubr_z_p_zz"):
- case Hash("lsl_z_p_zw"):
- case Hash("lsl_z_p_zz"):
- case Hash("lslr_z_p_zz"):
- case Hash("lsr_z_p_zw"):
- case Hash("lsr_z_p_zz"):
- case Hash("lsrr_z_p_zz"):
- case Hash("mul_z_p_zz"):
- case Hash("neg_z_p_z"):
- case Hash("not_z_p_z"):
- case Hash("orr_z_p_zz"):
- case Hash("rbit_z_p_z"):
- case Hash("revb_z_z"):
- case Hash("revh_z_z"):
- case Hash("revw_z_z"):
- case Hash("sabd_z_p_zz"):
- case Hash("sadalp_z_p_z"):
- case Hash("sdiv_z_p_zz"):
- case Hash("sdivr_z_p_zz"):
- case Hash("shadd_z_p_zz"):
- case Hash("shsub_z_p_zz"):
- case Hash("shsubr_z_p_zz"):
- case Hash("smax_z_p_zz"):
- case Hash("smin_z_p_zz"):
- case Hash("smulh_z_p_zz"):
- case Hash("sqabs_z_p_z"):
- case Hash("sqadd_z_p_zz"):
- case Hash("sqneg_z_p_z"):
- case Hash("sqrshl_z_p_zz"):
- case Hash("sqrshlr_z_p_zz"):
- case Hash("sqshl_z_p_zz"):
- case Hash("sqshlr_z_p_zz"):
- case Hash("sqsub_z_p_zz"):
- case Hash("sqsubr_z_p_zz"):
- case Hash("srhadd_z_p_zz"):
- case Hash("srshl_z_p_zz"):
- case Hash("srshlr_z_p_zz"):
- case Hash("sub_z_p_zz"):
- case Hash("subr_z_p_zz"):
- case Hash("suqadd_z_p_zz"):
- case Hash("sxtb_z_p_z"):
- case Hash("sxth_z_p_z"):
- case Hash("sxtw_z_p_z"):
- case Hash("uabd_z_p_zz"):
- case Hash("uadalp_z_p_z"):
- case Hash("udiv_z_p_zz"):
- case Hash("udivr_z_p_zz"):
- case Hash("uhadd_z_p_zz"):
- case Hash("uhsub_z_p_zz"):
- case Hash("uhsubr_z_p_zz"):
- case Hash("umax_z_p_zz"):
- case Hash("umin_z_p_zz"):
- case Hash("umulh_z_p_zz"):
- case Hash("uqadd_z_p_zz"):
- case Hash("uqrshl_z_p_zz"):
- case Hash("uqrshlr_z_p_zz"):
- case Hash("uqshl_z_p_zz"):
- case Hash("uqshlr_z_p_zz"):
- case Hash("uqsub_z_p_zz"):
- case Hash("uqsubr_z_p_zz"):
- case Hash("urecpe_z_p_z"):
- case Hash("urhadd_z_p_zz"):
- case Hash("urshl_z_p_zz"):
- case Hash("urshlr_z_p_zz"):
- case Hash("ursqrte_z_p_z"):
- case Hash("usqadd_z_p_zz"):
- case Hash("uxtb_z_p_z"):
- case Hash("uxth_z_p_z"):
- case Hash("uxtw_z_p_z"):
+ case "abs_z_p_z"_h:
+ case "add_z_p_zz"_h:
+ case "and_z_p_zz"_h:
+ case "asr_z_p_zw"_h:
+ case "asr_z_p_zz"_h:
+ case "asrr_z_p_zz"_h:
+ case "bic_z_p_zz"_h:
+ case "cls_z_p_z"_h:
+ case "clz_z_p_z"_h:
+ case "cnot_z_p_z"_h:
+ case "cnt_z_p_z"_h:
+ case "cpy_z_p_v"_h:
+ case "eor_z_p_zz"_h:
+ case "fabd_z_p_zz"_h:
+ case "fabs_z_p_z"_h:
+ case "fadd_z_p_zz"_h:
+ case "fcadd_z_p_zz"_h:
+ case "fdiv_z_p_zz"_h:
+ case "fdivr_z_p_zz"_h:
+ case "fmax_z_p_zz"_h:
+ case "fmaxnm_z_p_zz"_h:
+ case "fmin_z_p_zz"_h:
+ case "fminnm_z_p_zz"_h:
+ case "fmul_z_p_zz"_h:
+ case "fmulx_z_p_zz"_h:
+ case "fneg_z_p_z"_h:
+ case "frecpx_z_p_z"_h:
+ case "frinta_z_p_z"_h:
+ case "frinti_z_p_z"_h:
+ case "frintm_z_p_z"_h:
+ case "frintn_z_p_z"_h:
+ case "frintp_z_p_z"_h:
+ case "frintx_z_p_z"_h:
+ case "frintz_z_p_z"_h:
+ case "fscale_z_p_zz"_h:
+ case "fsqrt_z_p_z"_h:
+ case "fsub_z_p_zz"_h:
+ case "fsubr_z_p_zz"_h:
+ case "lsl_z_p_zw"_h:
+ case "lsl_z_p_zz"_h:
+ case "lslr_z_p_zz"_h:
+ case "lsr_z_p_zw"_h:
+ case "lsr_z_p_zz"_h:
+ case "lsrr_z_p_zz"_h:
+ case "mul_z_p_zz"_h:
+ case "neg_z_p_z"_h:
+ case "not_z_p_z"_h:
+ case "orr_z_p_zz"_h:
+ case "rbit_z_p_z"_h:
+ case "revb_z_z"_h:
+ case "revh_z_z"_h:
+ case "revw_z_z"_h:
+ case "sabd_z_p_zz"_h:
+ case "sadalp_z_p_z"_h:
+ case "sdiv_z_p_zz"_h:
+ case "sdivr_z_p_zz"_h:
+ case "shadd_z_p_zz"_h:
+ case "shsub_z_p_zz"_h:
+ case "shsubr_z_p_zz"_h:
+ case "smax_z_p_zz"_h:
+ case "smin_z_p_zz"_h:
+ case "smulh_z_p_zz"_h:
+ case "sqabs_z_p_z"_h:
+ case "sqadd_z_p_zz"_h:
+ case "sqneg_z_p_z"_h:
+ case "sqrshl_z_p_zz"_h:
+ case "sqrshlr_z_p_zz"_h:
+ case "sqshl_z_p_zz"_h:
+ case "sqshlr_z_p_zz"_h:
+ case "sqsub_z_p_zz"_h:
+ case "sqsubr_z_p_zz"_h:
+ case "srhadd_z_p_zz"_h:
+ case "srshl_z_p_zz"_h:
+ case "srshlr_z_p_zz"_h:
+ case "sub_z_p_zz"_h:
+ case "subr_z_p_zz"_h:
+ case "suqadd_z_p_zz"_h:
+ case "sxtb_z_p_z"_h:
+ case "sxth_z_p_z"_h:
+ case "sxtw_z_p_z"_h:
+ case "uabd_z_p_zz"_h:
+ case "uadalp_z_p_z"_h:
+ case "udiv_z_p_zz"_h:
+ case "udivr_z_p_zz"_h:
+ case "uhadd_z_p_zz"_h:
+ case "uhsub_z_p_zz"_h:
+ case "uhsubr_z_p_zz"_h:
+ case "umax_z_p_zz"_h:
+ case "umin_z_p_zz"_h:
+ case "umulh_z_p_zz"_h:
+ case "uqadd_z_p_zz"_h:
+ case "uqrshl_z_p_zz"_h:
+ case "uqrshlr_z_p_zz"_h:
+ case "uqshl_z_p_zz"_h:
+ case "uqshlr_z_p_zz"_h:
+ case "uqsub_z_p_zz"_h:
+ case "uqsubr_z_p_zz"_h:
+ case "urecpe_z_p_z"_h:
+ case "urhadd_z_p_zz"_h:
+ case "urshl_z_p_zz"_h:
+ case "urshlr_z_p_zz"_h:
+ case "ursqrte_z_p_z"_h:
+ case "usqadd_z_p_zz"_h:
+ case "uxtb_z_p_z"_h:
+ case "uxth_z_p_z"_h:
+ case "uxtw_z_p_z"_h:
return (movprfx_is_unpredicated || (pg_matches_low8 && vform_matches)) &&
zd_isnt_zn && zd_matches;
- case Hash("cpy_z_p_r"):
- case Hash("fadd_z_p_zs"):
- case Hash("fmax_z_p_zs"):
- case Hash("fmaxnm_z_p_zs"):
- case Hash("fmin_z_p_zs"):
- case Hash("fminnm_z_p_zs"):
- case Hash("fmul_z_p_zs"):
- case Hash("fsub_z_p_zs"):
- case Hash("fsubr_z_p_zs"):
+ case "cpy_z_p_r"_h:
+ case "fadd_z_p_zs"_h:
+ case "fmax_z_p_zs"_h:
+ case "fmaxnm_z_p_zs"_h:
+ case "fmin_z_p_zs"_h:
+ case "fminnm_z_p_zs"_h:
+ case "fmul_z_p_zs"_h:
+ case "fsub_z_p_zs"_h:
+ case "fsubr_z_p_zs"_h:
return (movprfx_is_unpredicated || (pg_matches_low8 && vform_matches)) &&
zd_matches;
default:
diff --git a/src/aarch64/instructions-aarch64.h b/src/aarch64/instructions-aarch64.h
index 6e08b32..542e96e 100644
--- a/src/aarch64/instructions-aarch64.h
+++ b/src/aarch64/instructions-aarch64.h
@@ -119,7 +119,7 @@
// We can't define a static kZRegSize because the size depends on the
// implementation. However, it is sometimes useful to know the minimum and
-// maxmimum possible sizes.
+// maximum possible sizes.
const unsigned kZRegMinSize = 128;
const unsigned kZRegMinSizeLog2 = 7;
const unsigned kZRegMinSizeInBytes = kZRegMinSize / 8;
@@ -768,7 +768,7 @@
enum SubstitutionMode { kPlaceholder, kFormat };
// Construct a format decoder with increasingly specific format maps for each
- // subsitution. If no format map is specified, the default is the integer
+ // substitution. If no format map is specified, the default is the integer
// format map.
explicit NEONFormatDecoder(const Instruction* instr) {
instrbits_ = instr->GetInstructionBits();
diff --git a/src/aarch64/logic-aarch64.cc b/src/aarch64/logic-aarch64.cc
index 61d03d6..a79780a 100644
--- a/src/aarch64/logic-aarch64.cc
+++ b/src/aarch64/logic-aarch64.cc
@@ -2299,7 +2299,7 @@
bool src1_gt_src2 = is_signed ? (src1.Int(vform, i) > src2.Int(vform, i))
: (src1.Uint(vform, i) > src2.Uint(vform, i));
// Always calculate the answer using unsigned arithmetic, to avoid
- // implemenation-defined signed overflow.
+ // implementation-defined signed overflow.
if (src1_gt_src2) {
dst.SetUint(vform, i, src1.Uint(vform, i) - src2.Uint(vform, i));
} else {
@@ -7825,7 +7825,7 @@
for (int i = 0; i < LaneCountFromFormat(vform); i++) {
// Elements outside a multiple of 4T are set to zero. This happens only
// for double precision operations, when the VL is a multiple of 128 bits,
- // but not a mutiple of 256 bits.
+ // but not a multiple of 256 bits.
T value = (i < (T_per_segment * segment_count)) ? result[i] : 0;
srcdst.SetFloat<T>(vform, i, value);
}
diff --git a/src/aarch64/operands-aarch64.h b/src/aarch64/operands-aarch64.h
index 08ee4a6..0c20367 100644
--- a/src/aarch64/operands-aarch64.h
+++ b/src/aarch64/operands-aarch64.h
@@ -873,7 +873,7 @@
return TryEncodeAsShiftedIntNForLane<N, 0>(zd, imm);
}
- // As above, but for unsigned fields. This is usuaully a simple operation, but
+ // As above, but for unsigned fields. This is usually a simple operation, but
// is provided for symmetry.
template <unsigned N, unsigned kShift, typename T>
bool TryEncodeAsShiftedUintNForLane(const CPURegister& zd, T* imm) const {
diff --git a/src/aarch64/registers-aarch64.cc b/src/aarch64/registers-aarch64.cc
index 735f43c..90201a6 100644
--- a/src/aarch64/registers-aarch64.cc
+++ b/src/aarch64/registers-aarch64.cc
@@ -122,7 +122,7 @@
IsValidPRegister();
}
-// Most coersions simply invoke the necessary constructor.
+// Most coercions simply invoke the necessary constructor.
#define VIXL_CPUREG_COERCION_LIST(U) \
U(Register, W, R) \
U(Register, X, R) \
@@ -143,7 +143,7 @@
#undef VIXL_CPUREG_COERCION_LIST
#undef VIXL_DEFINE_CPUREG_COERCION
-// NEON lane-format coersions always return VRegisters.
+// NEON lane-format coercions always return VRegisters.
#define VIXL_CPUREG_NEON_COERCION_LIST(V) \
V(8, B) \
V(16, B) \
@@ -163,7 +163,7 @@
#undef VIXL_CPUREG_NEON_COERCION_LIST
#undef VIXL_DEFINE_CPUREG_NEON_COERCION
-// Semantic type coersion for sdot and udot.
+// Semantic type coercion for sdot and udot.
// TODO: Use the qualifiers_ field to distinguish this from ::S().
VRegister VRegister::S4B() const {
VIXL_ASSERT(IsVRegister());
diff --git a/src/aarch64/registers-aarch64.h b/src/aarch64/registers-aarch64.h
index 911974a..f9a6d89 100644
--- a/src/aarch64/registers-aarch64.h
+++ b/src/aarch64/registers-aarch64.h
@@ -67,7 +67,8 @@
// specialised register types can avoid run-time checks, and should therefore be
// preferred where run-time polymorphism isn't required.
//
-// Type-specific modifers are typically implemented only on the derived classes.
+// Type-specific modifiers are typically implemented only on the derived
+// classes.
//
// The encoding is such that CPURegister objects are cheap to pass by value.
class CPURegister {
diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc
index bdb9a2f..c98fb21 100644
--- a/src/aarch64/simulator-aarch64.cc
+++ b/src/aarch64/simulator-aarch64.cc
@@ -74,363 +74,364 @@
static const FormToVisitorFnMap form_to_visitor = {
DEFAULT_FORM_TO_VISITOR_MAP(Simulator),
SIM_AUD_VISITOR_MAP(Simulator),
- {"smlal_asimdelem_l", &Simulator::SimulateNEONMulByElementLong},
- {"smlsl_asimdelem_l", &Simulator::SimulateNEONMulByElementLong},
- {"smull_asimdelem_l", &Simulator::SimulateNEONMulByElementLong},
- {"sqdmlal_asimdelem_l", &Simulator::SimulateNEONMulByElementLong},
- {"sqdmlsl_asimdelem_l", &Simulator::SimulateNEONMulByElementLong},
- {"sqdmull_asimdelem_l", &Simulator::SimulateNEONMulByElementLong},
- {"umlal_asimdelem_l", &Simulator::SimulateNEONMulByElementLong},
- {"umlsl_asimdelem_l", &Simulator::SimulateNEONMulByElementLong},
- {"umull_asimdelem_l", &Simulator::SimulateNEONMulByElementLong},
- {"fcmla_asimdelem_c_h", &Simulator::SimulateNEONComplexMulByElement},
- {"fcmla_asimdelem_c_s", &Simulator::SimulateNEONComplexMulByElement},
- {"fmlal2_asimdelem_lh", &Simulator::SimulateNEONFPMulByElementLong},
- {"fmlal_asimdelem_lh", &Simulator::SimulateNEONFPMulByElementLong},
- {"fmlsl2_asimdelem_lh", &Simulator::SimulateNEONFPMulByElementLong},
- {"fmlsl_asimdelem_lh", &Simulator::SimulateNEONFPMulByElementLong},
- {"fmla_asimdelem_rh_h", &Simulator::SimulateNEONFPMulByElement},
- {"fmls_asimdelem_rh_h", &Simulator::SimulateNEONFPMulByElement},
- {"fmulx_asimdelem_rh_h", &Simulator::SimulateNEONFPMulByElement},
- {"fmul_asimdelem_rh_h", &Simulator::SimulateNEONFPMulByElement},
- {"fmla_asimdelem_r_sd", &Simulator::SimulateNEONFPMulByElement},
- {"fmls_asimdelem_r_sd", &Simulator::SimulateNEONFPMulByElement},
- {"fmulx_asimdelem_r_sd", &Simulator::SimulateNEONFPMulByElement},
- {"fmul_asimdelem_r_sd", &Simulator::SimulateNEONFPMulByElement},
- {"sdot_asimdelem_d", &Simulator::SimulateNEONDotProdByElement},
- {"udot_asimdelem_d", &Simulator::SimulateNEONDotProdByElement},
- {"adclb_z_zzz", &Simulator::SimulateSVEAddSubCarry},
- {"adclt_z_zzz", &Simulator::SimulateSVEAddSubCarry},
- {"addhnb_z_zz", &Simulator::SimulateSVEAddSubHigh},
- {"addhnt_z_zz", &Simulator::SimulateSVEAddSubHigh},
- {"addp_z_p_zz", &Simulator::SimulateSVEIntArithPair},
- {"bcax_z_zzz", &Simulator::SimulateSVEBitwiseTernary},
- {"bdep_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmT},
- {"bext_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmT},
- {"bgrp_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmT},
- {"bsl1n_z_zzz", &Simulator::SimulateSVEBitwiseTernary},
- {"bsl2n_z_zzz", &Simulator::SimulateSVEBitwiseTernary},
- {"bsl_z_zzz", &Simulator::SimulateSVEBitwiseTernary},
- {"cadd_z_zz", &Simulator::Simulate_ZdnT_ZdnT_ZmT_const},
- {"cdot_z_zzz", &Simulator::SimulateSVEComplexDotProduct},
- {"cdot_z_zzzi_d", &Simulator::SimulateSVEComplexDotProduct},
- {"cdot_z_zzzi_s", &Simulator::SimulateSVEComplexDotProduct},
- {"cmla_z_zzz", &Simulator::SimulateSVEComplexIntMulAdd},
- {"cmla_z_zzzi_h", &Simulator::SimulateSVEComplexIntMulAdd},
- {"cmla_z_zzzi_s", &Simulator::SimulateSVEComplexIntMulAdd},
- {"eor3_z_zzz", &Simulator::SimulateSVEBitwiseTernary},
- {"eorbt_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmT},
- {"eortb_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmT},
- {"ext_z_zi_con", &Simulator::Simulate_ZdB_Zn1B_Zn2B_imm},
- {"faddp_z_p_zz", &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
- {"fcvtlt_z_p_z_h2s", &Simulator::SimulateSVEFPConvertLong},
- {"fcvtlt_z_p_z_s2d", &Simulator::SimulateSVEFPConvertLong},
- {"fcvtnt_z_p_z_d2s", &Simulator::Simulate_ZdS_PgM_ZnD},
- {"fcvtnt_z_p_z_s2h", &Simulator::Simulate_ZdH_PgM_ZnS},
- {"fcvtx_z_p_z_d2s", &Simulator::Simulate_ZdS_PgM_ZnD},
- {"fcvtxnt_z_p_z_d2s", &Simulator::Simulate_ZdS_PgM_ZnD},
- {"flogb_z_p_z", &Simulator::Simulate_ZdT_PgM_ZnT},
- {"fmaxnmp_z_p_zz", &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
- {"fmaxp_z_p_zz", &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
- {"fminnmp_z_p_zz", &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
- {"fminp_z_p_zz", &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
- {"fmlalb_z_zzz", &Simulator::Simulate_ZdaS_ZnH_ZmH},
- {"fmlalb_z_zzzi_s", &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
- {"fmlalt_z_zzz", &Simulator::Simulate_ZdaS_ZnH_ZmH},
- {"fmlalt_z_zzzi_s", &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
- {"fmlslb_z_zzz", &Simulator::Simulate_ZdaS_ZnH_ZmH},
- {"fmlslb_z_zzzi_s", &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
- {"fmlslt_z_zzz", &Simulator::Simulate_ZdaS_ZnH_ZmH},
- {"fmlslt_z_zzzi_s", &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
- {"histcnt_z_p_zz", &Simulator::Simulate_ZdT_PgZ_ZnT_ZmT},
- {"histseg_z_zz", &Simulator::Simulate_ZdB_ZnB_ZmB},
- {"ldnt1b_z_p_ar_d_64_unscaled", &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
- {"ldnt1b_z_p_ar_s_x32_unscaled", &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
- {"ldnt1d_z_p_ar_d_64_unscaled", &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
- {"ldnt1h_z_p_ar_d_64_unscaled", &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
- {"ldnt1h_z_p_ar_s_x32_unscaled", &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
- {"ldnt1sb_z_p_ar_d_64_unscaled", &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
- {"ldnt1sb_z_p_ar_s_x32_unscaled", &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
- {"ldnt1sh_z_p_ar_d_64_unscaled", &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
- {"ldnt1sh_z_p_ar_s_x32_unscaled", &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
- {"ldnt1sw_z_p_ar_d_64_unscaled", &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
- {"ldnt1w_z_p_ar_d_64_unscaled", &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
- {"ldnt1w_z_p_ar_s_x32_unscaled", &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
- {"match_p_p_zz", &Simulator::Simulate_PdT_PgZ_ZnT_ZmT},
- {"mla_z_zzzi_d", &Simulator::SimulateSVEMlaMlsIndex},
- {"mla_z_zzzi_h", &Simulator::SimulateSVEMlaMlsIndex},
- {"mla_z_zzzi_s", &Simulator::SimulateSVEMlaMlsIndex},
- {"mls_z_zzzi_d", &Simulator::SimulateSVEMlaMlsIndex},
- {"mls_z_zzzi_h", &Simulator::SimulateSVEMlaMlsIndex},
- {"mls_z_zzzi_s", &Simulator::SimulateSVEMlaMlsIndex},
- {"mul_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmT},
- {"mul_z_zzi_d", &Simulator::SimulateSVEMulIndex},
- {"mul_z_zzi_h", &Simulator::SimulateSVEMulIndex},
- {"mul_z_zzi_s", &Simulator::SimulateSVEMulIndex},
- {"nbsl_z_zzz", &Simulator::SimulateSVEBitwiseTernary},
- {"nmatch_p_p_zz", &Simulator::Simulate_PdT_PgZ_ZnT_ZmT},
- {"pmul_z_zz", &Simulator::Simulate_ZdB_ZnB_ZmB},
- {"pmullb_z_zz", &Simulator::SimulateSVEIntMulLongVec},
- {"pmullt_z_zz", &Simulator::SimulateSVEIntMulLongVec},
- {"raddhnb_z_zz", &Simulator::SimulateSVEAddSubHigh},
- {"raddhnt_z_zz", &Simulator::SimulateSVEAddSubHigh},
- {"rshrnb_z_zi", &Simulator::SimulateSVENarrow},
- {"rshrnt_z_zi", &Simulator::SimulateSVENarrow},
- {"rsubhnb_z_zz", &Simulator::SimulateSVEAddSubHigh},
- {"rsubhnt_z_zz", &Simulator::SimulateSVEAddSubHigh},
- {"saba_z_zzz", &Simulator::Simulate_ZdaT_ZnT_ZmT},
- {"sabalb_z_zzz", &Simulator::SimulateSVEInterleavedArithLong},
- {"sabalt_z_zzz", &Simulator::SimulateSVEInterleavedArithLong},
- {"sabdlb_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"sabdlt_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"sadalp_z_p_z", &Simulator::Simulate_ZdaT_PgM_ZnTb},
- {"saddlb_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"saddlbt_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"saddlt_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"saddwb_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmTb},
- {"saddwt_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmTb},
- {"sbclb_z_zzz", &Simulator::SimulateSVEAddSubCarry},
- {"sbclt_z_zzz", &Simulator::SimulateSVEAddSubCarry},
- {"shadd_z_p_zz", &Simulator::SimulateSVEHalvingAddSub},
- {"shrnb_z_zi", &Simulator::SimulateSVENarrow},
- {"shrnt_z_zi", &Simulator::SimulateSVENarrow},
- {"shsub_z_p_zz", &Simulator::SimulateSVEHalvingAddSub},
- {"shsubr_z_p_zz", &Simulator::SimulateSVEHalvingAddSub},
- {"sli_z_zzi", &Simulator::Simulate_ZdT_ZnT_const},
- {"smaxp_z_p_zz", &Simulator::SimulateSVEIntArithPair},
- {"sminp_z_p_zz", &Simulator::SimulateSVEIntArithPair},
- {"smlalb_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"smlalb_z_zzzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"smlalb_z_zzzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"smlalt_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"smlalt_z_zzzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"smlalt_z_zzzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"smlslb_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"smlslb_z_zzzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"smlslb_z_zzzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"smlslt_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"smlslt_z_zzzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"smlslt_z_zzzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"smulh_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmT},
- {"smullb_z_zz", &Simulator::SimulateSVEIntMulLongVec},
- {"smullb_z_zzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"smullb_z_zzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"smullt_z_zz", &Simulator::SimulateSVEIntMulLongVec},
- {"smullt_z_zzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"smullt_z_zzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"splice_z_p_zz_con", &Simulator::VisitSVEVectorSplice},
- {"sqabs_z_p_z", &Simulator::Simulate_ZdT_PgM_ZnT},
- {"sqadd_z_p_zz", &Simulator::SimulateSVESaturatingArithmetic},
- {"sqcadd_z_zz", &Simulator::Simulate_ZdnT_ZdnT_ZmT_const},
- {"sqdmlalb_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"sqdmlalb_z_zzzi_d", &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
- {"sqdmlalb_z_zzzi_s", &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
- {"sqdmlalbt_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"sqdmlalt_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"sqdmlalt_z_zzzi_d", &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
- {"sqdmlalt_z_zzzi_s", &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
- {"sqdmlslb_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"sqdmlslb_z_zzzi_d", &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
- {"sqdmlslb_z_zzzi_s", &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
- {"sqdmlslbt_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"sqdmlslt_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"sqdmlslt_z_zzzi_d", &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
- {"sqdmlslt_z_zzzi_s", &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
- {"sqdmulh_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmT},
- {"sqdmulh_z_zzi_d", &Simulator::SimulateSVESaturatingMulHighIndex},
- {"sqdmulh_z_zzi_h", &Simulator::SimulateSVESaturatingMulHighIndex},
- {"sqdmulh_z_zzi_s", &Simulator::SimulateSVESaturatingMulHighIndex},
- {"sqdmullb_z_zz", &Simulator::SimulateSVEIntMulLongVec},
- {"sqdmullb_z_zzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"sqdmullb_z_zzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"sqdmullt_z_zz", &Simulator::SimulateSVEIntMulLongVec},
- {"sqdmullt_z_zzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"sqdmullt_z_zzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"sqneg_z_p_z", &Simulator::Simulate_ZdT_PgM_ZnT},
- {"sqrdcmlah_z_zzz", &Simulator::SimulateSVEComplexIntMulAdd},
- {"sqrdcmlah_z_zzzi_h", &Simulator::SimulateSVEComplexIntMulAdd},
- {"sqrdcmlah_z_zzzi_s", &Simulator::SimulateSVEComplexIntMulAdd},
- {"sqrdmlah_z_zzz", &Simulator::SimulateSVESaturatingMulAddHigh},
- {"sqrdmlah_z_zzzi_d", &Simulator::SimulateSVESaturatingMulAddHigh},
- {"sqrdmlah_z_zzzi_h", &Simulator::SimulateSVESaturatingMulAddHigh},
- {"sqrdmlah_z_zzzi_s", &Simulator::SimulateSVESaturatingMulAddHigh},
- {"sqrdmlsh_z_zzz", &Simulator::SimulateSVESaturatingMulAddHigh},
- {"sqrdmlsh_z_zzzi_d", &Simulator::SimulateSVESaturatingMulAddHigh},
- {"sqrdmlsh_z_zzzi_h", &Simulator::SimulateSVESaturatingMulAddHigh},
- {"sqrdmlsh_z_zzzi_s", &Simulator::SimulateSVESaturatingMulAddHigh},
- {"sqrdmulh_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmT},
- {"sqrdmulh_z_zzi_d", &Simulator::SimulateSVESaturatingMulHighIndex},
- {"sqrdmulh_z_zzi_h", &Simulator::SimulateSVESaturatingMulHighIndex},
- {"sqrdmulh_z_zzi_s", &Simulator::SimulateSVESaturatingMulHighIndex},
- {"sqrshl_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"sqrshlr_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"sqrshrnb_z_zi", &Simulator::SimulateSVENarrow},
- {"sqrshrnt_z_zi", &Simulator::SimulateSVENarrow},
- {"sqrshrunb_z_zi", &Simulator::SimulateSVENarrow},
- {"sqrshrunt_z_zi", &Simulator::SimulateSVENarrow},
- {"sqshl_z_p_zi", &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
- {"sqshl_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"sqshlr_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"sqshlu_z_p_zi", &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
- {"sqshrnb_z_zi", &Simulator::SimulateSVENarrow},
- {"sqshrnt_z_zi", &Simulator::SimulateSVENarrow},
- {"sqshrunb_z_zi", &Simulator::SimulateSVENarrow},
- {"sqshrunt_z_zi", &Simulator::SimulateSVENarrow},
- {"sqsub_z_p_zz", &Simulator::SimulateSVESaturatingArithmetic},
- {"sqsubr_z_p_zz", &Simulator::SimulateSVESaturatingArithmetic},
- {"sqxtnb_z_zz", &Simulator::SimulateSVENarrow},
- {"sqxtnt_z_zz", &Simulator::SimulateSVENarrow},
- {"sqxtunb_z_zz", &Simulator::SimulateSVENarrow},
- {"sqxtunt_z_zz", &Simulator::SimulateSVENarrow},
- {"srhadd_z_p_zz", &Simulator::SimulateSVEHalvingAddSub},
- {"sri_z_zzi", &Simulator::Simulate_ZdT_ZnT_const},
- {"srshl_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"srshlr_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"srshr_z_p_zi", &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
- {"srsra_z_zi", &Simulator::Simulate_ZdaT_ZnT_const},
- {"sshllb_z_zi", &Simulator::SimulateSVEShiftLeftImm},
- {"sshllt_z_zi", &Simulator::SimulateSVEShiftLeftImm},
- {"ssra_z_zi", &Simulator::Simulate_ZdaT_ZnT_const},
- {"ssublb_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"ssublbt_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"ssublt_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"ssubltb_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"ssubwb_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmTb},
- {"ssubwt_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmTb},
- {"stnt1b_z_p_ar_d_64_unscaled", &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
- {"stnt1b_z_p_ar_s_x32_unscaled", &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
- {"stnt1d_z_p_ar_d_64_unscaled", &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
- {"stnt1h_z_p_ar_d_64_unscaled", &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
- {"stnt1h_z_p_ar_s_x32_unscaled", &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
- {"stnt1w_z_p_ar_d_64_unscaled", &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
- {"stnt1w_z_p_ar_s_x32_unscaled", &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
- {"subhnb_z_zz", &Simulator::SimulateSVEAddSubHigh},
- {"subhnt_z_zz", &Simulator::SimulateSVEAddSubHigh},
- {"suqadd_z_p_zz", &Simulator::SimulateSVESaturatingArithmetic},
- {"tbl_z_zz_2", &Simulator::VisitSVETableLookup},
- {"tbx_z_zz", &Simulator::VisitSVETableLookup},
- {"uaba_z_zzz", &Simulator::Simulate_ZdaT_ZnT_ZmT},
- {"uabalb_z_zzz", &Simulator::SimulateSVEInterleavedArithLong},
- {"uabalt_z_zzz", &Simulator::SimulateSVEInterleavedArithLong},
- {"uabdlb_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"uabdlt_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"uadalp_z_p_z", &Simulator::Simulate_ZdaT_PgM_ZnTb},
- {"uaddlb_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"uaddlt_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"uaddwb_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmTb},
- {"uaddwt_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmTb},
- {"uhadd_z_p_zz", &Simulator::SimulateSVEHalvingAddSub},
- {"uhsub_z_p_zz", &Simulator::SimulateSVEHalvingAddSub},
- {"uhsubr_z_p_zz", &Simulator::SimulateSVEHalvingAddSub},
- {"umaxp_z_p_zz", &Simulator::SimulateSVEIntArithPair},
- {"uminp_z_p_zz", &Simulator::SimulateSVEIntArithPair},
- {"umlalb_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"umlalb_z_zzzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"umlalb_z_zzzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"umlalt_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"umlalt_z_zzzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"umlalt_z_zzzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"umlslb_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"umlslb_z_zzzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"umlslb_z_zzzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"umlslt_z_zzz", &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
- {"umlslt_z_zzzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"umlslt_z_zzzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"umulh_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmT},
- {"umullb_z_zz", &Simulator::SimulateSVEIntMulLongVec},
- {"umullb_z_zzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"umullb_z_zzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"umullt_z_zz", &Simulator::SimulateSVEIntMulLongVec},
- {"umullt_z_zzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"umullt_z_zzi_s", &Simulator::SimulateSVESaturatingIntMulLongIdx},
- {"uqadd_z_p_zz", &Simulator::SimulateSVESaturatingArithmetic},
- {"uqrshl_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"uqrshlr_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"uqrshrnb_z_zi", &Simulator::SimulateSVENarrow},
- {"uqrshrnt_z_zi", &Simulator::SimulateSVENarrow},
- {"uqshl_z_p_zi", &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
- {"uqshl_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"uqshlr_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"uqshrnb_z_zi", &Simulator::SimulateSVENarrow},
- {"uqshrnt_z_zi", &Simulator::SimulateSVENarrow},
- {"uqsub_z_p_zz", &Simulator::SimulateSVESaturatingArithmetic},
- {"uqsubr_z_p_zz", &Simulator::SimulateSVESaturatingArithmetic},
- {"uqxtnb_z_zz", &Simulator::SimulateSVENarrow},
- {"uqxtnt_z_zz", &Simulator::SimulateSVENarrow},
- {"urecpe_z_p_z", &Simulator::Simulate_ZdS_PgM_ZnS},
- {"urhadd_z_p_zz", &Simulator::SimulateSVEHalvingAddSub},
- {"urshl_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"urshlr_z_p_zz", &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
- {"urshr_z_p_zi", &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
- {"ursqrte_z_p_z", &Simulator::Simulate_ZdS_PgM_ZnS},
- {"ursra_z_zi", &Simulator::Simulate_ZdaT_ZnT_const},
- {"ushllb_z_zi", &Simulator::SimulateSVEShiftLeftImm},
- {"ushllt_z_zi", &Simulator::SimulateSVEShiftLeftImm},
- {"usqadd_z_p_zz", &Simulator::SimulateSVESaturatingArithmetic},
- {"usra_z_zi", &Simulator::Simulate_ZdaT_ZnT_const},
- {"usublb_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"usublt_z_zz", &Simulator::SimulateSVEInterleavedArithLong},
- {"usubwb_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmTb},
- {"usubwt_z_zz", &Simulator::Simulate_ZdT_ZnT_ZmTb},
- {"whilege_p_p_rr", &Simulator::VisitSVEIntCompareScalarCountAndLimit},
- {"whilegt_p_p_rr", &Simulator::VisitSVEIntCompareScalarCountAndLimit},
- {"whilehi_p_p_rr", &Simulator::VisitSVEIntCompareScalarCountAndLimit},
- {"whilehs_p_p_rr", &Simulator::VisitSVEIntCompareScalarCountAndLimit},
- {"whilerw_p_rr", &Simulator::Simulate_PdT_Xn_Xm},
- {"whilewr_p_rr", &Simulator::Simulate_PdT_Xn_Xm},
- {"xar_z_zzi", &Simulator::SimulateSVEExclusiveOrRotate},
- {"smmla_z_zzz", &Simulator::SimulateMatrixMul},
- {"ummla_z_zzz", &Simulator::SimulateMatrixMul},
- {"usmmla_z_zzz", &Simulator::SimulateMatrixMul},
- {"smmla_asimdsame2_g", &Simulator::SimulateMatrixMul},
- {"ummla_asimdsame2_g", &Simulator::SimulateMatrixMul},
- {"usmmla_asimdsame2_g", &Simulator::SimulateMatrixMul},
- {"fmmla_z_zzz_s", &Simulator::SimulateSVEFPMatrixMul},
- {"fmmla_z_zzz_d", &Simulator::SimulateSVEFPMatrixMul},
- {"ld1row_z_p_bi_u32",
+ {"smlal_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
+ {"smlsl_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
+ {"smull_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
+ {"sqdmlal_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
+ {"sqdmlsl_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
+ {"sqdmull_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
+ {"umlal_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
+ {"umlsl_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
+ {"umull_asimdelem_l"_h, &Simulator::SimulateNEONMulByElementLong},
+ {"fcmla_asimdelem_c_h"_h, &Simulator::SimulateNEONComplexMulByElement},
+ {"fcmla_asimdelem_c_s"_h, &Simulator::SimulateNEONComplexMulByElement},
+ {"fmlal2_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
+ {"fmlal_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
+ {"fmlsl2_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
+ {"fmlsl_asimdelem_lh"_h, &Simulator::SimulateNEONFPMulByElementLong},
+ {"fmla_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
+ {"fmls_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
+ {"fmulx_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
+ {"fmul_asimdelem_rh_h"_h, &Simulator::SimulateNEONFPMulByElement},
+ {"fmla_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
+ {"fmls_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
+ {"fmulx_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
+ {"fmul_asimdelem_r_sd"_h, &Simulator::SimulateNEONFPMulByElement},
+ {"sdot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
+ {"udot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
+ {"adclb_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
+ {"adclt_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
+ {"addhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
+ {"addhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
+ {"addp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
+ {"bcax_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
+ {"bdep_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
+ {"bext_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
+ {"bgrp_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
+ {"bsl1n_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
+ {"bsl2n_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
+ {"bsl_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
+ {"cadd_z_zz"_h, &Simulator::Simulate_ZdnT_ZdnT_ZmT_const},
+ {"cdot_z_zzz"_h, &Simulator::SimulateSVEComplexDotProduct},
+ {"cdot_z_zzzi_d"_h, &Simulator::SimulateSVEComplexDotProduct},
+ {"cdot_z_zzzi_s"_h, &Simulator::SimulateSVEComplexDotProduct},
+ {"cmla_z_zzz"_h, &Simulator::SimulateSVEComplexIntMulAdd},
+ {"cmla_z_zzzi_h"_h, &Simulator::SimulateSVEComplexIntMulAdd},
+ {"cmla_z_zzzi_s"_h, &Simulator::SimulateSVEComplexIntMulAdd},
+ {"eor3_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
+ {"eorbt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
+ {"eortb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
+ {"ext_z_zi_con"_h, &Simulator::Simulate_ZdB_Zn1B_Zn2B_imm},
+ {"faddp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
+ {"fcvtlt_z_p_z_h2s"_h, &Simulator::SimulateSVEFPConvertLong},
+ {"fcvtlt_z_p_z_s2d"_h, &Simulator::SimulateSVEFPConvertLong},
+ {"fcvtnt_z_p_z_d2s"_h, &Simulator::Simulate_ZdS_PgM_ZnD},
+ {"fcvtnt_z_p_z_s2h"_h, &Simulator::Simulate_ZdH_PgM_ZnS},
+ {"fcvtx_z_p_z_d2s"_h, &Simulator::Simulate_ZdS_PgM_ZnD},
+ {"fcvtxnt_z_p_z_d2s"_h, &Simulator::Simulate_ZdS_PgM_ZnD},
+ {"flogb_z_p_z"_h, &Simulator::Simulate_ZdT_PgM_ZnT},
+ {"fmaxnmp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
+ {"fmaxp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
+ {"fminnmp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
+ {"fminp_z_p_zz"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_ZmT},
+ {"fmlalb_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
+ {"fmlalb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
+ {"fmlalt_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
+ {"fmlalt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
+ {"fmlslb_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
+ {"fmlslb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
+ {"fmlslt_z_zzz"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH},
+ {"fmlslt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
+ {"histcnt_z_p_zz"_h, &Simulator::Simulate_ZdT_PgZ_ZnT_ZmT},
+ {"histseg_z_zz"_h, &Simulator::Simulate_ZdB_ZnB_ZmB},
+ {"ldnt1b_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
+ {"ldnt1b_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
+ {"ldnt1d_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
+ {"ldnt1h_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
+ {"ldnt1h_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
+ {"ldnt1sb_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
+ {"ldnt1sb_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
+ {"ldnt1sh_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
+ {"ldnt1sh_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
+ {"ldnt1sw_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
+ {"ldnt1w_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_PgZ_ZnD_Xm},
+ {"ldnt1w_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_PgZ_ZnS_Xm},
+ {"match_p_p_zz"_h, &Simulator::Simulate_PdT_PgZ_ZnT_ZmT},
+ {"mla_z_zzzi_d"_h, &Simulator::SimulateSVEMlaMlsIndex},
+ {"mla_z_zzzi_h"_h, &Simulator::SimulateSVEMlaMlsIndex},
+ {"mla_z_zzzi_s"_h, &Simulator::SimulateSVEMlaMlsIndex},
+ {"mls_z_zzzi_d"_h, &Simulator::SimulateSVEMlaMlsIndex},
+ {"mls_z_zzzi_h"_h, &Simulator::SimulateSVEMlaMlsIndex},
+ {"mls_z_zzzi_s"_h, &Simulator::SimulateSVEMlaMlsIndex},
+ {"mul_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
+ {"mul_z_zzi_d"_h, &Simulator::SimulateSVEMulIndex},
+ {"mul_z_zzi_h"_h, &Simulator::SimulateSVEMulIndex},
+ {"mul_z_zzi_s"_h, &Simulator::SimulateSVEMulIndex},
+ {"nbsl_z_zzz"_h, &Simulator::SimulateSVEBitwiseTernary},
+ {"nmatch_p_p_zz"_h, &Simulator::Simulate_PdT_PgZ_ZnT_ZmT},
+ {"pmul_z_zz"_h, &Simulator::Simulate_ZdB_ZnB_ZmB},
+ {"pmullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
+ {"pmullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
+ {"raddhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
+ {"raddhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
+ {"rshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"rshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"rsubhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
+ {"rsubhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
+ {"saba_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnT_ZmT},
+ {"sabalb_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"sabalt_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"sabdlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"sabdlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"sadalp_z_p_z"_h, &Simulator::Simulate_ZdaT_PgM_ZnTb},
+ {"saddlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"saddlbt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"saddlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"saddwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
+ {"saddwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
+ {"sbclb_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
+ {"sbclt_z_zzz"_h, &Simulator::SimulateSVEAddSubCarry},
+ {"shadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
+ {"shrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"shrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"shsub_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
+ {"shsubr_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
+ {"sli_z_zzi"_h, &Simulator::Simulate_ZdT_ZnT_const},
+ {"smaxp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
+ {"sminp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
+ {"smlalb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"smlalb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"smlalb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"smlalt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"smlalt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"smlalt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"smlslb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"smlslb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"smlslb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"smlslt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"smlslt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"smlslt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"smulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
+ {"smullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
+ {"smullb_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"smullb_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"smullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
+ {"smullt_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"smullt_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"splice_z_p_zz_con"_h, &Simulator::VisitSVEVectorSplice},
+ {"sqabs_z_p_z"_h, &Simulator::Simulate_ZdT_PgM_ZnT},
+ {"sqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
+ {"sqcadd_z_zz"_h, &Simulator::Simulate_ZdnT_ZdnT_ZmT_const},
+ {"sqdmlalb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"sqdmlalb_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
+ {"sqdmlalb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
+ {"sqdmlalbt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"sqdmlalt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"sqdmlalt_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
+ {"sqdmlalt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
+ {"sqdmlslb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"sqdmlslb_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
+ {"sqdmlslb_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
+ {"sqdmlslbt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"sqdmlslt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"sqdmlslt_z_zzzi_d"_h, &Simulator::Simulate_ZdaD_ZnS_ZmS_imm},
+ {"sqdmlslt_z_zzzi_s"_h, &Simulator::Simulate_ZdaS_ZnH_ZmH_imm},
+ {"sqdmulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
+ {"sqdmulh_z_zzi_d"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
+ {"sqdmulh_z_zzi_h"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
+ {"sqdmulh_z_zzi_s"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
+ {"sqdmullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
+ {"sqdmullb_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"sqdmullb_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"sqdmullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
+ {"sqdmullt_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"sqdmullt_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"sqneg_z_p_z"_h, &Simulator::Simulate_ZdT_PgM_ZnT},
+ {"sqrdcmlah_z_zzz"_h, &Simulator::SimulateSVEComplexIntMulAdd},
+ {"sqrdcmlah_z_zzzi_h"_h, &Simulator::SimulateSVEComplexIntMulAdd},
+ {"sqrdcmlah_z_zzzi_s"_h, &Simulator::SimulateSVEComplexIntMulAdd},
+ {"sqrdmlah_z_zzz"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
+ {"sqrdmlah_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
+ {"sqrdmlah_z_zzzi_h"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
+ {"sqrdmlah_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
+ {"sqrdmlsh_z_zzz"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
+ {"sqrdmlsh_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
+ {"sqrdmlsh_z_zzzi_h"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
+ {"sqrdmlsh_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingMulAddHigh},
+ {"sqrdmulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
+ {"sqrdmulh_z_zzi_d"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
+ {"sqrdmulh_z_zzi_h"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
+ {"sqrdmulh_z_zzi_s"_h, &Simulator::SimulateSVESaturatingMulHighIndex},
+ {"sqrshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"sqrshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"sqrshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"sqrshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"sqrshrunb_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"sqrshrunt_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"sqshl_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
+ {"sqshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"sqshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"sqshlu_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
+ {"sqshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"sqshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"sqshrunb_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"sqshrunt_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"sqsub_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
+ {"sqsubr_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
+ {"sqxtnb_z_zz"_h, &Simulator::SimulateSVENarrow},
+ {"sqxtnt_z_zz"_h, &Simulator::SimulateSVENarrow},
+ {"sqxtunb_z_zz"_h, &Simulator::SimulateSVENarrow},
+ {"sqxtunt_z_zz"_h, &Simulator::SimulateSVENarrow},
+ {"srhadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
+ {"sri_z_zzi"_h, &Simulator::Simulate_ZdT_ZnT_const},
+ {"srshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"srshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"srshr_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
+ {"srsra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
+ {"sshllb_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
+ {"sshllt_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
+ {"ssra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
+ {"ssublb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"ssublbt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"ssublt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"ssubltb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"ssubwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
+ {"ssubwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
+ {"stnt1b_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
+ {"stnt1b_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
+ {"stnt1d_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
+ {"stnt1h_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
+ {"stnt1h_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
+ {"stnt1w_z_p_ar_d_64_unscaled"_h, &Simulator::Simulate_ZtD_Pg_ZnD_Xm},
+ {"stnt1w_z_p_ar_s_x32_unscaled"_h, &Simulator::Simulate_ZtS_Pg_ZnS_Xm},
+ {"subhnb_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
+ {"subhnt_z_zz"_h, &Simulator::SimulateSVEAddSubHigh},
+ {"suqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
+ {"tbl_z_zz_2"_h, &Simulator::VisitSVETableLookup},
+ {"tbx_z_zz"_h, &Simulator::VisitSVETableLookup},
+ {"uaba_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnT_ZmT},
+ {"uabalb_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"uabalt_z_zzz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"uabdlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"uabdlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"uadalp_z_p_z"_h, &Simulator::Simulate_ZdaT_PgM_ZnTb},
+ {"uaddlb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"uaddlt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"uaddwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
+ {"uaddwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
+ {"uhadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
+ {"uhsub_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
+ {"uhsubr_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
+ {"umaxp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
+ {"uminp_z_p_zz"_h, &Simulator::SimulateSVEIntArithPair},
+ {"umlalb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"umlalb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"umlalb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"umlalt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"umlalt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"umlalt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"umlslb_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"umlslb_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"umlslb_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"umlslt_z_zzz"_h, &Simulator::Simulate_ZdaT_ZnTb_ZmTb},
+ {"umlslt_z_zzzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"umlslt_z_zzzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"umulh_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmT},
+ {"umullb_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
+ {"umullb_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"umullb_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"umullt_z_zz"_h, &Simulator::SimulateSVEIntMulLongVec},
+ {"umullt_z_zzi_d"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"umullt_z_zzi_s"_h, &Simulator::SimulateSVESaturatingIntMulLongIdx},
+ {"uqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
+ {"uqrshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"uqrshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"uqrshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"uqrshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"uqshl_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
+ {"uqshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"uqshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"uqshrnb_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"uqshrnt_z_zi"_h, &Simulator::SimulateSVENarrow},
+ {"uqsub_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
+ {"uqsubr_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
+ {"uqxtnb_z_zz"_h, &Simulator::SimulateSVENarrow},
+ {"uqxtnt_z_zz"_h, &Simulator::SimulateSVENarrow},
+ {"urecpe_z_p_z"_h, &Simulator::Simulate_ZdS_PgM_ZnS},
+ {"urhadd_z_p_zz"_h, &Simulator::SimulateSVEHalvingAddSub},
+ {"urshl_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"urshlr_z_p_zz"_h, &Simulator::VisitSVEBitwiseShiftByVector_Predicated},
+ {"urshr_z_p_zi"_h, &Simulator::Simulate_ZdnT_PgM_ZdnT_const},
+ {"ursqrte_z_p_z"_h, &Simulator::Simulate_ZdS_PgM_ZnS},
+ {"ursra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
+ {"ushllb_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
+ {"ushllt_z_zi"_h, &Simulator::SimulateSVEShiftLeftImm},
+ {"usqadd_z_p_zz"_h, &Simulator::SimulateSVESaturatingArithmetic},
+ {"usra_z_zi"_h, &Simulator::Simulate_ZdaT_ZnT_const},
+ {"usublb_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"usublt_z_zz"_h, &Simulator::SimulateSVEInterleavedArithLong},
+ {"usubwb_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
+ {"usubwt_z_zz"_h, &Simulator::Simulate_ZdT_ZnT_ZmTb},
+ {"whilege_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
+ {"whilegt_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
+ {"whilehi_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
+ {"whilehs_p_p_rr"_h, &Simulator::VisitSVEIntCompareScalarCountAndLimit},
+ {"whilerw_p_rr"_h, &Simulator::Simulate_PdT_Xn_Xm},
+ {"whilewr_p_rr"_h, &Simulator::Simulate_PdT_Xn_Xm},
+ {"xar_z_zzi"_h, &Simulator::SimulateSVEExclusiveOrRotate},
+ {"smmla_z_zzz"_h, &Simulator::SimulateMatrixMul},
+ {"ummla_z_zzz"_h, &Simulator::SimulateMatrixMul},
+ {"usmmla_z_zzz"_h, &Simulator::SimulateMatrixMul},
+ {"smmla_asimdsame2_g"_h, &Simulator::SimulateMatrixMul},
+ {"ummla_asimdsame2_g"_h, &Simulator::SimulateMatrixMul},
+ {"usmmla_asimdsame2_g"_h, &Simulator::SimulateMatrixMul},
+ {"fmmla_z_zzz_s"_h, &Simulator::SimulateSVEFPMatrixMul},
+ {"fmmla_z_zzz_d"_h, &Simulator::SimulateSVEFPMatrixMul},
+ {"ld1row_z_p_bi_u32"_h,
&Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
- {"ld1row_z_p_br_contiguous",
+ {"ld1row_z_p_br_contiguous"_h,
&Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
- {"ld1rod_z_p_bi_u64",
+ {"ld1rod_z_p_bi_u64"_h,
&Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
- {"ld1rod_z_p_br_contiguous",
+ {"ld1rod_z_p_br_contiguous"_h,
&Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
- {"ld1rob_z_p_bi_u8",
+ {"ld1rob_z_p_bi_u8"_h,
&Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
- {"ld1rob_z_p_br_contiguous",
+ {"ld1rob_z_p_br_contiguous"_h,
&Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
- {"ld1roh_z_p_bi_u16",
+ {"ld1roh_z_p_bi_u16"_h,
&Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusImm},
- {"ld1roh_z_p_br_contiguous",
+ {"ld1roh_z_p_br_contiguous"_h,
&Simulator::VisitSVELoadAndBroadcastQOWord_ScalarPlusScalar},
- {"usdot_z_zzz_s", &Simulator::VisitSVEIntMulAddUnpredicated},
- {"sudot_z_zzzi_s", &Simulator::VisitSVEMulIndex},
- {"usdot_z_zzzi_s", &Simulator::VisitSVEMulIndex},
- {"usdot_asimdsame2_d", &Simulator::VisitNEON3SameExtra},
- {"sudot_asimdelem_d", &Simulator::SimulateNEONDotProdByElement},
- {"usdot_asimdelem_d", &Simulator::SimulateNEONDotProdByElement},
- {"addg_64_addsub_immtags", &Simulator::SimulateMTEAddSubTag},
- {"gmi_64g_dp_2src", &Simulator::SimulateMTETagMaskInsert},
- {"irg_64i_dp_2src", &Simulator::Simulate_XdSP_XnSP_Xm},
- {"ldg_64loffset_ldsttags", &Simulator::SimulateMTELoadTag},
- {"st2g_64soffset_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"st2g_64spost_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"st2g_64spre_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"stgp_64_ldstpair_off", &Simulator::SimulateMTEStoreTagPair},
- {"stgp_64_ldstpair_post", &Simulator::SimulateMTEStoreTagPair},
- {"stgp_64_ldstpair_pre", &Simulator::SimulateMTEStoreTagPair},
- {"stg_64soffset_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"stg_64spost_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"stg_64spre_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"stz2g_64soffset_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"stz2g_64spost_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"stz2g_64spre_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"stzg_64soffset_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"stzg_64spost_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"stzg_64spre_ldsttags", &Simulator::Simulator::SimulateMTEStoreTag},
- {"subg_64_addsub_immtags", &Simulator::SimulateMTEAddSubTag},
- {"subps_64s_dp_2src", &Simulator::SimulateMTESubPointer},
- {"subp_64s_dp_2src", &Simulator::SimulateMTESubPointer},
+ {"usdot_z_zzz_s"_h, &Simulator::VisitSVEIntMulAddUnpredicated},
+ {"sudot_z_zzzi_s"_h, &Simulator::VisitSVEMulIndex},
+ {"usdot_z_zzzi_s"_h, &Simulator::VisitSVEMulIndex},
+ {"usdot_asimdsame2_d"_h, &Simulator::VisitNEON3SameExtra},
+ {"sudot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
+ {"usdot_asimdelem_d"_h, &Simulator::SimulateNEONDotProdByElement},
+ {"addg_64_addsub_immtags"_h, &Simulator::SimulateMTEAddSubTag},
+ {"gmi_64g_dp_2src"_h, &Simulator::SimulateMTETagMaskInsert},
+ {"irg_64i_dp_2src"_h, &Simulator::Simulate_XdSP_XnSP_Xm},
+ {"ldg_64loffset_ldsttags"_h, &Simulator::SimulateMTELoadTag},
+ {"st2g_64soffset_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
+ {"st2g_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
+ {"st2g_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
+ {"stgp_64_ldstpair_off"_h, &Simulator::SimulateMTEStoreTagPair},
+ {"stgp_64_ldstpair_post"_h, &Simulator::SimulateMTEStoreTagPair},
+ {"stgp_64_ldstpair_pre"_h, &Simulator::SimulateMTEStoreTagPair},
+ {"stg_64soffset_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
+ {"stg_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
+ {"stg_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
+ {"stz2g_64soffset_ldsttags"_h,
+ &Simulator::Simulator::SimulateMTEStoreTag},
+ {"stz2g_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
+ {"stz2g_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
+ {"stzg_64soffset_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
+ {"stzg_64spost_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
+ {"stzg_64spre_ldsttags"_h, &Simulator::Simulator::SimulateMTEStoreTag},
+ {"subg_64_addsub_immtags"_h, &Simulator::SimulateMTEAddSubTag},
+ {"subps_64s_dp_2src"_h, &Simulator::SimulateMTESubPointer},
+ {"subp_64s_dp_2src"_h, &Simulator::SimulateMTESubPointer},
};
return &form_to_visitor;
}
@@ -925,7 +926,7 @@
bool is_negative = (uvalue & GetSignMask(reg_size)) != 0;
// The behavior is undefined in c++ if the shift amount greater than or
// equal to the register lane size. Work out the shifted result based on
- // architectural behavior before performing the c++ type shfit operations.
+ // architectural behavior before performing the c++ type shift operations.
switch (shift_type) {
case LSL:
if (amount >= reg_size) {
@@ -2005,12 +2006,13 @@
void Simulator::Visit(Metadata* metadata, const Instruction* instr) {
VIXL_ASSERT(metadata->count("form") > 0);
std::string form = (*metadata)["form"];
+ form_hash_ = Hash(form.c_str());
const FormToVisitorFnMap* fv = Simulator::GetFormToVisitorFnMap();
- if ((fv->count(form) > 0) && fv->at(form)) {
- form_hash_ = Hash(form.c_str());
- fv->at(form)(this, instr);
- } else {
+ FormToVisitorFnMap::const_iterator it = fv->find(form_hash_);
+ if (it == fv->end()) {
VisitUnimplemented(instr);
+ } else {
+ (it->second)(this, instr);
}
}
@@ -2022,10 +2024,10 @@
SimVRegister& zn = ReadVRegister(instr->GetRn());
switch (form_hash_) {
- case Hash("match_p_p_zz"):
+ case "match_p_p_zz"_h:
match(vform, pd, zn, zm, /* negate_match = */ false);
break;
- case Hash("nmatch_p_p_zz"):
+ case "nmatch_p_p_zz"_h:
match(vform, pd, zn, zm, /* negate_match = */ true);
break;
default:
@@ -2046,10 +2048,10 @@
bool no_conflict = false;
switch (form_hash_) {
- case Hash("whilerw_p_rr"):
+ case "whilerw_p_rr"_h:
no_conflict = (absdiff == 0);
break;
- case Hash("whilewr_p_rr"):
+ case "whilewr_p_rr"_h:
no_conflict = (absdiff == 0) || (src2 <= src1);
break;
default:
@@ -2067,7 +2069,7 @@
}
void Simulator::Simulate_ZdB_Zn1B_Zn2B_imm(const Instruction* instr) {
- VIXL_ASSERT(form_hash_ == Hash("ext_z_zi_con"));
+ VIXL_ASSERT(form_hash_ == "ext_z_zi_con"_h);
SimVRegister& zd = ReadVRegister(instr->GetRd());
SimVRegister& zn = ReadVRegister(instr->GetRn());
@@ -2086,7 +2088,7 @@
SimVRegister& zn = ReadVRegister(instr->GetRn());
switch (form_hash_) {
- case Hash("histseg_z_zz"):
+ case "histseg_z_zz"_h:
if (instr->GetSVEVectorFormat() == kFormatVnB) {
histogram(kFormatVnB,
zd,
@@ -2098,7 +2100,7 @@
VIXL_UNIMPLEMENTED();
}
break;
- case Hash("pmul_z_zz"):
+ case "pmul_z_zz"_h:
pmul(kFormatVnB, zd, zn, zm);
break;
default:
@@ -2116,9 +2118,9 @@
// supported.
if (vform == kFormatVnB) vform = kFormatVnH;
- VIXL_ASSERT((form_hash_ == Hash("mul_z_zzi_d")) ||
- (form_hash_ == Hash("mul_z_zzi_h")) ||
- (form_hash_ == Hash("mul_z_zzi_s")));
+ VIXL_ASSERT((form_hash_ == "mul_z_zzi_d"_h) ||
+ (form_hash_ == "mul_z_zzi_h"_h) ||
+ (form_hash_ == "mul_z_zzi_s"_h));
SimVRegister temp;
dup_elements_to_segments(vform, temp, instr->GetSVEMulZmAndIndex());
@@ -2135,12 +2137,10 @@
// supported.
if (vform == kFormatVnB) vform = kFormatVnH;
- VIXL_ASSERT((form_hash_ == Hash("mla_z_zzzi_d")) ||
- (form_hash_ == Hash("mla_z_zzzi_h")) ||
- (form_hash_ == Hash("mla_z_zzzi_s")) ||
- (form_hash_ == Hash("mls_z_zzzi_d")) ||
- (form_hash_ == Hash("mls_z_zzzi_h")) ||
- (form_hash_ == Hash("mls_z_zzzi_s")));
+ VIXL_ASSERT(
+ (form_hash_ == "mla_z_zzzi_d"_h) || (form_hash_ == "mla_z_zzzi_h"_h) ||
+ (form_hash_ == "mla_z_zzzi_s"_h) || (form_hash_ == "mls_z_zzzi_d"_h) ||
+ (form_hash_ == "mls_z_zzzi_h"_h) || (form_hash_ == "mls_z_zzzi_s"_h));
SimVRegister temp;
dup_elements_to_segments(vform, temp, instr->GetSVEMulZmAndIndex());
@@ -2166,14 +2166,14 @@
SimVRegister temp;
dup_elements_to_segments(vform, temp, instr->GetSVEMulZmAndIndex());
switch (form_hash_) {
- case Hash("sqdmulh_z_zzi_h"):
- case Hash("sqdmulh_z_zzi_s"):
- case Hash("sqdmulh_z_zzi_d"):
+ case "sqdmulh_z_zzi_h"_h:
+ case "sqdmulh_z_zzi_s"_h:
+ case "sqdmulh_z_zzi_d"_h:
sqdmulh(vform, zd, zn, temp);
break;
- case Hash("sqrdmulh_z_zzi_h"):
- case Hash("sqrdmulh_z_zzi_s"):
- case Hash("sqrdmulh_z_zzi_d"):
+ case "sqrdmulh_z_zzi_h"_h:
+ case "sqrdmulh_z_zzi_s"_h:
+ case "sqrdmulh_z_zzi_d"_h:
sqrdmulh(vform, zd, zn, temp);
break;
default:
@@ -2199,64 +2199,64 @@
pack_odd_elements(vform_half, zn_t, zn);
switch (form_hash_) {
- case Hash("smullb_z_zzi_s"):
- case Hash("smullb_z_zzi_d"):
+ case "smullb_z_zzi_s"_h:
+ case "smullb_z_zzi_d"_h:
smull(vform, zd, zn_b, zm_idx);
break;
- case Hash("smullt_z_zzi_s"):
- case Hash("smullt_z_zzi_d"):
+ case "smullt_z_zzi_s"_h:
+ case "smullt_z_zzi_d"_h:
smull(vform, zd, zn_t, zm_idx);
break;
- case Hash("sqdmullb_z_zzi_d"):
+ case "sqdmullb_z_zzi_d"_h:
sqdmull(vform, zd, zn_b, zm_idx);
break;
- case Hash("sqdmullt_z_zzi_d"):
+ case "sqdmullt_z_zzi_d"_h:
sqdmull(vform, zd, zn_t, zm_idx);
break;
- case Hash("umullb_z_zzi_s"):
- case Hash("umullb_z_zzi_d"):
+ case "umullb_z_zzi_s"_h:
+ case "umullb_z_zzi_d"_h:
umull(vform, zd, zn_b, zm_idx);
break;
- case Hash("umullt_z_zzi_s"):
- case Hash("umullt_z_zzi_d"):
+ case "umullt_z_zzi_s"_h:
+ case "umullt_z_zzi_d"_h:
umull(vform, zd, zn_t, zm_idx);
break;
- case Hash("sqdmullb_z_zzi_s"):
+ case "sqdmullb_z_zzi_s"_h:
sqdmull(vform, zd, zn_b, zm_idx);
break;
- case Hash("sqdmullt_z_zzi_s"):
+ case "sqdmullt_z_zzi_s"_h:
sqdmull(vform, zd, zn_t, zm_idx);
break;
- case Hash("smlalb_z_zzzi_s"):
- case Hash("smlalb_z_zzzi_d"):
+ case "smlalb_z_zzzi_s"_h:
+ case "smlalb_z_zzzi_d"_h:
smlal(vform, zd, zn_b, zm_idx);
break;
- case Hash("smlalt_z_zzzi_s"):
- case Hash("smlalt_z_zzzi_d"):
+ case "smlalt_z_zzzi_s"_h:
+ case "smlalt_z_zzzi_d"_h:
smlal(vform, zd, zn_t, zm_idx);
break;
- case Hash("smlslb_z_zzzi_s"):
- case Hash("smlslb_z_zzzi_d"):
+ case "smlslb_z_zzzi_s"_h:
+ case "smlslb_z_zzzi_d"_h:
smlsl(vform, zd, zn_b, zm_idx);
break;
- case Hash("smlslt_z_zzzi_s"):
- case Hash("smlslt_z_zzzi_d"):
+ case "smlslt_z_zzzi_s"_h:
+ case "smlslt_z_zzzi_d"_h:
smlsl(vform, zd, zn_t, zm_idx);
break;
- case Hash("umlalb_z_zzzi_s"):
- case Hash("umlalb_z_zzzi_d"):
+ case "umlalb_z_zzzi_s"_h:
+ case "umlalb_z_zzzi_d"_h:
umlal(vform, zd, zn_b, zm_idx);
break;
- case Hash("umlalt_z_zzzi_s"):
- case Hash("umlalt_z_zzzi_d"):
+ case "umlalt_z_zzzi_s"_h:
+ case "umlalt_z_zzzi_d"_h:
umlal(vform, zd, zn_t, zm_idx);
break;
- case Hash("umlslb_z_zzzi_s"):
- case Hash("umlslb_z_zzzi_d"):
+ case "umlslb_z_zzzi_s"_h:
+ case "umlslb_z_zzzi_d"_h:
umlsl(vform, zd, zn_b, zm_idx);
break;
- case Hash("umlslt_z_zzzi_s"):
- case Hash("umlslt_z_zzzi_d"):
+ case "umlslt_z_zzzi_s"_h:
+ case "umlslt_z_zzzi_d"_h:
umlsl(vform, zd, zn_t, zm_idx);
break;
default:
@@ -2273,7 +2273,7 @@
pack_even_elements(kFormatVnH, zd_b, zd);
switch (form_hash_) {
- case Hash("fcvtnt_z_p_z_s2h"):
+ case "fcvtnt_z_p_z_s2h"_h:
fcvt(kFormatVnH, kFormatVnS, result, pg, zn);
pack_even_elements(kFormatVnH, result, result);
zip1(kFormatVnH, result, zd_b, result);
@@ -2294,16 +2294,16 @@
pack_even_elements(kFormatVnS, zd_b, zd);
switch (form_hash_) {
- case Hash("fcvtnt_z_p_z_d2s"):
+ case "fcvtnt_z_p_z_d2s"_h:
fcvt(kFormatVnS, kFormatVnD, result, pg, zn);
pack_even_elements(kFormatVnS, result, result);
zip1(kFormatVnS, result, zd_b, result);
break;
- case Hash("fcvtx_z_p_z_d2s"):
+ case "fcvtx_z_p_z_d2s"_h:
fcvtxn(kFormatVnS, result, zn);
zip1(kFormatVnS, result, result, zero);
break;
- case Hash("fcvtxnt_z_p_z_d2s"):
+ case "fcvtxnt_z_p_z_d2s"_h:
fcvtxn(kFormatVnS, result, zn);
zip1(kFormatVnS, result, zd_b, result);
break;
@@ -2320,11 +2320,11 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("fcvtlt_z_p_z_h2s"):
+ case "fcvtlt_z_p_z_h2s"_h:
ext(kFormatVnB, result, zn, zn, kHRegSizeInBytes);
fcvt(kFormatVnS, kFormatVnH, zd, pg, result);
break;
- case Hash("fcvtlt_z_p_z_s2d"):
+ case "fcvtlt_z_p_z_s2d"_h:
ext(kFormatVnB, result, zn, zn, kSRegSizeInBytes);
fcvt(kFormatVnD, kFormatVnS, zd, pg, result);
break;
@@ -2345,10 +2345,10 @@
}
switch (form_hash_) {
- case Hash("urecpe_z_p_z"):
+ case "urecpe_z_p_z"_h:
urecpe(vform, result, zn);
break;
- case Hash("ursqrte_z_p_z"):
+ case "ursqrte_z_p_z"_h:
ursqrte(vform, result, zn);
break;
default:
@@ -2365,14 +2365,14 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("flogb_z_p_z"):
+ case "flogb_z_p_z"_h:
vform = instr->GetSVEVectorFormat(17);
flogb(vform, result, zn);
break;
- case Hash("sqabs_z_p_z"):
+ case "sqabs_z_p_z"_h:
abs(vform, result, zn).SignedSaturate(vform);
break;
- case Hash("sqneg_z_p_z"):
+ case "sqneg_z_p_z"_h:
neg(vform, result, zn).SignedSaturate(vform);
break;
default:
@@ -2389,7 +2389,7 @@
SimVRegister& zn = ReadVRegister(instr->GetRn());
SimVRegister result;
- VIXL_ASSERT(form_hash_ == Hash("histcnt_z_p_zz"));
+ VIXL_ASSERT(form_hash_ == "histcnt_z_p_zz"_h);
if ((vform == kFormatVnS) || (vform == kFormatVnD)) {
histogram(vform, result, pg, zn, zm);
mov_zeroing(vform, zd, pg, result);
@@ -2407,38 +2407,38 @@
bool do_bext = false;
switch (form_hash_) {
- case Hash("bdep_z_zz"):
+ case "bdep_z_zz"_h:
bdep(vform, zd, zn, zm);
break;
- case Hash("bext_z_zz"):
+ case "bext_z_zz"_h:
do_bext = true;
VIXL_FALLTHROUGH();
- case Hash("bgrp_z_zz"):
+ case "bgrp_z_zz"_h:
bgrp(vform, zd, zn, zm, do_bext);
break;
- case Hash("eorbt_z_zz"):
+ case "eorbt_z_zz"_h:
rotate_elements_right(vform, result, zm, 1);
SVEBitwiseLogicalUnpredicatedHelper(EOR, kFormatVnD, result, zn, result);
mov_alternating(vform, zd, result, 0);
break;
- case Hash("eortb_z_zz"):
+ case "eortb_z_zz"_h:
rotate_elements_right(vform, result, zm, -1);
SVEBitwiseLogicalUnpredicatedHelper(EOR, kFormatVnD, result, zn, result);
mov_alternating(vform, zd, result, 1);
break;
- case Hash("mul_z_zz"):
+ case "mul_z_zz"_h:
mul(vform, zd, zn, zm);
break;
- case Hash("smulh_z_zz"):
+ case "smulh_z_zz"_h:
smulh(vform, zd, zn, zm);
break;
- case Hash("sqdmulh_z_zz"):
+ case "sqdmulh_z_zz"_h:
sqdmulh(vform, zd, zn, zm);
break;
- case Hash("sqrdmulh_z_zz"):
+ case "sqrdmulh_z_zz"_h:
sqrdmulh(vform, zd, zn, zm);
break;
- case Hash("umulh_z_zz"):
+ case "umulh_z_zz"_h:
umulh(vform, zd, zn, zm);
break;
default:
@@ -2458,28 +2458,28 @@
pack_odd_elements(vform_half, zm_t, zm);
switch (form_hash_) {
- case Hash("saddwb_z_zz"):
+ case "saddwb_z_zz"_h:
saddw(vform, zd, zn, zm_b);
break;
- case Hash("saddwt_z_zz"):
+ case "saddwt_z_zz"_h:
saddw(vform, zd, zn, zm_t);
break;
- case Hash("ssubwb_z_zz"):
+ case "ssubwb_z_zz"_h:
ssubw(vform, zd, zn, zm_b);
break;
- case Hash("ssubwt_z_zz"):
+ case "ssubwt_z_zz"_h:
ssubw(vform, zd, zn, zm_t);
break;
- case Hash("uaddwb_z_zz"):
+ case "uaddwb_z_zz"_h:
uaddw(vform, zd, zn, zm_b);
break;
- case Hash("uaddwt_z_zz"):
+ case "uaddwt_z_zz"_h:
uaddw(vform, zd, zn, zm_t);
break;
- case Hash("usubwb_z_zz"):
+ case "usubwb_z_zz"_h:
usubw(vform, zd, zn, zm_b);
break;
- case Hash("usubwt_z_zz"):
+ case "usubwt_z_zz"_h:
usubw(vform, zd, zn, zm_t);
break;
default:
@@ -2500,13 +2500,13 @@
int shift_dist = shift_and_lane_size.first;
switch (form_hash_) {
- case Hash("sli_z_zzi"):
+ case "sli_z_zzi"_h:
// Shift distance is computed differently for left shifts. Convert the
// result.
shift_dist = (8 << lane_size) - shift_dist;
sli(vform, zd, zn, shift_dist);
break;
- case Hash("sri_z_zzi"):
+ case "sri_z_zzi"_h:
sri(vform, zd, zn, shift_dist);
break;
default:
@@ -2529,70 +2529,70 @@
bool top = false;
switch (form_hash_) {
- case Hash("sqxtnt_z_zz"):
+ case "sqxtnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqxtnb_z_zz"):
+ case "sqxtnb_z_zz"_h:
sqxtn(vform, result, zn);
break;
- case Hash("sqxtunt_z_zz"):
+ case "sqxtunt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqxtunb_z_zz"):
+ case "sqxtunb_z_zz"_h:
sqxtun(vform, result, zn);
break;
- case Hash("uqxtnt_z_zz"):
+ case "uqxtnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("uqxtnb_z_zz"):
+ case "uqxtnb_z_zz"_h:
uqxtn(vform, result, zn);
break;
- case Hash("rshrnt_z_zi"):
+ case "rshrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("rshrnb_z_zi"):
+ case "rshrnb_z_zi"_h:
rshrn(vform, result, zn, right_shift_dist);
break;
- case Hash("shrnt_z_zi"):
+ case "shrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("shrnb_z_zi"):
+ case "shrnb_z_zi"_h:
shrn(vform, result, zn, right_shift_dist);
break;
- case Hash("sqrshrnt_z_zi"):
+ case "sqrshrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqrshrnb_z_zi"):
+ case "sqrshrnb_z_zi"_h:
sqrshrn(vform, result, zn, right_shift_dist);
break;
- case Hash("sqrshrunt_z_zi"):
+ case "sqrshrunt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqrshrunb_z_zi"):
+ case "sqrshrunb_z_zi"_h:
sqrshrun(vform, result, zn, right_shift_dist);
break;
- case Hash("sqshrnt_z_zi"):
+ case "sqshrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqshrnb_z_zi"):
+ case "sqshrnb_z_zi"_h:
sqshrn(vform, result, zn, right_shift_dist);
break;
- case Hash("sqshrunt_z_zi"):
+ case "sqshrunt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqshrunb_z_zi"):
+ case "sqshrunb_z_zi"_h:
sqshrun(vform, result, zn, right_shift_dist);
break;
- case Hash("uqrshrnt_z_zi"):
+ case "uqrshrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("uqrshrnb_z_zi"):
+ case "uqrshrnb_z_zi"_h:
uqrshrn(vform, result, zn, right_shift_dist);
break;
- case Hash("uqshrnt_z_zi"):
+ case "uqshrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("uqshrnb_z_zi"):
+ case "uqshrnb_z_zi"_h:
uqshrn(vform, result, zn, right_shift_dist);
break;
default:
@@ -2627,61 +2627,61 @@
pack_odd_elements(vform_half, zm_t, zm);
switch (form_hash_) {
- case Hash("sabdlb_z_zz"):
+ case "sabdlb_z_zz"_h:
sabdl(vform, zd, zn_b, zm_b);
break;
- case Hash("sabdlt_z_zz"):
+ case "sabdlt_z_zz"_h:
sabdl(vform, zd, zn_t, zm_t);
break;
- case Hash("saddlb_z_zz"):
+ case "saddlb_z_zz"_h:
saddl(vform, zd, zn_b, zm_b);
break;
- case Hash("saddlbt_z_zz"):
+ case "saddlbt_z_zz"_h:
saddl(vform, zd, zn_b, zm_t);
break;
- case Hash("saddlt_z_zz"):
+ case "saddlt_z_zz"_h:
saddl(vform, zd, zn_t, zm_t);
break;
- case Hash("ssublb_z_zz"):
+ case "ssublb_z_zz"_h:
ssubl(vform, zd, zn_b, zm_b);
break;
- case Hash("ssublbt_z_zz"):
+ case "ssublbt_z_zz"_h:
ssubl(vform, zd, zn_b, zm_t);
break;
- case Hash("ssublt_z_zz"):
+ case "ssublt_z_zz"_h:
ssubl(vform, zd, zn_t, zm_t);
break;
- case Hash("ssubltb_z_zz"):
+ case "ssubltb_z_zz"_h:
ssubl(vform, zd, zn_t, zm_b);
break;
- case Hash("uabdlb_z_zz"):
+ case "uabdlb_z_zz"_h:
uabdl(vform, zd, zn_b, zm_b);
break;
- case Hash("uabdlt_z_zz"):
+ case "uabdlt_z_zz"_h:
uabdl(vform, zd, zn_t, zm_t);
break;
- case Hash("uaddlb_z_zz"):
+ case "uaddlb_z_zz"_h:
uaddl(vform, zd, zn_b, zm_b);
break;
- case Hash("uaddlt_z_zz"):
+ case "uaddlt_z_zz"_h:
uaddl(vform, zd, zn_t, zm_t);
break;
- case Hash("usublb_z_zz"):
+ case "usublb_z_zz"_h:
usubl(vform, zd, zn_b, zm_b);
break;
- case Hash("usublt_z_zz"):
+ case "usublt_z_zz"_h:
usubl(vform, zd, zn_t, zm_t);
break;
- case Hash("sabalb_z_zzz"):
+ case "sabalb_z_zzz"_h:
sabal(vform, zd, zn_b, zm_b);
break;
- case Hash("sabalt_z_zzz"):
+ case "sabalt_z_zzz"_h:
sabal(vform, zd, zn_t, zm_t);
break;
- case Hash("uabalb_z_zzz"):
+ case "uabalb_z_zzz"_h:
uabal(vform, zd, zn_b, zm_b);
break;
- case Hash("uabalt_z_zzz"):
+ case "uabalt_z_zzz"_h:
uabal(vform, zd, zn_t, zm_t);
break;
default:
@@ -2702,36 +2702,36 @@
pack_odd_elements(vform_half, zm_t, zm);
switch (form_hash_) {
- case Hash("pmullb_z_zz"):
+ case "pmullb_z_zz"_h:
// '00' is reserved for Q-sized lane.
if (vform == kFormatVnB) {
VIXL_UNIMPLEMENTED();
}
pmull(vform, zd, zn_b, zm_b);
break;
- case Hash("pmullt_z_zz"):
+ case "pmullt_z_zz"_h:
// '00' is reserved for Q-sized lane.
if (vform == kFormatVnB) {
VIXL_UNIMPLEMENTED();
}
pmull(vform, zd, zn_t, zm_t);
break;
- case Hash("smullb_z_zz"):
+ case "smullb_z_zz"_h:
smull(vform, zd, zn_b, zm_b);
break;
- case Hash("smullt_z_zz"):
+ case "smullt_z_zz"_h:
smull(vform, zd, zn_t, zm_t);
break;
- case Hash("sqdmullb_z_zz"):
+ case "sqdmullb_z_zz"_h:
sqdmull(vform, zd, zn_b, zm_b);
break;
- case Hash("sqdmullt_z_zz"):
+ case "sqdmullt_z_zz"_h:
sqdmull(vform, zd, zn_t, zm_t);
break;
- case Hash("umullb_z_zz"):
+ case "umullb_z_zz"_h:
umull(vform, zd, zn_b, zm_b);
break;
- case Hash("umullt_z_zz"):
+ case "umullt_z_zz"_h:
umull(vform, zd, zn_t, zm_t);
break;
default:
@@ -2753,28 +2753,28 @@
VectorFormat vform = VectorFormatHalfWidth(vform_src);
switch (form_hash_) {
- case Hash("addhnt_z_zz"):
+ case "addhnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("addhnb_z_zz"):
+ case "addhnb_z_zz"_h:
addhn(vform, result, zn, zm);
break;
- case Hash("raddhnt_z_zz"):
+ case "raddhnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("raddhnb_z_zz"):
+ case "raddhnb_z_zz"_h:
raddhn(vform, result, zn, zm);
break;
- case Hash("rsubhnt_z_zz"):
+ case "rsubhnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("rsubhnb_z_zz"):
+ case "rsubhnb_z_zz"_h:
rsubhn(vform, result, zn, zm);
break;
- case Hash("subhnt_z_zz"):
+ case "subhnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("subhnb_z_zz"):
+ case "subhnb_z_zz"_h:
subhn(vform, result, zn, zm);
break;
default:
@@ -2814,16 +2814,16 @@
pack_odd_elements(vform_half, zn_t, zn);
switch (form_hash_) {
- case Hash("sshllb_z_zi"):
+ case "sshllb_z_zi"_h:
sshll(vform, zd, zn_b, left_shift_dist);
break;
- case Hash("sshllt_z_zi"):
+ case "sshllt_z_zi"_h:
sshll(vform, zd, zn_t, left_shift_dist);
break;
- case Hash("ushllb_z_zi"):
+ case "ushllb_z_zi"_h:
ushll(vform, zd, zn_b, left_shift_dist);
break;
- case Hash("ushllt_z_zi"):
+ case "ushllt_z_zi"_h:
ushll(vform, zd, zn_t, left_shift_dist);
break;
default:
@@ -2840,32 +2840,32 @@
bool is_mla = false;
switch (form_hash_) {
- case Hash("sqrdmlah_z_zzz"):
+ case "sqrdmlah_z_zzz"_h:
is_mla = true;
VIXL_FALLTHROUGH();
- case Hash("sqrdmlsh_z_zzz"):
+ case "sqrdmlsh_z_zzz"_h:
// Nothing to do.
break;
- case Hash("sqrdmlah_z_zzzi_h"):
+ case "sqrdmlah_z_zzzi_h"_h:
is_mla = true;
VIXL_FALLTHROUGH();
- case Hash("sqrdmlsh_z_zzzi_h"):
+ case "sqrdmlsh_z_zzzi_h"_h:
vform = kFormatVnH;
index = (instr->ExtractBit(22) << 2) | instr->ExtractBits(20, 19);
zm_code = instr->ExtractBits(18, 16);
break;
- case Hash("sqrdmlah_z_zzzi_s"):
+ case "sqrdmlah_z_zzzi_s"_h:
is_mla = true;
VIXL_FALLTHROUGH();
- case Hash("sqrdmlsh_z_zzzi_s"):
+ case "sqrdmlsh_z_zzzi_s"_h:
vform = kFormatVnS;
index = instr->ExtractBits(20, 19);
zm_code = instr->ExtractBits(18, 16);
break;
- case Hash("sqrdmlah_z_zzzi_d"):
+ case "sqrdmlah_z_zzzi_d"_h:
is_mla = true;
VIXL_FALLTHROUGH();
- case Hash("sqrdmlsh_z_zzzi_d"):
+ case "sqrdmlsh_z_zzzi_d"_h:
vform = kFormatVnD;
index = instr->ExtractBit(20);
zm_code = instr->ExtractBits(19, 16);
@@ -2900,16 +2900,16 @@
pack_odd_elements(kFormatVnS, zn_t, zn);
switch (form_hash_) {
- case Hash("sqdmlalb_z_zzzi_d"):
+ case "sqdmlalb_z_zzzi_d"_h:
sqdmlal(kFormatVnD, zda, zn_b, zm_idx);
break;
- case Hash("sqdmlalt_z_zzzi_d"):
+ case "sqdmlalt_z_zzzi_d"_h:
sqdmlal(kFormatVnD, zda, zn_t, zm_idx);
break;
- case Hash("sqdmlslb_z_zzzi_d"):
+ case "sqdmlslb_z_zzzi_d"_h:
sqdmlsl(kFormatVnD, zda, zn_b, zm_idx);
break;
- case Hash("sqdmlslt_z_zzzi_d"):
+ case "sqdmlslt_z_zzzi_d"_h:
sqdmlsl(kFormatVnD, zda, zn_t, zm_idx);
break;
default:
@@ -2929,16 +2929,16 @@
pack_odd_elements(kFormatVnH, zm_t, zm);
switch (form_hash_) {
- case Hash("fmlalb_z_zzz"):
+ case "fmlalb_z_zzz"_h:
fmlal(kFormatVnS, zda, zn_b, zm_b);
break;
- case Hash("fmlalt_z_zzz"):
+ case "fmlalt_z_zzz"_h:
fmlal(kFormatVnS, zda, zn_t, zm_t);
break;
- case Hash("fmlslb_z_zzz"):
+ case "fmlslb_z_zzz"_h:
fmlsl(kFormatVnS, zda, zn_b, zm_b);
break;
- case Hash("fmlslt_z_zzz"):
+ case "fmlslt_z_zzz"_h:
fmlsl(kFormatVnS, zda, zn_t, zm_t);
break;
default:
@@ -2959,28 +2959,28 @@
pack_odd_elements(kFormatVnH, zn_t, zn);
switch (form_hash_) {
- case Hash("fmlalb_z_zzzi_s"):
+ case "fmlalb_z_zzzi_s"_h:
fmlal(kFormatVnS, zda, zn_b, zm_idx);
break;
- case Hash("fmlalt_z_zzzi_s"):
+ case "fmlalt_z_zzzi_s"_h:
fmlal(kFormatVnS, zda, zn_t, zm_idx);
break;
- case Hash("fmlslb_z_zzzi_s"):
+ case "fmlslb_z_zzzi_s"_h:
fmlsl(kFormatVnS, zda, zn_b, zm_idx);
break;
- case Hash("fmlslt_z_zzzi_s"):
+ case "fmlslt_z_zzzi_s"_h:
fmlsl(kFormatVnS, zda, zn_t, zm_idx);
break;
- case Hash("sqdmlalb_z_zzzi_s"):
+ case "sqdmlalb_z_zzzi_s"_h:
sqdmlal(kFormatVnS, zda, zn_b, zm_idx);
break;
- case Hash("sqdmlalt_z_zzzi_s"):
+ case "sqdmlalt_z_zzzi_s"_h:
sqdmlal(kFormatVnS, zda, zn_t, zm_idx);
break;
- case Hash("sqdmlslb_z_zzzi_s"):
+ case "sqdmlslb_z_zzzi_s"_h:
sqdmlsl(kFormatVnS, zda, zn_b, zm_idx);
break;
- case Hash("sqdmlslt_z_zzzi_s"):
+ case "sqdmlslt_z_zzzi_s"_h:
sqdmlsl(kFormatVnS, zda, zn_t, zm_idx);
break;
default:
@@ -2996,10 +2996,10 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("sadalp_z_p_z"):
+ case "sadalp_z_p_z"_h:
sadalp(vform, result, zn);
break;
- case Hash("uadalp_z_p_z"):
+ case "uadalp_z_p_z"_h:
uadalp(vform, result, zn);
break;
default:
@@ -3018,16 +3018,16 @@
not_(vform, not_zn, zn);
switch (form_hash_) {
- case Hash("adclb_z_zzz"):
+ case "adclb_z_zzz"_h:
adcl(vform, zda, zn, zm, /* top = */ false);
break;
- case Hash("adclt_z_zzz"):
+ case "adclt_z_zzz"_h:
adcl(vform, zda, zn, zm, /* top = */ true);
break;
- case Hash("sbclb_z_zzz"):
+ case "sbclb_z_zzz"_h:
adcl(vform, zda, not_zn, zm, /* top = */ false);
break;
- case Hash("sbclt_z_zzz"):
+ case "sbclt_z_zzz"_h:
adcl(vform, zda, not_zn, zm, /* top = */ true);
break;
default:
@@ -3042,10 +3042,10 @@
SimVRegister& zn = ReadVRegister(instr->GetRn());
switch (form_hash_) {
- case Hash("saba_z_zzz"):
+ case "saba_z_zzz"_h:
saba(vform, zda, zn, zm);
break;
- case Hash("uaba_z_zzz"):
+ case "uaba_z_zzz"_h:
uaba(vform, zda, zn, zm);
break;
default:
@@ -3068,22 +3068,22 @@
int idx_s = instr->ExtractBit(20);
switch (form_hash_) {
- case Hash("cmla_z_zzz"):
+ case "cmla_z_zzz"_h:
cmla(vform, zda, zda, zn, zm, rot);
break;
- case Hash("cmla_z_zzzi_h"):
+ case "cmla_z_zzzi_h"_h:
cmla(kFormatVnH, zda, zda, zn, zm_h, idx_h, rot);
break;
- case Hash("cmla_z_zzzi_s"):
+ case "cmla_z_zzzi_s"_h:
cmla(kFormatVnS, zda, zda, zn, zm_s, idx_s, rot);
break;
- case Hash("sqrdcmlah_z_zzz"):
+ case "sqrdcmlah_z_zzz"_h:
sqrdcmlah(vform, zda, zda, zn, zm, rot);
break;
- case Hash("sqrdcmlah_z_zzzi_h"):
+ case "sqrdcmlah_z_zzzi_h"_h:
sqrdcmlah(kFormatVnH, zda, zda, zn, zm_h, idx_h, rot);
break;
- case Hash("sqrdcmlah_z_zzzi_s"):
+ case "sqrdcmlah_z_zzzi_s"_h:
sqrdcmlah(kFormatVnS, zda, zda, zn, zm_s, idx_s, rot);
break;
default:
@@ -3104,16 +3104,16 @@
int shift_dist = shift_and_lane_size.first;
switch (form_hash_) {
- case Hash("srsra_z_zi"):
+ case "srsra_z_zi"_h:
srsra(vform, zd, zn, shift_dist);
break;
- case Hash("ssra_z_zi"):
+ case "ssra_z_zi"_h:
ssra(vform, zd, zn, shift_dist);
break;
- case Hash("ursra_z_zi"):
+ case "ursra_z_zi"_h:
ursra(vform, zd, zn, shift_dist);
break;
- case Hash("usra_z_zi"):
+ case "usra_z_zi"_h:
usra(vform, zd, zn, shift_dist);
break;
default:
@@ -3137,46 +3137,46 @@
uzp2(vform_half, zm_t, zm, zero);
switch (form_hash_) {
- case Hash("smlalb_z_zzz"):
+ case "smlalb_z_zzz"_h:
smlal(vform, zda, zn_b, zm_b);
break;
- case Hash("smlalt_z_zzz"):
+ case "smlalt_z_zzz"_h:
smlal(vform, zda, zn_t, zm_t);
break;
- case Hash("smlslb_z_zzz"):
+ case "smlslb_z_zzz"_h:
smlsl(vform, zda, zn_b, zm_b);
break;
- case Hash("smlslt_z_zzz"):
+ case "smlslt_z_zzz"_h:
smlsl(vform, zda, zn_t, zm_t);
break;
- case Hash("sqdmlalb_z_zzz"):
+ case "sqdmlalb_z_zzz"_h:
sqdmlal(vform, zda, zn_b, zm_b);
break;
- case Hash("sqdmlalbt_z_zzz"):
+ case "sqdmlalbt_z_zzz"_h:
sqdmlal(vform, zda, zn_b, zm_t);
break;
- case Hash("sqdmlalt_z_zzz"):
+ case "sqdmlalt_z_zzz"_h:
sqdmlal(vform, zda, zn_t, zm_t);
break;
- case Hash("sqdmlslb_z_zzz"):
+ case "sqdmlslb_z_zzz"_h:
sqdmlsl(vform, zda, zn_b, zm_b);
break;
- case Hash("sqdmlslbt_z_zzz"):
+ case "sqdmlslbt_z_zzz"_h:
sqdmlsl(vform, zda, zn_b, zm_t);
break;
- case Hash("sqdmlslt_z_zzz"):
+ case "sqdmlslt_z_zzz"_h:
sqdmlsl(vform, zda, zn_t, zm_t);
break;
- case Hash("umlalb_z_zzz"):
+ case "umlalb_z_zzz"_h:
umlal(vform, zda, zn_b, zm_b);
break;
- case Hash("umlalt_z_zzz"):
+ case "umlalt_z_zzz"_h:
umlal(vform, zda, zn_t, zm_t);
break;
- case Hash("umlslb_z_zzz"):
+ case "umlslb_z_zzz"_h:
umlsl(vform, zda, zn_b, zm_b);
break;
- case Hash("umlslt_z_zzz"):
+ case "umlslt_z_zzz"_h:
umlsl(vform, zda, zn_t, zm_t);
break;
default:
@@ -3193,14 +3193,14 @@
int index = -1;
switch (form_hash_) {
- case Hash("cdot_z_zzz"):
+ case "cdot_z_zzz"_h:
// Nothing to do.
break;
- case Hash("cdot_z_zzzi_s"):
+ case "cdot_z_zzzi_s"_h:
index = zm_code >> 3;
zm_code &= 0x7;
break;
- case Hash("cdot_z_zzzi_d"):
+ case "cdot_z_zzzi_d"_h:
index = zm_code >> 4;
zm_code &= 0xf;
break;
@@ -3222,26 +3222,26 @@
SimVRegister temp;
switch (form_hash_) {
- case Hash("bcax_z_zzz"):
+ case "bcax_z_zzz"_h:
bic(vform, temp, zm, zk);
eor(vform, zdn, temp, zdn);
break;
- case Hash("bsl1n_z_zzz"):
+ case "bsl1n_z_zzz"_h:
not_(vform, temp, zdn);
bsl(vform, zdn, zk, temp, zm);
break;
- case Hash("bsl2n_z_zzz"):
+ case "bsl2n_z_zzz"_h:
not_(vform, temp, zm);
bsl(vform, zdn, zk, zdn, temp);
break;
- case Hash("bsl_z_zzz"):
+ case "bsl_z_zzz"_h:
bsl(vform, zdn, zk, zdn, zm);
break;
- case Hash("eor3_z_zzz"):
+ case "eor3_z_zzz"_h:
eor(vform, temp, zdn, zm);
eor(vform, zdn, temp, zk);
break;
- case Hash("nbsl_z_zzz"):
+ case "nbsl_z_zzz"_h:
bsl(vform, zdn, zk, zdn, zm);
not_(vform, zdn, zdn);
break;
@@ -3258,28 +3258,28 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("shadd_z_p_zz"):
+ case "shadd_z_p_zz"_h:
add(vform, result, zdn, zm).Halve(vform);
break;
- case Hash("shsub_z_p_zz"):
+ case "shsub_z_p_zz"_h:
sub(vform, result, zdn, zm).Halve(vform);
break;
- case Hash("shsubr_z_p_zz"):
+ case "shsubr_z_p_zz"_h:
sub(vform, result, zm, zdn).Halve(vform);
break;
- case Hash("srhadd_z_p_zz"):
+ case "srhadd_z_p_zz"_h:
add(vform, result, zdn, zm).Halve(vform).Round(vform);
break;
- case Hash("uhadd_z_p_zz"):
+ case "uhadd_z_p_zz"_h:
add(vform, result, zdn, zm).Uhalve(vform);
break;
- case Hash("uhsub_z_p_zz"):
+ case "uhsub_z_p_zz"_h:
sub(vform, result, zdn, zm).Uhalve(vform);
break;
- case Hash("uhsubr_z_p_zz"):
+ case "uhsubr_z_p_zz"_h:
sub(vform, result, zm, zdn).Uhalve(vform);
break;
- case Hash("urhadd_z_p_zz"):
+ case "urhadd_z_p_zz"_h:
add(vform, result, zdn, zm).Uhalve(vform).Round(vform);
break;
default:
@@ -3297,28 +3297,28 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("sqadd_z_p_zz"):
+ case "sqadd_z_p_zz"_h:
add(vform, result, zdn, zm).SignedSaturate(vform);
break;
- case Hash("sqsub_z_p_zz"):
+ case "sqsub_z_p_zz"_h:
sub(vform, result, zdn, zm).SignedSaturate(vform);
break;
- case Hash("sqsubr_z_p_zz"):
+ case "sqsubr_z_p_zz"_h:
sub(vform, result, zm, zdn).SignedSaturate(vform);
break;
- case Hash("suqadd_z_p_zz"):
+ case "suqadd_z_p_zz"_h:
suqadd(vform, result, zdn, zm);
break;
- case Hash("uqadd_z_p_zz"):
+ case "uqadd_z_p_zz"_h:
add(vform, result, zdn, zm).UnsignedSaturate(vform);
break;
- case Hash("uqsub_z_p_zz"):
+ case "uqsub_z_p_zz"_h:
sub(vform, result, zdn, zm).UnsignedSaturate(vform);
break;
- case Hash("uqsubr_z_p_zz"):
+ case "uqsubr_z_p_zz"_h:
sub(vform, result, zm, zdn).UnsignedSaturate(vform);
break;
- case Hash("usqadd_z_p_zz"):
+ case "usqadd_z_p_zz"_h:
usqadd(vform, result, zdn, zm);
break;
default:
@@ -3336,19 +3336,19 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("addp_z_p_zz"):
+ case "addp_z_p_zz"_h:
addp(vform, result, zdn, zm);
break;
- case Hash("smaxp_z_p_zz"):
+ case "smaxp_z_p_zz"_h:
smaxp(vform, result, zdn, zm);
break;
- case Hash("sminp_z_p_zz"):
+ case "sminp_z_p_zz"_h:
sminp(vform, result, zdn, zm);
break;
- case Hash("umaxp_z_p_zz"):
+ case "umaxp_z_p_zz"_h:
umaxp(vform, result, zdn, zm);
break;
- case Hash("uminp_z_p_zz"):
+ case "uminp_z_p_zz"_h:
uminp(vform, result, zdn, zm);
break;
default:
@@ -3366,19 +3366,19 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("faddp_z_p_zz"):
+ case "faddp_z_p_zz"_h:
faddp(vform, result, zdn, zm);
break;
- case Hash("fmaxnmp_z_p_zz"):
+ case "fmaxnmp_z_p_zz"_h:
fmaxnmp(vform, result, zdn, zm);
break;
- case Hash("fmaxp_z_p_zz"):
+ case "fmaxp_z_p_zz"_h:
fmaxp(vform, result, zdn, zm);
break;
- case Hash("fminnmp_z_p_zz"):
+ case "fminnmp_z_p_zz"_h:
fminnmp(vform, result, zdn, zm);
break;
- case Hash("fminp_z_p_zz"):
+ case "fminp_z_p_zz"_h:
fminp(vform, result, zdn, zm);
break;
default:
@@ -3400,19 +3400,19 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("sqshl_z_p_zi"):
+ case "sqshl_z_p_zi"_h:
sqshl(vform, result, zdn, left_shift_dist);
break;
- case Hash("sqshlu_z_p_zi"):
+ case "sqshlu_z_p_zi"_h:
sqshlu(vform, result, zdn, left_shift_dist);
break;
- case Hash("srshr_z_p_zi"):
+ case "srshr_z_p_zi"_h:
sshr(vform, result, zdn, right_shift_dist).Round(vform);
break;
- case Hash("uqshl_z_p_zi"):
+ case "uqshl_z_p_zi"_h:
uqshl(vform, result, zdn, left_shift_dist);
break;
- case Hash("urshr_z_p_zi"):
+ case "urshr_z_p_zi"_h:
ushr(vform, result, zdn, right_shift_dist).Round(vform);
break;
default:
@@ -3422,7 +3422,7 @@
}
void Simulator::SimulateSVEExclusiveOrRotate(const Instruction* instr) {
- VIXL_ASSERT(form_hash_ == Hash("xar_z_zzi"));
+ VIXL_ASSERT(form_hash_ == "xar_z_zzi"_h);
SimVRegister& zdn = ReadVRegister(instr->GetRd());
SimVRegister& zm = ReadVRegister(instr->GetRn());
@@ -3444,10 +3444,10 @@
int rot = (instr->ExtractBit(10) == 0) ? 90 : 270;
switch (form_hash_) {
- case Hash("cadd_z_zz"):
+ case "cadd_z_zz"_h:
cadd(vform, zdn, zdn, zm, rot);
break;
- case Hash("sqcadd_z_zz"):
+ case "sqcadd_z_zz"_h:
cadd(vform, zdn, zdn, zm, rot, /* saturate = */ true);
break;
default:
@@ -3465,28 +3465,28 @@
bool is_signed = false;
switch (form_hash_) {
- case Hash("ldnt1b_z_p_ar_d_64_unscaled"):
+ case "ldnt1b_z_p_ar_d_64_unscaled"_h:
msize = 0;
break;
- case Hash("ldnt1d_z_p_ar_d_64_unscaled"):
+ case "ldnt1d_z_p_ar_d_64_unscaled"_h:
msize = 3;
break;
- case Hash("ldnt1h_z_p_ar_d_64_unscaled"):
+ case "ldnt1h_z_p_ar_d_64_unscaled"_h:
msize = 1;
break;
- case Hash("ldnt1sb_z_p_ar_d_64_unscaled"):
+ case "ldnt1sb_z_p_ar_d_64_unscaled"_h:
msize = 0;
is_signed = true;
break;
- case Hash("ldnt1sh_z_p_ar_d_64_unscaled"):
+ case "ldnt1sh_z_p_ar_d_64_unscaled"_h:
msize = 1;
is_signed = true;
break;
- case Hash("ldnt1sw_z_p_ar_d_64_unscaled"):
+ case "ldnt1sw_z_p_ar_d_64_unscaled"_h:
msize = 2;
is_signed = true;
break;
- case Hash("ldnt1w_z_p_ar_d_64_unscaled"):
+ case "ldnt1w_z_p_ar_d_64_unscaled"_h:
msize = 2;
break;
default:
@@ -3502,10 +3502,10 @@
uint64_t xm = ReadXRegister(instr->GetRm());
LogicSVEAddressVector addr(xm, &zn, kFormatVnD);
- VIXL_ASSERT((form_hash_ == Hash("stnt1b_z_p_ar_d_64_unscaled")) ||
- (form_hash_ == Hash("stnt1d_z_p_ar_d_64_unscaled")) ||
- (form_hash_ == Hash("stnt1h_z_p_ar_d_64_unscaled")) ||
- (form_hash_ == Hash("stnt1w_z_p_ar_d_64_unscaled")));
+ VIXL_ASSERT((form_hash_ == "stnt1b_z_p_ar_d_64_unscaled"_h) ||
+ (form_hash_ == "stnt1d_z_p_ar_d_64_unscaled"_h) ||
+ (form_hash_ == "stnt1h_z_p_ar_d_64_unscaled"_h) ||
+ (form_hash_ == "stnt1w_z_p_ar_d_64_unscaled"_h));
addr.SetMsizeInBytesLog2(
instr->GetSVEMsizeFromDtype(/* is_signed = */ false));
@@ -3522,21 +3522,21 @@
bool is_signed = false;
switch (form_hash_) {
- case Hash("ldnt1b_z_p_ar_s_x32_unscaled"):
+ case "ldnt1b_z_p_ar_s_x32_unscaled"_h:
msize = 0;
break;
- case Hash("ldnt1h_z_p_ar_s_x32_unscaled"):
+ case "ldnt1h_z_p_ar_s_x32_unscaled"_h:
msize = 1;
break;
- case Hash("ldnt1sb_z_p_ar_s_x32_unscaled"):
+ case "ldnt1sb_z_p_ar_s_x32_unscaled"_h:
msize = 0;
is_signed = true;
break;
- case Hash("ldnt1sh_z_p_ar_s_x32_unscaled"):
+ case "ldnt1sh_z_p_ar_s_x32_unscaled"_h:
msize = 1;
is_signed = true;
break;
- case Hash("ldnt1w_z_p_ar_s_x32_unscaled"):
+ case "ldnt1w_z_p_ar_s_x32_unscaled"_h:
msize = 2;
break;
default:
@@ -3552,9 +3552,9 @@
uint64_t xm = ReadXRegister(instr->GetRm());
LogicSVEAddressVector addr(xm, &zn, kFormatVnS);
- VIXL_ASSERT((form_hash_ == Hash("stnt1b_z_p_ar_s_x32_unscaled")) ||
- (form_hash_ == Hash("stnt1h_z_p_ar_s_x32_unscaled")) ||
- (form_hash_ == Hash("stnt1w_z_p_ar_s_x32_unscaled")));
+ VIXL_ASSERT((form_hash_ == "stnt1b_z_p_ar_s_x32_unscaled"_h) ||
+ (form_hash_ == "stnt1h_z_p_ar_s_x32_unscaled"_h) ||
+ (form_hash_ == "stnt1w_z_p_ar_s_x32_unscaled"_h));
addr.SetMsizeInBytesLog2(
instr->GetSVEMsizeFromDtype(/* is_signed = */ false));
@@ -7448,27 +7448,27 @@
VectorFormat vf = nfd.GetVectorFormat();
switch (form_hash_) {
- case Hash("fcmla_asimdsame2_c"):
+ case "fcmla_asimdsame2_c"_h:
rot = instr->GetImmRotFcmlaVec();
fcmla(vf, rd, rn, rm, rd, rot);
break;
- case Hash("fcadd_asimdsame2_c"):
+ case "fcadd_asimdsame2_c"_h:
rot = instr->GetImmRotFcadd();
fcadd(vf, rd, rn, rm, rot);
break;
- case Hash("sdot_asimdsame2_d"):
+ case "sdot_asimdsame2_d"_h:
sdot(vf, rd, rn, rm);
break;
- case Hash("udot_asimdsame2_d"):
+ case "udot_asimdsame2_d"_h:
udot(vf, rd, rn, rm);
break;
- case Hash("usdot_asimdsame2_d"):
+ case "usdot_asimdsame2_d"_h:
usdot(vf, rd, rn, rm);
break;
- case Hash("sqrdmlah_asimdsame2_only"):
+ case "sqrdmlah_asimdsame2_only"_h:
sqrdmlah(vf, rd, rn, rm);
break;
- case Hash("sqrdmlsh_asimdsame2_only"):
+ case "sqrdmlsh_asimdsame2_only"_h:
sqrdmlsh(vf, rd, rn, rm);
break;
}
@@ -7747,31 +7747,31 @@
bool is_2 = instr->Mask(NEON_Q) ? true : false;
switch (form_hash_) {
- case Hash("smull_asimdelem_l"):
+ case "smull_asimdelem_l"_h:
smull(vf, rd, rn, temp, is_2);
break;
- case Hash("umull_asimdelem_l"):
+ case "umull_asimdelem_l"_h:
umull(vf, rd, rn, temp, is_2);
break;
- case Hash("smlal_asimdelem_l"):
+ case "smlal_asimdelem_l"_h:
smlal(vf, rd, rn, temp, is_2);
break;
- case Hash("umlal_asimdelem_l"):
+ case "umlal_asimdelem_l"_h:
umlal(vf, rd, rn, temp, is_2);
break;
- case Hash("smlsl_asimdelem_l"):
+ case "smlsl_asimdelem_l"_h:
smlsl(vf, rd, rn, temp, is_2);
break;
- case Hash("umlsl_asimdelem_l"):
+ case "umlsl_asimdelem_l"_h:
umlsl(vf, rd, rn, temp, is_2);
break;
- case Hash("sqdmull_asimdelem_l"):
+ case "sqdmull_asimdelem_l"_h:
sqdmull(vf, rd, rn, temp, is_2);
break;
- case Hash("sqdmlal_asimdelem_l"):
+ case "sqdmlal_asimdelem_l"_h:
sqdmlal(vf, rd, rn, temp, is_2);
break;
- case Hash("sqdmlsl_asimdelem_l"):
+ case "sqdmlsl_asimdelem_l"_h:
sqdmlsl(vf, rd, rn, temp, is_2);
break;
default:
@@ -7789,16 +7789,16 @@
(instr->GetNEONH() << 2) | (instr->GetNEONL() << 1) | instr->GetNEONM();
switch (form_hash_) {
- case Hash("fmlal_asimdelem_lh"):
+ case "fmlal_asimdelem_lh"_h:
fmlal(vform, rd, rn, rm, index);
break;
- case Hash("fmlal2_asimdelem_lh"):
+ case "fmlal2_asimdelem_lh"_h:
fmlal2(vform, rd, rn, rm, index);
break;
- case Hash("fmlsl_asimdelem_lh"):
+ case "fmlsl_asimdelem_lh"_h:
fmlsl(vform, rd, rn, rm, index);
break;
- case Hash("fmlsl2_asimdelem_lh"):
+ case "fmlsl2_asimdelem_lh"_h:
fmlsl2(vform, rd, rn, rm, index);
break;
default:
@@ -7833,20 +7833,20 @@
SimVRegister& rm = ReadVRegister(rm_reg);
switch (form_hash_) {
- case Hash("fmul_asimdelem_rh_h"):
- case Hash("fmul_asimdelem_r_sd"):
+ case "fmul_asimdelem_rh_h"_h:
+ case "fmul_asimdelem_r_sd"_h:
fmul(vform, rd, rn, rm, index);
break;
- case Hash("fmla_asimdelem_rh_h"):
- case Hash("fmla_asimdelem_r_sd"):
+ case "fmla_asimdelem_rh_h"_h:
+ case "fmla_asimdelem_r_sd"_h:
fmla(vform, rd, rn, rm, index);
break;
- case Hash("fmls_asimdelem_rh_h"):
- case Hash("fmls_asimdelem_r_sd"):
+ case "fmls_asimdelem_rh_h"_h:
+ case "fmls_asimdelem_r_sd"_h:
fmls(vform, rd, rn, rm, index);
break;
- case Hash("fmulx_asimdelem_rh_h"):
- case Hash("fmulx_asimdelem_r_sd"):
+ case "fmulx_asimdelem_rh_h"_h:
+ case "fmulx_asimdelem_r_sd"_h:
fmulx(vform, rd, rn, rm, index);
break;
default:
@@ -7862,11 +7862,11 @@
int index = (instr->GetNEONH() << 1) | instr->GetNEONL();
switch (form_hash_) {
- case Hash("fcmla_asimdelem_c_s"):
+ case "fcmla_asimdelem_c_s"_h:
vform = kFormat4S;
index >>= 1;
VIXL_FALLTHROUGH();
- case Hash("fcmla_asimdelem_c_h"):
+ case "fcmla_asimdelem_c_h"_h:
fcmla(vform, rd, rn, rm, index, instr->GetImmRotFcmlaSca());
break;
default:
@@ -7888,16 +7888,16 @@
dup_elements_to_segments(VectorFormatFillQ(vform), temp, rm, index);
switch (form_hash_) {
- case Hash("sdot_asimdelem_d"):
+ case "sdot_asimdelem_d"_h:
sdot(vform, rd, rn, temp);
break;
- case Hash("udot_asimdelem_d"):
+ case "udot_asimdelem_d"_h:
udot(vform, rd, rn, temp);
break;
- case Hash("sudot_asimdelem_d"):
+ case "sudot_asimdelem_d"_h:
usdot(vform, rd, temp, rn);
break;
- case Hash("usdot_asimdelem_d"):
+ case "usdot_asimdelem_d"_h:
usdot(vform, rd, rn, temp);
break;
}
@@ -7921,25 +7921,25 @@
SimVRegister& rm = ReadVRegister(rm_reg);
switch (form_hash_) {
- case Hash("mul_asimdelem_r"):
+ case "mul_asimdelem_r"_h:
mul(vform, rd, rn, rm, index);
break;
- case Hash("mla_asimdelem_r"):
+ case "mla_asimdelem_r"_h:
mla(vform, rd, rn, rm, index);
break;
- case Hash("mls_asimdelem_r"):
+ case "mls_asimdelem_r"_h:
mls(vform, rd, rn, rm, index);
break;
- case Hash("sqdmulh_asimdelem_r"):
+ case "sqdmulh_asimdelem_r"_h:
sqdmulh(vform, rd, rn, rm, index);
break;
- case Hash("sqrdmulh_asimdelem_r"):
+ case "sqrdmulh_asimdelem_r"_h:
sqrdmulh(vform, rd, rn, rm, index);
break;
- case Hash("sqrdmlah_asimdelem_r"):
+ case "sqrdmlah_asimdelem_r"_h:
sqrdmlah(vform, rd, rn, rm, index);
break;
- case Hash("sqrdmlsh_asimdelem_r"):
+ case "sqrdmlsh_asimdelem_r"_h:
sqrdmlsh(vform, rd, rn, rm, index);
break;
}
@@ -9569,66 +9569,66 @@
bool shift_in_ls_byte = false;
switch (form_hash_) {
- case Hash("asrr_z_p_zz"):
+ case "asrr_z_p_zz"_h:
sshr(vform, result, zm, zdn);
break;
- case Hash("asr_z_p_zz"):
+ case "asr_z_p_zz"_h:
sshr(vform, result, zdn, zm);
break;
- case Hash("lslr_z_p_zz"):
+ case "lslr_z_p_zz"_h:
sshl(vform, result, zm, zdn, shift_in_ls_byte);
break;
- case Hash("lsl_z_p_zz"):
+ case "lsl_z_p_zz"_h:
sshl(vform, result, zdn, zm, shift_in_ls_byte);
break;
- case Hash("lsrr_z_p_zz"):
+ case "lsrr_z_p_zz"_h:
ushr(vform, result, zm, zdn);
break;
- case Hash("lsr_z_p_zz"):
+ case "lsr_z_p_zz"_h:
ushr(vform, result, zdn, zm);
break;
- case Hash("sqrshl_z_p_zz"):
+ case "sqrshl_z_p_zz"_h:
sshl(vform, result, zdn, zm, shift_in_ls_byte)
.Round(vform)
.SignedSaturate(vform);
break;
- case Hash("sqrshlr_z_p_zz"):
+ case "sqrshlr_z_p_zz"_h:
sshl(vform, result, zm, zdn, shift_in_ls_byte)
.Round(vform)
.SignedSaturate(vform);
break;
- case Hash("sqshl_z_p_zz"):
+ case "sqshl_z_p_zz"_h:
sshl(vform, result, zdn, zm, shift_in_ls_byte).SignedSaturate(vform);
break;
- case Hash("sqshlr_z_p_zz"):
+ case "sqshlr_z_p_zz"_h:
sshl(vform, result, zm, zdn, shift_in_ls_byte).SignedSaturate(vform);
break;
- case Hash("srshl_z_p_zz"):
+ case "srshl_z_p_zz"_h:
sshl(vform, result, zdn, zm, shift_in_ls_byte).Round(vform);
break;
- case Hash("srshlr_z_p_zz"):
+ case "srshlr_z_p_zz"_h:
sshl(vform, result, zm, zdn, shift_in_ls_byte).Round(vform);
break;
- case Hash("uqrshl_z_p_zz"):
+ case "uqrshl_z_p_zz"_h:
ushl(vform, result, zdn, zm, shift_in_ls_byte)
.Round(vform)
.UnsignedSaturate(vform);
break;
- case Hash("uqrshlr_z_p_zz"):
+ case "uqrshlr_z_p_zz"_h:
ushl(vform, result, zm, zdn, shift_in_ls_byte)
.Round(vform)
.UnsignedSaturate(vform);
break;
- case Hash("uqshl_z_p_zz"):
+ case "uqshl_z_p_zz"_h:
ushl(vform, result, zdn, zm, shift_in_ls_byte).UnsignedSaturate(vform);
break;
- case Hash("uqshlr_z_p_zz"):
+ case "uqshlr_z_p_zz"_h:
ushl(vform, result, zm, zdn, shift_in_ls_byte).UnsignedSaturate(vform);
break;
- case Hash("urshl_z_p_zz"):
+ case "urshl_z_p_zz"_h:
ushl(vform, result, zdn, zm, shift_in_ls_byte).Round(vform);
break;
- case Hash("urshlr_z_p_zz"):
+ case "urshlr_z_p_zz"_h:
ushl(vform, result, zm, zdn, shift_in_ls_byte).Round(vform);
break;
default:
@@ -11073,10 +11073,10 @@
int64_t ssrc2 = is_64_bit ? ReadXRegister(rm_code) : ReadWRegister(rm_code);
uint64_t usrc2 = ssrc2 & mask;
- bool reverse = (form_hash_ == Hash("whilege_p_p_rr")) ||
- (form_hash_ == Hash("whilegt_p_p_rr")) ||
- (form_hash_ == Hash("whilehi_p_p_rr")) ||
- (form_hash_ == Hash("whilehs_p_p_rr"));
+ bool reverse = (form_hash_ == "whilege_p_p_rr"_h) ||
+ (form_hash_ == "whilegt_p_p_rr"_h) ||
+ (form_hash_ == "whilehi_p_p_rr"_h) ||
+ (form_hash_ == "whilehs_p_p_rr"_h);
int lane_count = LaneCountFromFormat(vform);
bool last = true;
@@ -11086,28 +11086,28 @@
bool cond = false;
switch (form_hash_) {
- case Hash("whilele_p_p_rr"):
+ case "whilele_p_p_rr"_h:
cond = ssrc1 <= ssrc2;
break;
- case Hash("whilelo_p_p_rr"):
+ case "whilelo_p_p_rr"_h:
cond = usrc1 < usrc2;
break;
- case Hash("whilels_p_p_rr"):
+ case "whilels_p_p_rr"_h:
cond = usrc1 <= usrc2;
break;
- case Hash("whilelt_p_p_rr"):
+ case "whilelt_p_p_rr"_h:
cond = ssrc1 < ssrc2;
break;
- case Hash("whilege_p_p_rr"):
+ case "whilege_p_p_rr"_h:
cond = ssrc1 >= ssrc2;
break;
- case Hash("whilegt_p_p_rr"):
+ case "whilegt_p_p_rr"_h:
cond = ssrc1 > ssrc2;
break;
- case Hash("whilehi_p_p_rr"):
+ case "whilehi_p_p_rr"_h:
cond = usrc1 > usrc2;
break;
- case Hash("whilehs_p_p_rr"):
+ case "whilehs_p_p_rr"_h:
cond = usrc1 >= usrc2;
break;
default:
@@ -11389,13 +11389,13 @@
SimVRegister& zm = ReadVRegister(instr->GetRm());
switch (form_hash_) {
- case Hash("sdot_z_zzz"):
+ case "sdot_z_zzz"_h:
sdot(vform, zda, zn, zm);
break;
- case Hash("udot_z_zzz"):
+ case "udot_z_zzz"_h:
udot(vform, zda, zn, zm);
break;
- case Hash("usdot_z_zzz_s"):
+ case "usdot_z_zzz_s"_h:
usdot(vform, zda, zn, zm);
break;
default:
@@ -12239,10 +12239,10 @@
uint64_t dwords = 2;
VectorFormat vform_dst = kFormatVnQ;
- if ((form_hash_ == Hash("ld1rob_z_p_bi_u8")) ||
- (form_hash_ == Hash("ld1roh_z_p_bi_u16")) ||
- (form_hash_ == Hash("ld1row_z_p_bi_u32")) ||
- (form_hash_ == Hash("ld1rod_z_p_bi_u64"))) {
+ if ((form_hash_ == "ld1rob_z_p_bi_u8"_h) ||
+ (form_hash_ == "ld1roh_z_p_bi_u16"_h) ||
+ (form_hash_ == "ld1row_z_p_bi_u32"_h) ||
+ (form_hash_ == "ld1rod_z_p_bi_u64"_h)) {
dwords = 4;
vform_dst = kFormatVnO;
}
@@ -12267,10 +12267,10 @@
uint64_t bytes = 16;
VectorFormat vform_dst = kFormatVnQ;
- if ((form_hash_ == Hash("ld1rob_z_p_br_contiguous")) ||
- (form_hash_ == Hash("ld1roh_z_p_br_contiguous")) ||
- (form_hash_ == Hash("ld1row_z_p_br_contiguous")) ||
- (form_hash_ == Hash("ld1rod_z_p_br_contiguous"))) {
+ if ((form_hash_ == "ld1rob_z_p_br_contiguous"_h) ||
+ (form_hash_ == "ld1roh_z_p_br_contiguous"_h) ||
+ (form_hash_ == "ld1row_z_p_br_contiguous"_h) ||
+ (form_hash_ == "ld1rod_z_p_br_contiguous"_h)) {
bytes = 32;
vform_dst = kFormatVnO;
}
@@ -12840,18 +12840,18 @@
dup_elements_to_segments(vform, temp, zm, index);
switch (form_hash_) {
- case Hash("sdot_z_zzzi_d"):
- case Hash("sdot_z_zzzi_s"):
+ case "sdot_z_zzzi_d"_h:
+ case "sdot_z_zzzi_s"_h:
sdot(vform, zda, zn, temp);
break;
- case Hash("udot_z_zzzi_d"):
- case Hash("udot_z_zzzi_s"):
+ case "udot_z_zzzi_d"_h:
+ case "udot_z_zzzi_s"_h:
udot(vform, zda, zn, temp);
break;
- case Hash("sudot_z_zzzi_s"):
+ case "sudot_z_zzzi_s"_h:
usdot(vform, zda, temp, zn);
break;
- case Hash("usdot_z_zzzi_s"):
+ case "usdot_z_zzzi_s"_h:
usdot(vform, zda, zn, temp);
break;
default:
@@ -12869,22 +12869,22 @@
bool n_signed = false;
bool m_signed = false;
switch (form_hash_) {
- case Hash("smmla_asimdsame2_g"):
+ case "smmla_asimdsame2_g"_h:
vform = kFormat4S;
VIXL_FALLTHROUGH();
- case Hash("smmla_z_zzz"):
+ case "smmla_z_zzz"_h:
n_signed = m_signed = true;
break;
- case Hash("ummla_asimdsame2_g"):
+ case "ummla_asimdsame2_g"_h:
vform = kFormat4S;
VIXL_FALLTHROUGH();
- case Hash("ummla_z_zzz"):
+ case "ummla_z_zzz"_h:
// Nothing to do.
break;
- case Hash("usmmla_asimdsame2_g"):
+ case "usmmla_asimdsame2_g"_h:
vform = kFormat4S;
VIXL_FALLTHROUGH();
- case Hash("usmmla_z_zzz"):
+ case "usmmla_z_zzz"_h:
m_signed = true;
break;
default:
@@ -12901,8 +12901,8 @@
SimVRegister& zm = ReadVRegister(instr->GetRm());
switch (form_hash_) {
- case Hash("fmmla_z_zzz_s"):
- case Hash("fmmla_z_zzz_d"):
+ case "fmmla_z_zzz_s"_h:
+ case "fmmla_z_zzz_d"_h:
fmatmul(vform, zdn, zn, zm);
break;
default:
@@ -13354,10 +13354,10 @@
SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
switch (form_hash_) {
- case Hash("splice_z_p_zz_des"):
+ case "splice_z_p_zz_des"_h:
splice(vform, zd, pg, zd, zn);
break;
- case Hash("splice_z_p_zz_con"):
+ case "splice_z_p_zz_con"_h:
splice(vform, zd, pg, zn, zn2);
break;
default:
@@ -13473,13 +13473,13 @@
SimVRegister& zm = ReadVRegister(instr->GetRm());
switch (form_hash_) {
- case Hash("tbl_z_zz_1"):
+ case "tbl_z_zz_1"_h:
tbl(vform, zd, zn, zm);
break;
- case Hash("tbl_z_zz_2"):
+ case "tbl_z_zz_2"_h:
tbl(vform, zd, zn, zn2, zm);
break;
- case Hash("tbx_z_zz"):
+ case "tbx_z_zz"_h:
tbx(vform, zd, zn, zm);
break;
default:
diff --git a/src/aarch64/simulator-aarch64.h b/src/aarch64/simulator-aarch64.h
index d38e8b0..1555922 100644
--- a/src/aarch64/simulator-aarch64.h
+++ b/src/aarch64/simulator-aarch64.h
@@ -1286,8 +1286,8 @@
}
}
- bool last_instr_was_movprfx = (form_hash_ == Hash("movprfx_z_z")) ||
- (form_hash_ == Hash("movprfx_z_p_z"));
+ bool last_instr_was_movprfx =
+ (form_hash_ == "movprfx_z_z"_h) || (form_hash_ == "movprfx_z_p_z"_h);
// decoder_->Decode(...) triggers at least the following visitors:
// 1. The CPUFeaturesAuditor (`cpu_features_auditor_`).
@@ -4976,7 +4976,7 @@
private:
using FormToVisitorFnMap =
- std::unordered_map<std::string,
+ std::unordered_map<uint32_t,
std::function<void(Simulator*, const Instruction*)>>;
static const FormToVisitorFnMap* GetFormToVisitorFnMap();
diff --git a/src/globals-vixl.h b/src/globals-vixl.h
index 4dc8c02..c7da8a6 100644
--- a/src/globals-vixl.h
+++ b/src/globals-vixl.h
@@ -158,7 +158,7 @@
#endif
// This is not as powerful as template based assertions, but it is simple.
// It assumes that the descriptions are unique. If this starts being a problem,
-// we can switch to a different implemention.
+// we can switch to a different implementation.
#define VIXL_CONCAT(a, b) a##b
#if __cplusplus >= 201103L
#define VIXL_STATIC_ASSERT_LINE(line_unused, condition, message) \
diff --git a/src/invalset-vixl.h b/src/invalset-vixl.h
index 8bd6035..671dc0d 100644
--- a/src/invalset-vixl.h
+++ b/src/invalset-vixl.h
@@ -112,7 +112,7 @@
size_t size() const;
// Returns true if no elements are stored in the set.
- // Note that this does not mean the the backing storage is empty: it can still
+ // Note that this does not mean the backing storage is empty: it can still
// contain invalid elements.
bool empty() const;
diff --git a/src/pool-manager.h b/src/pool-manager.h
index 2e73f8e..27fa69e 100644
--- a/src/pool-manager.h
+++ b/src/pool-manager.h
@@ -369,8 +369,8 @@
// Specify the possible locations where the object could be stored. AArch32's
// PC offset, and T32's PC alignment calculations should be applied by the
- // Assembler, not here. The PoolManager deals only with simple locationes.
- // Including min_object_adddress_ is necessary to handle AArch32 some
+ // Assembler, not here. The PoolManager deals only with simple locations.
+ // Including min_object_address_ is necessary to handle AArch32 some
// instructions which have a minimum offset of 0, but also have the implicit
// PC offset.
// Note that this structure cannot handle sparse ranges, such as A32's ADR,
diff --git a/src/utils-vixl.h b/src/utils-vixl.h
index 8a5f6b9..3813b59 100644
--- a/src/utils-vixl.h
+++ b/src/utils-vixl.h
@@ -318,7 +318,7 @@
bool operator>(SimFloat16 rhs) const;
bool operator==(SimFloat16 rhs) const;
bool operator!=(SimFloat16 rhs) const;
- // This is necessary for conversions peformed in (macro asm) Fmov.
+ // This is necessary for conversions performed in (macro asm) Fmov.
bool operator==(double rhs) const;
operator double() const;
};
@@ -1412,6 +1412,8 @@
}
}
+constexpr uint32_t operator"" _h(const char* x, size_t) { return Hash(x); }
+
} // namespace vixl
#endif // VIXL_UTILS_H
diff --git a/test/aarch32/config/cond-rd-operand-rn-shift-rs-t32.json b/test/aarch32/config/cond-rd-operand-rn-shift-rs-t32.json
index 6e8f4c8..4d0064d 100644
--- a/test/aarch32/config/cond-rd-operand-rn-shift-rs-t32.json
+++ b/test/aarch32/config/cond-rd-operand-rn-shift-rs-t32.json
@@ -97,7 +97,7 @@
"type": "assembler",
"test-cases": [
{
- "name": "Unconditionnal",
+ "name": "Unconditional",
"operands": [
"cond", "rd", "rn", "shift", "rs"
],
diff --git a/test/aarch32/config/cond-rd-rn-operand-rm-t32.json b/test/aarch32/config/cond-rd-rn-operand-rm-t32.json
index 0affe92..b810c3c 100644
--- a/test/aarch32/config/cond-rd-rn-operand-rm-t32.json
+++ b/test/aarch32/config/cond-rd-rn-operand-rm-t32.json
@@ -192,7 +192,7 @@
"type": "assembler",
"test-cases": [
{
- "name": "Unconditionnal",
+ "name": "Unconditional",
"operands": [
"cond", "rd", "rn", "rm"
],
diff --git a/test/aarch32/config/data-types.json b/test/aarch32/config/data-types.json
index c3409b0..aa773d6 100644
--- a/test/aarch32/config/data-types.json
+++ b/test/aarch32/config/data-types.json
@@ -1100,7 +1100,7 @@
"identifier": "OffsetLowerThan4096",
"type": "int32_t",
// These variants are a random sample of 500 integers out of all integers
- // from 1 to 4094 (included). We've added 0 and 4095 explicitely.
+ // from 1 to 4094 (included). We've added 0 and 4095 explicitly.
"variants": [
"0",
"4095",
@@ -1700,7 +1700,7 @@
],
"default": "NoFlag"
},
- // TODO: Consider having a seperate list for inputs for which we are only
+ // TODO: Consider having a separate list for inputs for which we are only
// interested in recording the value after the instruction has executed.
// This applies to `Q` and `GE`.
{
@@ -1781,7 +1781,7 @@
"identifier": "RegisterOffsetLowerThan4096",
"type": "Register",
// These values are a random sample of 500 integers out of all integers
- // from 1 to 4094 (included). We've added 0 and 4095 explicitely.
+ // from 1 to 4094 (included). We've added 0 and 4095 explicitly.
"values": [
"0",
"4095",
diff --git a/test/aarch32/config/template-assembler-aarch32.cc.in b/test/aarch32/config/template-assembler-aarch32.cc.in
index a602860..456668d 100644
--- a/test/aarch32/config/template-assembler-aarch32.cc.in
+++ b/test/aarch32/config/template-assembler-aarch32.cc.in
@@ -49,7 +49,7 @@
${instruction_list_declaration}
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/config/template-assembler-negative-aarch32.cc.in b/test/aarch32/config/template-assembler-negative-aarch32.cc.in
index 8a7cd63..006ff01 100644
--- a/test/aarch32/config/template-assembler-negative-aarch32.cc.in
+++ b/test/aarch32/config/template-assembler-negative-aarch32.cc.in
@@ -49,7 +49,7 @@
${instruction_list_declaration}
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/config/template-macro-assembler-aarch32.cc.in b/test/aarch32/config/template-macro-assembler-aarch32.cc.in
index ab37208..c76b311 100644
--- a/test/aarch32/config/template-macro-assembler-aarch32.cc.in
+++ b/test/aarch32/config/template-macro-assembler-aarch32.cc.in
@@ -53,7 +53,7 @@
${instruction_list_declaration}
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/config/template-simulator-aarch32.cc.in b/test/aarch32/config/template-simulator-aarch32.cc.in
index 9e24225..619bb8d 100644
--- a/test/aarch32/config/template-simulator-aarch32.cc.in
+++ b/test/aarch32/config/template-simulator-aarch32.cc.in
@@ -113,7 +113,7 @@
${instruction_list_declaration}
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-assembler-aarch32.cc b/test/aarch32/test-assembler-aarch32.cc
index 418bc11..3432a80 100644
--- a/test/aarch32/test-assembler-aarch32.cc
+++ b/test/aarch32/test-assembler-aarch32.cc
@@ -1490,7 +1490,7 @@
VIXL_CHECK(masm->GetCursorOffset() == end);
}
- // Check that the pool has not been emited along the way.
+ // Check that the pool has not been emitted along the way.
CHECK_POOL_SIZE(8);
// This extra instruction should trigger an emit of the pool.
__ Nop();
@@ -3653,7 +3653,7 @@
// below). The cases are split in 4 groups:
//
// - 0..3: Generate various amount of nops.
- // - 4..7: Generate various load intstructions with literals.
+ // - 4..7: Generate various load instructions with literals.
// - 8..14: Generate various branch instructions.
// - 15..19: Generate various amount of nops.
//
@@ -4849,7 +4849,7 @@
// Generate a "B" and a "Cbz" which have the same checkpoint. Without proper
// management (i.e. if the veneers were only generated at the shared
-// checkpoint), one one of the branches would be out of range.
+// checkpoint), one of the branches would be out of range.
TEST_T32(veneer_simultaneous) {
SETUP();
@@ -5109,7 +5109,7 @@
__ Ldr(r11, literal);
// The range for ldr is 4095, the range for cbz is 127. Generate nops
- // to have the ldr becomming out of range just before the cbz.
+ // to have the ldr becoming out of range just before the cbz.
const int NUM_NOPS = 2044;
const int NUM_RANGE = 58;
@@ -5184,7 +5184,7 @@
__ add(r1, r1, 3);
}
__ Bind(&labels[test_num]);
- // Emit the literal pool if it has not beeen emitted (it's the case for
+ // Emit the literal pool if it has not been emitted (it's the case for
// the lower values of test_num).
__ EmitLiteralPool(PoolManager<int32_t>::kBranchRequired);
}
diff --git a/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc b/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc
index f9e09bf..497ceac 100644
--- a/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc
+++ b/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc
@@ -63,7 +63,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc b/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc
index 1ef8aff..36182a3 100644
--- a/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc
+++ b/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc
@@ -63,7 +63,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-not-f16-a32.cc b/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-not-f16-a32.cc
index 1bb0f55..d2cc92c 100644
--- a/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-not-f16-a32.cc
+++ b/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-not-f16-a32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-not-f16-t32.cc b/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-not-f16-t32.cc
index d2de584..94ef61f 100644
--- a/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-not-f16-t32.cc
+++ b/test/aarch32/test-assembler-cond-dt-drt-drd-drn-drm-float-not-f16-t32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-memop-immediate-512-a32.cc b/test/aarch32/test-assembler-cond-rd-memop-immediate-512-a32.cc
index b4f3b52..251d5ec 100644
--- a/test/aarch32/test-assembler-cond-rd-memop-immediate-512-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-memop-immediate-512-a32.cc
@@ -56,7 +56,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-memop-immediate-8192-a32.cc b/test/aarch32/test-assembler-cond-rd-memop-immediate-8192-a32.cc
index 2a06bc8..4489c43 100644
--- a/test/aarch32/test-assembler-cond-rd-memop-immediate-8192-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-memop-immediate-8192-a32.cc
@@ -56,7 +56,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-memop-rs-a32.cc b/test/aarch32/test-assembler-cond-rd-memop-rs-a32.cc
index 00e19be..e88b260 100644
--- a/test/aarch32/test-assembler-cond-rd-memop-rs-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-memop-rs-a32.cc
@@ -60,7 +60,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc b/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc
index 733f8de..3fe9c2f 100644
--- a/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc
@@ -56,7 +56,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc b/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc
index bdb57c5..b3300a7 100644
--- a/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc
@@ -56,7 +56,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-const-can-use-pc-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-const-can-use-pc-a32.cc
index 22021a4..714ea04 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-const-can-use-pc-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-const-can-use-pc-a32.cc
@@ -56,7 +56,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-const-cannot-use-pc-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-const-cannot-use-pc-a32.cc
index ebbab48..ceb6dea 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-const-cannot-use-pc-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-const-cannot-use-pc-a32.cc
@@ -56,7 +56,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-const-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-const-t32.cc
index c20cc62..837d208 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-const-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-const-t32.cc
@@ -60,7 +60,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-imm16-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-imm16-t32.cc
index 0557e6f..35487e0 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-imm16-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-imm16-t32.cc
@@ -55,7 +55,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-a32.cc
index c64109a..2e2d861 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-a32.cc
@@ -66,7 +66,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-identical-low-registers-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-identical-low-registers-in-it-block-t32.cc
index eb0563f..ed6c6d8 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-identical-low-registers-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-identical-low-registers-in-it-block-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-in-it-block-t32.cc
index 11c29ca..2e3a61b 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-in-it-block-t32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc
index be7e421..2dd7130 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc
index a2c6125..4a37546 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-a32.cc
@@ -58,7 +58,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc
index 6372cde..398c32f 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-ror-amount-t32.cc
@@ -58,7 +58,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc
index ef95d1e..1aebeff 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc
@@ -60,7 +60,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc
index 1a92f9b..f55bd9a 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc
index 1ba217d..c9a4cd9 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc
@@ -60,7 +60,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc
index ef719ee..5f94dbe 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc
@@ -60,7 +60,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc
index 6ea6ef4..896d2e3 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc
index 33d8ca2..f7fc177 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc
@@ -60,7 +60,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc
index 3276576..962d108 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-a32.cc
@@ -60,7 +60,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc
index 5571d79..0134848 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc
index df3f955..a182e9e 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc
index 2035a1c..0fddef2 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-shift-rs-t32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-operand-rn-t32.cc b/test/aarch32/test-assembler-cond-rd-operand-rn-t32.cc
index 4c494fd..62a0ca6 100644
--- a/test/aarch32/test-assembler-cond-rd-operand-rn-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-operand-rn-t32.cc
@@ -66,7 +66,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-pc-operand-imm12-t32.cc b/test/aarch32/test-assembler-cond-rd-pc-operand-imm12-t32.cc
index fe7c799..c01fae7 100644
--- a/test/aarch32/test-assembler-cond-rd-pc-operand-imm12-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-pc-operand-imm12-t32.cc
@@ -55,7 +55,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-pc-operand-imm8-t32.cc b/test/aarch32/test-assembler-cond-rd-pc-operand-imm8-t32.cc
index 405a829..3b17bdd 100644
--- a/test/aarch32/test-assembler-cond-rd-pc-operand-imm8-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-pc-operand-imm8-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-a32.cc
index a0a7579..615e634 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-a32.cc
@@ -59,7 +59,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-const-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-const-a32.cc
index ea6f4ca..6cf4ba0 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-const-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-const-a32.cc
@@ -72,7 +72,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-const-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-const-t32.cc
index 7edd26d..0d7b92a 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-const-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-const-t32.cc
@@ -72,7 +72,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-imm12-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-imm12-t32.cc
index d8bc2ca..0adc38c 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-imm12-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-imm12-t32.cc
@@ -56,7 +56,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-a32.cc
index 9b94950..1d2141d 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-a32.cc
@@ -86,7 +86,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc
index 1c805b1..3993792 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc
index f51718a..5013001 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc
@@ -62,7 +62,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-t32.cc
index 0114858..b979b3a 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rd-is-rn-is-sp-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rd-is-rn-is-sp-in-it-block-t32.cc
index fae7287..a5c876c 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rd-is-rn-is-sp-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rd-is-rn-is-sp-in-it-block-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rn-is-sp-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rn-is-sp-in-it-block-t32.cc
index 7de517d..4b015d0 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rn-is-sp-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-rn-is-sp-in-it-block-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc
index 03fd978..3c4d6dd 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc
@@ -58,7 +58,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc
index f3590bb..41c4c14 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc
@@ -58,7 +58,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
index f7bd97d..7d0375f 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
@@ -72,7 +72,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
index ebe495d..885a3cf 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
@@ -72,7 +72,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
index a0ca121..803d67f 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
@@ -72,7 +72,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
index 318b6f9..254f915 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
@@ -72,7 +72,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc
index d181fcc..7f41a0b 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc
@@ -72,7 +72,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32.cc
index ed0b7fe..a9c9e8f 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-operand-rm-t32.cc
@@ -86,7 +86,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-rm-a32.cc b/test/aarch32/test-assembler-cond-rd-rn-rm-a32.cc
index 3f6c7fc..a0a5315 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-rm-a32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-rm-a32.cc
@@ -110,7 +110,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-rm-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-rm-t32.cc
index c7812c8..f052c2e 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-rm-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-rm-t32.cc
@@ -109,7 +109,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-rn-t32.cc b/test/aarch32/test-assembler-cond-rd-rn-t32.cc
index bc39853..bebef77 100644
--- a/test/aarch32/test-assembler-cond-rd-rn-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-rn-t32.cc
@@ -59,7 +59,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rd-sp-operand-imm8-t32.cc b/test/aarch32/test-assembler-cond-rd-sp-operand-imm8-t32.cc
index bd1f020..57fecaa 100644
--- a/test/aarch32/test-assembler-cond-rd-sp-operand-imm8-t32.cc
+++ b/test/aarch32/test-assembler-cond-rd-sp-operand-imm8-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rdlow-operand-imm8-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rdlow-operand-imm8-in-it-block-t32.cc
index 217af34..ed99425 100644
--- a/test/aarch32/test-assembler-cond-rdlow-operand-imm8-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-operand-imm8-in-it-block-t32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32.cc b/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32.cc
index 1332b8f..50fddd9 100644
--- a/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-operand-imm8-t32.cc
@@ -55,7 +55,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc
index ef6f0d2..bb71431 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-t32.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-t32.cc
index 9d303cb..029e37f 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm3-t32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc
index 11bb597..1a6a704 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-t32.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-t32.cc
index b946215..2cd95af 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-imm8-t32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc
index ded8ee0..1ad13e3 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-zero-t32.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-zero-t32.cc
index 5f7f55c..f6b06c3 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-zero-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-operand-immediate-zero-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc
index fc8fe31..bcf9dcb 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc b/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc
index 279c443..e45a648 100644
--- a/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc
+++ b/test/aarch32/test-assembler-cond-rdlow-rnlow-rmlow-t32.cc
@@ -52,7 +52,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-cond-sp-sp-operand-imm7-t32.cc b/test/aarch32/test-assembler-cond-sp-sp-operand-imm7-t32.cc
index fd9d3da..93c66fe 100644
--- a/test/aarch32/test-assembler-cond-sp-sp-operand-imm7-t32.cc
+++ b/test/aarch32/test-assembler-cond-sp-sp-operand-imm7-t32.cc
@@ -54,7 +54,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc b/test/aarch32/test-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc
index 18d4c02..d88aa9f 100644
--- a/test/aarch32/test-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc
+++ b/test/aarch32/test-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc
@@ -72,7 +72,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-rd-rn-rm-a32.cc b/test/aarch32/test-assembler-rd-rn-rm-a32.cc
index c838c75..05662a2 100644
--- a/test/aarch32/test-assembler-rd-rn-rm-a32.cc
+++ b/test/aarch32/test-assembler-rd-rn-rm-a32.cc
@@ -58,7 +58,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-assembler-rd-rn-rm-t32.cc b/test/aarch32/test-assembler-rd-rn-rm-t32.cc
index a49c67f..7da4587 100644
--- a/test/aarch32/test-assembler-rd-rn-rm-t32.cc
+++ b/test/aarch32/test-assembler-rd-rn-rm-t32.cc
@@ -58,7 +58,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-disasm-a32.cc b/test/aarch32/test-disasm-a32.cc
index c6acac9..c229c2f 100644
--- a/test/aarch32/test-disasm-a32.cc
+++ b/test/aarch32/test-disasm-a32.cc
@@ -505,11 +505,11 @@
// - Immediate form. We can always re-use `rn`.
- // No need for temporay registers.
+ // No need for temporary registers.
COMPARE_T32(Rsc(r0, r1, 1),
"mvn r0, r1\n"
"adc r0, #1\n");
- // No need for temporay registers.
+ // No need for temporary registers.
COMPARE_T32(Rscs(r0, r0, 2),
"mvn r0, r0\n"
"adcs r0, #2\n");
@@ -568,7 +568,7 @@
// - Shifted register form.
- // No need for temporay registers.
+ // No need for temporary registers.
COMPARE_T32(Rsc(r0, r1, Operand(r2, LSL, 1)),
"mvn r0, r1\n"
"adc r0, r2, lsl #1\n");
@@ -1508,7 +1508,7 @@
TEST(macro_assembler_InstructionCondSizeRROp) {
SETUP();
- // Special case for Orr <-> Orn correspondance.
+ // Special case for Orr <-> Orn correspondence.
COMPARE_T32(Orr(r0, r1, 0x00ffffff), "orn r0, r1, #0xff000000\n");
COMPARE_T32(Orrs(r0, r1, 0x00ffffff), "orns r0, r1, #0xff000000\n");
diff --git a/test/aarch32/test-macro-assembler-cond-rd-rn-a32.cc b/test/aarch32/test-macro-assembler-cond-rd-rn-a32.cc
index be77bd9..46706e3 100644
--- a/test/aarch32/test-macro-assembler-cond-rd-rn-a32.cc
+++ b/test/aarch32/test-macro-assembler-cond-rd-rn-a32.cc
@@ -63,7 +63,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-macro-assembler-cond-rd-rn-pc-a32.cc b/test/aarch32/test-macro-assembler-cond-rd-rn-pc-a32.cc
index 830edd1..47af778 100644
--- a/test/aarch32/test-macro-assembler-cond-rd-rn-pc-a32.cc
+++ b/test/aarch32/test-macro-assembler-cond-rd-rn-pc-a32.cc
@@ -56,7 +56,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-macro-assembler-cond-rd-rn-t32.cc b/test/aarch32/test-macro-assembler-cond-rd-rn-t32.cc
index d88cbf3..eccd35e 100644
--- a/test/aarch32/test-macro-assembler-cond-rd-rn-t32.cc
+++ b/test/aarch32/test-macro-assembler-cond-rd-rn-t32.cc
@@ -63,7 +63,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` has
// various layouts across generated tests so it absolutely cannot be shared.
diff --git a/test/aarch32/test-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc b/test/aarch32/test-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc
index a8417e0..db9ce9c 100644
--- a/test/aarch32/test-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc
+++ b/test/aarch32/test-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc
@@ -118,7 +118,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc b/test/aarch32/test-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc
index b9c97b6..a9843c5 100644
--- a/test/aarch32/test-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc
+++ b/test/aarch32/test-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc
@@ -118,7 +118,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-memop-immediate-512-a32.cc b/test/aarch32/test-simulator-cond-rd-memop-immediate-512-a32.cc
index 4fa3175..3945393 100644
--- a/test/aarch32/test-simulator-cond-rd-memop-immediate-512-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-memop-immediate-512-a32.cc
@@ -120,7 +120,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-memop-immediate-8192-a32.cc b/test/aarch32/test-simulator-cond-rd-memop-immediate-8192-a32.cc
index 7936fa4..18a8156 100644
--- a/test/aarch32/test-simulator-cond-rd-memop-immediate-8192-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-memop-immediate-8192-a32.cc
@@ -120,7 +120,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-memop-rs-a32.cc b/test/aarch32/test-simulator-cond-rd-memop-rs-a32.cc
index 3feb4fc..d8fdf9a 100644
--- a/test/aarch32/test-simulator-cond-rd-memop-rs-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-memop-rs-a32.cc
@@ -124,7 +124,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc b/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc
index ce16a6f..de4b428 100644
--- a/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc
@@ -120,7 +120,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc b/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc
index 797ec6c..ab4c4d7 100644
--- a/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc
@@ -120,7 +120,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-const-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-const-a32.cc
index 8211042..207996d 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-const-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-const-a32.cc
@@ -124,7 +124,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-const-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-const-t32.cc
index 08de626..291afec 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-const-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-const-t32.cc
@@ -124,7 +124,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-imm16-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-imm16-t32.cc
index 10fe377..0b4c89e 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-imm16-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-imm16-t32.cc
@@ -118,7 +118,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-a32.cc
index b8131d5..bceb77d 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-a32.cc
@@ -130,7 +130,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc
index cd3addb..4b55b01 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-a32.cc
@@ -122,7 +122,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc
index 3d6ea35..ca10bb6 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-ror-amount-t32.cc
@@ -122,7 +122,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc
index 41c1eea..1af354c 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc
@@ -124,7 +124,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc
index 83d79e8..8d67b8d 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc
@@ -124,7 +124,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc
index 7327a5f..c189843 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc
@@ -124,7 +124,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc
index af87801..3c9fb1a 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc
@@ -124,7 +124,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc
index 3df8bcc..daa5ba4 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-a32.cc
@@ -124,7 +124,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc
index 9c3fc8f..ced940f 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-shift-rs-t32.cc
@@ -118,7 +118,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-operand-rn-t32.cc b/test/aarch32/test-simulator-cond-rd-operand-rn-t32.cc
index d410510..c60c666 100644
--- a/test/aarch32/test-simulator-cond-rd-operand-rn-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-operand-rn-t32.cc
@@ -130,7 +130,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-a32.cc
index 25530f7..33776c3 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-a32.cc
@@ -123,7 +123,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-const-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-const-a32.cc
index e2836d1..7862115 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-const-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-const-a32.cc
@@ -136,7 +136,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-const-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-const-t32.cc
index 6fe473a..1c640a6 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-const-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-const-t32.cc
@@ -136,7 +136,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-imm12-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-imm12-t32.cc
index bee7d00..f6644d3 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-imm12-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-imm12-t32.cc
@@ -118,7 +118,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-a32.cc
index 606e6bb..8f13e0a 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-a32.cc
@@ -150,7 +150,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc
index 536c0ef..fdedd4b 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc
@@ -122,7 +122,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc
index ea0eebb..ce8881a 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc
@@ -122,7 +122,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
index b654ac3..18fa62e 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc
@@ -136,7 +136,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
index bf35690..0566348 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc
@@ -136,7 +136,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
index ab0b3cd..bba5896 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc
@@ -136,7 +136,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
index 44506e7..f0cf8b3 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc
@@ -136,7 +136,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc
index f3a64b6..7070d6d 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc
@@ -136,7 +136,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-t32.cc
index ebca6dc..8527ce0 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-operand-rm-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-operand-rm-t32.cc
@@ -150,7 +150,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-a32.cc
index 5b4fbe1..f4acc7f 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-a32.cc
@@ -174,7 +174,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-ge-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-ge-a32.cc
index 0ad798e..1f147c9 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-ge-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-ge-a32.cc
@@ -128,7 +128,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-ge-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-ge-t32.cc
index 1f1fced..385552e 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-ge-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-ge-t32.cc
@@ -128,7 +128,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-q-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-q-a32.cc
index a6e19c9..7df7810 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-q-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-q-a32.cc
@@ -120,7 +120,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-q-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-q-t32.cc
index e0339c7..3a4fbe6 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-q-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-q-t32.cc
@@ -120,7 +120,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-sel-a32.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-sel-a32.cc
index c497839..f1228b5 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-sel-a32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-sel-a32.cc
@@ -116,7 +116,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-sel-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-sel-t32.cc
index 399f42e..9b31427 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-sel-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-sel-t32.cc
@@ -116,7 +116,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-rm-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-rm-t32.cc
index 25622b5..627d0c3 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-rm-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-rm-t32.cc
@@ -173,7 +173,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rd-rn-t32.cc b/test/aarch32/test-simulator-cond-rd-rn-t32.cc
index f7b2d44..7dd893b 100644
--- a/test/aarch32/test-simulator-cond-rd-rn-t32.cc
+++ b/test/aarch32/test-simulator-cond-rd-rn-t32.cc
@@ -123,7 +123,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rdlow-operand-imm8-t32.cc b/test/aarch32/test-simulator-cond-rdlow-operand-imm8-t32.cc
index 501009a..c23ccb9 100644
--- a/test/aarch32/test-simulator-cond-rdlow-operand-imm8-t32.cc
+++ b/test/aarch32/test-simulator-cond-rdlow-operand-imm8-t32.cc
@@ -119,7 +119,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc b/test/aarch32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc
index 3609ab3..fdf6d2e 100644
--- a/test/aarch32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc
+++ b/test/aarch32/test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc
@@ -122,7 +122,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc b/test/aarch32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc
index e6893ab..bb92981 100644
--- a/test/aarch32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc
+++ b/test/aarch32/test-simulator-cond-rdlow-rnlow-rmlow-t32.cc
@@ -118,7 +118,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-rd-rn-rm-a32.cc b/test/aarch32/test-simulator-rd-rn-rm-a32.cc
index 5ad3ba4..97d1c35 100644
--- a/test/aarch32/test-simulator-rd-rn-rm-a32.cc
+++ b/test/aarch32/test-simulator-rd-rn-rm-a32.cc
@@ -122,7 +122,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-simulator-rd-rn-rm-t32.cc b/test/aarch32/test-simulator-rd-rn-rm-t32.cc
index de34ff0..2d52cb7 100644
--- a/test/aarch32/test-simulator-rd-rn-rm-t32.cc
+++ b/test/aarch32/test-simulator-rd-rn-rm-t32.cc
@@ -122,7 +122,7 @@
// The following definitions are defined again in each generated test, therefore
-// we need to place them in an anomymous namespace. It expresses that they are
+// we need to place them in an anonymous namespace. It expresses that they are
// local to this file only, and the compiler is not allowed to share these types
// across test files during template instantiation. Specifically, `Operands` and
// `Inputs` have various layouts across generated tests so they absolutely
diff --git a/test/aarch32/test-utils-aarch32.cc b/test/aarch32/test-utils-aarch32.cc
index 3c6574e..ad4cbd5 100644
--- a/test/aarch32/test-utils-aarch32.cc
+++ b/test/aarch32/test-utils-aarch32.cc
@@ -41,7 +41,7 @@
Register dump_base = r0;
Register tmp = r1;
- // Check that the the dump registers can be used
+ // Check that the dump registers can be used
VIXL_STATIC_ASSERT(sizeof(dump_.r_[0]) == kRegSizeInBytes);
VIXL_STATIC_ASSERT(sizeof(dump_.d_[0]) == kDRegSizeInBytes);
diff --git a/test/aarch64/examples/test-examples.cc b/test/aarch64/examples/test-examples.cc
index 3cbbe8d..0b4dbb0 100644
--- a/test/aarch64/examples/test-examples.cc
+++ b/test/aarch64/examples/test-examples.cc
@@ -129,7 +129,7 @@
masm.GetLabelAddress<uint64_t>(&Func)); \
simulator.RunFrom(masm.GetLabelAddress<Instruction*>(&test)); \
\
- /* Check that callee-saved regsiters are preserved. */ \
+ /* Check that callee-saved registers are preserved. */ \
VIXL_CHECK(saved_xregs[0] == simulator.ReadXRegister(19)); \
VIXL_CHECK(saved_xregs[1] == simulator.ReadXRegister(20)); \
VIXL_CHECK(saved_xregs[2] == simulator.ReadXRegister(21)); \
diff --git a/test/aarch64/test-api-aarch64.cc b/test/aarch64/test-api-aarch64.cc
index b25fa7c..53cb54e 100644
--- a/test/aarch64/test-api-aarch64.cc
+++ b/test/aarch64/test-api-aarch64.cc
@@ -510,7 +510,7 @@
}
-TEST(areconsecutive) {
+TEST(are_consecutive) {
VIXL_CHECK(AreConsecutive(b0, NoVReg));
VIXL_CHECK(AreConsecutive(b1, b2));
VIXL_CHECK(AreConsecutive(b3, b4, b5));
@@ -1593,7 +1593,7 @@
temps.Exclude(ZRegister(12), ZRegister(13, kHRegSize), z14);
temps.Exclude(CPURegList(z16, z17, z18));
helper.RecordActionsAndCheck(0x77700);
- // Exluding a register again has no effect.
+ // Excluding a register again has no effect.
temps.Exclude(ZRegister(18));
temps.Exclude(ZRegister(17, kFormatVnB));
temps.Exclude(CPURegister(z16));
diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc
index 1820136..5b5a4ad 100644
--- a/test/aarch64/test-assembler-aarch64.cc
+++ b/test/aarch64/test-assembler-aarch64.cc
@@ -9512,7 +9512,7 @@
TEST(blr_lr) {
- // A simple test to check that the simulator correcty handle "blr lr".
+ // A simple test to check that the simulator correctly handle "blr lr".
SETUP();
START();
diff --git a/test/aarch64/test-assembler-aarch64.h b/test/aarch64/test-assembler-aarch64.h
index d2a4e4a..ee7467b 100644
--- a/test/aarch64/test-assembler-aarch64.h
+++ b/test/aarch64/test-assembler-aarch64.h
@@ -172,7 +172,7 @@
RUN_WITHOUT_SEEN_FEATURE_CHECK(); \
{ \
/* We expect the test to use all of the features it requested, plus the */ \
- /* features that the instructure code requires. */ \
+ /* features that the instruction code requires. */ \
CPUFeatures const& expected_features = \
simulator.GetCPUFeatures()->With(CPUFeatures::kNEON); \
CPUFeatures const& seen = simulator.GetSeenFeatures(); \
diff --git a/test/aarch64/test-assembler-fp-aarch64.cc b/test/aarch64/test-assembler-fp-aarch64.cc
index 4ae9ec7..c49a1fb 100644
--- a/test/aarch64/test-assembler-fp-aarch64.cc
+++ b/test/aarch64/test-assembler-fp-aarch64.cc
@@ -4692,7 +4692,7 @@
TEST(scvtf_ucvtf_double) {
// Simple conversions of positive numbers which require no rounding; the
- // results should not depened on the rounding mode, and ucvtf and scvtf should
+ // results should not depend on the rounding mode, and ucvtf and scvtf should
// produce the same result.
TestUScvtfHelper(0x0000000000000000, 0x0000000000000000, 0x0000000000000000);
TestUScvtfHelper(0x0000000000000001, 0x3ff0000000000000, 0x3ff0000000000000);
@@ -4847,7 +4847,7 @@
TEST(scvtf_ucvtf_float) {
// Simple conversions of positive numbers which require no rounding; the
- // results should not depened on the rounding mode, and ucvtf and scvtf should
+ // results should not depend on the rounding mode, and ucvtf and scvtf should
// produce the same result.
TestUScvtf32Helper(0x0000000000000000, 0x00000000, 0x00000000);
TestUScvtf32Helper(0x0000000000000001, 0x3f800000, 0x3f800000);
diff --git a/test/aarch64/test-assembler-sve-aarch64.cc b/test/aarch64/test-assembler-sve-aarch64.cc
index 053d5c8..21a7bae 100644
--- a/test/aarch64/test-assembler-sve-aarch64.cc
+++ b/test/aarch64/test-assembler-sve-aarch64.cc
@@ -287,7 +287,7 @@
CPUFeatures::kSVE);
START();
- // The Simulator has two mechansisms for writing V registers:
+ // The Simulator has two mechanisms for writing V registers:
// - Write*Register, calling through to SimRegisterBase::Write.
// - LogicVRegister::ClearForWrite followed by one or more lane updates.
// Try to cover both variants.
@@ -7244,7 +7244,7 @@
uint8_t* data = new uint8_t[data_size];
memset(data, 0, data_size);
- // Set the base half-way through the buffer so we can use negative indeces.
+ // Set the base half-way through the buffer so we can use negative indices.
__ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
__ Index(z14.VnB(), 1, -3);
@@ -7416,7 +7416,7 @@
uint8_t* data = new uint8_t[data_size];
memset(data, 0, data_size);
- // Set the base half-way through the buffer so we can use negative indeces.
+ // Set the base half-way through the buffer so we can use negative indices.
__ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
__ Index(z10.VnB(), -4, 11);
@@ -7589,7 +7589,7 @@
uint8_t* data = new uint8_t[data_size];
memset(data, 0, data_size);
- // Set the base half-way through the buffer so we can use negative indeces.
+ // Set the base half-way through the buffer so we can use negative indices.
__ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
// We can test ld3 by comparing the values loaded with the values stored.
@@ -7795,7 +7795,7 @@
uint8_t* data = new uint8_t[data_size];
memset(data, 0, data_size);
- // Set the base half-way through the buffer so we can use negative indeces.
+ // Set the base half-way through the buffer so we can use negative indices.
__ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
// We can test ld3 by comparing the values loaded with the values stored.
@@ -8009,7 +8009,7 @@
uint8_t* data = new uint8_t[data_size];
memset(data, 0, data_size);
- // Set the base half-way through the buffer so we can use negative indeces.
+ // Set the base half-way through the buffer so we can use negative indices.
__ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
// We can test ld4 by comparing the values loaded with the values stored.
@@ -8259,7 +8259,7 @@
uint8_t* data = new uint8_t[data_size];
memset(data, 0, data_size);
- // Set the base half-way through the buffer so we can use negative indeces.
+ // Set the base half-way through the buffer so we can use negative indices.
__ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
// We can test ld4 by comparing the values loaded with the values stored.
@@ -15382,7 +15382,7 @@
PRegisterWithLaneSize pg_all_active = p0.WithLaneSize(lane_size_in_bits);
__ Ptrue(pg_all_active);
- // Test floating-point conversions with all lanes actived.
+ // Test floating-point conversions with all lanes activated.
(masm.*macro_m)(zd_all_active.WithLaneSize(dst_type_size_in_bits),
pg_all_active.Merging(),
zn.WithLaneSize(src_type_size_in_bits));
@@ -15936,7 +15936,7 @@
PRegisterWithLaneSize pg_all_active = p0.WithLaneSize(lane_size_in_bits);
__ Ptrue(pg_all_active);
- // Test integer conversions with all lanes actived.
+ // Test integer conversions with all lanes activated.
__ Scvtf(zd_scvtf_all_active.WithLaneSize(dst_type_size_in_bits),
pg_all_active.Merging(),
zn.WithLaneSize(src_type_size_in_bits));
@@ -16006,7 +16006,7 @@
// clang-format off
CvtfTestDataSet data_set_1[] = {
// Simple conversions of positive numbers which require no rounding; the
- // results should not depened on the rounding mode, and ucvtf and scvtf should
+ // results should not depend on the rounding mode, and ucvtf and scvtf should
// produce the same result.
{0x0000, 0x0000, 0x0000},
{0x0001, 0x3c00, 0x3c00},
@@ -16062,7 +16062,7 @@
int src_lane_size = kSRegSize;
// Simple conversions of positive numbers which require no rounding; the
- // results should not depened on the rounding mode, and ucvtf and scvtf should
+ // results should not depend on the rounding mode, and ucvtf and scvtf should
// produce the same result.
CvtfTestDataSet data_set_1[] = {
{0x00000000, 0x00000000, 0x00000000},
@@ -16118,7 +16118,7 @@
int src_lane_size = kDRegSize;
// Simple conversions of positive numbers which require no rounding; the
- // results should not depened on the rounding mode, and ucvtf and scvtf should
+ // results should not depend on the rounding mode, and ucvtf and scvtf should
// produce the same result.
CvtfTestDataSet data_set_1[] = {
{0x0000000000000000, 0x00000000, 0x00000000},
@@ -16178,7 +16178,7 @@
int src_lane_size = kDRegSize;
// Simple conversions of positive numbers which require no rounding; the
- // results should not depened on the rounding mode, and ucvtf and scvtf should
+ // results should not depend on the rounding mode, and ucvtf and scvtf should
// produce the same result.
CvtfTestDataSet data_set_1[] = {
{0x0000000000000000, 0x0000000000000000, 0x0000000000000000},
@@ -16237,7 +16237,7 @@
int src_lane_size = kSRegSize;
// Simple conversions of positive numbers which require no rounding; the
- // results should not depened on the rounding mode, and ucvtf and scvtf should
+ // results should not depend on the rounding mode, and ucvtf and scvtf should
// produce the same result.
CvtfTestDataSet data_set_1[] = {
{0x00000000, 0x0000000000000000, 0x0000000000000000},
@@ -18122,7 +18122,7 @@
macro_m,
macro_z);
- // The complementary of above precicate to get full input coverage.
+ // The complementary of above predicate to get full input coverage.
uint64_t pg_c_inputs[] = {0x5aa55aa55aa55aa5,
0x5aa55aa55aa55aa5,
0x5aa55aa55aa55aa5,
@@ -19735,7 +19735,7 @@
// Manually constructed simulator test to avoid creating a VL128 variant.
#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
-void Testsve_fmatmul(Test* config) {
+void Test_sve_fmatmul(Test* config) {
SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM);
// Only double-precision matrix multiply is tested here. Single-precision is
@@ -19845,13 +19845,13 @@
}
}
Test* test_sve_fmatmul_list[] =
- {Test::MakeSVETest(256, "AARCH64_ASM_sve_fmatmul_vl256", &Testsve_fmatmul),
- Test::MakeSVETest(384, "AARCH64_ASM_sve_fmatmul_vl384", &Testsve_fmatmul),
+ {Test::MakeSVETest(256, "AARCH64_ASM_sve_fmatmul_vl256", &Test_sve_fmatmul),
+ Test::MakeSVETest(384, "AARCH64_ASM_sve_fmatmul_vl384", &Test_sve_fmatmul),
Test::MakeSVETest(2048,
"AARCH64_ASM_sve_fmatmul_vl2048",
- &Testsve_fmatmul)};
+ &Test_sve_fmatmul)};
-void Testsve_ld1ro(Test* config) {
+void Test_sve_ld1ro(Test* config) {
SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE, CPUFeatures::kSVEF64MM);
START();
@@ -19975,9 +19975,9 @@
}
}
Test* test_sve_ld1ro_list[] =
- {Test::MakeSVETest(256, "AARCH64_ASM_sve_ld1ro_vl256", &Testsve_ld1ro),
- Test::MakeSVETest(384, "AARCH64_ASM_sve_ld1ro_vl384", &Testsve_ld1ro),
- Test::MakeSVETest(2048, "AARCH64_ASM_sve_ld1ro_vl2048", &Testsve_ld1ro)};
+ {Test::MakeSVETest(256, "AARCH64_ASM_sve_ld1ro_vl256", &Test_sve_ld1ro),
+ Test::MakeSVETest(384, "AARCH64_ASM_sve_ld1ro_vl384", &Test_sve_ld1ro),
+ Test::MakeSVETest(2048, "AARCH64_ASM_sve_ld1ro_vl2048", &Test_sve_ld1ro)};
#endif
} // namespace aarch64
diff --git a/test/aarch64/test-disasm-sve-aarch64.cc b/test/aarch64/test-disasm-sve-aarch64.cc
index 03abdee..933e808 100644
--- a/test/aarch64/test-disasm-sve-aarch64.cc
+++ b/test/aarch64/test-disasm-sve-aarch64.cc
@@ -66,59 +66,59 @@
CLEANUP();
}
-TEST(sve_unimplemented_fp_byte_type) {
+TEST(sve_unallocated_fp_byte_type) {
// Ensure disassembly of FP instructions does not report byte-sized lanes.
SETUP();
- COMPARE_PREFIX(dci(0x650003ca), "unimplemented");
- COMPARE_PREFIX(dci(0x6500230b), "unimplemented");
- COMPARE_PREFIX(dci(0x6500424c), "unimplemented");
- COMPARE_PREFIX(dci(0x6500618d), "unimplemented");
- COMPARE_PREFIX(dci(0x6500a00f), "unimplemented");
- COMPARE_PREFIX(dci(0x6500de91), "unimplemented");
- COMPARE_PREFIX(dci(0x6500fdd2), "unimplemented");
- COMPARE_PREFIX(dci(0x65011d13), "unimplemented");
- COMPARE_PREFIX(dci(0x65015b95), "unimplemented");
- COMPARE_PREFIX(dci(0x65017ad6), "unimplemented");
- COMPARE_PREFIX(dci(0x65019a17), "unimplemented");
- COMPARE_PREFIX(dci(0x6501b958), "unimplemented");
- COMPARE_PREFIX(dci(0x6502941f), "unimplemented");
- COMPARE_PREFIX(dci(0x6502b360), "unimplemented");
- COMPARE_PREFIX(dci(0x6502d2a1), "unimplemented");
- COMPARE_PREFIX(dci(0x65038e27), "unimplemented");
- COMPARE_PREFIX(dci(0x6503ad68), "unimplemented");
- COMPARE_PREFIX(dci(0x65042a6c), "unimplemented");
- COMPARE_PREFIX(dci(0x6504882f), "unimplemented");
- COMPARE_PREFIX(dci(0x6504a770), "unimplemented");
- COMPARE_PREFIX(dci(0x65052474), "unimplemented");
- COMPARE_PREFIX(dci(0x65058237), "unimplemented");
- COMPARE_PREFIX(dci(0x65063dbd), "unimplemented");
- COMPARE_PREFIX(dci(0x65069b80), "unimplemented");
- COMPARE_PREFIX(dci(0x6506bac1), "unimplemented");
- COMPARE_PREFIX(dci(0x65071884), "unimplemented");
- COMPARE_PREFIX(dci(0x650737c5), "unimplemented");
- COMPARE_PREFIX(dci(0x65079588), "unimplemented");
- COMPARE_PREFIX(dci(0x6507b4c9), "unimplemented");
- COMPARE_PREFIX(dci(0x65088f90), "unimplemented");
- COMPARE_PREFIX(dci(0x65090c94), "unimplemented");
- COMPARE_PREFIX(dci(0x65098998), "unimplemented");
- COMPARE_PREFIX(dci(0x650a83a0), "unimplemented");
- COMPARE_PREFIX(dci(0x650c96f1), "unimplemented");
- COMPARE_PREFIX(dci(0x650d90f9), "unimplemented");
- COMPARE_PREFIX(dci(0x65113a97), "unimplemented");
- COMPARE_PREFIX(dci(0x65183010), "unimplemented");
- COMPARE_PREFIX(dci(0x65200050), "unimplemented");
- COMPARE_PREFIX(dci(0x65203ed2), "unimplemented");
- COMPARE_PREFIX(dci(0x65205e13), "unimplemented");
- COMPARE_PREFIX(dci(0x65207d54), "unimplemented");
- COMPARE_PREFIX(dci(0x65209c95), "unimplemented");
- COMPARE_PREFIX(dci(0x6520bbd6), "unimplemented");
- COMPARE_PREFIX(dci(0x6520db17), "unimplemented");
- COMPARE_PREFIX(dci(0x6520fa58), "unimplemented");
- COMPARE_PREFIX(dci(0x650f31e1), "unimplemented");
- COMPARE_PREFIX(dci(0x650e30f7), "unimplemented");
- COMPARE_PREFIX(dci(0x6511376e), "unimplemented");
+ COMPARE_PREFIX(dci(0x650003ca), "unallocated");
+ COMPARE_PREFIX(dci(0x6500230b), "unallocated");
+ COMPARE_PREFIX(dci(0x6500424c), "unallocated");
+ COMPARE_PREFIX(dci(0x6500618d), "unallocated");
+ COMPARE_PREFIX(dci(0x6500a00f), "unallocated");
+ COMPARE_PREFIX(dci(0x6500de91), "unallocated");
+ COMPARE_PREFIX(dci(0x6500fdd2), "unallocated");
+ COMPARE_PREFIX(dci(0x65011d13), "unallocated");
+ COMPARE_PREFIX(dci(0x65015b95), "unallocated");
+ COMPARE_PREFIX(dci(0x65017ad6), "unallocated");
+ COMPARE_PREFIX(dci(0x65019a17), "unallocated");
+ COMPARE_PREFIX(dci(0x6501b958), "unallocated");
+ COMPARE_PREFIX(dci(0x6502941f), "unallocated");
+ COMPARE_PREFIX(dci(0x6502b360), "unallocated");
+ COMPARE_PREFIX(dci(0x6502d2a1), "unallocated");
+ COMPARE_PREFIX(dci(0x65038e27), "unallocated");
+ COMPARE_PREFIX(dci(0x6503ad68), "unallocated");
+ COMPARE_PREFIX(dci(0x65042a6c), "unallocated");
+ COMPARE_PREFIX(dci(0x6504882f), "unallocated");
+ COMPARE_PREFIX(dci(0x6504a770), "unallocated");
+ COMPARE_PREFIX(dci(0x65052474), "unallocated");
+ COMPARE_PREFIX(dci(0x65058237), "unallocated");
+ COMPARE_PREFIX(dci(0x65063dbd), "unallocated");
+ COMPARE_PREFIX(dci(0x65069b80), "unallocated");
+ COMPARE_PREFIX(dci(0x6506bac1), "unallocated");
+ COMPARE_PREFIX(dci(0x65071884), "unallocated");
+ COMPARE_PREFIX(dci(0x650737c5), "unallocated");
+ COMPARE_PREFIX(dci(0x65079588), "unallocated");
+ COMPARE_PREFIX(dci(0x6507b4c9), "unallocated");
+ COMPARE_PREFIX(dci(0x65088f90), "unallocated");
+ COMPARE_PREFIX(dci(0x65090c94), "unallocated");
+ COMPARE_PREFIX(dci(0x65098998), "unallocated");
+ COMPARE_PREFIX(dci(0x650a83a0), "unallocated");
+ COMPARE_PREFIX(dci(0x650c96f1), "unallocated");
+ COMPARE_PREFIX(dci(0x650d90f9), "unallocated");
+ COMPARE_PREFIX(dci(0x65113a97), "unallocated");
+ COMPARE_PREFIX(dci(0x65183010), "unallocated");
+ COMPARE_PREFIX(dci(0x65200050), "unallocated");
+ COMPARE_PREFIX(dci(0x65203ed2), "unallocated");
+ COMPARE_PREFIX(dci(0x65205e13), "unallocated");
+ COMPARE_PREFIX(dci(0x65207d54), "unallocated");
+ COMPARE_PREFIX(dci(0x65209c95), "unallocated");
+ COMPARE_PREFIX(dci(0x6520bbd6), "unallocated");
+ COMPARE_PREFIX(dci(0x6520db17), "unallocated");
+ COMPARE_PREFIX(dci(0x6520fa58), "unallocated");
+ COMPARE_PREFIX(dci(0x650f31e1), "unallocated");
+ COMPARE_PREFIX(dci(0x650e30f7), "unallocated");
+ COMPARE_PREFIX(dci(0x6511376e), "unallocated");
CLEANUP();
}
diff --git a/test/aarch64/test-simulator-inputs-aarch64.h b/test/aarch64/test-simulator-inputs-aarch64.h
index d19a39e..620c164 100644
--- a/test/aarch64/test-simulator-inputs-aarch64.h
+++ b/test/aarch64/test-simulator-inputs-aarch64.h
@@ -37,7 +37,7 @@
// This header should only be used by test/test-simulator-aarch64.cc, so it
// doesn't need the usual header guard.
#ifdef VIXL_AARCH64_TEST_SIMULATOR_INPUTS_AARCH64_H_
-#error This header should be inluded only once.
+#error This header should be included only once.
#endif
#define VIXL_AARCH64_TEST_SIMULATOR_INPUTS_AARCH64_H_
diff --git a/test/aarch64/test-utils-aarch64.cc b/test/aarch64/test-utils-aarch64.cc
index 76e7eae..55eccc7 100644
--- a/test/aarch64/test-utils-aarch64.cc
+++ b/test/aarch64/test-utils-aarch64.cc
@@ -780,7 +780,7 @@
}
// Note that the function assumes p0, p1, p2 and p3 are set to all true in b-,
-// h-, s- and d-lane sizes respectively, and p4, p5 are clobberred as a temp
+// h-, s- and d-lane sizes respectively, and p4, p5 are clobbered as a temp
// predicate.
template <typename T, size_t N>
void SetFpData(MacroAssembler* masm,
diff --git a/test/aarch64/test-utils-aarch64.h b/test/aarch64/test-utils-aarch64.h
index b1c2898..fde3ad1 100644
--- a/test/aarch64/test-utils-aarch64.h
+++ b/test/aarch64/test-utils-aarch64.h
@@ -501,7 +501,7 @@
int reg_count,
RegList allowed);
-// Ovewrite the contents of the specified registers. This enables tests to
+// Overwrite the contents of the specified registers. This enables tests to
// check that register contents are written in cases where it's likely that the
// correct outcome could already be stored in the register.
//
diff --git a/test/test-pool-manager.cc b/test/test-pool-manager.cc
index df2f32b..e49f1ca 100644
--- a/test/test-pool-manager.cc
+++ b/test/test-pool-manager.cc
@@ -797,7 +797,7 @@
// Increment PC to close to the checkpoint of the pools minus a known
- // thershold.
+ // threshold.
const int kBigObjectSize = 1024;
TestPoolManager test(&pool_manager);
pc = test.GetPoolCheckpoint() - kBigObjectSize;
diff --git a/tools/code_coverage.log b/tools/code_coverage.log
index b028541..891ad27 100644
--- a/tools/code_coverage.log
+++ b/tools/code_coverage.log
@@ -7,4 +7,6 @@
1646150629 82.94% 97.51% 95.36%
1647535694 82.93% 97.52% 95.36%
1650549095 82.93% 97.52% 95.33%
+1651138061 82.94% 97.52% 95.36%
+1653484786 82.79% 97.46% 95.51%
1657620989 82.93% 97.52% 95.33%
diff --git a/tools/test_generator/data_types.py b/tools/test_generator/data_types.py
index f51f2bb..40d2bf3 100644
--- a/tools/test_generator/data_types.py
+++ b/tools/test_generator/data_types.py
@@ -456,7 +456,7 @@
def Prologue(self):
# When clearing or setting the `Q` bit, we need to make sure the `NZCV`
- # flags are not overriden. Therefore we use two scratch registers that we
+ # flags are not overridden. Therefore we use two scratch registers that we
# push on the stack first to allow the instruction to use them as operands.
code = """{{
UseScratchRegisterScope temp_registers(&masm);
diff --git a/tools/test_generator/generator.py b/tools/test_generator/generator.py
index 37afee7..baa970c 100644
--- a/tools/test_generator/generator.py
+++ b/tools/test_generator/generator.py
@@ -83,7 +83,7 @@
class InputList(object):
"""
- Convevience class representing a list of input objects.
+ Convenience class representing a list of input objects.
This class is an iterator over input objects.
@@ -113,7 +113,7 @@
Attributes:
name Name of the test case, it is used to name the array to
produce.
- seed Seed value to use for reproducable random generation.
+ seed Seed value to use for reproducible random generation.
operand_names List of operand names this test case covers.
input_names List of input names this test case covers.
operand_filter Python expression as a string to filter out operands.
@@ -320,7 +320,7 @@
# A simulator test cannot easily make use of the PC and SP registers.
if self.test_type == "simulator":
- # We need to explicitely create our own deep copy the operands before we
+ # We need to explicitly create our own deep copy the operands before we
# can modify them.
self.operands = deepcopy(operands)
self.operands.ExcludeVariants("Register", ["r13", "r15"])
diff --git a/tools/test_generator/parser.py b/tools/test_generator/parser.py
index af042e2..65b76df 100644
--- a/tools/test_generator/parser.py
+++ b/tools/test_generator/parser.py
@@ -165,7 +165,7 @@
Parse the instruction description into a
(`generator.OperandList`, `generator.InputList`) tuple.
- Example for an instruction that takes a condidition code, two registers and an
+ Example for an instruction that takes a condition code, two registers and an
immediate as operand. It will also need inputs for the registers, as well as
NZCV flags.
~~~
@@ -400,12 +400,12 @@
"""
# Strip the ".json" extension
stripped_basename = os.path.splitext(os.path.basename(filename))[0]
- # The ISA is the last element in the filename, seperated with "-".
+ # The ISA is the last element in the filename, separated with "-".
if stripped_basename.endswith(('-a32', '-t32')):
isa = [stripped_basename[-3:]]
test_name = stripped_basename[:-4]
else:
- # If the ISA is ommitted, support both.
+ # If the ISA is omitted, support both.
isa = ["a32", "t32"]
test_name = stripped_basename
diff --git a/tools/util.py b/tools/util.py
index 9152584..b3f4489 100644
--- a/tools/util.py
+++ b/tools/util.py
@@ -77,10 +77,10 @@
return os.path.relpath(os.path.realpath(path), start)
# Query the compiler about its preprocessor directives and return all of them as
-# a dictionnary.
+# a dictionary.
def GetCompilerDirectives(env):
args = [env['compiler']]
- # Pass the CXXFLAGS varables to the compile, in case we've used "-m32" to
+ # Pass the CXXFLAGS variables to the compile, in case we've used "-m32" to
# compile for i386.
if env['CXXFLAGS']:
args.append(str(env['CXXFLAGS']))
@@ -116,7 +116,7 @@
elif "__aarch64__" in directives:
return "aarch64"
else:
- raise Exception("Unsupported archtecture")
+ raise Exception("Unsupported architecture")
# Class representing the compiler toolchain and version.
class CompilerInformation(object):
diff --git a/tools/verify_assembler_traces.py b/tools/verify_assembler_traces.py
index d1d29db..d78d17c 100755
--- a/tools/verify_assembler_traces.py
+++ b/tools/verify_assembler_traces.py
@@ -31,7 +31,7 @@
This script will find all files in `test/aarch32/traces/` with names starting
will `assembler`, and check them against `llvm-mc`. It checks our assembler is
-correct by looking up what instruction we meant to asssemble, assemble it with
+correct by looking up what instruction we meant to assemble, assemble it with
`llvm` and check the result is bit identical to what our assembler generated.
You may run the script with no arguments from VIXL's top-level directory as long
@@ -136,7 +136,7 @@
"""
Take an string representing an instruction and convert it to assembly syntax
for LLVM. VIXL's test generation framework will print instruction
- representations as a space seperated list. The first element is the mnemonic
+ representations as a space separated list. The first element is the mnemonic
and the following elements are operands.
"""
@@ -304,12 +304,12 @@
]
# Our test generator framework uses mnemonics starting with a capital letters.
- # We need everythin to be lower case for LLVM.
+ # We need everything to be lower case for LLVM.
vixl_instruction = vixl_instruction.lower()
llvm_instruction = []
- # VIXL may have generated more than one instruction seperated by ';'
+ # VIXL may have generated more than one instruction separated by ';'
# (an IT instruction for example).
for instruction in vixl_instruction.split(';'):
# Strip out extra white spaces.
@@ -401,7 +401,7 @@
# due to IT instructions preceding every instruction under test. VIXL's
# assembly reference files will contain a single array of 4 bytes encoding
# both the IT and the following instruction. While LLVM will have decoded them
- # into two seperate 2 bytes arrays.
+ # into two separate 2 bytes arrays.
if len(llvm_encodings) == 2 * len(vixl_encodings):
llvm_encodings = [
llvm_encodings[i * 2] + llvm_encodings[(i * 2) + 1]