commit ed5e03d47e75e1a8eecd65ecefdcc70e25e7ddef
author Martyn Capewell <martyn.capewell@arm.com> Thu Jun 24 16:44:24 2021 +0100
committer Martyn Capewell <martyn.capewell@arm.com> Wed Jul 07 14:55:05 2021 +0100
tree 51c204861d659228bf1b38a7093427732ce8b926
parent 8b1e739d7df7bfb167731c6d1ec6181e9a17f59b

Re-enable clang-tidy for simulator

Fix typo in the clang-tidy script that prevented it checking the simulator,
and address the new problems it's found.

tools/clang_tidy.py

diff --git a/tools/clang_tidy.py b/tools/clang_tidy.py
index 7ba1874..8607547 100755
--- a/tools/clang_tidy.py
+++ b/tools/clang_tidy.py
@@ -143,7 +143,7 @@
     return -1
 
   opts = ['--', '-DVIXL_INCLUDE_TARGET_AARCH64', '-DVIXL_CODE_BUFFER_MALLOC',
-          '-DVIXL_DEBUG','-DVIXL_INCLUDE_SIMLUATOR_AARCH64',
+          '-DVIXL_DEBUG','-DVIXL_INCLUDE_SIMULATOR_AARCH64',
           '-DVIXL_INCLUDE_TARGET_A32','-DVIXL_INCLUDE_TARGET_T32',
           '-DVIXL_INCLUDE_TARGET_A64']
   opts += ['-I%s' % config.dir_src_vixl]