Replace Hash() calls with user-defined literal
Where possible, apply the hash-computing user-defined literal ""_h, for clarity
and maintainability.
diff --git a/src/aarch64/disasm-aarch64.cc b/src/aarch64/disasm-aarch64.cc
index 9cc9b3c..54cf9a1 100644
--- a/src/aarch64/disasm-aarch64.cc
+++ b/src/aarch64/disasm-aarch64.cc
@@ -1302,19 +1302,19 @@
const char *form = "'Xn";
switch (form_hash_) {
- case Hash("ret_64r_branch_reg"):
+ case "ret_64r_branch_reg"_h:
if (instr->GetRn() == kLinkRegCode) {
form = "";
}
break;
- case Hash("retaa_64e_branch_reg"):
- case Hash("retab_64e_branch_reg"):
+ case "retaa_64e_branch_reg"_h:
+ case "retab_64e_branch_reg"_h:
form = "";
break;
- case Hash("braa_64p_branch_reg"):
- case Hash("brab_64p_branch_reg"):
- case Hash("blraa_64p_branch_reg"):
- case Hash("blrab_64p_branch_reg"):
+ case "braa_64p_branch_reg"_h:
+ case "brab_64p_branch_reg"_h:
+ case "blraa_64p_branch_reg"_h:
+ case "blrab_64p_branch_reg"_h:
form = "'Xn, 'Xds";
break;
}
@@ -2723,17 +2723,17 @@
const char *suffix = NULL;
switch (form_hash_) {
- case Hash("clrex_bn_barriers"):
+ case "clrex_bn_barriers"_h:
form = (instr->GetCRm() == 0xf) ? "" : "'IX";
break;
- case Hash("mrs_rs_systemmove"):
+ case "mrs_rs_systemmove"_h:
form = "'Xt, 'IY";
break;
- case Hash("msr_si_pstate"):
- case Hash("msr_sr_systemmove"):
+ case "msr_si_pstate"_h:
+ case "msr_sr_systemmove"_h:
form = "'IY, 'Xt";
break;
- case Hash("bti_hb_hints"):
+ case "bti_hb_hints"_h:
switch (instr->ExtractBits(7, 6)) {
case 0:
form = "";
@@ -2749,14 +2749,14 @@
break;
}
break;
- case Hash("hint_hm_hints"):
+ case "hint_hm_hints"_h:
form = "'IH";
break;
- case Hash("dmb_bo_barriers"):
- case Hash("dsb_bo_barriers"):
+ case "dmb_bo_barriers"_h:
+ case "dsb_bo_barriers"_h:
form = "'M";
break;
- case Hash("sys_cr_systeminstrs"):
+ case "sys_cr_systeminstrs"_h:
mnemonic = "dc";
suffix = ", 'Xt";
switch (instr->GetSysOp()) {
@@ -2884,10 +2884,10 @@
VectorFormat vform_dst = nfd.GetVectorFormat(0);
switch (form_hash_) {
- case Hash("fcvtl_asimdmisc_l"):
+ case "fcvtl_asimdmisc_l"_h:
nfd.SetFormatMaps(&map_cvt_ta, &map_cvt_tb);
break;
- case Hash("fcvtxn_asimdmisc_n"):
+ case "fcvtxn_asimdmisc_n"_h:
if ((vform_dst != kFormat2S) && (vform_dst != kFormat4S)) {
mnemonic = NULL;
}
@@ -2907,7 +2907,7 @@
const char *mnemonic = mnemonic_.c_str();
const char *form = "'Vd.%s, 'Vn.%s";
NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
- if (form_hash_ == Hash("not_asimdmisc_r")) {
+ if (form_hash_ == "not_asimdmisc_r"_h) {
mnemonic = "mvn";
}
Format(instr, mnemonic, nfd.Substitute(form));
@@ -2921,7 +2921,7 @@
NEONFormatDecoder::IntegerFormatMap(),
NEONFormatDecoder::LongIntegerFormatMap());
- if (form_hash_ == Hash("shll_asimdmisc_s")) {
+ if (form_hash_ == "shll_asimdmisc_s"_h) {
nfd.SetFormatMaps(nfd.LongIntegerFormatMap(), nfd.IntegerFormatMap());
switch (instr->GetNEONSize()) {
case 0:
@@ -2947,27 +2947,27 @@
if (vform_dst != kFormatUndefined) {
uint32_t ls_dst = LaneSizeInBitsFromFormat(vform_dst);
switch (form_hash_) {
- case Hash("cnt_asimdmisc_r"):
- case Hash("rev16_asimdmisc_r"):
+ case "cnt_asimdmisc_r"_h:
+ case "rev16_asimdmisc_r"_h:
if (ls_dst != kBRegSize) {
mnemonic = NULL;
}
break;
- case Hash("rev32_asimdmisc_r"):
+ case "rev32_asimdmisc_r"_h:
if ((ls_dst == kDRegSize) || (ls_dst == kSRegSize)) {
mnemonic = NULL;
}
break;
- case Hash("urecpe_asimdmisc_r"):
- case Hash("ursqrte_asimdmisc_r"):
+ case "urecpe_asimdmisc_r"_h:
+ case "ursqrte_asimdmisc_r"_h:
// For urecpe and ursqrte, only S-sized elements are supported. The MSB
// of the size field is always set by the instruction (0b1x) so we need
// only check and discard D-sized elements here.
VIXL_ASSERT((ls_dst == kSRegSize) || (ls_dst == kDRegSize));
VIXL_FALLTHROUGH();
- case Hash("clz_asimdmisc_r"):
- case Hash("cls_asimdmisc_r"):
- case Hash("rev64_asimdmisc_r"):
+ case "clz_asimdmisc_r"_h:
+ case "cls_asimdmisc_r"_h:
+ case "rev64_asimdmisc_r"_h:
if (ls_dst == kDRegSize) {
mnemonic = NULL;
}
@@ -2984,11 +2984,11 @@
const char *suffix = NULL;
switch (form_hash_) {
- case Hash("fcmeq_asimdmiscfp16_fz"):
- case Hash("fcmge_asimdmiscfp16_fz"):
- case Hash("fcmgt_asimdmiscfp16_fz"):
- case Hash("fcmle_asimdmiscfp16_fz"):
- case Hash("fcmlt_asimdmiscfp16_fz"):
+ case "fcmeq_asimdmiscfp16_fz"_h:
+ case "fcmge_asimdmiscfp16_fz"_h:
+ case "fcmgt_asimdmiscfp16_fz"_h:
+ case "fcmle_asimdmiscfp16_fz"_h:
+ case "fcmlt_asimdmiscfp16_fz"_h:
suffix = ", #0.0";
}
Format(instr, mnemonic, form, suffix);
@@ -3000,13 +3000,13 @@
NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
switch (form_hash_) {
- case Hash("orr_asimdsame_only"):
+ case "orr_asimdsame_only"_h:
if (instr->GetRm() == instr->GetRn()) {
mnemonic = "mov";
form = "'Vd.%s, 'Vn.%s";
}
break;
- case Hash("pmul_asimdsame_only"):
+ case "pmul_asimdsame_only"_h:
if (instr->GetNEONSize() != 0) {
mnemonic = NULL;
}
@@ -3043,8 +3043,8 @@
if (vform_dst != kFormatUndefined) {
uint32_t ls_dst = LaneSizeInBitsFromFormat(vform_dst);
switch (form_hash_) {
- case Hash("sqdmulh_asimdsame_only"):
- case Hash("sqrdmulh_asimdsame_only"):
+ case "sqdmulh_asimdsame_only"_h:
+ case "sqrdmulh_asimdsame_only"_h:
if ((ls_dst == kBRegSize) || (ls_dst == kDRegSize)) {
mnemonic = NULL;
}
@@ -3072,16 +3072,16 @@
NEONFormatDecoder nfd(instr);
switch (form_hash_) {
- case Hash("fcmla_asimdsame2_c"):
+ case "fcmla_asimdsame2_c"_h:
suffix = ", #'u1211*90";
break;
- case Hash("fcadd_asimdsame2_c"):
+ case "fcadd_asimdsame2_c"_h:
// Bit 10 is always set, so this gives 90 * 1 or 3.
suffix = ", #'u1212:1010*90";
break;
- case Hash("sdot_asimdsame2_d"):
- case Hash("udot_asimdsame2_d"):
- case Hash("usdot_asimdsame2_d"):
+ case "sdot_asimdsame2_d"_h:
+ case "udot_asimdsame2_d"_h:
+ case "usdot_asimdsame2_d"_h:
nfd.SetFormatMap(1, &map_usdot);
nfd.SetFormatMap(2, &map_usdot);
break;
@@ -3102,27 +3102,27 @@
nfd.SetFormatMap(0, nfd.LongIntegerFormatMap());
switch (form_hash_) {
- case Hash("saddw_asimddiff_w"):
- case Hash("ssubw_asimddiff_w"):
- case Hash("uaddw_asimddiff_w"):
- case Hash("usubw_asimddiff_w"):
+ case "saddw_asimddiff_w"_h:
+ case "ssubw_asimddiff_w"_h:
+ case "uaddw_asimddiff_w"_h:
+ case "usubw_asimddiff_w"_h:
nfd.SetFormatMap(1, nfd.LongIntegerFormatMap());
break;
- case Hash("addhn_asimddiff_n"):
- case Hash("raddhn_asimddiff_n"):
- case Hash("rsubhn_asimddiff_n"):
- case Hash("subhn_asimddiff_n"):
+ case "addhn_asimddiff_n"_h:
+ case "raddhn_asimddiff_n"_h:
+ case "rsubhn_asimddiff_n"_h:
+ case "subhn_asimddiff_n"_h:
nfd.SetFormatMaps(nfd.LongIntegerFormatMap());
nfd.SetFormatMap(0, nfd.IntegerFormatMap());
break;
- case Hash("pmull_asimddiff_l"):
+ case "pmull_asimddiff_l"_h:
if (nfd.GetVectorFormat(0) != kFormat8H) {
mnemonic = NULL;
}
break;
- case Hash("sqdmlal_asimddiff_l"):
- case Hash("sqdmlsl_asimddiff_l"):
- case Hash("sqdmull_asimddiff_l"):
+ case "sqdmlal_asimddiff_l"_h:
+ case "sqdmlsl_asimddiff_l"_h:
+ case "sqdmull_asimddiff_l"_h:
if (nfd.GetVectorFormat(0) == kFormat8H) {
mnemonic = NULL;
}
@@ -3155,8 +3155,8 @@
NEONFormatDecoder::IntegerFormatMap());
switch (form_hash_) {
- case Hash("saddlv_asimdall_only"):
- case Hash("uaddlv_asimdall_only"):
+ case "saddlv_asimdall_only"_h:
+ case "uaddlv_asimdall_only"_h:
nfd.SetFormatMap(0, nfd.LongScalarFormatMap());
}
@@ -3242,12 +3242,12 @@
NEONFormatDecoder::TriangularScalarFormatMap());
switch (form_hash_) {
- case Hash("ins_asimdins_iv_v"):
+ case "ins_asimdins_iv_v"_h:
mnemonic = "mov";
nfd.SetFormatMap(0, nfd.TriangularScalarFormatMap());
form = "'Vd.%s['IVInsIndex1], 'Vn.%s['IVInsIndex2]";
break;
- case Hash("ins_asimdins_ir_r"):
+ case "ins_asimdins_ir_r"_h:
mnemonic = "mov";
nfd.SetFormatMap(0, nfd.TriangularScalarFormatMap());
if (nfd.GetVectorFormat() == kFormatD) {
@@ -3256,8 +3256,8 @@
form = "'Vd.%s['IVInsIndex1], 'Wn";
}
break;
- case Hash("umov_asimdins_w_w"):
- case Hash("umov_asimdins_x_x"):
+ case "umov_asimdins_w_w"_h:
+ case "umov_asimdins_x_x"_h:
if (instr->Mask(NEON_Q) || ((instr->GetImmNEON5() & 7) == 4)) {
mnemonic = "mov";
}
@@ -3268,8 +3268,8 @@
form = "'Wd, 'Vn.%s['IVInsIndex1]";
}
break;
- case Hash("smov_asimdins_w_w"):
- case Hash("smov_asimdins_x_x"): {
+ case "smov_asimdins_w_w"_h:
+ case "smov_asimdins_x_x"_h: {
nfd.SetFormatMap(0, nfd.TriangularScalarFormatMap());
VectorFormat vform = nfd.GetVectorFormat();
if ((vform == kFormatD) ||
@@ -3279,10 +3279,10 @@
form = "'R30d, 'Vn.%s['IVInsIndex1]";
break;
}
- case Hash("dup_asimdins_dv_v"):
+ case "dup_asimdins_dv_v"_h:
form = "'Vd.%s, 'Vn.%s['IVInsIndex1]";
break;
- case Hash("dup_asimdins_dr_r"):
+ case "dup_asimdins_dr_r"_h:
if (nfd.GetVectorFormat() == kFormat2D) {
form = "'Vd.%s, 'Xn";
} else {
@@ -3835,40 +3835,40 @@
NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
switch (form_hash_) {
- case Hash("movi_asimdimm_n_b"):
+ case "movi_asimdimm_n_b"_h:
form = "'Vt.%s, 'IVMIImm8";
break;
- case Hash("bic_asimdimm_l_hl"):
- case Hash("movi_asimdimm_l_hl"):
- case Hash("mvni_asimdimm_l_hl"):
- case Hash("orr_asimdimm_l_hl"):
+ case "bic_asimdimm_l_hl"_h:
+ case "movi_asimdimm_l_hl"_h:
+ case "mvni_asimdimm_l_hl"_h:
+ case "orr_asimdimm_l_hl"_h:
nfd.SetFormatMap(0, &map_h);
break;
- case Hash("movi_asimdimm_m_sm"):
- case Hash("mvni_asimdimm_m_sm"):
+ case "movi_asimdimm_m_sm"_h:
+ case "mvni_asimdimm_m_sm"_h:
form = "'Vt.%s, 'IVMIImm8, msl 'IVMIShiftAmt2";
VIXL_FALLTHROUGH();
- case Hash("bic_asimdimm_l_sl"):
- case Hash("movi_asimdimm_l_sl"):
- case Hash("mvni_asimdimm_l_sl"):
- case Hash("orr_asimdimm_l_sl"):
+ case "bic_asimdimm_l_sl"_h:
+ case "movi_asimdimm_l_sl"_h:
+ case "mvni_asimdimm_l_sl"_h:
+ case "orr_asimdimm_l_sl"_h:
nfd.SetFormatMap(0, &map_s);
break;
- case Hash("movi_asimdimm_d_ds"):
+ case "movi_asimdimm_d_ds"_h:
form = "'Dd, 'IVMIImm";
break;
- case Hash("movi_asimdimm_d2_d"):
+ case "movi_asimdimm_d2_d"_h:
form = "'Vt.2d, 'IVMIImm";
break;
- case Hash("fmov_asimdimm_h_h"):
+ case "fmov_asimdimm_h_h"_h:
form = "'Vt.%s, 'IFPNeon";
nfd.SetFormatMap(0, &map_h);
break;
- case Hash("fmov_asimdimm_s_s"):
+ case "fmov_asimdimm_s_s"_h:
form = "'Vt.%s, 'IFPNeon";
nfd.SetFormatMap(0, &map_s);
break;
- case Hash("fmov_asimdimm_d2_d"):
+ case "fmov_asimdimm_d2_d"_h:
form = "'Vt.2d, 'IFPNeon";
break;
}
@@ -3885,8 +3885,8 @@
mnemonic = NULL;
}
switch (form_hash_) {
- case Hash("abs_asisdmisc_r"):
- case Hash("neg_asisdmisc_r"):
+ case "abs_asisdmisc_r"_h:
+ case "neg_asisdmisc_r"_h:
suffix = NULL;
}
Format(instr, mnemonic, form, suffix);
@@ -3898,14 +3898,14 @@
const char *suffix = NULL;
NEONFormatDecoder nfd(instr, NEONFormatDecoder::FPScalarFormatMap());
switch (form_hash_) {
- case Hash("fcmeq_asisdmisc_fz"):
- case Hash("fcmge_asisdmisc_fz"):
- case Hash("fcmgt_asisdmisc_fz"):
- case Hash("fcmle_asisdmisc_fz"):
- case Hash("fcmlt_asisdmisc_fz"):
+ case "fcmeq_asisdmisc_fz"_h:
+ case "fcmge_asisdmisc_fz"_h:
+ case "fcmgt_asisdmisc_fz"_h:
+ case "fcmle_asisdmisc_fz"_h:
+ case "fcmlt_asisdmisc_fz"_h:
suffix = ", #0.0";
break;
- case Hash("fcvtxn_asisdmisc_n"):
+ case "fcvtxn_asisdmisc_n"_h:
if (nfd.GetVectorFormat(0) == kFormatS) { // Source format.
mnemonic = NULL;
}
@@ -3919,9 +3919,9 @@
const char *form = "%sd, %sn";
NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
switch (form_hash_) {
- case Hash("sqxtn_asisdmisc_n"):
- case Hash("sqxtun_asisdmisc_n"):
- case Hash("uqxtn_asisdmisc_n"):
+ case "sqxtn_asisdmisc_n"_h:
+ case "sqxtun_asisdmisc_n"_h:
+ case "uqxtn_asisdmisc_n"_h:
nfd.SetFormatMap(1, nfd.LongScalarFormatMap());
}
Format(instr, mnemonic, nfd.SubstitutePlaceholders(form));
@@ -3933,11 +3933,11 @@
const char *suffix = NULL;
switch (form_hash_) {
- case Hash("fcmeq_asisdmiscfp16_fz"):
- case Hash("fcmge_asisdmiscfp16_fz"):
- case Hash("fcmgt_asisdmiscfp16_fz"):
- case Hash("fcmle_asisdmiscfp16_fz"):
- case Hash("fcmlt_asisdmiscfp16_fz"):
+ case "fcmeq_asisdmiscfp16_fz"_h:
+ case "fcmge_asisdmiscfp16_fz"_h:
+ case "fcmgt_asisdmiscfp16_fz"_h:
+ case "fcmle_asisdmiscfp16_fz"_h:
+ case "fcmlt_asisdmiscfp16_fz"_h:
suffix = ", #0.0";
}
Format(instr, mnemonic, form, suffix);
@@ -3978,16 +3978,16 @@
NEONFormatDecoder nfd(instr, NEONFormatDecoder::ScalarFormatMap());
VectorFormat vform = nfd.GetVectorFormat(0);
switch (form_hash_) {
- case Hash("srshl_asisdsame_only"):
- case Hash("urshl_asisdsame_only"):
- case Hash("sshl_asisdsame_only"):
- case Hash("ushl_asisdsame_only"):
+ case "srshl_asisdsame_only"_h:
+ case "urshl_asisdsame_only"_h:
+ case "sshl_asisdsame_only"_h:
+ case "ushl_asisdsame_only"_h:
if (vform != kFormatD) {
mnemonic = NULL;
}
break;
- case Hash("sqdmulh_asisdsame_only"):
- case Hash("sqrdmulh_asisdsame_only"):
+ case "sqdmulh_asisdsame_only"_h:
+ case "sqrdmulh_asisdsame_only"_h:
if ((vform == kFormatB) || (vform == kFormatD)) {
mnemonic = NULL;
}
@@ -4063,7 +4063,7 @@
void Disassembler::VisitNEONScalarPairwise(const Instruction *instr) {
const char *mnemonic = mnemonic_.c_str();
- if (form_hash_ == Hash("addp_asisdpair_only")) {
+ if (form_hash_ == "addp_asisdpair_only"_h) {
// All pairwise operations except ADDP use bit U to differentiate FP16
// from FP32/FP64 variations.
if (instr->GetNEONSize() != 3) {
@@ -4095,8 +4095,8 @@
}
switch (form_hash_) {
- case Hash("shl_asisdshf_r"):
- case Hash("sli_asisdshf_r"):
+ case "shl_asisdshf_r"_h:
+ case "sli_asisdshf_r"_h:
suffix = "'IsL";
}
@@ -4129,9 +4129,9 @@
// clang-format on
NEONFormatDecoder nfd(instr, &map);
switch (form_hash_) {
- case Hash("sqshlu_asisdshf_r"):
- case Hash("sqshl_asisdshf_r"):
- case Hash("uqshl_asisdshf_r"):
+ case "sqshlu_asisdshf_r"_h:
+ case "sqshl_asisdshf_r"_h:
+ case "uqshl_asisdshf_r"_h:
suffix = "'IsL";
break;
default:
@@ -4153,9 +4153,9 @@
if (instr->GetImmNEONImmb() == 0 &&
CountSetBits(instr->GetImmNEONImmh(), 32) == 1) { // xtl variant.
- VIXL_ASSERT((form_hash_ == Hash("sshll_asimdshf_l")) ||
- (form_hash_ == Hash("ushll_asimdshf_l")));
- mnemonic = (form_hash_ == Hash("sshll_asimdshf_l")) ? "sxtl" : "uxtl";
+ VIXL_ASSERT((form_hash_ == "sshll_asimdshf_l"_h) ||
+ (form_hash_ == "ushll_asimdshf_l"_h));
+ mnemonic = (form_hash_ == "sshll_asimdshf_l"_h) ? "sxtl" : "uxtl";
suffix = NULL;
}
Format(instr, nfd.Mnemonic(mnemonic), nfd.Substitute(form), suffix);
@@ -4170,10 +4170,10 @@
if (vform_dst != kFormatUndefined) {
uint32_t ls_dst = LaneSizeInBitsFromFormat(vform_dst);
switch (form_hash_) {
- case Hash("scvtf_asimdshf_c"):
- case Hash("ucvtf_asimdshf_c"):
- case Hash("fcvtzs_asimdshf_c"):
- case Hash("fcvtzu_asimdshf_c"):
+ case "scvtf_asimdshf_c"_h:
+ case "ucvtf_asimdshf_c"_h:
+ case "fcvtzs_asimdshf_c"_h:
+ case "fcvtzu_asimdshf_c"_h:
if (ls_dst == kBRegSize) {
mnemonic = NULL;
}
@@ -4214,16 +4214,16 @@
NEONFormatDecoder nfd(instr, NEONFormatDecoder::LogicalFormatMap());
switch (form_hash_) {
- case Hash("tbl_asimdtbl_l2_2"):
- case Hash("tbx_asimdtbl_l2_2"):
+ case "tbl_asimdtbl_l2_2"_h:
+ case "tbx_asimdtbl_l2_2"_h:
form = form_2v;
break;
- case Hash("tbl_asimdtbl_l3_3"):
- case Hash("tbx_asimdtbl_l3_3"):
+ case "tbl_asimdtbl_l3_3"_h:
+ case "tbx_asimdtbl_l3_3"_h:
form = form_3v;
break;
- case Hash("tbl_asimdtbl_l4_4"):
- case Hash("tbx_asimdtbl_l4_4"):
+ case "tbl_asimdtbl_l4_4"_h:
+ case "tbx_asimdtbl_l4_4"_h:
form = form_4v;
break;
}
@@ -5078,17 +5078,17 @@
form = "(SVEBitwiseShiftByImm_Predicated)";
} else {
switch (form_hash_) {
- case Hash("lsl_z_p_zi"):
- case Hash("sqshl_z_p_zi"):
- case Hash("sqshlu_z_p_zi"):
- case Hash("uqshl_z_p_zi"):
+ case "lsl_z_p_zi"_h:
+ case "sqshl_z_p_zi"_h:
+ case "sqshlu_z_p_zi"_h:
+ case "uqshl_z_p_zi"_h:
suffix = "'ITriSvep";
break;
- case Hash("asrd_z_p_zi"):
- case Hash("asr_z_p_zi"):
- case Hash("lsr_z_p_zi"):
- case Hash("srshr_z_p_zi"):
- case Hash("urshr_z_p_zi"):
+ case "asrd_z_p_zi"_h:
+ case "asr_z_p_zi"_h:
+ case "lsr_z_p_zi"_h:
+ case "srshr_z_p_zi"_h:
+ case "urshr_z_p_zi"_h:
suffix = "'ITriSveq";
break;
default:
@@ -6753,16 +6753,16 @@
const char *suffix = ", #'s1916*16]";
switch (form_hash_) {
- case Hash("ld1rqb_z_p_bi_u8"):
- case Hash("ld1rqd_z_p_bi_u64"):
- case Hash("ld1rqh_z_p_bi_u16"):
- case Hash("ld1rqw_z_p_bi_u32"):
+ case "ld1rqb_z_p_bi_u8"_h:
+ case "ld1rqd_z_p_bi_u64"_h:
+ case "ld1rqh_z_p_bi_u16"_h:
+ case "ld1rqw_z_p_bi_u32"_h:
// Nothing to do.
break;
- case Hash("ld1rob_z_p_bi_u8"):
- case Hash("ld1rod_z_p_bi_u64"):
- case Hash("ld1roh_z_p_bi_u16"):
- case Hash("ld1row_z_p_bi_u32"):
+ case "ld1rob_z_p_bi_u8"_h:
+ case "ld1rod_z_p_bi_u64"_h:
+ case "ld1roh_z_p_bi_u16"_h:
+ case "ld1row_z_p_bi_u32"_h:
suffix = ", #'s1916*32]";
break;
default:
@@ -6781,16 +6781,16 @@
const char *suffix = "'Rm, lsl #'u2423]";
switch (form_hash_) {
- case Hash("ld1rqb_z_p_br_contiguous"):
- case Hash("ld1rob_z_p_br_contiguous"):
+ case "ld1rqb_z_p_br_contiguous"_h:
+ case "ld1rob_z_p_br_contiguous"_h:
suffix = "'Rm]";
break;
- case Hash("ld1rqd_z_p_br_contiguous"):
- case Hash("ld1rod_z_p_br_contiguous"):
- case Hash("ld1rqh_z_p_br_contiguous"):
- case Hash("ld1roh_z_p_br_contiguous"):
- case Hash("ld1rqw_z_p_br_contiguous"):
- case Hash("ld1row_z_p_br_contiguous"):
+ case "ld1rqd_z_p_br_contiguous"_h:
+ case "ld1rod_z_p_br_contiguous"_h:
+ case "ld1rqh_z_p_br_contiguous"_h:
+ case "ld1roh_z_p_br_contiguous"_h:
+ case "ld1rqw_z_p_br_contiguous"_h:
+ case "ld1row_z_p_br_contiguous"_h:
// Nothing to do.
break;
default:
@@ -7644,13 +7644,13 @@
const char *form_i = "'Zd.'tszs, 'Zn.'tszs, ";
switch (form_hash_) {
- case Hash("asr_z_zi"):
- case Hash("lsr_z_zi"):
- case Hash("sri_z_zzi"):
- case Hash("srsra_z_zi"):
- case Hash("ssra_z_zi"):
- case Hash("ursra_z_zi"):
- case Hash("usra_z_zi"):
+ case "asr_z_zi"_h:
+ case "lsr_z_zi"_h:
+ case "sri_z_zzi"_h:
+ case "srsra_z_zi"_h:
+ case "ssra_z_zi"_h:
+ case "ursra_z_zi"_h:
+ case "usra_z_zi"_h:
if (tsize != 0) {
// The tsz field must not be zero.
mnemonic = mnemonic_.c_str();
@@ -7658,8 +7658,8 @@
suffix = "'ITriSves";
}
break;
- case Hash("lsl_z_zi"):
- case Hash("sli_z_zzi"):
+ case "lsl_z_zi"_h:
+ case "sli_z_zzi"_h:
if (tsize != 0) {
// The tsz field must not be zero.
mnemonic = mnemonic_.c_str();
@@ -7667,9 +7667,9 @@
suffix = "'ITriSver";
}
break;
- case Hash("asr_z_zw"):
- case Hash("lsl_z_zw"):
- case Hash("lsr_z_zw"):
+ case "asr_z_zw"_h:
+ case "lsl_z_zw"_h:
+ case "lsr_z_zw"_h:
if (lane_size <= kSRegSizeInBytesLog2) {
mnemonic = mnemonic_.c_str();
form = "'Zd.'t, 'Zn.'t, 'Zm.d";
@@ -8407,24 +8407,24 @@
VectorFormat vform = instr->GetSVEVectorFormat();
switch (form_hash_) {
- case Hash("sxtw_z_p_z"):
- case Hash("uxtw_z_p_z"):
+ case "sxtw_z_p_z"_h:
+ case "uxtw_z_p_z"_h:
if (vform == kFormatVnS) {
VisitUnallocated(instr);
return;
}
VIXL_FALLTHROUGH();
- case Hash("sxth_z_p_z"):
- case Hash("uxth_z_p_z"):
+ case "sxth_z_p_z"_h:
+ case "uxth_z_p_z"_h:
if (vform == kFormatVnH) {
VisitUnallocated(instr);
return;
}
VIXL_FALLTHROUGH();
- case Hash("sxtb_z_p_z"):
- case Hash("uxtb_z_p_z"):
- case Hash("fabs_z_p_z"):
- case Hash("fneg_z_p_z"):
+ case "sxtb_z_p_z"_h:
+ case "uxtb_z_p_z"_h:
+ case "fabs_z_p_z"_h:
+ case "fneg_z_p_z"_h:
if (vform == kFormatVnB) {
VisitUnallocated(instr);
return;
@@ -8440,14 +8440,14 @@
const char *form = "(SVEMulIndex)";
switch (form_hash_) {
- case Hash("sdot_z_zzzi_d"):
- case Hash("udot_z_zzzi_d"):
+ case "sdot_z_zzzi_d"_h:
+ case "udot_z_zzzi_d"_h:
form = "'Zd.d, 'Zn.h, z'u1916.h['u2020]";
break;
- case Hash("sdot_z_zzzi_s"):
- case Hash("sudot_z_zzzi_s"):
- case Hash("udot_z_zzzi_s"):
- case Hash("usdot_z_zzzi_s"):
+ case "sdot_z_zzzi_s"_h:
+ case "sudot_z_zzzi_s"_h:
+ case "udot_z_zzzi_s"_h:
+ case "usdot_z_zzzi_s"_h:
form = "'Zd.s, 'Zn.b, z'u1816.b['u2019]";
break;
default:
diff --git a/src/aarch64/instructions-aarch64.cc b/src/aarch64/instructions-aarch64.cc
index 2adf24a..4718e2d 100644
--- a/src/aarch64/instructions-aarch64.cc
+++ b/src/aarch64/instructions-aarch64.cc
@@ -68,197 +68,197 @@
bool zd_isnt_zm = movprfx_zd != GetRm();
switch (form_hash) {
- case Hash("cdot_z_zzzi_s"):
- case Hash("sdot_z_zzzi_s"):
- case Hash("sudot_z_zzzi_s"):
- case Hash("udot_z_zzzi_s"):
- case Hash("usdot_z_zzzi_s"):
+ case "cdot_z_zzzi_s"_h:
+ case "sdot_z_zzzi_s"_h:
+ case "sudot_z_zzzi_s"_h:
+ case "udot_z_zzzi_s"_h:
+ case "usdot_z_zzzi_s"_h:
return (GetRd() != static_cast<int>(ExtractBits(18, 16))) &&
movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
- case Hash("cdot_z_zzzi_d"):
- case Hash("sdot_z_zzzi_d"):
- case Hash("udot_z_zzzi_d"):
+ case "cdot_z_zzzi_d"_h:
+ case "sdot_z_zzzi_d"_h:
+ case "udot_z_zzzi_d"_h:
return (GetRd() != static_cast<int>(ExtractBits(19, 16))) &&
movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
- case Hash("fmlalb_z_zzzi_s"):
- case Hash("fmlalt_z_zzzi_s"):
- case Hash("fmlslb_z_zzzi_s"):
- case Hash("fmlslt_z_zzzi_s"):
- case Hash("smlalb_z_zzzi_d"):
- case Hash("smlalb_z_zzzi_s"):
- case Hash("smlalt_z_zzzi_d"):
- case Hash("smlalt_z_zzzi_s"):
- case Hash("smlslb_z_zzzi_d"):
- case Hash("smlslb_z_zzzi_s"):
- case Hash("smlslt_z_zzzi_d"):
- case Hash("smlslt_z_zzzi_s"):
- case Hash("sqdmlalb_z_zzzi_d"):
- case Hash("sqdmlalb_z_zzzi_s"):
- case Hash("sqdmlalt_z_zzzi_d"):
- case Hash("sqdmlalt_z_zzzi_s"):
- case Hash("sqdmlslb_z_zzzi_d"):
- case Hash("sqdmlslb_z_zzzi_s"):
- case Hash("sqdmlslt_z_zzzi_d"):
- case Hash("sqdmlslt_z_zzzi_s"):
- case Hash("umlalb_z_zzzi_d"):
- case Hash("umlalb_z_zzzi_s"):
- case Hash("umlalt_z_zzzi_d"):
- case Hash("umlalt_z_zzzi_s"):
- case Hash("umlslb_z_zzzi_d"):
- case Hash("umlslb_z_zzzi_s"):
- case Hash("umlslt_z_zzzi_d"):
- case Hash("umlslt_z_zzzi_s"):
+ case "fmlalb_z_zzzi_s"_h:
+ case "fmlalt_z_zzzi_s"_h:
+ case "fmlslb_z_zzzi_s"_h:
+ case "fmlslt_z_zzzi_s"_h:
+ case "smlalb_z_zzzi_d"_h:
+ case "smlalb_z_zzzi_s"_h:
+ case "smlalt_z_zzzi_d"_h:
+ case "smlalt_z_zzzi_s"_h:
+ case "smlslb_z_zzzi_d"_h:
+ case "smlslb_z_zzzi_s"_h:
+ case "smlslt_z_zzzi_d"_h:
+ case "smlslt_z_zzzi_s"_h:
+ case "sqdmlalb_z_zzzi_d"_h:
+ case "sqdmlalb_z_zzzi_s"_h:
+ case "sqdmlalt_z_zzzi_d"_h:
+ case "sqdmlalt_z_zzzi_s"_h:
+ case "sqdmlslb_z_zzzi_d"_h:
+ case "sqdmlslb_z_zzzi_s"_h:
+ case "sqdmlslt_z_zzzi_d"_h:
+ case "sqdmlslt_z_zzzi_s"_h:
+ case "umlalb_z_zzzi_d"_h:
+ case "umlalb_z_zzzi_s"_h:
+ case "umlalt_z_zzzi_d"_h:
+ case "umlalt_z_zzzi_s"_h:
+ case "umlslb_z_zzzi_d"_h:
+ case "umlslb_z_zzzi_s"_h:
+ case "umlslt_z_zzzi_d"_h:
+ case "umlslt_z_zzzi_s"_h:
return (GetRd() != GetSVEMulLongZmAndIndex().first) &&
movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
- case Hash("cmla_z_zzzi_h"):
- case Hash("cmla_z_zzzi_s"):
- case Hash("fcmla_z_zzzi_h"):
- case Hash("fcmla_z_zzzi_s"):
- case Hash("fmla_z_zzzi_d"):
- case Hash("fmla_z_zzzi_h"):
- case Hash("fmla_z_zzzi_s"):
- case Hash("fmls_z_zzzi_d"):
- case Hash("fmls_z_zzzi_h"):
- case Hash("fmls_z_zzzi_s"):
- case Hash("mla_z_zzzi_d"):
- case Hash("mla_z_zzzi_h"):
- case Hash("mla_z_zzzi_s"):
- case Hash("mls_z_zzzi_d"):
- case Hash("mls_z_zzzi_h"):
- case Hash("mls_z_zzzi_s"):
- case Hash("sqrdcmlah_z_zzzi_h"):
- case Hash("sqrdcmlah_z_zzzi_s"):
- case Hash("sqrdmlah_z_zzzi_d"):
- case Hash("sqrdmlah_z_zzzi_h"):
- case Hash("sqrdmlah_z_zzzi_s"):
- case Hash("sqrdmlsh_z_zzzi_d"):
- case Hash("sqrdmlsh_z_zzzi_h"):
- case Hash("sqrdmlsh_z_zzzi_s"):
+ case "cmla_z_zzzi_h"_h:
+ case "cmla_z_zzzi_s"_h:
+ case "fcmla_z_zzzi_h"_h:
+ case "fcmla_z_zzzi_s"_h:
+ case "fmla_z_zzzi_d"_h:
+ case "fmla_z_zzzi_h"_h:
+ case "fmla_z_zzzi_s"_h:
+ case "fmls_z_zzzi_d"_h:
+ case "fmls_z_zzzi_h"_h:
+ case "fmls_z_zzzi_s"_h:
+ case "mla_z_zzzi_d"_h:
+ case "mla_z_zzzi_h"_h:
+ case "mla_z_zzzi_s"_h:
+ case "mls_z_zzzi_d"_h:
+ case "mls_z_zzzi_h"_h:
+ case "mls_z_zzzi_s"_h:
+ case "sqrdcmlah_z_zzzi_h"_h:
+ case "sqrdcmlah_z_zzzi_s"_h:
+ case "sqrdmlah_z_zzzi_d"_h:
+ case "sqrdmlah_z_zzzi_h"_h:
+ case "sqrdmlah_z_zzzi_s"_h:
+ case "sqrdmlsh_z_zzzi_d"_h:
+ case "sqrdmlsh_z_zzzi_h"_h:
+ case "sqrdmlsh_z_zzzi_s"_h:
return (GetRd() != GetSVEMulZmAndIndex().first) &&
movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
- case Hash("adclb_z_zzz"):
- case Hash("adclt_z_zzz"):
- case Hash("bcax_z_zzz"):
- case Hash("bsl1n_z_zzz"):
- case Hash("bsl2n_z_zzz"):
- case Hash("bsl_z_zzz"):
- case Hash("cdot_z_zzz"):
- case Hash("cmla_z_zzz"):
- case Hash("eor3_z_zzz"):
- case Hash("eorbt_z_zz"):
- case Hash("eortb_z_zz"):
- case Hash("fmlalb_z_zzz"):
- case Hash("fmlalt_z_zzz"):
- case Hash("fmlslb_z_zzz"):
- case Hash("fmlslt_z_zzz"):
- case Hash("nbsl_z_zzz"):
- case Hash("saba_z_zzz"):
- case Hash("sabalb_z_zzz"):
- case Hash("sabalt_z_zzz"):
- case Hash("sbclb_z_zzz"):
- case Hash("sbclt_z_zzz"):
- case Hash("sdot_z_zzz"):
- case Hash("smlalb_z_zzz"):
- case Hash("smlalt_z_zzz"):
- case Hash("smlslb_z_zzz"):
- case Hash("smlslt_z_zzz"):
- case Hash("sqdmlalb_z_zzz"):
- case Hash("sqdmlalbt_z_zzz"):
- case Hash("sqdmlalt_z_zzz"):
- case Hash("sqdmlslb_z_zzz"):
- case Hash("sqdmlslbt_z_zzz"):
- case Hash("sqdmlslt_z_zzz"):
- case Hash("sqrdcmlah_z_zzz"):
- case Hash("sqrdmlah_z_zzz"):
- case Hash("sqrdmlsh_z_zzz"):
- case Hash("uaba_z_zzz"):
- case Hash("uabalb_z_zzz"):
- case Hash("uabalt_z_zzz"):
- case Hash("udot_z_zzz"):
- case Hash("umlalb_z_zzz"):
- case Hash("umlalt_z_zzz"):
- case Hash("umlslb_z_zzz"):
- case Hash("umlslt_z_zzz"):
- case Hash("usdot_z_zzz_s"):
- case Hash("fmmla_z_zzz_s"):
- case Hash("fmmla_z_zzz_d"):
- case Hash("smmla_z_zzz"):
- case Hash("ummla_z_zzz"):
- case Hash("usmmla_z_zzz"):
+ case "adclb_z_zzz"_h:
+ case "adclt_z_zzz"_h:
+ case "bcax_z_zzz"_h:
+ case "bsl1n_z_zzz"_h:
+ case "bsl2n_z_zzz"_h:
+ case "bsl_z_zzz"_h:
+ case "cdot_z_zzz"_h:
+ case "cmla_z_zzz"_h:
+ case "eor3_z_zzz"_h:
+ case "eorbt_z_zz"_h:
+ case "eortb_z_zz"_h:
+ case "fmlalb_z_zzz"_h:
+ case "fmlalt_z_zzz"_h:
+ case "fmlslb_z_zzz"_h:
+ case "fmlslt_z_zzz"_h:
+ case "nbsl_z_zzz"_h:
+ case "saba_z_zzz"_h:
+ case "sabalb_z_zzz"_h:
+ case "sabalt_z_zzz"_h:
+ case "sbclb_z_zzz"_h:
+ case "sbclt_z_zzz"_h:
+ case "sdot_z_zzz"_h:
+ case "smlalb_z_zzz"_h:
+ case "smlalt_z_zzz"_h:
+ case "smlslb_z_zzz"_h:
+ case "smlslt_z_zzz"_h:
+ case "sqdmlalb_z_zzz"_h:
+ case "sqdmlalbt_z_zzz"_h:
+ case "sqdmlalt_z_zzz"_h:
+ case "sqdmlslb_z_zzz"_h:
+ case "sqdmlslbt_z_zzz"_h:
+ case "sqdmlslt_z_zzz"_h:
+ case "sqrdcmlah_z_zzz"_h:
+ case "sqrdmlah_z_zzz"_h:
+ case "sqrdmlsh_z_zzz"_h:
+ case "uaba_z_zzz"_h:
+ case "uabalb_z_zzz"_h:
+ case "uabalt_z_zzz"_h:
+ case "udot_z_zzz"_h:
+ case "umlalb_z_zzz"_h:
+ case "umlalt_z_zzz"_h:
+ case "umlslb_z_zzz"_h:
+ case "umlslt_z_zzz"_h:
+ case "usdot_z_zzz_s"_h:
+ case "fmmla_z_zzz_s"_h:
+ case "fmmla_z_zzz_d"_h:
+ case "smmla_z_zzz"_h:
+ case "ummla_z_zzz"_h:
+ case "usmmla_z_zzz"_h:
return movprfx_is_unpredicated && zd_isnt_zm && zd_isnt_zn && zd_matches;
- case Hash("addp_z_p_zz"):
- case Hash("cadd_z_zz"):
- case Hash("clasta_z_p_zz"):
- case Hash("clastb_z_p_zz"):
- case Hash("decd_z_zs"):
- case Hash("dech_z_zs"):
- case Hash("decw_z_zs"):
- case Hash("faddp_z_p_zz"):
- case Hash("fmaxnmp_z_p_zz"):
- case Hash("fmaxp_z_p_zz"):
- case Hash("fminnmp_z_p_zz"):
- case Hash("fminp_z_p_zz"):
- case Hash("ftmad_z_zzi"):
- case Hash("incd_z_zs"):
- case Hash("inch_z_zs"):
- case Hash("incw_z_zs"):
- case Hash("insr_z_v"):
- case Hash("smaxp_z_p_zz"):
- case Hash("sminp_z_p_zz"):
- case Hash("splice_z_p_zz_con"):
- case Hash("splice_z_p_zz_des"):
- case Hash("sqcadd_z_zz"):
- case Hash("sqdecd_z_zs"):
- case Hash("sqdech_z_zs"):
- case Hash("sqdecw_z_zs"):
- case Hash("sqincd_z_zs"):
- case Hash("sqinch_z_zs"):
- case Hash("sqincw_z_zs"):
- case Hash("srsra_z_zi"):
- case Hash("ssra_z_zi"):
- case Hash("umaxp_z_p_zz"):
- case Hash("uminp_z_p_zz"):
- case Hash("uqdecd_z_zs"):
- case Hash("uqdech_z_zs"):
- case Hash("uqdecw_z_zs"):
- case Hash("uqincd_z_zs"):
- case Hash("uqinch_z_zs"):
- case Hash("uqincw_z_zs"):
- case Hash("ursra_z_zi"):
- case Hash("usra_z_zi"):
- case Hash("xar_z_zzi"):
+ case "addp_z_p_zz"_h:
+ case "cadd_z_zz"_h:
+ case "clasta_z_p_zz"_h:
+ case "clastb_z_p_zz"_h:
+ case "decd_z_zs"_h:
+ case "dech_z_zs"_h:
+ case "decw_z_zs"_h:
+ case "faddp_z_p_zz"_h:
+ case "fmaxnmp_z_p_zz"_h:
+ case "fmaxp_z_p_zz"_h:
+ case "fminnmp_z_p_zz"_h:
+ case "fminp_z_p_zz"_h:
+ case "ftmad_z_zzi"_h:
+ case "incd_z_zs"_h:
+ case "inch_z_zs"_h:
+ case "incw_z_zs"_h:
+ case "insr_z_v"_h:
+ case "smaxp_z_p_zz"_h:
+ case "sminp_z_p_zz"_h:
+ case "splice_z_p_zz_con"_h:
+ case "splice_z_p_zz_des"_h:
+ case "sqcadd_z_zz"_h:
+ case "sqdecd_z_zs"_h:
+ case "sqdech_z_zs"_h:
+ case "sqdecw_z_zs"_h:
+ case "sqincd_z_zs"_h:
+ case "sqinch_z_zs"_h:
+ case "sqincw_z_zs"_h:
+ case "srsra_z_zi"_h:
+ case "ssra_z_zi"_h:
+ case "umaxp_z_p_zz"_h:
+ case "uminp_z_p_zz"_h:
+ case "uqdecd_z_zs"_h:
+ case "uqdech_z_zs"_h:
+ case "uqdecw_z_zs"_h:
+ case "uqincd_z_zs"_h:
+ case "uqinch_z_zs"_h:
+ case "uqincw_z_zs"_h:
+ case "ursra_z_zi"_h:
+ case "usra_z_zi"_h:
+ case "xar_z_zzi"_h:
return movprfx_is_unpredicated && zd_isnt_zn && zd_matches;
- case Hash("add_z_zi"):
- case Hash("and_z_zi"):
- case Hash("decp_z_p_z"):
- case Hash("eor_z_zi"):
- case Hash("incp_z_p_z"):
- case Hash("insr_z_r"):
- case Hash("mul_z_zi"):
- case Hash("orr_z_zi"):
- case Hash("smax_z_zi"):
- case Hash("smin_z_zi"):
- case Hash("sqadd_z_zi"):
- case Hash("sqdecp_z_p_z"):
- case Hash("sqincp_z_p_z"):
- case Hash("sqsub_z_zi"):
- case Hash("sub_z_zi"):
- case Hash("subr_z_zi"):
- case Hash("umax_z_zi"):
- case Hash("umin_z_zi"):
- case Hash("uqadd_z_zi"):
- case Hash("uqdecp_z_p_z"):
- case Hash("uqincp_z_p_z"):
- case Hash("uqsub_z_zi"):
+ case "add_z_zi"_h:
+ case "and_z_zi"_h:
+ case "decp_z_p_z"_h:
+ case "eor_z_zi"_h:
+ case "incp_z_p_z"_h:
+ case "insr_z_r"_h:
+ case "mul_z_zi"_h:
+ case "orr_z_zi"_h:
+ case "smax_z_zi"_h:
+ case "smin_z_zi"_h:
+ case "sqadd_z_zi"_h:
+ case "sqdecp_z_p_z"_h:
+ case "sqincp_z_p_z"_h:
+ case "sqsub_z_zi"_h:
+ case "sub_z_zi"_h:
+ case "subr_z_zi"_h:
+ case "umax_z_zi"_h:
+ case "umin_z_zi"_h:
+ case "uqadd_z_zi"_h:
+ case "uqdecp_z_p_z"_h:
+ case "uqincp_z_p_z"_h:
+ case "uqsub_z_zi"_h:
return movprfx_is_unpredicated && zd_matches;
- case Hash("cpy_z_p_i"):
+ case "cpy_z_p_i"_h:
if (movprfx_is_predicated) {
if (!vform_matches) return false;
if (movprfx_pg != GetRx<19, 16>()) return false;
@@ -267,25 +267,25 @@
if (ExtractBit(14) == 0) return false;
return zd_matches;
- case Hash("fcpy_z_p_i"):
+ case "fcpy_z_p_i"_h:
return (movprfx_is_unpredicated ||
((movprfx_pg == GetRx<19, 16>()) && vform_matches)) &&
zd_matches;
- case Hash("flogb_z_p_z"):
+ case "flogb_z_p_z"_h:
return (movprfx_is_unpredicated ||
((movprfx_vform == GetSVEVectorFormat(17)) && pg_matches_low8)) &&
zd_isnt_zn && zd_matches;
- case Hash("asr_z_p_zi"):
- case Hash("asrd_z_p_zi"):
- case Hash("lsl_z_p_zi"):
- case Hash("lsr_z_p_zi"):
- case Hash("sqshl_z_p_zi"):
- case Hash("sqshlu_z_p_zi"):
- case Hash("srshr_z_p_zi"):
- case Hash("uqshl_z_p_zi"):
- case Hash("urshr_z_p_zi"):
+ case "asr_z_p_zi"_h:
+ case "asrd_z_p_zi"_h:
+ case "lsl_z_p_zi"_h:
+ case "lsr_z_p_zi"_h:
+ case "sqshl_z_p_zi"_h:
+ case "sqshlu_z_p_zi"_h:
+ case "srshr_z_p_zi"_h:
+ case "uqshl_z_p_zi"_h:
+ case "urshr_z_p_zi"_h:
return (movprfx_is_unpredicated ||
((movprfx_vform ==
SVEFormatFromLaneSizeInBytesLog2(
@@ -293,187 +293,187 @@
pg_matches_low8)) &&
zd_matches;
- case Hash("fcvt_z_p_z_d2h"):
- case Hash("fcvt_z_p_z_d2s"):
- case Hash("fcvt_z_p_z_h2d"):
- case Hash("fcvt_z_p_z_s2d"):
- case Hash("fcvtx_z_p_z_d2s"):
- case Hash("fcvtzs_z_p_z_d2w"):
- case Hash("fcvtzs_z_p_z_d2x"):
- case Hash("fcvtzs_z_p_z_fp162x"):
- case Hash("fcvtzs_z_p_z_s2x"):
- case Hash("fcvtzu_z_p_z_d2w"):
- case Hash("fcvtzu_z_p_z_d2x"):
- case Hash("fcvtzu_z_p_z_fp162x"):
- case Hash("fcvtzu_z_p_z_s2x"):
- case Hash("scvtf_z_p_z_w2d"):
- case Hash("scvtf_z_p_z_x2d"):
- case Hash("scvtf_z_p_z_x2fp16"):
- case Hash("scvtf_z_p_z_x2s"):
- case Hash("ucvtf_z_p_z_w2d"):
- case Hash("ucvtf_z_p_z_x2d"):
- case Hash("ucvtf_z_p_z_x2fp16"):
- case Hash("ucvtf_z_p_z_x2s"):
+ case "fcvt_z_p_z_d2h"_h:
+ case "fcvt_z_p_z_d2s"_h:
+ case "fcvt_z_p_z_h2d"_h:
+ case "fcvt_z_p_z_s2d"_h:
+ case "fcvtx_z_p_z_d2s"_h:
+ case "fcvtzs_z_p_z_d2w"_h:
+ case "fcvtzs_z_p_z_d2x"_h:
+ case "fcvtzs_z_p_z_fp162x"_h:
+ case "fcvtzs_z_p_z_s2x"_h:
+ case "fcvtzu_z_p_z_d2w"_h:
+ case "fcvtzu_z_p_z_d2x"_h:
+ case "fcvtzu_z_p_z_fp162x"_h:
+ case "fcvtzu_z_p_z_s2x"_h:
+ case "scvtf_z_p_z_w2d"_h:
+ case "scvtf_z_p_z_x2d"_h:
+ case "scvtf_z_p_z_x2fp16"_h:
+ case "scvtf_z_p_z_x2s"_h:
+ case "ucvtf_z_p_z_w2d"_h:
+ case "ucvtf_z_p_z_x2d"_h:
+ case "ucvtf_z_p_z_x2fp16"_h:
+ case "ucvtf_z_p_z_x2s"_h:
return (movprfx_is_unpredicated ||
((movprfx_vform == kFormatVnD) && pg_matches_low8)) &&
zd_isnt_zn && zd_matches;
- case Hash("fcvtzs_z_p_z_fp162h"):
- case Hash("fcvtzu_z_p_z_fp162h"):
- case Hash("scvtf_z_p_z_h2fp16"):
- case Hash("ucvtf_z_p_z_h2fp16"):
+ case "fcvtzs_z_p_z_fp162h"_h:
+ case "fcvtzu_z_p_z_fp162h"_h:
+ case "scvtf_z_p_z_h2fp16"_h:
+ case "ucvtf_z_p_z_h2fp16"_h:
return (movprfx_is_unpredicated ||
((movprfx_vform == kFormatVnH) && pg_matches_low8)) &&
zd_isnt_zn && zd_matches;
- case Hash("fcvt_z_p_z_h2s"):
- case Hash("fcvt_z_p_z_s2h"):
- case Hash("fcvtzs_z_p_z_fp162w"):
- case Hash("fcvtzs_z_p_z_s2w"):
- case Hash("fcvtzu_z_p_z_fp162w"):
- case Hash("fcvtzu_z_p_z_s2w"):
- case Hash("scvtf_z_p_z_w2fp16"):
- case Hash("scvtf_z_p_z_w2s"):
- case Hash("ucvtf_z_p_z_w2fp16"):
- case Hash("ucvtf_z_p_z_w2s"):
+ case "fcvt_z_p_z_h2s"_h:
+ case "fcvt_z_p_z_s2h"_h:
+ case "fcvtzs_z_p_z_fp162w"_h:
+ case "fcvtzs_z_p_z_s2w"_h:
+ case "fcvtzu_z_p_z_fp162w"_h:
+ case "fcvtzu_z_p_z_s2w"_h:
+ case "scvtf_z_p_z_w2fp16"_h:
+ case "scvtf_z_p_z_w2s"_h:
+ case "ucvtf_z_p_z_w2fp16"_h:
+ case "ucvtf_z_p_z_w2s"_h:
return (movprfx_is_unpredicated ||
((movprfx_vform == kFormatVnS) && pg_matches_low8)) &&
zd_isnt_zn && zd_matches;
- case Hash("fcmla_z_p_zzz"):
- case Hash("fmad_z_p_zzz"):
- case Hash("fmla_z_p_zzz"):
- case Hash("fmls_z_p_zzz"):
- case Hash("fmsb_z_p_zzz"):
- case Hash("fnmad_z_p_zzz"):
- case Hash("fnmla_z_p_zzz"):
- case Hash("fnmls_z_p_zzz"):
- case Hash("fnmsb_z_p_zzz"):
- case Hash("mad_z_p_zzz"):
- case Hash("mla_z_p_zzz"):
- case Hash("mls_z_p_zzz"):
- case Hash("msb_z_p_zzz"):
+ case "fcmla_z_p_zzz"_h:
+ case "fmad_z_p_zzz"_h:
+ case "fmla_z_p_zzz"_h:
+ case "fmls_z_p_zzz"_h:
+ case "fmsb_z_p_zzz"_h:
+ case "fnmad_z_p_zzz"_h:
+ case "fnmla_z_p_zzz"_h:
+ case "fnmls_z_p_zzz"_h:
+ case "fnmsb_z_p_zzz"_h:
+ case "mad_z_p_zzz"_h:
+ case "mla_z_p_zzz"_h:
+ case "mls_z_p_zzz"_h:
+ case "msb_z_p_zzz"_h:
return (movprfx_is_unpredicated || (pg_matches_low8 && vform_matches)) &&
zd_isnt_zm && zd_isnt_zn && zd_matches;
- case Hash("abs_z_p_z"):
- case Hash("add_z_p_zz"):
- case Hash("and_z_p_zz"):
- case Hash("asr_z_p_zw"):
- case Hash("asr_z_p_zz"):
- case Hash("asrr_z_p_zz"):
- case Hash("bic_z_p_zz"):
- case Hash("cls_z_p_z"):
- case Hash("clz_z_p_z"):
- case Hash("cnot_z_p_z"):
- case Hash("cnt_z_p_z"):
- case Hash("cpy_z_p_v"):
- case Hash("eor_z_p_zz"):
- case Hash("fabd_z_p_zz"):
- case Hash("fabs_z_p_z"):
- case Hash("fadd_z_p_zz"):
- case Hash("fcadd_z_p_zz"):
- case Hash("fdiv_z_p_zz"):
- case Hash("fdivr_z_p_zz"):
- case Hash("fmax_z_p_zz"):
- case Hash("fmaxnm_z_p_zz"):
- case Hash("fmin_z_p_zz"):
- case Hash("fminnm_z_p_zz"):
- case Hash("fmul_z_p_zz"):
- case Hash("fmulx_z_p_zz"):
- case Hash("fneg_z_p_z"):
- case Hash("frecpx_z_p_z"):
- case Hash("frinta_z_p_z"):
- case Hash("frinti_z_p_z"):
- case Hash("frintm_z_p_z"):
- case Hash("frintn_z_p_z"):
- case Hash("frintp_z_p_z"):
- case Hash("frintx_z_p_z"):
- case Hash("frintz_z_p_z"):
- case Hash("fscale_z_p_zz"):
- case Hash("fsqrt_z_p_z"):
- case Hash("fsub_z_p_zz"):
- case Hash("fsubr_z_p_zz"):
- case Hash("lsl_z_p_zw"):
- case Hash("lsl_z_p_zz"):
- case Hash("lslr_z_p_zz"):
- case Hash("lsr_z_p_zw"):
- case Hash("lsr_z_p_zz"):
- case Hash("lsrr_z_p_zz"):
- case Hash("mul_z_p_zz"):
- case Hash("neg_z_p_z"):
- case Hash("not_z_p_z"):
- case Hash("orr_z_p_zz"):
- case Hash("rbit_z_p_z"):
- case Hash("revb_z_z"):
- case Hash("revh_z_z"):
- case Hash("revw_z_z"):
- case Hash("sabd_z_p_zz"):
- case Hash("sadalp_z_p_z"):
- case Hash("sdiv_z_p_zz"):
- case Hash("sdivr_z_p_zz"):
- case Hash("shadd_z_p_zz"):
- case Hash("shsub_z_p_zz"):
- case Hash("shsubr_z_p_zz"):
- case Hash("smax_z_p_zz"):
- case Hash("smin_z_p_zz"):
- case Hash("smulh_z_p_zz"):
- case Hash("sqabs_z_p_z"):
- case Hash("sqadd_z_p_zz"):
- case Hash("sqneg_z_p_z"):
- case Hash("sqrshl_z_p_zz"):
- case Hash("sqrshlr_z_p_zz"):
- case Hash("sqshl_z_p_zz"):
- case Hash("sqshlr_z_p_zz"):
- case Hash("sqsub_z_p_zz"):
- case Hash("sqsubr_z_p_zz"):
- case Hash("srhadd_z_p_zz"):
- case Hash("srshl_z_p_zz"):
- case Hash("srshlr_z_p_zz"):
- case Hash("sub_z_p_zz"):
- case Hash("subr_z_p_zz"):
- case Hash("suqadd_z_p_zz"):
- case Hash("sxtb_z_p_z"):
- case Hash("sxth_z_p_z"):
- case Hash("sxtw_z_p_z"):
- case Hash("uabd_z_p_zz"):
- case Hash("uadalp_z_p_z"):
- case Hash("udiv_z_p_zz"):
- case Hash("udivr_z_p_zz"):
- case Hash("uhadd_z_p_zz"):
- case Hash("uhsub_z_p_zz"):
- case Hash("uhsubr_z_p_zz"):
- case Hash("umax_z_p_zz"):
- case Hash("umin_z_p_zz"):
- case Hash("umulh_z_p_zz"):
- case Hash("uqadd_z_p_zz"):
- case Hash("uqrshl_z_p_zz"):
- case Hash("uqrshlr_z_p_zz"):
- case Hash("uqshl_z_p_zz"):
- case Hash("uqshlr_z_p_zz"):
- case Hash("uqsub_z_p_zz"):
- case Hash("uqsubr_z_p_zz"):
- case Hash("urecpe_z_p_z"):
- case Hash("urhadd_z_p_zz"):
- case Hash("urshl_z_p_zz"):
- case Hash("urshlr_z_p_zz"):
- case Hash("ursqrte_z_p_z"):
- case Hash("usqadd_z_p_zz"):
- case Hash("uxtb_z_p_z"):
- case Hash("uxth_z_p_z"):
- case Hash("uxtw_z_p_z"):
+ case "abs_z_p_z"_h:
+ case "add_z_p_zz"_h:
+ case "and_z_p_zz"_h:
+ case "asr_z_p_zw"_h:
+ case "asr_z_p_zz"_h:
+ case "asrr_z_p_zz"_h:
+ case "bic_z_p_zz"_h:
+ case "cls_z_p_z"_h:
+ case "clz_z_p_z"_h:
+ case "cnot_z_p_z"_h:
+ case "cnt_z_p_z"_h:
+ case "cpy_z_p_v"_h:
+ case "eor_z_p_zz"_h:
+ case "fabd_z_p_zz"_h:
+ case "fabs_z_p_z"_h:
+ case "fadd_z_p_zz"_h:
+ case "fcadd_z_p_zz"_h:
+ case "fdiv_z_p_zz"_h:
+ case "fdivr_z_p_zz"_h:
+ case "fmax_z_p_zz"_h:
+ case "fmaxnm_z_p_zz"_h:
+ case "fmin_z_p_zz"_h:
+ case "fminnm_z_p_zz"_h:
+ case "fmul_z_p_zz"_h:
+ case "fmulx_z_p_zz"_h:
+ case "fneg_z_p_z"_h:
+ case "frecpx_z_p_z"_h:
+ case "frinta_z_p_z"_h:
+ case "frinti_z_p_z"_h:
+ case "frintm_z_p_z"_h:
+ case "frintn_z_p_z"_h:
+ case "frintp_z_p_z"_h:
+ case "frintx_z_p_z"_h:
+ case "frintz_z_p_z"_h:
+ case "fscale_z_p_zz"_h:
+ case "fsqrt_z_p_z"_h:
+ case "fsub_z_p_zz"_h:
+ case "fsubr_z_p_zz"_h:
+ case "lsl_z_p_zw"_h:
+ case "lsl_z_p_zz"_h:
+ case "lslr_z_p_zz"_h:
+ case "lsr_z_p_zw"_h:
+ case "lsr_z_p_zz"_h:
+ case "lsrr_z_p_zz"_h:
+ case "mul_z_p_zz"_h:
+ case "neg_z_p_z"_h:
+ case "not_z_p_z"_h:
+ case "orr_z_p_zz"_h:
+ case "rbit_z_p_z"_h:
+ case "revb_z_z"_h:
+ case "revh_z_z"_h:
+ case "revw_z_z"_h:
+ case "sabd_z_p_zz"_h:
+ case "sadalp_z_p_z"_h:
+ case "sdiv_z_p_zz"_h:
+ case "sdivr_z_p_zz"_h:
+ case "shadd_z_p_zz"_h:
+ case "shsub_z_p_zz"_h:
+ case "shsubr_z_p_zz"_h:
+ case "smax_z_p_zz"_h:
+ case "smin_z_p_zz"_h:
+ case "smulh_z_p_zz"_h:
+ case "sqabs_z_p_z"_h:
+ case "sqadd_z_p_zz"_h:
+ case "sqneg_z_p_z"_h:
+ case "sqrshl_z_p_zz"_h:
+ case "sqrshlr_z_p_zz"_h:
+ case "sqshl_z_p_zz"_h:
+ case "sqshlr_z_p_zz"_h:
+ case "sqsub_z_p_zz"_h:
+ case "sqsubr_z_p_zz"_h:
+ case "srhadd_z_p_zz"_h:
+ case "srshl_z_p_zz"_h:
+ case "srshlr_z_p_zz"_h:
+ case "sub_z_p_zz"_h:
+ case "subr_z_p_zz"_h:
+ case "suqadd_z_p_zz"_h:
+ case "sxtb_z_p_z"_h:
+ case "sxth_z_p_z"_h:
+ case "sxtw_z_p_z"_h:
+ case "uabd_z_p_zz"_h:
+ case "uadalp_z_p_z"_h:
+ case "udiv_z_p_zz"_h:
+ case "udivr_z_p_zz"_h:
+ case "uhadd_z_p_zz"_h:
+ case "uhsub_z_p_zz"_h:
+ case "uhsubr_z_p_zz"_h:
+ case "umax_z_p_zz"_h:
+ case "umin_z_p_zz"_h:
+ case "umulh_z_p_zz"_h:
+ case "uqadd_z_p_zz"_h:
+ case "uqrshl_z_p_zz"_h:
+ case "uqrshlr_z_p_zz"_h:
+ case "uqshl_z_p_zz"_h:
+ case "uqshlr_z_p_zz"_h:
+ case "uqsub_z_p_zz"_h:
+ case "uqsubr_z_p_zz"_h:
+ case "urecpe_z_p_z"_h:
+ case "urhadd_z_p_zz"_h:
+ case "urshl_z_p_zz"_h:
+ case "urshlr_z_p_zz"_h:
+ case "ursqrte_z_p_z"_h:
+ case "usqadd_z_p_zz"_h:
+ case "uxtb_z_p_z"_h:
+ case "uxth_z_p_z"_h:
+ case "uxtw_z_p_z"_h:
return (movprfx_is_unpredicated || (pg_matches_low8 && vform_matches)) &&
zd_isnt_zn && zd_matches;
- case Hash("cpy_z_p_r"):
- case Hash("fadd_z_p_zs"):
- case Hash("fmax_z_p_zs"):
- case Hash("fmaxnm_z_p_zs"):
- case Hash("fmin_z_p_zs"):
- case Hash("fminnm_z_p_zs"):
- case Hash("fmul_z_p_zs"):
- case Hash("fsub_z_p_zs"):
- case Hash("fsubr_z_p_zs"):
+ case "cpy_z_p_r"_h:
+ case "fadd_z_p_zs"_h:
+ case "fmax_z_p_zs"_h:
+ case "fmaxnm_z_p_zs"_h:
+ case "fmin_z_p_zs"_h:
+ case "fminnm_z_p_zs"_h:
+ case "fmul_z_p_zs"_h:
+ case "fsub_z_p_zs"_h:
+ case "fsubr_z_p_zs"_h:
return (movprfx_is_unpredicated || (pg_matches_low8 && vform_matches)) &&
zd_matches;
default:
diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc
index 10e4f8f..d183dc3 100644
--- a/src/aarch64/simulator-aarch64.cc
+++ b/src/aarch64/simulator-aarch64.cc
@@ -1995,10 +1995,10 @@
SimVRegister& zn = ReadVRegister(instr->GetRn());
switch (form_hash_) {
- case Hash("match_p_p_zz"):
+ case "match_p_p_zz"_h:
match(vform, pd, zn, zm, /* negate_match = */ false);
break;
- case Hash("nmatch_p_p_zz"):
+ case "nmatch_p_p_zz"_h:
match(vform, pd, zn, zm, /* negate_match = */ true);
break;
default:
@@ -2019,10 +2019,10 @@
bool no_conflict = false;
switch (form_hash_) {
- case Hash("whilerw_p_rr"):
+ case "whilerw_p_rr"_h:
no_conflict = (absdiff == 0);
break;
- case Hash("whilewr_p_rr"):
+ case "whilewr_p_rr"_h:
no_conflict = (absdiff == 0) || (src2 <= src1);
break;
default:
@@ -2040,7 +2040,7 @@
}
void Simulator::Simulate_ZdB_Zn1B_Zn2B_imm(const Instruction* instr) {
- VIXL_ASSERT(form_hash_ == Hash("ext_z_zi_con"));
+ VIXL_ASSERT(form_hash_ == "ext_z_zi_con"_h);
SimVRegister& zd = ReadVRegister(instr->GetRd());
SimVRegister& zn = ReadVRegister(instr->GetRn());
@@ -2059,7 +2059,7 @@
SimVRegister& zn = ReadVRegister(instr->GetRn());
switch (form_hash_) {
- case Hash("histseg_z_zz"):
+ case "histseg_z_zz"_h:
if (instr->GetSVEVectorFormat() == kFormatVnB) {
histogram(kFormatVnB,
zd,
@@ -2071,7 +2071,7 @@
VIXL_UNIMPLEMENTED();
}
break;
- case Hash("pmul_z_zz"):
+ case "pmul_z_zz"_h:
pmul(kFormatVnB, zd, zn, zm);
break;
default:
@@ -2089,9 +2089,9 @@
// supported.
if (vform == kFormatVnB) vform = kFormatVnH;
- VIXL_ASSERT((form_hash_ == Hash("mul_z_zzi_d")) ||
- (form_hash_ == Hash("mul_z_zzi_h")) ||
- (form_hash_ == Hash("mul_z_zzi_s")));
+ VIXL_ASSERT((form_hash_ == "mul_z_zzi_d"_h) ||
+ (form_hash_ == "mul_z_zzi_h"_h) ||
+ (form_hash_ == "mul_z_zzi_s"_h));
SimVRegister temp;
dup_elements_to_segments(vform, temp, instr->GetSVEMulZmAndIndex());
@@ -2108,12 +2108,10 @@
// supported.
if (vform == kFormatVnB) vform = kFormatVnH;
- VIXL_ASSERT((form_hash_ == Hash("mla_z_zzzi_d")) ||
- (form_hash_ == Hash("mla_z_zzzi_h")) ||
- (form_hash_ == Hash("mla_z_zzzi_s")) ||
- (form_hash_ == Hash("mls_z_zzzi_d")) ||
- (form_hash_ == Hash("mls_z_zzzi_h")) ||
- (form_hash_ == Hash("mls_z_zzzi_s")));
+ VIXL_ASSERT(
+ (form_hash_ == "mla_z_zzzi_d"_h) || (form_hash_ == "mla_z_zzzi_h"_h) ||
+ (form_hash_ == "mla_z_zzzi_s"_h) || (form_hash_ == "mls_z_zzzi_d"_h) ||
+ (form_hash_ == "mls_z_zzzi_h"_h) || (form_hash_ == "mls_z_zzzi_s"_h));
SimVRegister temp;
dup_elements_to_segments(vform, temp, instr->GetSVEMulZmAndIndex());
@@ -2139,14 +2137,14 @@
SimVRegister temp;
dup_elements_to_segments(vform, temp, instr->GetSVEMulZmAndIndex());
switch (form_hash_) {
- case Hash("sqdmulh_z_zzi_h"):
- case Hash("sqdmulh_z_zzi_s"):
- case Hash("sqdmulh_z_zzi_d"):
+ case "sqdmulh_z_zzi_h"_h:
+ case "sqdmulh_z_zzi_s"_h:
+ case "sqdmulh_z_zzi_d"_h:
sqdmulh(vform, zd, zn, temp);
break;
- case Hash("sqrdmulh_z_zzi_h"):
- case Hash("sqrdmulh_z_zzi_s"):
- case Hash("sqrdmulh_z_zzi_d"):
+ case "sqrdmulh_z_zzi_h"_h:
+ case "sqrdmulh_z_zzi_s"_h:
+ case "sqrdmulh_z_zzi_d"_h:
sqrdmulh(vform, zd, zn, temp);
break;
default:
@@ -2172,64 +2170,64 @@
pack_odd_elements(vform_half, zn_t, zn);
switch (form_hash_) {
- case Hash("smullb_z_zzi_s"):
- case Hash("smullb_z_zzi_d"):
+ case "smullb_z_zzi_s"_h:
+ case "smullb_z_zzi_d"_h:
smull(vform, zd, zn_b, zm_idx);
break;
- case Hash("smullt_z_zzi_s"):
- case Hash("smullt_z_zzi_d"):
+ case "smullt_z_zzi_s"_h:
+ case "smullt_z_zzi_d"_h:
smull(vform, zd, zn_t, zm_idx);
break;
- case Hash("sqdmullb_z_zzi_d"):
+ case "sqdmullb_z_zzi_d"_h:
sqdmull(vform, zd, zn_b, zm_idx);
break;
- case Hash("sqdmullt_z_zzi_d"):
+ case "sqdmullt_z_zzi_d"_h:
sqdmull(vform, zd, zn_t, zm_idx);
break;
- case Hash("umullb_z_zzi_s"):
- case Hash("umullb_z_zzi_d"):
+ case "umullb_z_zzi_s"_h:
+ case "umullb_z_zzi_d"_h:
umull(vform, zd, zn_b, zm_idx);
break;
- case Hash("umullt_z_zzi_s"):
- case Hash("umullt_z_zzi_d"):
+ case "umullt_z_zzi_s"_h:
+ case "umullt_z_zzi_d"_h:
umull(vform, zd, zn_t, zm_idx);
break;
- case Hash("sqdmullb_z_zzi_s"):
+ case "sqdmullb_z_zzi_s"_h:
sqdmull(vform, zd, zn_b, zm_idx);
break;
- case Hash("sqdmullt_z_zzi_s"):
+ case "sqdmullt_z_zzi_s"_h:
sqdmull(vform, zd, zn_t, zm_idx);
break;
- case Hash("smlalb_z_zzzi_s"):
- case Hash("smlalb_z_zzzi_d"):
+ case "smlalb_z_zzzi_s"_h:
+ case "smlalb_z_zzzi_d"_h:
smlal(vform, zd, zn_b, zm_idx);
break;
- case Hash("smlalt_z_zzzi_s"):
- case Hash("smlalt_z_zzzi_d"):
+ case "smlalt_z_zzzi_s"_h:
+ case "smlalt_z_zzzi_d"_h:
smlal(vform, zd, zn_t, zm_idx);
break;
- case Hash("smlslb_z_zzzi_s"):
- case Hash("smlslb_z_zzzi_d"):
+ case "smlslb_z_zzzi_s"_h:
+ case "smlslb_z_zzzi_d"_h:
smlsl(vform, zd, zn_b, zm_idx);
break;
- case Hash("smlslt_z_zzzi_s"):
- case Hash("smlslt_z_zzzi_d"):
+ case "smlslt_z_zzzi_s"_h:
+ case "smlslt_z_zzzi_d"_h:
smlsl(vform, zd, zn_t, zm_idx);
break;
- case Hash("umlalb_z_zzzi_s"):
- case Hash("umlalb_z_zzzi_d"):
+ case "umlalb_z_zzzi_s"_h:
+ case "umlalb_z_zzzi_d"_h:
umlal(vform, zd, zn_b, zm_idx);
break;
- case Hash("umlalt_z_zzzi_s"):
- case Hash("umlalt_z_zzzi_d"):
+ case "umlalt_z_zzzi_s"_h:
+ case "umlalt_z_zzzi_d"_h:
umlal(vform, zd, zn_t, zm_idx);
break;
- case Hash("umlslb_z_zzzi_s"):
- case Hash("umlslb_z_zzzi_d"):
+ case "umlslb_z_zzzi_s"_h:
+ case "umlslb_z_zzzi_d"_h:
umlsl(vform, zd, zn_b, zm_idx);
break;
- case Hash("umlslt_z_zzzi_s"):
- case Hash("umlslt_z_zzzi_d"):
+ case "umlslt_z_zzzi_s"_h:
+ case "umlslt_z_zzzi_d"_h:
umlsl(vform, zd, zn_t, zm_idx);
break;
default:
@@ -2246,7 +2244,7 @@
pack_even_elements(kFormatVnH, zd_b, zd);
switch (form_hash_) {
- case Hash("fcvtnt_z_p_z_s2h"):
+ case "fcvtnt_z_p_z_s2h"_h:
fcvt(kFormatVnH, kFormatVnS, result, pg, zn);
pack_even_elements(kFormatVnH, result, result);
zip1(kFormatVnH, result, zd_b, result);
@@ -2267,16 +2265,16 @@
pack_even_elements(kFormatVnS, zd_b, zd);
switch (form_hash_) {
- case Hash("fcvtnt_z_p_z_d2s"):
+ case "fcvtnt_z_p_z_d2s"_h:
fcvt(kFormatVnS, kFormatVnD, result, pg, zn);
pack_even_elements(kFormatVnS, result, result);
zip1(kFormatVnS, result, zd_b, result);
break;
- case Hash("fcvtx_z_p_z_d2s"):
+ case "fcvtx_z_p_z_d2s"_h:
fcvtxn(kFormatVnS, result, zn);
zip1(kFormatVnS, result, result, zero);
break;
- case Hash("fcvtxnt_z_p_z_d2s"):
+ case "fcvtxnt_z_p_z_d2s"_h:
fcvtxn(kFormatVnS, result, zn);
zip1(kFormatVnS, result, zd_b, result);
break;
@@ -2293,11 +2291,11 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("fcvtlt_z_p_z_h2s"):
+ case "fcvtlt_z_p_z_h2s"_h:
ext(kFormatVnB, result, zn, zn, kHRegSizeInBytes);
fcvt(kFormatVnS, kFormatVnH, zd, pg, result);
break;
- case Hash("fcvtlt_z_p_z_s2d"):
+ case "fcvtlt_z_p_z_s2d"_h:
ext(kFormatVnB, result, zn, zn, kSRegSizeInBytes);
fcvt(kFormatVnD, kFormatVnS, zd, pg, result);
break;
@@ -2318,10 +2316,10 @@
}
switch (form_hash_) {
- case Hash("urecpe_z_p_z"):
+ case "urecpe_z_p_z"_h:
urecpe(vform, result, zn);
break;
- case Hash("ursqrte_z_p_z"):
+ case "ursqrte_z_p_z"_h:
ursqrte(vform, result, zn);
break;
default:
@@ -2338,14 +2336,14 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("flogb_z_p_z"):
+ case "flogb_z_p_z"_h:
vform = instr->GetSVEVectorFormat(17);
flogb(vform, result, zn);
break;
- case Hash("sqabs_z_p_z"):
+ case "sqabs_z_p_z"_h:
abs(vform, result, zn).SignedSaturate(vform);
break;
- case Hash("sqneg_z_p_z"):
+ case "sqneg_z_p_z"_h:
neg(vform, result, zn).SignedSaturate(vform);
break;
default:
@@ -2362,7 +2360,7 @@
SimVRegister& zn = ReadVRegister(instr->GetRn());
SimVRegister result;
- VIXL_ASSERT(form_hash_ == Hash("histcnt_z_p_zz"));
+ VIXL_ASSERT(form_hash_ == "histcnt_z_p_zz"_h);
if ((vform == kFormatVnS) || (vform == kFormatVnD)) {
histogram(vform, result, pg, zn, zm);
mov_zeroing(vform, zd, pg, result);
@@ -2380,38 +2378,38 @@
bool do_bext = false;
switch (form_hash_) {
- case Hash("bdep_z_zz"):
+ case "bdep_z_zz"_h:
bdep(vform, zd, zn, zm);
break;
- case Hash("bext_z_zz"):
+ case "bext_z_zz"_h:
do_bext = true;
VIXL_FALLTHROUGH();
- case Hash("bgrp_z_zz"):
+ case "bgrp_z_zz"_h:
bgrp(vform, zd, zn, zm, do_bext);
break;
- case Hash("eorbt_z_zz"):
+ case "eorbt_z_zz"_h:
rotate_elements_right(vform, result, zm, 1);
SVEBitwiseLogicalUnpredicatedHelper(EOR, kFormatVnD, result, zn, result);
mov_alternating(vform, zd, result, 0);
break;
- case Hash("eortb_z_zz"):
+ case "eortb_z_zz"_h:
rotate_elements_right(vform, result, zm, -1);
SVEBitwiseLogicalUnpredicatedHelper(EOR, kFormatVnD, result, zn, result);
mov_alternating(vform, zd, result, 1);
break;
- case Hash("mul_z_zz"):
+ case "mul_z_zz"_h:
mul(vform, zd, zn, zm);
break;
- case Hash("smulh_z_zz"):
+ case "smulh_z_zz"_h:
smulh(vform, zd, zn, zm);
break;
- case Hash("sqdmulh_z_zz"):
+ case "sqdmulh_z_zz"_h:
sqdmulh(vform, zd, zn, zm);
break;
- case Hash("sqrdmulh_z_zz"):
+ case "sqrdmulh_z_zz"_h:
sqrdmulh(vform, zd, zn, zm);
break;
- case Hash("umulh_z_zz"):
+ case "umulh_z_zz"_h:
umulh(vform, zd, zn, zm);
break;
default:
@@ -2431,28 +2429,28 @@
pack_odd_elements(vform_half, zm_t, zm);
switch (form_hash_) {
- case Hash("saddwb_z_zz"):
+ case "saddwb_z_zz"_h:
saddw(vform, zd, zn, zm_b);
break;
- case Hash("saddwt_z_zz"):
+ case "saddwt_z_zz"_h:
saddw(vform, zd, zn, zm_t);
break;
- case Hash("ssubwb_z_zz"):
+ case "ssubwb_z_zz"_h:
ssubw(vform, zd, zn, zm_b);
break;
- case Hash("ssubwt_z_zz"):
+ case "ssubwt_z_zz"_h:
ssubw(vform, zd, zn, zm_t);
break;
- case Hash("uaddwb_z_zz"):
+ case "uaddwb_z_zz"_h:
uaddw(vform, zd, zn, zm_b);
break;
- case Hash("uaddwt_z_zz"):
+ case "uaddwt_z_zz"_h:
uaddw(vform, zd, zn, zm_t);
break;
- case Hash("usubwb_z_zz"):
+ case "usubwb_z_zz"_h:
usubw(vform, zd, zn, zm_b);
break;
- case Hash("usubwt_z_zz"):
+ case "usubwt_z_zz"_h:
usubw(vform, zd, zn, zm_t);
break;
default:
@@ -2473,13 +2471,13 @@
int shift_dist = shift_and_lane_size.first;
switch (form_hash_) {
- case Hash("sli_z_zzi"):
+ case "sli_z_zzi"_h:
// Shift distance is computed differently for left shifts. Convert the
// result.
shift_dist = (8 << lane_size) - shift_dist;
sli(vform, zd, zn, shift_dist);
break;
- case Hash("sri_z_zzi"):
+ case "sri_z_zzi"_h:
sri(vform, zd, zn, shift_dist);
break;
default:
@@ -2502,70 +2500,70 @@
bool top = false;
switch (form_hash_) {
- case Hash("sqxtnt_z_zz"):
+ case "sqxtnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqxtnb_z_zz"):
+ case "sqxtnb_z_zz"_h:
sqxtn(vform, result, zn);
break;
- case Hash("sqxtunt_z_zz"):
+ case "sqxtunt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqxtunb_z_zz"):
+ case "sqxtunb_z_zz"_h:
sqxtun(vform, result, zn);
break;
- case Hash("uqxtnt_z_zz"):
+ case "uqxtnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("uqxtnb_z_zz"):
+ case "uqxtnb_z_zz"_h:
uqxtn(vform, result, zn);
break;
- case Hash("rshrnt_z_zi"):
+ case "rshrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("rshrnb_z_zi"):
+ case "rshrnb_z_zi"_h:
rshrn(vform, result, zn, right_shift_dist);
break;
- case Hash("shrnt_z_zi"):
+ case "shrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("shrnb_z_zi"):
+ case "shrnb_z_zi"_h:
shrn(vform, result, zn, right_shift_dist);
break;
- case Hash("sqrshrnt_z_zi"):
+ case "sqrshrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqrshrnb_z_zi"):
+ case "sqrshrnb_z_zi"_h:
sqrshrn(vform, result, zn, right_shift_dist);
break;
- case Hash("sqrshrunt_z_zi"):
+ case "sqrshrunt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqrshrunb_z_zi"):
+ case "sqrshrunb_z_zi"_h:
sqrshrun(vform, result, zn, right_shift_dist);
break;
- case Hash("sqshrnt_z_zi"):
+ case "sqshrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqshrnb_z_zi"):
+ case "sqshrnb_z_zi"_h:
sqshrn(vform, result, zn, right_shift_dist);
break;
- case Hash("sqshrunt_z_zi"):
+ case "sqshrunt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("sqshrunb_z_zi"):
+ case "sqshrunb_z_zi"_h:
sqshrun(vform, result, zn, right_shift_dist);
break;
- case Hash("uqrshrnt_z_zi"):
+ case "uqrshrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("uqrshrnb_z_zi"):
+ case "uqrshrnb_z_zi"_h:
uqrshrn(vform, result, zn, right_shift_dist);
break;
- case Hash("uqshrnt_z_zi"):
+ case "uqshrnt_z_zi"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("uqshrnb_z_zi"):
+ case "uqshrnb_z_zi"_h:
uqshrn(vform, result, zn, right_shift_dist);
break;
default:
@@ -2600,61 +2598,61 @@
pack_odd_elements(vform_half, zm_t, zm);
switch (form_hash_) {
- case Hash("sabdlb_z_zz"):
+ case "sabdlb_z_zz"_h:
sabdl(vform, zd, zn_b, zm_b);
break;
- case Hash("sabdlt_z_zz"):
+ case "sabdlt_z_zz"_h:
sabdl(vform, zd, zn_t, zm_t);
break;
- case Hash("saddlb_z_zz"):
+ case "saddlb_z_zz"_h:
saddl(vform, zd, zn_b, zm_b);
break;
- case Hash("saddlbt_z_zz"):
+ case "saddlbt_z_zz"_h:
saddl(vform, zd, zn_b, zm_t);
break;
- case Hash("saddlt_z_zz"):
+ case "saddlt_z_zz"_h:
saddl(vform, zd, zn_t, zm_t);
break;
- case Hash("ssublb_z_zz"):
+ case "ssublb_z_zz"_h:
ssubl(vform, zd, zn_b, zm_b);
break;
- case Hash("ssublbt_z_zz"):
+ case "ssublbt_z_zz"_h:
ssubl(vform, zd, zn_b, zm_t);
break;
- case Hash("ssublt_z_zz"):
+ case "ssublt_z_zz"_h:
ssubl(vform, zd, zn_t, zm_t);
break;
- case Hash("ssubltb_z_zz"):
+ case "ssubltb_z_zz"_h:
ssubl(vform, zd, zn_t, zm_b);
break;
- case Hash("uabdlb_z_zz"):
+ case "uabdlb_z_zz"_h:
uabdl(vform, zd, zn_b, zm_b);
break;
- case Hash("uabdlt_z_zz"):
+ case "uabdlt_z_zz"_h:
uabdl(vform, zd, zn_t, zm_t);
break;
- case Hash("uaddlb_z_zz"):
+ case "uaddlb_z_zz"_h:
uaddl(vform, zd, zn_b, zm_b);
break;
- case Hash("uaddlt_z_zz"):
+ case "uaddlt_z_zz"_h:
uaddl(vform, zd, zn_t, zm_t);
break;
- case Hash("usublb_z_zz"):
+ case "usublb_z_zz"_h:
usubl(vform, zd, zn_b, zm_b);
break;
- case Hash("usublt_z_zz"):
+ case "usublt_z_zz"_h:
usubl(vform, zd, zn_t, zm_t);
break;
- case Hash("sabalb_z_zzz"):
+ case "sabalb_z_zzz"_h:
sabal(vform, zd, zn_b, zm_b);
break;
- case Hash("sabalt_z_zzz"):
+ case "sabalt_z_zzz"_h:
sabal(vform, zd, zn_t, zm_t);
break;
- case Hash("uabalb_z_zzz"):
+ case "uabalb_z_zzz"_h:
uabal(vform, zd, zn_b, zm_b);
break;
- case Hash("uabalt_z_zzz"):
+ case "uabalt_z_zzz"_h:
uabal(vform, zd, zn_t, zm_t);
break;
default:
@@ -2675,36 +2673,36 @@
pack_odd_elements(vform_half, zm_t, zm);
switch (form_hash_) {
- case Hash("pmullb_z_zz"):
+ case "pmullb_z_zz"_h:
// '00' is reserved for Q-sized lane.
if (vform == kFormatVnB) {
VIXL_UNIMPLEMENTED();
}
pmull(vform, zd, zn_b, zm_b);
break;
- case Hash("pmullt_z_zz"):
+ case "pmullt_z_zz"_h:
// '00' is reserved for Q-sized lane.
if (vform == kFormatVnB) {
VIXL_UNIMPLEMENTED();
}
pmull(vform, zd, zn_t, zm_t);
break;
- case Hash("smullb_z_zz"):
+ case "smullb_z_zz"_h:
smull(vform, zd, zn_b, zm_b);
break;
- case Hash("smullt_z_zz"):
+ case "smullt_z_zz"_h:
smull(vform, zd, zn_t, zm_t);
break;
- case Hash("sqdmullb_z_zz"):
+ case "sqdmullb_z_zz"_h:
sqdmull(vform, zd, zn_b, zm_b);
break;
- case Hash("sqdmullt_z_zz"):
+ case "sqdmullt_z_zz"_h:
sqdmull(vform, zd, zn_t, zm_t);
break;
- case Hash("umullb_z_zz"):
+ case "umullb_z_zz"_h:
umull(vform, zd, zn_b, zm_b);
break;
- case Hash("umullt_z_zz"):
+ case "umullt_z_zz"_h:
umull(vform, zd, zn_t, zm_t);
break;
default:
@@ -2726,28 +2724,28 @@
VectorFormat vform = VectorFormatHalfWidth(vform_src);
switch (form_hash_) {
- case Hash("addhnt_z_zz"):
+ case "addhnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("addhnb_z_zz"):
+ case "addhnb_z_zz"_h:
addhn(vform, result, zn, zm);
break;
- case Hash("raddhnt_z_zz"):
+ case "raddhnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("raddhnb_z_zz"):
+ case "raddhnb_z_zz"_h:
raddhn(vform, result, zn, zm);
break;
- case Hash("rsubhnt_z_zz"):
+ case "rsubhnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("rsubhnb_z_zz"):
+ case "rsubhnb_z_zz"_h:
rsubhn(vform, result, zn, zm);
break;
- case Hash("subhnt_z_zz"):
+ case "subhnt_z_zz"_h:
top = true;
VIXL_FALLTHROUGH();
- case Hash("subhnb_z_zz"):
+ case "subhnb_z_zz"_h:
subhn(vform, result, zn, zm);
break;
default:
@@ -2787,16 +2785,16 @@
pack_odd_elements(vform_half, zn_t, zn);
switch (form_hash_) {
- case Hash("sshllb_z_zi"):
+ case "sshllb_z_zi"_h:
sshll(vform, zd, zn_b, left_shift_dist);
break;
- case Hash("sshllt_z_zi"):
+ case "sshllt_z_zi"_h:
sshll(vform, zd, zn_t, left_shift_dist);
break;
- case Hash("ushllb_z_zi"):
+ case "ushllb_z_zi"_h:
ushll(vform, zd, zn_b, left_shift_dist);
break;
- case Hash("ushllt_z_zi"):
+ case "ushllt_z_zi"_h:
ushll(vform, zd, zn_t, left_shift_dist);
break;
default:
@@ -2813,32 +2811,32 @@
bool is_mla = false;
switch (form_hash_) {
- case Hash("sqrdmlah_z_zzz"):
+ case "sqrdmlah_z_zzz"_h:
is_mla = true;
VIXL_FALLTHROUGH();
- case Hash("sqrdmlsh_z_zzz"):
+ case "sqrdmlsh_z_zzz"_h:
// Nothing to do.
break;
- case Hash("sqrdmlah_z_zzzi_h"):
+ case "sqrdmlah_z_zzzi_h"_h:
is_mla = true;
VIXL_FALLTHROUGH();
- case Hash("sqrdmlsh_z_zzzi_h"):
+ case "sqrdmlsh_z_zzzi_h"_h:
vform = kFormatVnH;
index = (instr->ExtractBit(22) << 2) | instr->ExtractBits(20, 19);
zm_code = instr->ExtractBits(18, 16);
break;
- case Hash("sqrdmlah_z_zzzi_s"):
+ case "sqrdmlah_z_zzzi_s"_h:
is_mla = true;
VIXL_FALLTHROUGH();
- case Hash("sqrdmlsh_z_zzzi_s"):
+ case "sqrdmlsh_z_zzzi_s"_h:
vform = kFormatVnS;
index = instr->ExtractBits(20, 19);
zm_code = instr->ExtractBits(18, 16);
break;
- case Hash("sqrdmlah_z_zzzi_d"):
+ case "sqrdmlah_z_zzzi_d"_h:
is_mla = true;
VIXL_FALLTHROUGH();
- case Hash("sqrdmlsh_z_zzzi_d"):
+ case "sqrdmlsh_z_zzzi_d"_h:
vform = kFormatVnD;
index = instr->ExtractBit(20);
zm_code = instr->ExtractBits(19, 16);
@@ -2873,16 +2871,16 @@
pack_odd_elements(kFormatVnS, zn_t, zn);
switch (form_hash_) {
- case Hash("sqdmlalb_z_zzzi_d"):
+ case "sqdmlalb_z_zzzi_d"_h:
sqdmlal(kFormatVnD, zda, zn_b, zm_idx);
break;
- case Hash("sqdmlalt_z_zzzi_d"):
+ case "sqdmlalt_z_zzzi_d"_h:
sqdmlal(kFormatVnD, zda, zn_t, zm_idx);
break;
- case Hash("sqdmlslb_z_zzzi_d"):
+ case "sqdmlslb_z_zzzi_d"_h:
sqdmlsl(kFormatVnD, zda, zn_b, zm_idx);
break;
- case Hash("sqdmlslt_z_zzzi_d"):
+ case "sqdmlslt_z_zzzi_d"_h:
sqdmlsl(kFormatVnD, zda, zn_t, zm_idx);
break;
default:
@@ -2902,16 +2900,16 @@
pack_odd_elements(kFormatVnH, zm_t, zm);
switch (form_hash_) {
- case Hash("fmlalb_z_zzz"):
+ case "fmlalb_z_zzz"_h:
fmlal(kFormatVnS, zda, zn_b, zm_b);
break;
- case Hash("fmlalt_z_zzz"):
+ case "fmlalt_z_zzz"_h:
fmlal(kFormatVnS, zda, zn_t, zm_t);
break;
- case Hash("fmlslb_z_zzz"):
+ case "fmlslb_z_zzz"_h:
fmlsl(kFormatVnS, zda, zn_b, zm_b);
break;
- case Hash("fmlslt_z_zzz"):
+ case "fmlslt_z_zzz"_h:
fmlsl(kFormatVnS, zda, zn_t, zm_t);
break;
default:
@@ -2932,28 +2930,28 @@
pack_odd_elements(kFormatVnH, zn_t, zn);
switch (form_hash_) {
- case Hash("fmlalb_z_zzzi_s"):
+ case "fmlalb_z_zzzi_s"_h:
fmlal(kFormatVnS, zda, zn_b, zm_idx);
break;
- case Hash("fmlalt_z_zzzi_s"):
+ case "fmlalt_z_zzzi_s"_h:
fmlal(kFormatVnS, zda, zn_t, zm_idx);
break;
- case Hash("fmlslb_z_zzzi_s"):
+ case "fmlslb_z_zzzi_s"_h:
fmlsl(kFormatVnS, zda, zn_b, zm_idx);
break;
- case Hash("fmlslt_z_zzzi_s"):
+ case "fmlslt_z_zzzi_s"_h:
fmlsl(kFormatVnS, zda, zn_t, zm_idx);
break;
- case Hash("sqdmlalb_z_zzzi_s"):
+ case "sqdmlalb_z_zzzi_s"_h:
sqdmlal(kFormatVnS, zda, zn_b, zm_idx);
break;
- case Hash("sqdmlalt_z_zzzi_s"):
+ case "sqdmlalt_z_zzzi_s"_h:
sqdmlal(kFormatVnS, zda, zn_t, zm_idx);
break;
- case Hash("sqdmlslb_z_zzzi_s"):
+ case "sqdmlslb_z_zzzi_s"_h:
sqdmlsl(kFormatVnS, zda, zn_b, zm_idx);
break;
- case Hash("sqdmlslt_z_zzzi_s"):
+ case "sqdmlslt_z_zzzi_s"_h:
sqdmlsl(kFormatVnS, zda, zn_t, zm_idx);
break;
default:
@@ -2969,10 +2967,10 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("sadalp_z_p_z"):
+ case "sadalp_z_p_z"_h:
sadalp(vform, result, zn);
break;
- case Hash("uadalp_z_p_z"):
+ case "uadalp_z_p_z"_h:
uadalp(vform, result, zn);
break;
default:
@@ -2991,16 +2989,16 @@
not_(vform, not_zn, zn);
switch (form_hash_) {
- case Hash("adclb_z_zzz"):
+ case "adclb_z_zzz"_h:
adcl(vform, zda, zn, zm, /* top = */ false);
break;
- case Hash("adclt_z_zzz"):
+ case "adclt_z_zzz"_h:
adcl(vform, zda, zn, zm, /* top = */ true);
break;
- case Hash("sbclb_z_zzz"):
+ case "sbclb_z_zzz"_h:
adcl(vform, zda, not_zn, zm, /* top = */ false);
break;
- case Hash("sbclt_z_zzz"):
+ case "sbclt_z_zzz"_h:
adcl(vform, zda, not_zn, zm, /* top = */ true);
break;
default:
@@ -3015,10 +3013,10 @@
SimVRegister& zn = ReadVRegister(instr->GetRn());
switch (form_hash_) {
- case Hash("saba_z_zzz"):
+ case "saba_z_zzz"_h:
saba(vform, zda, zn, zm);
break;
- case Hash("uaba_z_zzz"):
+ case "uaba_z_zzz"_h:
uaba(vform, zda, zn, zm);
break;
default:
@@ -3041,22 +3039,22 @@
int idx_s = instr->ExtractBit(20);
switch (form_hash_) {
- case Hash("cmla_z_zzz"):
+ case "cmla_z_zzz"_h:
cmla(vform, zda, zda, zn, zm, rot);
break;
- case Hash("cmla_z_zzzi_h"):
+ case "cmla_z_zzzi_h"_h:
cmla(kFormatVnH, zda, zda, zn, zm_h, idx_h, rot);
break;
- case Hash("cmla_z_zzzi_s"):
+ case "cmla_z_zzzi_s"_h:
cmla(kFormatVnS, zda, zda, zn, zm_s, idx_s, rot);
break;
- case Hash("sqrdcmlah_z_zzz"):
+ case "sqrdcmlah_z_zzz"_h:
sqrdcmlah(vform, zda, zda, zn, zm, rot);
break;
- case Hash("sqrdcmlah_z_zzzi_h"):
+ case "sqrdcmlah_z_zzzi_h"_h:
sqrdcmlah(kFormatVnH, zda, zda, zn, zm_h, idx_h, rot);
break;
- case Hash("sqrdcmlah_z_zzzi_s"):
+ case "sqrdcmlah_z_zzzi_s"_h:
sqrdcmlah(kFormatVnS, zda, zda, zn, zm_s, idx_s, rot);
break;
default:
@@ -3077,16 +3075,16 @@
int shift_dist = shift_and_lane_size.first;
switch (form_hash_) {
- case Hash("srsra_z_zi"):
+ case "srsra_z_zi"_h:
srsra(vform, zd, zn, shift_dist);
break;
- case Hash("ssra_z_zi"):
+ case "ssra_z_zi"_h:
ssra(vform, zd, zn, shift_dist);
break;
- case Hash("ursra_z_zi"):
+ case "ursra_z_zi"_h:
ursra(vform, zd, zn, shift_dist);
break;
- case Hash("usra_z_zi"):
+ case "usra_z_zi"_h:
usra(vform, zd, zn, shift_dist);
break;
default:
@@ -3110,46 +3108,46 @@
uzp2(vform_half, zm_t, zm, zero);
switch (form_hash_) {
- case Hash("smlalb_z_zzz"):
+ case "smlalb_z_zzz"_h:
smlal(vform, zda, zn_b, zm_b);
break;
- case Hash("smlalt_z_zzz"):
+ case "smlalt_z_zzz"_h:
smlal(vform, zda, zn_t, zm_t);
break;
- case Hash("smlslb_z_zzz"):
+ case "smlslb_z_zzz"_h:
smlsl(vform, zda, zn_b, zm_b);
break;
- case Hash("smlslt_z_zzz"):
+ case "smlslt_z_zzz"_h:
smlsl(vform, zda, zn_t, zm_t);
break;
- case Hash("sqdmlalb_z_zzz"):
+ case "sqdmlalb_z_zzz"_h:
sqdmlal(vform, zda, zn_b, zm_b);
break;
- case Hash("sqdmlalbt_z_zzz"):
+ case "sqdmlalbt_z_zzz"_h:
sqdmlal(vform, zda, zn_b, zm_t);
break;
- case Hash("sqdmlalt_z_zzz"):
+ case "sqdmlalt_z_zzz"_h:
sqdmlal(vform, zda, zn_t, zm_t);
break;
- case Hash("sqdmlslb_z_zzz"):
+ case "sqdmlslb_z_zzz"_h:
sqdmlsl(vform, zda, zn_b, zm_b);
break;
- case Hash("sqdmlslbt_z_zzz"):
+ case "sqdmlslbt_z_zzz"_h:
sqdmlsl(vform, zda, zn_b, zm_t);
break;
- case Hash("sqdmlslt_z_zzz"):
+ case "sqdmlslt_z_zzz"_h:
sqdmlsl(vform, zda, zn_t, zm_t);
break;
- case Hash("umlalb_z_zzz"):
+ case "umlalb_z_zzz"_h:
umlal(vform, zda, zn_b, zm_b);
break;
- case Hash("umlalt_z_zzz"):
+ case "umlalt_z_zzz"_h:
umlal(vform, zda, zn_t, zm_t);
break;
- case Hash("umlslb_z_zzz"):
+ case "umlslb_z_zzz"_h:
umlsl(vform, zda, zn_b, zm_b);
break;
- case Hash("umlslt_z_zzz"):
+ case "umlslt_z_zzz"_h:
umlsl(vform, zda, zn_t, zm_t);
break;
default:
@@ -3166,14 +3164,14 @@
int index = -1;
switch (form_hash_) {
- case Hash("cdot_z_zzz"):
+ case "cdot_z_zzz"_h:
// Nothing to do.
break;
- case Hash("cdot_z_zzzi_s"):
+ case "cdot_z_zzzi_s"_h:
index = zm_code >> 3;
zm_code &= 0x7;
break;
- case Hash("cdot_z_zzzi_d"):
+ case "cdot_z_zzzi_d"_h:
index = zm_code >> 4;
zm_code &= 0xf;
break;
@@ -3195,26 +3193,26 @@
SimVRegister temp;
switch (form_hash_) {
- case Hash("bcax_z_zzz"):
+ case "bcax_z_zzz"_h:
bic(vform, temp, zm, zk);
eor(vform, zdn, temp, zdn);
break;
- case Hash("bsl1n_z_zzz"):
+ case "bsl1n_z_zzz"_h:
not_(vform, temp, zdn);
bsl(vform, zdn, zk, temp, zm);
break;
- case Hash("bsl2n_z_zzz"):
+ case "bsl2n_z_zzz"_h:
not_(vform, temp, zm);
bsl(vform, zdn, zk, zdn, temp);
break;
- case Hash("bsl_z_zzz"):
+ case "bsl_z_zzz"_h:
bsl(vform, zdn, zk, zdn, zm);
break;
- case Hash("eor3_z_zzz"):
+ case "eor3_z_zzz"_h:
eor(vform, temp, zdn, zm);
eor(vform, zdn, temp, zk);
break;
- case Hash("nbsl_z_zzz"):
+ case "nbsl_z_zzz"_h:
bsl(vform, zdn, zk, zdn, zm);
not_(vform, zdn, zdn);
break;
@@ -3231,28 +3229,28 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("shadd_z_p_zz"):
+ case "shadd_z_p_zz"_h:
add(vform, result, zdn, zm).Halve(vform);
break;
- case Hash("shsub_z_p_zz"):
+ case "shsub_z_p_zz"_h:
sub(vform, result, zdn, zm).Halve(vform);
break;
- case Hash("shsubr_z_p_zz"):
+ case "shsubr_z_p_zz"_h:
sub(vform, result, zm, zdn).Halve(vform);
break;
- case Hash("srhadd_z_p_zz"):
+ case "srhadd_z_p_zz"_h:
add(vform, result, zdn, zm).Halve(vform).Round(vform);
break;
- case Hash("uhadd_z_p_zz"):
+ case "uhadd_z_p_zz"_h:
add(vform, result, zdn, zm).Uhalve(vform);
break;
- case Hash("uhsub_z_p_zz"):
+ case "uhsub_z_p_zz"_h:
sub(vform, result, zdn, zm).Uhalve(vform);
break;
- case Hash("uhsubr_z_p_zz"):
+ case "uhsubr_z_p_zz"_h:
sub(vform, result, zm, zdn).Uhalve(vform);
break;
- case Hash("urhadd_z_p_zz"):
+ case "urhadd_z_p_zz"_h:
add(vform, result, zdn, zm).Uhalve(vform).Round(vform);
break;
default:
@@ -3270,28 +3268,28 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("sqadd_z_p_zz"):
+ case "sqadd_z_p_zz"_h:
add(vform, result, zdn, zm).SignedSaturate(vform);
break;
- case Hash("sqsub_z_p_zz"):
+ case "sqsub_z_p_zz"_h:
sub(vform, result, zdn, zm).SignedSaturate(vform);
break;
- case Hash("sqsubr_z_p_zz"):
+ case "sqsubr_z_p_zz"_h:
sub(vform, result, zm, zdn).SignedSaturate(vform);
break;
- case Hash("suqadd_z_p_zz"):
+ case "suqadd_z_p_zz"_h:
suqadd(vform, result, zdn, zm);
break;
- case Hash("uqadd_z_p_zz"):
+ case "uqadd_z_p_zz"_h:
add(vform, result, zdn, zm).UnsignedSaturate(vform);
break;
- case Hash("uqsub_z_p_zz"):
+ case "uqsub_z_p_zz"_h:
sub(vform, result, zdn, zm).UnsignedSaturate(vform);
break;
- case Hash("uqsubr_z_p_zz"):
+ case "uqsubr_z_p_zz"_h:
sub(vform, result, zm, zdn).UnsignedSaturate(vform);
break;
- case Hash("usqadd_z_p_zz"):
+ case "usqadd_z_p_zz"_h:
usqadd(vform, result, zdn, zm);
break;
default:
@@ -3309,19 +3307,19 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("addp_z_p_zz"):
+ case "addp_z_p_zz"_h:
addp(vform, result, zdn, zm);
break;
- case Hash("smaxp_z_p_zz"):
+ case "smaxp_z_p_zz"_h:
smaxp(vform, result, zdn, zm);
break;
- case Hash("sminp_z_p_zz"):
+ case "sminp_z_p_zz"_h:
sminp(vform, result, zdn, zm);
break;
- case Hash("umaxp_z_p_zz"):
+ case "umaxp_z_p_zz"_h:
umaxp(vform, result, zdn, zm);
break;
- case Hash("uminp_z_p_zz"):
+ case "uminp_z_p_zz"_h:
uminp(vform, result, zdn, zm);
break;
default:
@@ -3339,19 +3337,19 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("faddp_z_p_zz"):
+ case "faddp_z_p_zz"_h:
faddp(vform, result, zdn, zm);
break;
- case Hash("fmaxnmp_z_p_zz"):
+ case "fmaxnmp_z_p_zz"_h:
fmaxnmp(vform, result, zdn, zm);
break;
- case Hash("fmaxp_z_p_zz"):
+ case "fmaxp_z_p_zz"_h:
fmaxp(vform, result, zdn, zm);
break;
- case Hash("fminnmp_z_p_zz"):
+ case "fminnmp_z_p_zz"_h:
fminnmp(vform, result, zdn, zm);
break;
- case Hash("fminp_z_p_zz"):
+ case "fminp_z_p_zz"_h:
fminp(vform, result, zdn, zm);
break;
default:
@@ -3373,19 +3371,19 @@
SimVRegister result;
switch (form_hash_) {
- case Hash("sqshl_z_p_zi"):
+ case "sqshl_z_p_zi"_h:
sqshl(vform, result, zdn, left_shift_dist);
break;
- case Hash("sqshlu_z_p_zi"):
+ case "sqshlu_z_p_zi"_h:
sqshlu(vform, result, zdn, left_shift_dist);
break;
- case Hash("srshr_z_p_zi"):
+ case "srshr_z_p_zi"_h:
sshr(vform, result, zdn, right_shift_dist).Round(vform);
break;
- case Hash("uqshl_z_p_zi"):
+ case "uqshl_z_p_zi"_h:
uqshl(vform, result, zdn, left_shift_dist);
break;
- case Hash("urshr_z_p_zi"):
+ case "urshr_z_p_zi"_h:
ushr(vform, result, zdn, right_shift_dist).Round(vform);
break;
default:
@@ -3395,7 +3393,7 @@
}
void Simulator::SimulateSVEExclusiveOrRotate(const Instruction* instr) {
- VIXL_ASSERT(form_hash_ == Hash("xar_z_zzi"));
+ VIXL_ASSERT(form_hash_ == "xar_z_zzi"_h);
SimVRegister& zdn = ReadVRegister(instr->GetRd());
SimVRegister& zm = ReadVRegister(instr->GetRn());
@@ -3417,10 +3415,10 @@
int rot = (instr->ExtractBit(10) == 0) ? 90 : 270;
switch (form_hash_) {
- case Hash("cadd_z_zz"):
+ case "cadd_z_zz"_h:
cadd(vform, zdn, zdn, zm, rot);
break;
- case Hash("sqcadd_z_zz"):
+ case "sqcadd_z_zz"_h:
cadd(vform, zdn, zdn, zm, rot, /* saturate = */ true);
break;
default:
@@ -3438,28 +3436,28 @@
bool is_signed = false;
switch (form_hash_) {
- case Hash("ldnt1b_z_p_ar_d_64_unscaled"):
+ case "ldnt1b_z_p_ar_d_64_unscaled"_h:
msize = 0;
break;
- case Hash("ldnt1d_z_p_ar_d_64_unscaled"):
+ case "ldnt1d_z_p_ar_d_64_unscaled"_h:
msize = 3;
break;
- case Hash("ldnt1h_z_p_ar_d_64_unscaled"):
+ case "ldnt1h_z_p_ar_d_64_unscaled"_h:
msize = 1;
break;
- case Hash("ldnt1sb_z_p_ar_d_64_unscaled"):
+ case "ldnt1sb_z_p_ar_d_64_unscaled"_h:
msize = 0;
is_signed = true;
break;
- case Hash("ldnt1sh_z_p_ar_d_64_unscaled"):
+ case "ldnt1sh_z_p_ar_d_64_unscaled"_h:
msize = 1;
is_signed = true;
break;
- case Hash("ldnt1sw_z_p_ar_d_64_unscaled"):
+ case "ldnt1sw_z_p_ar_d_64_unscaled"_h:
msize = 2;
is_signed = true;
break;
- case Hash("ldnt1w_z_p_ar_d_64_unscaled"):
+ case "ldnt1w_z_p_ar_d_64_unscaled"_h:
msize = 2;
break;
default:
@@ -3475,10 +3473,10 @@
uint64_t xm = ReadXRegister(instr->GetRm());
LogicSVEAddressVector addr(xm, &zn, kFormatVnD);
- VIXL_ASSERT((form_hash_ == Hash("stnt1b_z_p_ar_d_64_unscaled")) ||
- (form_hash_ == Hash("stnt1d_z_p_ar_d_64_unscaled")) ||
- (form_hash_ == Hash("stnt1h_z_p_ar_d_64_unscaled")) ||
- (form_hash_ == Hash("stnt1w_z_p_ar_d_64_unscaled")));
+ VIXL_ASSERT((form_hash_ == "stnt1b_z_p_ar_d_64_unscaled"_h) ||
+ (form_hash_ == "stnt1d_z_p_ar_d_64_unscaled"_h) ||
+ (form_hash_ == "stnt1h_z_p_ar_d_64_unscaled"_h) ||
+ (form_hash_ == "stnt1w_z_p_ar_d_64_unscaled"_h));
addr.SetMsizeInBytesLog2(
instr->GetSVEMsizeFromDtype(/* is_signed = */ false));
@@ -3495,21 +3493,21 @@
bool is_signed = false;
switch (form_hash_) {
- case Hash("ldnt1b_z_p_ar_s_x32_unscaled"):
+ case "ldnt1b_z_p_ar_s_x32_unscaled"_h:
msize = 0;
break;
- case Hash("ldnt1h_z_p_ar_s_x32_unscaled"):
+ case "ldnt1h_z_p_ar_s_x32_unscaled"_h:
msize = 1;
break;
- case Hash("ldnt1sb_z_p_ar_s_x32_unscaled"):
+ case "ldnt1sb_z_p_ar_s_x32_unscaled"_h:
msize = 0;
is_signed = true;
break;
- case Hash("ldnt1sh_z_p_ar_s_x32_unscaled"):
+ case "ldnt1sh_z_p_ar_s_x32_unscaled"_h:
msize = 1;
is_signed = true;
break;
- case Hash("ldnt1w_z_p_ar_s_x32_unscaled"):
+ case "ldnt1w_z_p_ar_s_x32_unscaled"_h:
msize = 2;
break;
default:
@@ -3525,9 +3523,9 @@
uint64_t xm = ReadXRegister(instr->GetRm());
LogicSVEAddressVector addr(xm, &zn, kFormatVnS);
- VIXL_ASSERT((form_hash_ == Hash("stnt1b_z_p_ar_s_x32_unscaled")) ||
- (form_hash_ == Hash("stnt1h_z_p_ar_s_x32_unscaled")) ||
- (form_hash_ == Hash("stnt1w_z_p_ar_s_x32_unscaled")));
+ VIXL_ASSERT((form_hash_ == "stnt1b_z_p_ar_s_x32_unscaled"_h) ||
+ (form_hash_ == "stnt1h_z_p_ar_s_x32_unscaled"_h) ||
+ (form_hash_ == "stnt1w_z_p_ar_s_x32_unscaled"_h));
addr.SetMsizeInBytesLog2(
instr->GetSVEMsizeFromDtype(/* is_signed = */ false));
@@ -7405,27 +7403,27 @@
VectorFormat vf = nfd.GetVectorFormat();
switch (form_hash_) {
- case Hash("fcmla_asimdsame2_c"):
+ case "fcmla_asimdsame2_c"_h:
rot = instr->GetImmRotFcmlaVec();
fcmla(vf, rd, rn, rm, rd, rot);
break;
- case Hash("fcadd_asimdsame2_c"):
+ case "fcadd_asimdsame2_c"_h:
rot = instr->GetImmRotFcadd();
fcadd(vf, rd, rn, rm, rot);
break;
- case Hash("sdot_asimdsame2_d"):
+ case "sdot_asimdsame2_d"_h:
sdot(vf, rd, rn, rm);
break;
- case Hash("udot_asimdsame2_d"):
+ case "udot_asimdsame2_d"_h:
udot(vf, rd, rn, rm);
break;
- case Hash("usdot_asimdsame2_d"):
+ case "usdot_asimdsame2_d"_h:
usdot(vf, rd, rn, rm);
break;
- case Hash("sqrdmlah_asimdsame2_only"):
+ case "sqrdmlah_asimdsame2_only"_h:
sqrdmlah(vf, rd, rn, rm);
break;
- case Hash("sqrdmlsh_asimdsame2_only"):
+ case "sqrdmlsh_asimdsame2_only"_h:
sqrdmlsh(vf, rd, rn, rm);
break;
}
@@ -7704,31 +7702,31 @@
bool is_2 = instr->Mask(NEON_Q) ? true : false;
switch (form_hash_) {
- case Hash("smull_asimdelem_l"):
+ case "smull_asimdelem_l"_h:
smull(vf, rd, rn, temp, is_2);
break;
- case Hash("umull_asimdelem_l"):
+ case "umull_asimdelem_l"_h:
umull(vf, rd, rn, temp, is_2);
break;
- case Hash("smlal_asimdelem_l"):
+ case "smlal_asimdelem_l"_h:
smlal(vf, rd, rn, temp, is_2);
break;
- case Hash("umlal_asimdelem_l"):
+ case "umlal_asimdelem_l"_h:
umlal(vf, rd, rn, temp, is_2);
break;
- case Hash("smlsl_asimdelem_l"):
+ case "smlsl_asimdelem_l"_h:
smlsl(vf, rd, rn, temp, is_2);
break;
- case Hash("umlsl_asimdelem_l"):
+ case "umlsl_asimdelem_l"_h:
umlsl(vf, rd, rn, temp, is_2);
break;
- case Hash("sqdmull_asimdelem_l"):
+ case "sqdmull_asimdelem_l"_h:
sqdmull(vf, rd, rn, temp, is_2);
break;
- case Hash("sqdmlal_asimdelem_l"):
+ case "sqdmlal_asimdelem_l"_h:
sqdmlal(vf, rd, rn, temp, is_2);
break;
- case Hash("sqdmlsl_asimdelem_l"):
+ case "sqdmlsl_asimdelem_l"_h:
sqdmlsl(vf, rd, rn, temp, is_2);
break;
default:
@@ -7746,16 +7744,16 @@
(instr->GetNEONH() << 2) | (instr->GetNEONL() << 1) | instr->GetNEONM();
switch (form_hash_) {
- case Hash("fmlal_asimdelem_lh"):
+ case "fmlal_asimdelem_lh"_h:
fmlal(vform, rd, rn, rm, index);
break;
- case Hash("fmlal2_asimdelem_lh"):
+ case "fmlal2_asimdelem_lh"_h:
fmlal2(vform, rd, rn, rm, index);
break;
- case Hash("fmlsl_asimdelem_lh"):
+ case "fmlsl_asimdelem_lh"_h:
fmlsl(vform, rd, rn, rm, index);
break;
- case Hash("fmlsl2_asimdelem_lh"):
+ case "fmlsl2_asimdelem_lh"_h:
fmlsl2(vform, rd, rn, rm, index);
break;
default:
@@ -7790,20 +7788,20 @@
SimVRegister& rm = ReadVRegister(rm_reg);
switch (form_hash_) {
- case Hash("fmul_asimdelem_rh_h"):
- case Hash("fmul_asimdelem_r_sd"):
+ case "fmul_asimdelem_rh_h"_h:
+ case "fmul_asimdelem_r_sd"_h:
fmul(vform, rd, rn, rm, index);
break;
- case Hash("fmla_asimdelem_rh_h"):
- case Hash("fmla_asimdelem_r_sd"):
+ case "fmla_asimdelem_rh_h"_h:
+ case "fmla_asimdelem_r_sd"_h:
fmla(vform, rd, rn, rm, index);
break;
- case Hash("fmls_asimdelem_rh_h"):
- case Hash("fmls_asimdelem_r_sd"):
+ case "fmls_asimdelem_rh_h"_h:
+ case "fmls_asimdelem_r_sd"_h:
fmls(vform, rd, rn, rm, index);
break;
- case Hash("fmulx_asimdelem_rh_h"):
- case Hash("fmulx_asimdelem_r_sd"):
+ case "fmulx_asimdelem_rh_h"_h:
+ case "fmulx_asimdelem_r_sd"_h:
fmulx(vform, rd, rn, rm, index);
break;
default:
@@ -7819,11 +7817,11 @@
int index = (instr->GetNEONH() << 1) | instr->GetNEONL();
switch (form_hash_) {
- case Hash("fcmla_asimdelem_c_s"):
+ case "fcmla_asimdelem_c_s"_h:
vform = kFormat4S;
index >>= 1;
VIXL_FALLTHROUGH();
- case Hash("fcmla_asimdelem_c_h"):
+ case "fcmla_asimdelem_c_h"_h:
fcmla(vform, rd, rn, rm, index, instr->GetImmRotFcmlaSca());
break;
default:
@@ -7845,16 +7843,16 @@
dup_elements_to_segments(VectorFormatFillQ(vform), temp, rm, index);
switch (form_hash_) {
- case Hash("sdot_asimdelem_d"):
+ case "sdot_asimdelem_d"_h:
sdot(vform, rd, rn, temp);
break;
- case Hash("udot_asimdelem_d"):
+ case "udot_asimdelem_d"_h:
udot(vform, rd, rn, temp);
break;
- case Hash("sudot_asimdelem_d"):
+ case "sudot_asimdelem_d"_h:
usdot(vform, rd, temp, rn);
break;
- case Hash("usdot_asimdelem_d"):
+ case "usdot_asimdelem_d"_h:
usdot(vform, rd, rn, temp);
break;
}
@@ -7878,25 +7876,25 @@
SimVRegister& rm = ReadVRegister(rm_reg);
switch (form_hash_) {
- case Hash("mul_asimdelem_r"):
+ case "mul_asimdelem_r"_h:
mul(vform, rd, rn, rm, index);
break;
- case Hash("mla_asimdelem_r"):
+ case "mla_asimdelem_r"_h:
mla(vform, rd, rn, rm, index);
break;
- case Hash("mls_asimdelem_r"):
+ case "mls_asimdelem_r"_h:
mls(vform, rd, rn, rm, index);
break;
- case Hash("sqdmulh_asimdelem_r"):
+ case "sqdmulh_asimdelem_r"_h:
sqdmulh(vform, rd, rn, rm, index);
break;
- case Hash("sqrdmulh_asimdelem_r"):
+ case "sqrdmulh_asimdelem_r"_h:
sqrdmulh(vform, rd, rn, rm, index);
break;
- case Hash("sqrdmlah_asimdelem_r"):
+ case "sqrdmlah_asimdelem_r"_h:
sqrdmlah(vform, rd, rn, rm, index);
break;
- case Hash("sqrdmlsh_asimdelem_r"):
+ case "sqrdmlsh_asimdelem_r"_h:
sqrdmlsh(vform, rd, rn, rm, index);
break;
}
@@ -9526,66 +9524,66 @@
bool shift_in_ls_byte = false;
switch (form_hash_) {
- case Hash("asrr_z_p_zz"):
+ case "asrr_z_p_zz"_h:
sshr(vform, result, zm, zdn);
break;
- case Hash("asr_z_p_zz"):
+ case "asr_z_p_zz"_h:
sshr(vform, result, zdn, zm);
break;
- case Hash("lslr_z_p_zz"):
+ case "lslr_z_p_zz"_h:
sshl(vform, result, zm, zdn, shift_in_ls_byte);
break;
- case Hash("lsl_z_p_zz"):
+ case "lsl_z_p_zz"_h:
sshl(vform, result, zdn, zm, shift_in_ls_byte);
break;
- case Hash("lsrr_z_p_zz"):
+ case "lsrr_z_p_zz"_h:
ushr(vform, result, zm, zdn);
break;
- case Hash("lsr_z_p_zz"):
+ case "lsr_z_p_zz"_h:
ushr(vform, result, zdn, zm);
break;
- case Hash("sqrshl_z_p_zz"):
+ case "sqrshl_z_p_zz"_h:
sshl(vform, result, zdn, zm, shift_in_ls_byte)
.Round(vform)
.SignedSaturate(vform);
break;
- case Hash("sqrshlr_z_p_zz"):
+ case "sqrshlr_z_p_zz"_h:
sshl(vform, result, zm, zdn, shift_in_ls_byte)
.Round(vform)
.SignedSaturate(vform);
break;
- case Hash("sqshl_z_p_zz"):
+ case "sqshl_z_p_zz"_h:
sshl(vform, result, zdn, zm, shift_in_ls_byte).SignedSaturate(vform);
break;
- case Hash("sqshlr_z_p_zz"):
+ case "sqshlr_z_p_zz"_h:
sshl(vform, result, zm, zdn, shift_in_ls_byte).SignedSaturate(vform);
break;
- case Hash("srshl_z_p_zz"):
+ case "srshl_z_p_zz"_h:
sshl(vform, result, zdn, zm, shift_in_ls_byte).Round(vform);
break;
- case Hash("srshlr_z_p_zz"):
+ case "srshlr_z_p_zz"_h:
sshl(vform, result, zm, zdn, shift_in_ls_byte).Round(vform);
break;
- case Hash("uqrshl_z_p_zz"):
+ case "uqrshl_z_p_zz"_h:
ushl(vform, result, zdn, zm, shift_in_ls_byte)
.Round(vform)
.UnsignedSaturate(vform);
break;
- case Hash("uqrshlr_z_p_zz"):
+ case "uqrshlr_z_p_zz"_h:
ushl(vform, result, zm, zdn, shift_in_ls_byte)
.Round(vform)
.UnsignedSaturate(vform);
break;
- case Hash("uqshl_z_p_zz"):
+ case "uqshl_z_p_zz"_h:
ushl(vform, result, zdn, zm, shift_in_ls_byte).UnsignedSaturate(vform);
break;
- case Hash("uqshlr_z_p_zz"):
+ case "uqshlr_z_p_zz"_h:
ushl(vform, result, zm, zdn, shift_in_ls_byte).UnsignedSaturate(vform);
break;
- case Hash("urshl_z_p_zz"):
+ case "urshl_z_p_zz"_h:
ushl(vform, result, zdn, zm, shift_in_ls_byte).Round(vform);
break;
- case Hash("urshlr_z_p_zz"):
+ case "urshlr_z_p_zz"_h:
ushl(vform, result, zm, zdn, shift_in_ls_byte).Round(vform);
break;
default:
@@ -11030,10 +11028,10 @@
int64_t ssrc2 = is_64_bit ? ReadXRegister(rm_code) : ReadWRegister(rm_code);
uint64_t usrc2 = ssrc2 & mask;
- bool reverse = (form_hash_ == Hash("whilege_p_p_rr")) ||
- (form_hash_ == Hash("whilegt_p_p_rr")) ||
- (form_hash_ == Hash("whilehi_p_p_rr")) ||
- (form_hash_ == Hash("whilehs_p_p_rr"));
+ bool reverse = (form_hash_ == "whilege_p_p_rr"_h) ||
+ (form_hash_ == "whilegt_p_p_rr"_h) ||
+ (form_hash_ == "whilehi_p_p_rr"_h) ||
+ (form_hash_ == "whilehs_p_p_rr"_h);
int lane_count = LaneCountFromFormat(vform);
bool last = true;
@@ -11043,28 +11041,28 @@
bool cond = false;
switch (form_hash_) {
- case Hash("whilele_p_p_rr"):
+ case "whilele_p_p_rr"_h:
cond = ssrc1 <= ssrc2;
break;
- case Hash("whilelo_p_p_rr"):
+ case "whilelo_p_p_rr"_h:
cond = usrc1 < usrc2;
break;
- case Hash("whilels_p_p_rr"):
+ case "whilels_p_p_rr"_h:
cond = usrc1 <= usrc2;
break;
- case Hash("whilelt_p_p_rr"):
+ case "whilelt_p_p_rr"_h:
cond = ssrc1 < ssrc2;
break;
- case Hash("whilege_p_p_rr"):
+ case "whilege_p_p_rr"_h:
cond = ssrc1 >= ssrc2;
break;
- case Hash("whilegt_p_p_rr"):
+ case "whilegt_p_p_rr"_h:
cond = ssrc1 > ssrc2;
break;
- case Hash("whilehi_p_p_rr"):
+ case "whilehi_p_p_rr"_h:
cond = usrc1 > usrc2;
break;
- case Hash("whilehs_p_p_rr"):
+ case "whilehs_p_p_rr"_h:
cond = usrc1 >= usrc2;
break;
default:
@@ -11346,13 +11344,13 @@
SimVRegister& zm = ReadVRegister(instr->GetRm());
switch (form_hash_) {
- case Hash("sdot_z_zzz"):
+ case "sdot_z_zzz"_h:
sdot(vform, zda, zn, zm);
break;
- case Hash("udot_z_zzz"):
+ case "udot_z_zzz"_h:
udot(vform, zda, zn, zm);
break;
- case Hash("usdot_z_zzz_s"):
+ case "usdot_z_zzz_s"_h:
usdot(vform, zda, zn, zm);
break;
default:
@@ -12196,10 +12194,10 @@
uint64_t dwords = 2;
VectorFormat vform_dst = kFormatVnQ;
- if ((form_hash_ == Hash("ld1rob_z_p_bi_u8")) ||
- (form_hash_ == Hash("ld1roh_z_p_bi_u16")) ||
- (form_hash_ == Hash("ld1row_z_p_bi_u32")) ||
- (form_hash_ == Hash("ld1rod_z_p_bi_u64"))) {
+ if ((form_hash_ == "ld1rob_z_p_bi_u8"_h) ||
+ (form_hash_ == "ld1roh_z_p_bi_u16"_h) ||
+ (form_hash_ == "ld1row_z_p_bi_u32"_h) ||
+ (form_hash_ == "ld1rod_z_p_bi_u64"_h)) {
dwords = 4;
vform_dst = kFormatVnO;
}
@@ -12224,10 +12222,10 @@
uint64_t bytes = 16;
VectorFormat vform_dst = kFormatVnQ;
- if ((form_hash_ == Hash("ld1rob_z_p_br_contiguous")) ||
- (form_hash_ == Hash("ld1roh_z_p_br_contiguous")) ||
- (form_hash_ == Hash("ld1row_z_p_br_contiguous")) ||
- (form_hash_ == Hash("ld1rod_z_p_br_contiguous"))) {
+ if ((form_hash_ == "ld1rob_z_p_br_contiguous"_h) ||
+ (form_hash_ == "ld1roh_z_p_br_contiguous"_h) ||
+ (form_hash_ == "ld1row_z_p_br_contiguous"_h) ||
+ (form_hash_ == "ld1rod_z_p_br_contiguous"_h)) {
bytes = 32;
vform_dst = kFormatVnO;
}
@@ -12797,18 +12795,18 @@
dup_elements_to_segments(vform, temp, zm, index);
switch (form_hash_) {
- case Hash("sdot_z_zzzi_d"):
- case Hash("sdot_z_zzzi_s"):
+ case "sdot_z_zzzi_d"_h:
+ case "sdot_z_zzzi_s"_h:
sdot(vform, zda, zn, temp);
break;
- case Hash("udot_z_zzzi_d"):
- case Hash("udot_z_zzzi_s"):
+ case "udot_z_zzzi_d"_h:
+ case "udot_z_zzzi_s"_h:
udot(vform, zda, zn, temp);
break;
- case Hash("sudot_z_zzzi_s"):
+ case "sudot_z_zzzi_s"_h:
usdot(vform, zda, temp, zn);
break;
- case Hash("usdot_z_zzzi_s"):
+ case "usdot_z_zzzi_s"_h:
usdot(vform, zda, zn, temp);
break;
default:
@@ -12826,22 +12824,22 @@
bool n_signed = false;
bool m_signed = false;
switch (form_hash_) {
- case Hash("smmla_asimdsame2_g"):
+ case "smmla_asimdsame2_g"_h:
vform = kFormat4S;
VIXL_FALLTHROUGH();
- case Hash("smmla_z_zzz"):
+ case "smmla_z_zzz"_h:
n_signed = m_signed = true;
break;
- case Hash("ummla_asimdsame2_g"):
+ case "ummla_asimdsame2_g"_h:
vform = kFormat4S;
VIXL_FALLTHROUGH();
- case Hash("ummla_z_zzz"):
+ case "ummla_z_zzz"_h:
// Nothing to do.
break;
- case Hash("usmmla_asimdsame2_g"):
+ case "usmmla_asimdsame2_g"_h:
vform = kFormat4S;
VIXL_FALLTHROUGH();
- case Hash("usmmla_z_zzz"):
+ case "usmmla_z_zzz"_h:
m_signed = true;
break;
default:
@@ -12858,8 +12856,8 @@
SimVRegister& zm = ReadVRegister(instr->GetRm());
switch (form_hash_) {
- case Hash("fmmla_z_zzz_s"):
- case Hash("fmmla_z_zzz_d"):
+ case "fmmla_z_zzz_s"_h:
+ case "fmmla_z_zzz_d"_h:
fmatmul(vform, zdn, zn, zm);
break;
default:
@@ -13311,10 +13309,10 @@
SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
switch (form_hash_) {
- case Hash("splice_z_p_zz_des"):
+ case "splice_z_p_zz_des"_h:
splice(vform, zd, pg, zd, zn);
break;
- case Hash("splice_z_p_zz_con"):
+ case "splice_z_p_zz_con"_h:
splice(vform, zd, pg, zn, zn2);
break;
default:
@@ -13430,13 +13428,13 @@
SimVRegister& zm = ReadVRegister(instr->GetRm());
switch (form_hash_) {
- case Hash("tbl_z_zz_1"):
+ case "tbl_z_zz_1"_h:
tbl(vform, zd, zn, zm);
break;
- case Hash("tbl_z_zz_2"):
+ case "tbl_z_zz_2"_h:
tbl(vform, zd, zn, zn2, zm);
break;
- case Hash("tbx_z_zz"):
+ case "tbx_z_zz"_h:
tbx(vform, zd, zn, zm);
break;
default:
diff --git a/src/aarch64/simulator-aarch64.h b/src/aarch64/simulator-aarch64.h
index ad6e1fb..1fdbb6f 100644
--- a/src/aarch64/simulator-aarch64.h
+++ b/src/aarch64/simulator-aarch64.h
@@ -1155,8 +1155,8 @@
}
}
- bool last_instr_was_movprfx = (form_hash_ == Hash("movprfx_z_z")) ||
- (form_hash_ == Hash("movprfx_z_p_z"));
+ bool last_instr_was_movprfx =
+ (form_hash_ == "movprfx_z_z"_h) || (form_hash_ == "movprfx_z_p_z"_h);
// decoder_->Decode(...) triggers at least the following visitors:
// 1. The CPUFeaturesAuditor (`cpu_features_auditor_`).