Enable clang-format in the tests
Extend the clang_format.py script to format everything by trace files in
the `test/` directory. Also, we have to add "on/off" marker in
`test-simualtor-inputs-aarch64.h` as clang-format is getting confused
there.
Change-Id: I1159498072bda1bfd049082aeccb347ec55e7825
diff --git a/test/test-code-generation-scopes.cc b/test/test-code-generation-scopes.cc
index 2a05544..7595527 100644
--- a/test/test-code-generation-scopes.cc
+++ b/test/test-code-generation-scopes.cc
@@ -34,13 +34,13 @@
#include "aarch64/macro-assembler-aarch64.h"
#endif
-#define TEST(name) TEST_(SCOPES_##name)
+#define TEST(name) TEST_(SCOPES_##name)
#ifdef VIXL_INCLUDE_TARGET_A32
-#define TEST_A32(name) TEST(name)
+#define TEST_A32(name) TEST(name)
#else
// Do not add this test to the harness.
-#define TEST_A32(name) void Test##name()
+#define TEST_A32(name) void Test##name()
#endif
#define __ masm.
@@ -337,7 +337,7 @@
#ifdef VIXL_INCLUDE_TARGET_AARCH32
-#define ASSERT_LITERAL_POOL_SIZE_32(expected) \
+#define ASSERT_LITERAL_POOL_SIZE_32(expected) \
VIXL_CHECK((expected) == masm.GetLiteralPoolSize())
TEST_A32(EmissionCheckScope_emit_pool_32) {
@@ -378,9 +378,9 @@
#ifdef VIXL_INCLUDE_TARGET_AARCH64
-#define ASSERT_LITERAL_POOL_SIZE_64(expected) \
- VIXL_CHECK( \
- (expected + aarch64::kInstructionSize) == masm.GetLiteralPoolSize())
+#define ASSERT_LITERAL_POOL_SIZE_64(expected) \
+ VIXL_CHECK((expected + aarch64::kInstructionSize) == \
+ masm.GetLiteralPoolSize())
TEST(EmissionCheckScope_emit_pool_64) {
aarch64::MacroAssembler masm;
@@ -712,7 +712,8 @@
// The literal pool should be generated when opening this scope, as
// otherwise the `Ldrd` will run out of range when we generate the `nop`
// instructions below.
- ExactAssemblyScope scope(&masm, n_nops * aarch32::kA32InstructionSizeInBytes);
+ ExactAssemblyScope scope(&masm,
+ n_nops * aarch32::kA32InstructionSizeInBytes);
// Although it must be, we do not check that the literal pool size is zero
// here, because we want this regression test to fail while or after we
@@ -765,4 +766,3 @@
} // namespace vixl
-