commit bcb9ee3ef8126ae6cb46bf0076615a545c498a8f
author Mai <mathew1800@gmail.com> Thu Aug 11 08:27:40 2022 -0400
committer GitHub <noreply@github.com> Thu Aug 11 13:27:40 2022 +0100
tree ed41b62190d839ebd9a50c3414584214faf1e103
parent b43d6ef204f345d3b5240435118ec7685de7bfea

cpu-features: Update OS queryable hwcaps (#43)

* cpu-features: Support hwcap for FEAT_MTE3
* cpu-features: Support hwcap for FEAT_SME
* cpu-aarch64: Allow specifying IDRegister field size
This will be necessary for testing some SME extensions.

Preserves existing behavior by defaulting the field size to 4 bits.

* cpu-aarch64: Add skeleton for AA64SMFR0_EL1
This register contains the bulk of the SME extension bitfields.

* cpu-features: Support hwcap for FEAT_SME_I16I64
* cpu-features: Support hwcap for FEAT_SME_F64F64
* cpu-features: Support hwcap for FEAT_SME_I8I32
* cpu-features: Support hwcap for FEAT_SME_F16F32
* cpu-features: Support hwcap for FEAT_SME_B16F32
* cpu-features: Support hwcap for FEAT_SME_F32F32
* cpu-features: Support hwcap for FEAT_SME_FA64

* cpu-aarch64: Handle hwcap auxvals separately
HWCAP2 makes use of bit 31 and bit 32 which would fall outside the range
of what can be handled by one array, so we can split the array into two
arrays and combine over them individually.

* cpu-features: Support hwcap for FEAT_WFxT
* cpu-features: Support hwcap for FEAT_EBF16

src/cpu-features.h

diff --git a/src/cpu-features.h b/src/cpu-features.h
index ebd0578..9006fcb 100644
--- a/src/cpu-features.h
+++ b/src/cpu-features.h
@@ -166,6 +166,7 @@
   /* Memory Tagging Extension.                                              */ \
   V(kMTEInstructions,     "MTE (EL0 instructions)", NULL)                      \
   V(kMTE,                 "MTE",                    NULL)                      \
+  V(kMTE3,                "MTE (asymmetric)",       "mte3")                    \
   /* PAuth extensions.                                                      */ \
   V(kPAuthEnhancedPAC,    "PAuth EnhancedPAC",      NULL)                      \
   V(kPAuthEnhancedPAC2,   "PAuth EnhancedPAC2",     NULL)                      \
@@ -183,7 +184,20 @@
   /* Enhanced Counter Virtualization                                        */ \
   V(kECV,                 "ECV",                    "ecv")                     \
   /* Increased precision of Reciprocal Estimate and Square Root Estimate    */ \
-  V(kRPRES,               "RPRES",                  "rpres")
+  V(kRPRES,               "RPRES",                  "rpres")                   \
+  /* Scalable Matrix Extension (SME)                                        */ \
+  V(kSME,                 "SME",                    "sme")                     \
+  V(kSMEi16i64,           "SME (i16i64)",           "smei16i64")               \
+  V(kSMEf64f64,           "SME (f64f64)",           "smef64f64")               \
+  V(kSMEi8i32,            "SME (i8i32)",            "smei8i32")                \
+  V(kSMEf16f32,           "SME (f16f32)",           "smef16f32")               \
+  V(kSMEb16f32,           "SME (b16f32)",           "smeb16f32")               \
+  V(kSMEf32f32,           "SME (f32f32)",           "smef32f32")               \
+  V(kSMEfa64,             "SME (fa64)",             "smefa64")                 \
+  /* WFET and WFIT instruction support                                      */ \
+  V(kWFXT,                "WFXT",                   "wfxt")                    \
+  /* Extended BFloat16 instructions                                         */ \
+  V(kEBF16,               "EBF16",                  "ebf16")
 // clang-format on