commit ada6b35f65d1256a9624378dd9344523329896f7
author TatWai Chong <tatwai.chong@arm.com> Fri Nov 06 13:48:09 2020 -0800
committer TatWai Chong <tatwai.chong@arm.com> Wed Dec 16 11:33:51 2020 -0800
tree d5279b0da0f25d11ff11b7260bdef1eb6c6892c3
parent 4a454b46819b4c4ec6fb8f22e02329472da003ba

[sve2] Implement complex integer multiply-add (vector).

Include cmla and sqrdcmlah.

Change-Id: Ic842db287b4cf5a7531de4205e9f8b431be2a8aa

src/aarch64/simulator-aarch64.cc

diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc
index 0d7dfcb..7a704d8 100644
--- a/src/aarch64/simulator-aarch64.cc
+++ b/src/aarch64/simulator-aarch64.cc
@@ -85,7 +85,7 @@
     {"cdot_z_zzz", &Simulator::SimulateSVEComplexDotProduct},
     {"cdot_z_zzzi_d", &Simulator::SimulateSVEComplexDotProduct},
     {"cdot_z_zzzi_s", &Simulator::SimulateSVEComplexDotProduct},
-    {"cmla_z_zzz", &Simulator::Simulate_ZdaT_ZnT_ZmT_const},
+    {"cmla_z_zzz", &Simulator::SimulateSVEComplexIntMulAdd},
     {"cmla_z_zzzi_h", &Simulator::Simulate_ZdaH_ZnH_ZmH_imm_const},
     {"cmla_z_zzzi_s", &Simulator::Simulate_ZdaS_ZnS_ZmS_imm_const},
     {"eor3_z_zzz", &Simulator::SimulateSVEBitwiseTernary},
@@ -217,7 +217,7 @@
     {"sqdmullt_z_zzi_d", &Simulator::SimulateSVESaturatingIntMulLongIdx},
     {"sqdmullt_z_zzi_s", &Simulator::Simulate_ZdS_ZnH_ZmH_imm},
     {"sqneg_z_p_z", &Simulator::Simulate_ZdT_PgM_ZnT},
-    {"sqrdcmlah_z_zzz", &Simulator::Simulate_ZdaT_ZnT_ZmT_const},
+    {"sqrdcmlah_z_zzz", &Simulator::SimulateSVEComplexIntMulAdd},
     {"sqrdcmlah_z_zzzi_h", &Simulator::Simulate_ZdaH_ZnH_ZmH_imm_const},
     {"sqrdcmlah_z_zzzi_s", &Simulator::Simulate_ZdaS_ZnS_ZmS_imm_const},
     {"sqrdmlah_z_zzz", &Simulator::Simulate_ZdaT_ZnT_ZmT},
@@ -3057,20 +3057,19 @@
   }
 }
 
-void Simulator::Simulate_ZdaT_ZnT_ZmT_const(const Instruction* instr) {
+void Simulator::SimulateSVEComplexIntMulAdd(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
   SimVRegister& zda = ReadVRegister(instr->GetRd());
-  USE(zda);
   SimVRegister& zm = ReadVRegister(instr->GetRm());
-  USE(zm);
   SimVRegister& zn = ReadVRegister(instr->GetRn());
-  USE(zn);
+  int rot = instr->ExtractBits(11, 10) * 90;
 
   switch (form_hash_) {
     case Hash("cmla_z_zzz"):
-      VIXL_UNIMPLEMENTED();
+      cmla(vform, zda, zda, zn, zm, rot);
       break;
     case Hash("sqrdcmlah_z_zzz"):
-      VIXL_UNIMPLEMENTED();
+      sqrdcmlah(vform, zda, zda, zn, zm, rot);
       break;
     default:
       VIXL_UNIMPLEMENTED();