commit 9a9331faeba996d6c85e6e2a6355ccfc22c6cab6
author Rodolph Perfetta <rodolph.perfetta@arm.com> Fri Dec 09 22:05:48 2016 +0000
committer Rodolph Perfetta <rodolph.perfetta@arm.com> Tue Jan 10 13:18:01 2017 +0000
tree b701e346a0004b6b4094ce77dd1da1f482a0c519
parent 6ee0978e4e0462cdaa4c92591e9a36fdeaef704d

Allow conditional inclusion of A32, T32 and A64.

The 'target_arch' option has been replace by 'target' which can be any
combination of aarch32, aarch64, a32, t32, a64.

Change-Id: Id5cd052276747cd718551f562b74f79443b91869

test/test-utils.cc

diff --git a/test/test-utils.cc b/test/test-utils.cc
index c480c13..4abcf56 100644
--- a/test/test-utils.cc
+++ b/test/test-utils.cc
@@ -57,7 +57,8 @@
 
 #if defined(__aarch64__) && defined(VIXL_INCLUDE_TARGET_AARCH64)
   aarch64::CPU::EnsureIAndDCacheCoherency(buffer, size);
-#elif defined(__arm__) && defined(VIXL_INCLUDE_TARGET_AARCH32)
+#elif defined(__arm__) && \
+      (defined(VIXL_INCLUDE_TARGET_A32) || defined(VIXL_INCLUDE_TARGET_T32))
   // TODO: Do not use __builtin___clear_cache and instead implement
   // `CPU::EnsureIAndDCacheCoherency` for aarch32.
   __builtin___clear_cache(buffer, reinterpret_cast<char*>(buffer) + size);