VIXL Release 1.8
Refer to the README.md and LICENCE files for details.
diff --git a/tools/generate_simulator_traces.py b/tools/generate_simulator_traces.py
index 7ab9aef..de017d4 100755
--- a/tools/generate_simulator_traces.py
+++ b/tools/generate_simulator_traces.py
@@ -1,6 +1,6 @@
#!/usr/bin/env python2.7
-# Copyright 2014, ARM Limited
+# Copyright 2015, ARM Limited
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -32,6 +32,78 @@
import re
import util
+copyright_header = """// Copyright 2015, ARM Limited
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// * Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+// * Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+// * Neither the name of ARM Limited nor the names of its contributors may be
+// used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+
+master_trace_header = """
+// This file holds the expected results for the instructions tested by
+// test-simulator-a64.
+//
+// If you update input lists in test-simulator-inputs-a64.h, or add a new test
+// to test-simulator-a64.cc, please run tools/generate_simulator_traces.py on a
+// reference platform to regenerate this file and trace files.
+//
+
+#ifndef VIXL_TEST_SIMULATOR_TRACES_A64_H_
+#define VIXL_TEST_SIMULATOR_TRACES_A64_H_
+
+#include <stdint.h>
+
+// To add a new simulator test to test-simulator-a64.cc, add dummy array(s)
+// below to build test-simulator-a64 for reference platform. Then, run
+// tools/generate_simulator_traces.py on a reference platform to regenerate this
+// file and traces files.
+
+// ---------------------------------------------------------------------
+// ADD DUMMY ARRAYS FOR NEW SIMULATOR TEST HERE.
+// ---------------------------------------------------------------------
+const uint64_t kExpected_dummy_64[] = { 0 };
+const size_t kExpectedCount_dummy_64 = 0;
+
+const uint32_t kExpected_dummy_32[] = { 0 };
+const size_t kExpectedCount_dummy_32 = 0;
+
+// ---------------------------------------------------------------------
+// Simulator test trace output files.
+// ---------------------------------------------------------------------
+"""
+master_trace_footer = """
+#endif // VIXL_TEST_SIMULATOR_TRACES_A64_H_
+"""
+
+trace_header = """
+// ---------------------------------------------------------------------
+// This file is auto generated using tools/generate_simulator_traces.py.
+//
+// PLEASE DO NOT EDIT.
+// ---------------------------------------------------------------------
+"""
+
def BuildOptions(root):
result = argparse.ArgumentParser(description = 'Simulator test generator.')
result.add_argument('--runner', action='store', default=root+'/test-runner',
@@ -49,36 +121,15 @@
args = BuildOptions(root_dir)
# Run each simulator test (SIM_*) with the --sim_test_trace option, and use
- # the output to update the traces header (from --out). The existing traces are
- # wholly replaced, but some boilerplate code exists in the header, so we find
- # the start of the traces, truncate the file to that point, then add the new
- # (updated) trace data.
+ # the output to create the traces header (from --out). In addition, the
+ # test-simulator-traces-a64.h file, the master trace file, which includes all
+ # other trace files is generated.
- # Find the output section of the traces file.
- marker = [
- '// ---------------------------------------------------------------------',
- '// Expected outputs.',
- '// Everything below this point is automatically generated.',
- '//',
- '// PLEASE DO NOT EDIT ANYTHING BELOW THIS COMMENT.',
- '// ---------------------------------------------------------------------',
- ]
- matched = 0
- f = open(args.out, 'r+')
- # Use readline (rather than for..in) so we can truncate at the right place.
- line = f.readline();
- while line:
- if line.strip() == marker[matched]:
- matched = matched + 1
- if matched == len(marker):
- f.truncate()
- break
- else:
- matched = 0
- line = f.readline()
-
- if matched != len(marker):
- util.abort('Failed to find output section in ' + args.out + '.')
+ # Create master trace file.
+ master_trace_f = open(args.out, 'w')
+ master_trace_f.write(copyright_header)
+ master_trace_f.write(master_trace_header)
+ master_trace_f.write('\n\n')
# Find the simulator tests.
status, output = util.getstatusoutput(args.runner + ' --list')
@@ -86,13 +137,31 @@
tests = filter(lambda t: 'SIM_' in t, output.split())
tests.sort()
- # Run each test.
for test in tests:
+ # Run each test.
+ print 'Generating trace for ' + test;
cmd = ' '.join([args.runner, '--sim_test_trace', test])
status, output = util.getstatusoutput(cmd)
if status != 0: util.abort('Failed to run ' + cmd + '.')
- f.write('\n\n' + output)
+ # Create a new trace header file.
+ trace_filename = test.lower().replace('_', '-') + "-trace-a64.h"
+ trace_f = open("test/traces/a64/" + trace_filename, 'w')
+ trace_f.write(copyright_header)
+ trace_f.write(trace_header)
+ trace_f.write('\n')
+ trace_f.write("#ifndef VIXL_" + test.upper() + "_TRACE_A64_H_\n")
+ trace_f.write("#define VIXL_" + test.upper() + "_TRACE_A64_H_\n")
+ trace_f.write('\n')
+ trace_f.write(output)
+ trace_f.write('\n')
+ trace_f.write('\n' + "#endif // VIXL_" + test.upper() + "_TRACE_A64_H_" + '\n')
+ trace_f.close()
- f.write('\n\n')
- f.close()
+ # Update master trace file.
+ master_trace_f.write('#include \"traces/a64/' + trace_filename + '\"\n')
+
+# Close master trace file.
+ master_trace_f.write(master_trace_footer)
+ master_trace_f.close()
+ print 'Trace generation COMPLETE'