commit 4d912ac1b98ffe0638320815636b0b9661a8846c
author Pierre Langlois <pierre.langlois@arm.com> Tue Nov 08 11:13:31 2016 +0000
committer Pierre Langlois <pierre.langlois@arm.com> Tue May 16 16:57:13 2017 +0000
tree 801d45a113275675bf97ae480f8acc7eee998c80
parent 0ad8a6ff05cdf7554d00be8b6e3b90d0b087323e

[test] Add preliminary FP tests for OP.<dt> <Dd>, <Dn>, <Dm>

Add floating point tests for instructions taking three D registers as
operands.

We have assembler tests for the following instrutions with F32 and F64:

- VABD
- VADD
- VCEQ
- VCGE
- VCGT
- VCLE
- VCLT
- VMAX
- VMIN
- VPADD
- VPMAX
- VPMIN
- VSUB

And simulation (as in execution on hardware) for the following instructions,
only with F64 as a datatype.

- VADD
- VSUB

Change-Id: I784ee821bd551a9ceb8b3fa3e66cc40fd0e12869

tools/generate_tests.py

diff --git a/tools/generate_tests.py b/tools/generate_tests.py
index cfb3257..4e420c5 100755
--- a/tools/generate_tests.py
+++ b/tools/generate_tests.py
@@ -619,6 +619,7 @@
 default_config_files = [
     # A32 and T32 tests
     'test/aarch32/config/rd-rn-rm.json',
+    'test/aarch32/config/cond-dt-drt-drd-drn-drm-float.json',
 
     # A32 specific tests
     'test/aarch32/config/cond-rd-rn-operand-const-a32.json',