commit 36fb1cec5777b87c8c6236dc1cdb9941abc58ead
author Vincent Belliard <vincent.belliard@arm.com> Fri Oct 06 07:38:27 2017 -0700
committer Vincent Belliard <vincent.belliard@arm.com> Wed Oct 18 14:28:50 2017 -0700
tree 7450d9cb75c84680a52509caea7399b866b312ed
parent 5d85018e08776bbf182bcb36edf6fbb764023a5f

Fix vld, vst instructions with post-index.

Change-Id: I23298cb948eb73e4a98c7b3e24fd0717214be8ee

src/aarch32/assembler-aarch32.cc

diff --git a/src/aarch32/assembler-aarch32.cc b/src/aarch32/assembler-aarch32.cc
index 7e88290..138a3c2 100644
--- a/src/aarch32/assembler-aarch32.cc
+++ b/src/aarch32/assembler-aarch32.cc
@@ -18862,7 +18862,7 @@
       if (encoded_dt.IsValid() && nreglist.IsTransferAllLanes() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al) || AllowStronglyDiscouraged()) {
           const DRegister& first = nreglist.GetFirstDRegister();
           uint32_t len_encoding = nreglist.IsSingleSpaced() ? 0x0 : 0x1;
@@ -18891,7 +18891,7 @@
       if (encoded_dt.IsValid() && nreglist.IsTransferOneLane() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al) || AllowStronglyDiscouraged()) {
           const DRegister& first = nreglist.GetFirstDRegister();
           EmitT32_32(0xf9a0020dU | (encoded_dt.GetEncodingValue() << 10) |
@@ -18920,7 +18920,7 @@
       if (encoded_dt.IsValid() && nreglist.IsTransferAllLanes() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al)) {
           const DRegister& first = nreglist.GetFirstDRegister();
           uint32_t len_encoding = nreglist.IsSingleSpaced() ? 0x0 : 0x1;
@@ -18947,7 +18947,7 @@
       if (encoded_dt.IsValid() && nreglist.IsTransferOneLane() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al)) {
           const DRegister& first = nreglist.GetFirstDRegister();
           EmitA32(0xf4a0020dU | (encoded_dt.GetEncodingValue() << 10) |
@@ -26679,7 +26679,7 @@
       if (encoded_dt.IsValid() && nreglist.IsTransferOneLane() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al) || AllowStronglyDiscouraged()) {
           const DRegister& first = nreglist.GetFirstDRegister();
           EmitT32_32(0xf980020dU | (encoded_dt.GetEncodingValue() << 10) |
@@ -26707,7 +26707,7 @@
       if (encoded_dt.IsValid() && nreglist.IsTransferOneLane() &&
           ((nreglist.IsSingleSpaced() && (nreglist.GetLength() == 3)) ||
            (nreglist.IsDoubleSpaced() && (nreglist.GetLength() == 3))) &&
-          operand.IsPreIndex() && (!rn.IsPC() || AllowUnpredictable())) {
+          operand.IsPostIndex() && (!rn.IsPC() || AllowUnpredictable())) {
         if (cond.Is(al)) {
           const DRegister& first = nreglist.GetFirstDRegister();
           EmitA32(0xf480020dU | (encoded_dt.GetEncodingValue() << 10) |