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author | Fathi Boudra <fathi.boudra@linaro.org> | 2013-04-28 09:33:08 +0300 |
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committer | Fathi Boudra <fathi.boudra@linaro.org> | 2013-04-28 09:33:08 +0300 |
commit | 3b4bd47f8f4ed3aaf7c81c9b5d2d37ad79fadf4a (patch) | |
tree | b9996006addfd7ae70a39672b76843b49aebc189 /Documentation/devicetree/bindings/pwm/vt8500-pwm.txt |
Imported Upstream version 3.9.0HEADupstream/3.9.0upstreammaster
Diffstat (limited to 'Documentation/devicetree/bindings/pwm/vt8500-pwm.txt')
-rw-r--r-- | Documentation/devicetree/bindings/pwm/vt8500-pwm.txt | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt new file mode 100644 index 00000000..d21d82d2 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/vt8500-pwm.txt @@ -0,0 +1,20 @@ +VIA/Wondermedia VT8500/WM8xxx series SoC PWM controller + +Required properties: +- compatible: should be "via,vt8500-pwm" +- reg: physical base address and length of the controller's registers +- #pwm-cells: Should be 3. Number of cells being used to specify PWM property. + First cell specifies the per-chip index of the PWM to use, the second + cell is the period in nanoseconds and bit 0 in the third cell is used to + encode the polarity of PWM output. Set bit 0 of the third in PWM specifier + to 1 for inverse polarity & set to 0 for normal polarity. +- clocks: phandle to the PWM source clock + +Example: + +pwm1: pwm@d8220000 { + #pwm-cells = <3>; + compatible = "via,vt8500-pwm"; + reg = <0xd8220000 0x1000>; + clocks = <&clkpwm>; +}; |