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author | Fathi Boudra <fathi.boudra@linaro.org> | 2013-04-28 09:33:08 +0300 |
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committer | Fathi Boudra <fathi.boudra@linaro.org> | 2013-04-28 09:33:08 +0300 |
commit | 3b4bd47f8f4ed3aaf7c81c9b5d2d37ad79fadf4a (patch) | |
tree | b9996006addfd7ae70a39672b76843b49aebc189 /Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt |
Imported Upstream version 3.9.0HEADupstream/3.9.0upstreammaster
Diffstat (limited to 'Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt')
-rw-r--r-- | Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt new file mode 100644 index 00000000..89fb5434 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra30-smmu.txt @@ -0,0 +1,21 @@ +NVIDIA Tegra 30 IOMMU H/W, SMMU (System Memory Management Unit) + +Required properties: +- compatible : "nvidia,tegra30-smmu" +- reg : Should contain 3 register banks(address and length) for each + of the SMMU register blocks. +- interrupts : Should contain MC General interrupt. +- nvidia,#asids : # of ASIDs +- dma-window : IOVA start address and length. +- nvidia,ahb : phandle to the ahb bus connected to SMMU. + +Example: + smmu { + compatible = "nvidia,tegra30-smmu"; + reg = <0x7000f010 0x02c + 0x7000f1f0 0x010 + 0x7000f228 0x05c>; + nvidia,#asids = <4>; /* # of ASIDs */ + dma-window = <0 0x40000000>; /* IOVA start & length */ + nvidia,ahb = <&ahb>; + }; |