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author | Fathi Boudra <fathi.boudra@linaro.org> | 2013-04-28 09:33:08 +0300 |
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committer | Fathi Boudra <fathi.boudra@linaro.org> | 2013-04-28 09:33:08 +0300 |
commit | 3b4bd47f8f4ed3aaf7c81c9b5d2d37ad79fadf4a (patch) | |
tree | b9996006addfd7ae70a39672b76843b49aebc189 /Documentation/devicetree/bindings/arm/arch_timer.txt |
Imported Upstream version 3.9.0HEADupstream/3.9.0upstreammaster
Diffstat (limited to 'Documentation/devicetree/bindings/arm/arch_timer.txt')
-rw-r--r-- | Documentation/devicetree/bindings/arm/arch_timer.txt | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt new file mode 100644 index 00000000..20746e5a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -0,0 +1,28 @@ +* ARM architected timer + +ARM cores may have a per-core architected timer, which provides per-cpu timers. + +The timer is attached to a GIC to deliver its per-processor interrupts. + +** Timer node properties: + +- compatible : Should at least contain one of + "arm,armv7-timer" + "arm,armv8-timer" + +- interrupts : Interrupt list for secure, non-secure, virtual and + hypervisor timers, in that order. + +- clock-frequency : The frequency of the main counter, in Hz. Optional. + +Example: + + timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + clock-frequency = <100000000>; + }; |