diff options
| author | Rajendra Nayak <rnayak@codeaurora.org> | 2015-12-16 15:26:37 +0530 |
|---|---|---|
| committer | Srinivas Kandagatla <srinivas.kandagatla@linaro.org> | 2017-03-22 10:21:57 +0100 |
| commit | 000519e9e15da7aebafd9d352cb718ce076d9f58 (patch) | |
| tree | ef828d14f5007b884a67d69b390c10969307bd5d | |
| parent | e4c1f870044a724b4f74bc77ca8920cbf7a0a2cf (diff) | |
arm64: dts: Add ufs dts nodes and enable needed configs
Added DT Nodes and configs needed for UFS.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 8 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8996.dtsi | 89 |
2 files changed, 97 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index e9de22a16339f..deebd58768315 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -236,6 +236,14 @@ cd-gpios = <&msmgpio 38 0x1>; status = "okay"; }; + + ufsphy@627000 { + status = "okay"; + }; + + ufshc@624000 { + status = "okay"; + }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 679035657e466..12ffc17acca1c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8996.h> #include <dt-bindings/clock/qcom,mmcc-msm8996.h> +#include <dt-bindings/clock/qcom,rpmcc.h> / { model = "Qualcomm Technologies, Inc. MSM8996"; @@ -251,6 +252,7 @@ clock-frequency = <32764>; clock-output-names = "sleep_clk"; }; + }; psci { @@ -602,8 +604,95 @@ <960000000>, <825000000>; }; + + + ufsphy1: ufsphy@627000 { + compatible = "qcom,msm8996-ufs-phy-qmp-14nm"; + reg = <0x627000 0xda8>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + vdda-phy-supply = <&pm8994_l28>; + vdda-pll-supply = <&pm8994_l12>; + + vdda-phy-max-microamp = <18380>; + vdda-pll-max-microamp = <9440>; + + vddp-ref-clk-supply = <&pm8994_l25>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; + clock-names = "ref_clk_src", "ref_clk"; + clocks = <&rpmcc MSM8996_RPM_SMD_LN_BB_CLK>, + <&gcc GCC_UFS_CLKREF_CLK>; + status = "disabled"; + power-domains = <&gcc UFS_GDSC>; + + }; + + ufshc@624000 { + compatible = "qcom,ufshc"; + reg = <0x624000 0x2500>; + interrupts = <0 265 0>; + + phys = <&ufsphy1>; + phy-names = "ufsphy"; + + vcc-supply = <&pm8994_l20>; + vccq-supply = <&pm8994_l25>; + vccq2-supply = <&pm8994_s4>; + + vcc-max-microamp = <600000>; + vccq-max-microamp = <450000>; + vccq2-max-microamp = <450000>; + + clock-names = + "core_clk_src", + "core_clk", + "bus_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro_src", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks = + <&gcc UFS_AXI_CLK_SRC>, + <&gcc GCC_UFS_AXI_CLK>, + <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, + <&gcc GCC_AGGRE2_UFS_AXI_CLK>, + <&gcc GCC_UFS_AHB_CLK>, + <&gcc UFS_ICE_CORE_CLK_SRC>, + <&gcc GCC_UFS_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_ICE_CORE_CLK>, + <&rpmcc MSM8996_RPM_SMD_LN_BB_CLK>, + <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; + freq-table-hz = + <100000000 200000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <150000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + lanes-per-direction = <1>; + status = "disabled"; + + ufs_variant { + compatible = "qcom,ufs_variant"; + }; + }; + }; + adsp-smp2p { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; |