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authorAlex Bennée <alex.bennee@linaro.org>2017-10-31 14:54:39 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-11-21 11:54:43 +0000
commitc2cf5909e86cb3087b53f19c1240049b678f13b4 (patch)
tree8adc69f0ed8474d1308fad2b1ecb856bca1c1bbc
parent1a62eb3e3c31953f633ffe6d1d0c320ec83815bf (diff)
downloadrisu-c2cf5909e86cb3087b53f19c1240049b678f13b4.tar.gz
aarch64.risu: remove duplicate AdvSIMD Scalar 3 same block
A chunk of the AArch64 definitions repeat themselves. Clean that up. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20171031145444.13766-3-alex.bennee@linaro.org
-rw-r--r--aarch64.risu22
1 files changed, 0 insertions, 22 deletions
diff --git a/aarch64.risu b/aarch64.risu
index 5e7ec59..c9f24cd 100644
--- a/aarch64.risu
+++ b/aarch64.risu
@@ -2165,28 +2165,6 @@ FCMGT A64_V 01 1 11110 1 size:1 1 rm:5 11100 1 rn:5 rd:5
FACGT A64_V 01 1 11110 1 size:1 1 rm:5 11101 1 rn:5 rd:5 \
!constraints { $size != 11; }
-CMTST A64_v 01 0 11110 size:2 1 rm:5 10001 1 rn:5 rd:5
-SQDMULH A64_v 01 0 11110 size:2 1 rm:5 10110 1 rn:5 rd:5
-FMULX A64_v 01 0 11110 0 size:1 1 rm:5 11011 1 rn:5 rd:5
-FCMEQ A64_v 01 0 11110 0 size:1 1 rm:5 11100 1 rn:5 rd:5
-FRECPS A64_v 01 0 11110 0 size:1 1 rm:5 11111 1 rn:5 rd:5
-FRSQRTS A64_v 01 0 11110 1 size:1 1 rm:5 11111 1 rn:5 rd:5
-UQADD A64_v 01 1 11110 size:2 1 rm:5 00001 1 rn:5 rd:5
-UQSUB A64_v 01 1 11110 size:2 1 rm:5 00101 1 rn:5 rd:5
-CMHI A64_v 01 1 11110 size:2 1 rm:5 00110 1 rn:5 rd:5
-CMHS A64_v 01 1 11110 size:2 1 rm:5 00111 1 rn:5 rd:5
-USHL A64_v 01 1 11110 size:2 1 rm:5 01000 1 rn:5 rd:5
-UQSHL A64_v 01 1 11110 size:2 1 rm:5 01001 1 rn:5 rd:5
-URSHL A64_v 01 1 11110 size:2 1 rm:5 01010 1 rn:5 rd:5
-UQRSHL A64_v 01 1 11110 size:2 1 rm:5 01011 1 rn:5 rd:5
-SUBv A64_v 01 1 11110 size:2 1 rm:5 10000 1 rn:5 rd:5
-CMEQ A64_v 01 1 11110 size:2 1 rm:5 10001 1 rn:5 rd:5
-SQRDMULH A64_v 01 1 11110 size:2 1 rm:5 10110 1 rn:5 rd:5
-FCMGE A64_v 01 1 11110 0 size:1 1 rm:5 11100 1 rn:5 rd:5
-FACGE A64_v 01 1 11110 0 size:1 1 rm:5 11101 1 rn:5 rd:5
-FABD A64_v 01 1 11110 1 size:1 1 rm:5 11010 1 rn:5 rd:5
-FCMGT A64_v 01 1 11110 1 size:1 1 rm:5 11100 1 rn:5 rd:5
-FACGT A64_v 01 1 11110 1 size:1 1 rm:5 11101 1 rn:5 rd:5
# C3.6.12 AdvSIMD scalar 2reg misc
CMGTzero A64_V 01 0 11110 size:2 10000 01000 10 rn:5 rd:5