aboutsummaryrefslogtreecommitdiff
path: root/hw/display/exynos4210_fimd.c
blob: 7e1cbb63c977ac8a9b5a21075f7c82bc63bf556f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
/*
 * Samsung exynos4210 Display Controller (FIMD)
 *
 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
 * All rights reserved.
 * Based on LCD controller for Samsung S5PC1xx-based board emulation
 * by Kirill Batuzov <batuzovk@ispras.ru>
 *
 * Contributed by Mitsyanko Igor <i.mitsyanko@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 */

#include "qemu-common.h"
#include "hw/sysbus.h"
#include "ui/console.h"
#include "ui/pixel_ops.h"
#include "qemu/bswap.h"

/* Debug messages configuration */
#define EXYNOS4210_FIMD_DEBUG              0
#define EXYNOS4210_FIMD_MODE_TRACE         0

#if EXYNOS4210_FIMD_DEBUG == 0
    #define DPRINT_L1(fmt, args...)       do { } while (0)
    #define DPRINT_L2(fmt, args...)       do { } while (0)
    #define DPRINT_ERROR(fmt, args...)    do { } while (0)
#elif EXYNOS4210_FIMD_DEBUG == 1
    #define DPRINT_L1(fmt, args...) \
        do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
    #define DPRINT_L2(fmt, args...)       do { } while (0)
    #define DPRINT_ERROR(fmt, args...)  \
        do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
#else
    #define DPRINT_L1(fmt, args...) \
        do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
    #define DPRINT_L2(fmt, args...) \
        do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
    #define DPRINT_ERROR(fmt, args...)  \
        do {fprintf(stderr, "QEMU FIMD ERROR: "fmt, ## args); } while (0)
#endif

#if EXYNOS4210_FIMD_MODE_TRACE == 0
    #define DPRINT_TRACE(fmt, args...)        do { } while (0)
#else
    #define DPRINT_TRACE(fmt, args...)        \
        do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
#endif

#define NUM_OF_WINDOWS              5
#define FIMD_REGS_SIZE              0x4114

/* Video main control registers */
#define FIMD_VIDCON0                0x0000
#define FIMD_VIDCON1                0x0004
#define FIMD_VIDCON2                0x0008
#define FIMD_VIDCON3                0x000C
#define FIMD_VIDCON0_ENVID_F        (1 << 0)
#define FIMD_VIDCON0_ENVID          (1 << 1)
#define FIMD_VIDCON0_ENVID_MASK     ((1 << 0) | (1 << 1))
#define FIMD_VIDCON1_ROMASK         0x07FFE000

/* Video time control registers */
#define FIMD_VIDTCON_START          0x10
#define FIMD_VIDTCON_END            0x1C
#define FIMD_VIDTCON2_SIZE_MASK     0x07FF
#define FIMD_VIDTCON2_HOR_SHIFT     0
#define FIMD_VIDTCON2_VER_SHIFT     11

/* Window control registers */
#define FIMD_WINCON_START           0x0020
#define FIMD_WINCON_END             0x0030
#define FIMD_WINCON_ROMASK          0x82200000
#define FIMD_WINCON_ENWIN           (1 << 0)
#define FIMD_WINCON_BLD_PIX         (1 << 6)
#define FIMD_WINCON_ALPHA_MUL       (1 << 7)
#define FIMD_WINCON_ALPHA_SEL       (1 << 1)
#define FIMD_WINCON_SWAP            0x078000
#define FIMD_WINCON_SWAP_SHIFT      15
#define FIMD_WINCON_SWAP_WORD       0x1
#define FIMD_WINCON_SWAP_HWORD      0x2
#define FIMD_WINCON_SWAP_BYTE       0x4
#define FIMD_WINCON_SWAP_BITS       0x8
#define FIMD_WINCON_BUFSTAT_L       (1 << 21)
#define FIMD_WINCON_BUFSTAT_H       (1 << 31)
#define FIMD_WINCON_BUFSTATUS       ((1 << 21) | (1 << 31))
#define FIMD_WINCON_BUF0_STAT       ((0 << 21) | (0 << 31))
#define FIMD_WINCON_BUF1_STAT       ((1 << 21) | (0 << 31))
#define FIMD_WINCON_BUF2_STAT       ((0 << 21) | (1 << 31))
#define FIMD_WINCON_BUFSELECT       ((1 << 20) | (1 << 30))
#define FIMD_WINCON_BUF0_SEL        ((0 << 20) | (0 << 30))
#define FIMD_WINCON_BUF1_SEL        ((1 << 20) | (0 << 30))
#define FIMD_WINCON_BUF2_SEL        ((0 << 20) | (1 << 30))
#define FIMD_WINCON_BUFMODE         (1 << 14)
#define IS_PALETTIZED_MODE(w)       (w->wincon & 0xC)
#define PAL_MODE_WITH_ALPHA(x)       ((x) == 7)
#define WIN_BPP_MODE(w)             ((w->wincon >> 2) & 0xF)
#define WIN_BPP_MODE_WITH_ALPHA(w)     \
    (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE)

/* Shadow control register */
#define FIMD_SHADOWCON              0x0034
#define FIMD_WINDOW_PROTECTED(s, w) ((s) & (1 << (10 + (w))))
/* Channel mapping control register */
#define FIMD_WINCHMAP               0x003C

/* Window position control registers */
#define FIMD_VIDOSD_START           0x0040
#define FIMD_VIDOSD_END             0x0088
#define FIMD_VIDOSD_COORD_MASK      0x07FF
#define FIMD_VIDOSD_HOR_SHIFT       11
#define FIMD_VIDOSD_VER_SHIFT       0
#define FIMD_VIDOSD_ALPHA_AEN0      0xFFF000
#define FIMD_VIDOSD_AEN0_SHIFT      12
#define FIMD_VIDOSD_ALPHA_AEN1      0x000FFF

/* Frame buffer address registers */
#define FIMD_VIDWADD0_START         0x00A0
#define FIMD_VIDWADD0_END           0x00C4
#define FIMD_VIDWADD0_END           0x00C4
#define FIMD_VIDWADD1_START         0x00D0
#define FIMD_VIDWADD1_END           0x00F4
#define FIMD_VIDWADD2_START         0x0100
#define FIMD_VIDWADD2_END           0x0110
#define FIMD_VIDWADD2_PAGEWIDTH     0x1FFF
#define FIMD_VIDWADD2_OFFSIZE       0x1FFF
#define FIMD_VIDWADD2_OFFSIZE_SHIFT 13
#define FIMD_VIDW0ADD0_B2           0x20A0
#define FIMD_VIDW4ADD0_B2           0x20C0

/* Video interrupt control registers */
#define FIMD_VIDINTCON0             0x130
#define FIMD_VIDINTCON1             0x134

/* Window color key registers */
#define FIMD_WKEYCON_START          0x140
#define FIMD_WKEYCON_END            0x15C
#define FIMD_WKEYCON0_COMPKEY       0x00FFFFFF
#define FIMD_WKEYCON0_CTL_SHIFT     24
#define FIMD_WKEYCON0_DIRCON        (1 << 24)
#define FIMD_WKEYCON0_KEYEN         (1 << 25)
#define FIMD_WKEYCON0_KEYBLEN       (1 << 26)
/* Window color key alpha control register */
#define FIMD_WKEYALPHA_START        0x160
#define FIMD_WKEYALPHA_END          0x16C

/* Dithering control register */
#define FIMD_DITHMODE               0x170

/* Window alpha control registers */
#define FIMD_VIDALPHA_ALPHA_LOWER   0x000F0F0F
#define FIMD_VIDALPHA_ALPHA_UPPER   0x00F0F0F0
#define FIMD_VIDWALPHA_START        0x21C
#define FIMD_VIDWALPHA_END          0x240

/* Window color map registers */
#define FIMD_WINMAP_START           0x180
#define FIMD_WINMAP_END             0x190
#define FIMD_WINMAP_EN              (1 << 24)
#define FIMD_WINMAP_COLOR_MASK      0x00FFFFFF

/* Window palette control registers */
#define FIMD_WPALCON_HIGH           0x019C
#define FIMD_WPALCON_LOW            0x01A0
#define FIMD_WPALCON_UPDATEEN       (1 << 9)
#define FIMD_WPAL_W0PAL_L           0x07
#define FIMD_WPAL_W0PAL_L_SHT        0
#define FIMD_WPAL_W1PAL_L           0x07
#define FIMD_WPAL_W1PAL_L_SHT       3
#define FIMD_WPAL_W2PAL_L           0x01
#define FIMD_WPAL_W2PAL_L_SHT       6
#define FIMD_WPAL_W2PAL_H           0x06
#define FIMD_WPAL_W2PAL_H_SHT       8
#define FIMD_WPAL_W3PAL_L           0x01
#define FIMD_WPAL_W3PAL_L_SHT       7
#define FIMD_WPAL_W3PAL_H           0x06
#define FIMD_WPAL_W3PAL_H_SHT       12
#define FIMD_WPAL_W4PAL_L           0x01
#define FIMD_WPAL_W4PAL_L_SHT       8
#define FIMD_WPAL_W4PAL_H           0x06
#define FIMD_WPAL_W4PAL_H_SHT       16

/* Trigger control registers */
#define FIMD_TRIGCON                0x01A4
#define FIMD_TRIGCON_ROMASK         0x00000004

/* LCD I80 Interface Control */
#define FIMD_I80IFCON_START         0x01B0
#define FIMD_I80IFCON_END           0x01BC
/* Color gain control register */
#define FIMD_COLORGAINCON           0x01C0
/* LCD i80 Interface Command Control */
#define FIMD_LDI_CMDCON0            0x01D0
#define FIMD_LDI_CMDCON1            0x01D4
/* I80 System Interface Manual Command Control */
#define FIMD_SIFCCON0               0x01E0
#define FIMD_SIFCCON2               0x01E8

/* Hue Control Registers */
#define FIMD_HUECOEFCR_START        0x01EC
#define FIMD_HUECOEFCR_END          0x01F4
#define FIMD_HUECOEFCB_START        0x01FC
#define FIMD_HUECOEFCB_END          0x0208
#define FIMD_HUEOFFSET              0x020C

/* Video interrupt control registers */
#define FIMD_VIDINT_INTFIFOPEND     (1 << 0)
#define FIMD_VIDINT_INTFRMPEND      (1 << 1)
#define FIMD_VIDINT_INTI80PEND      (1 << 2)
#define FIMD_VIDINT_INTEN           (1 << 0)
#define FIMD_VIDINT_INTFIFOEN       (1 << 1)
#define FIMD_VIDINT_INTFRMEN        (1 << 12)
#define FIMD_VIDINT_I80IFDONE       (1 << 17)

/* Window blend equation control registers */
#define FIMD_BLENDEQ_START          0x0244
#define FIMD_BLENDEQ_END            0x0250
#define FIMD_BLENDCON               0x0260
#define FIMD_ALPHA_8BIT             (1 << 0)
#define FIMD_BLENDEQ_COEF_MASK      0xF

/* Window RTQOS Control Registers */
#define FIMD_WRTQOSCON_START        0x0264
#define FIMD_WRTQOSCON_END          0x0274

/* LCD I80 Interface Command */
#define FIMD_I80IFCMD_START         0x0280
#define FIMD_I80IFCMD_END           0x02AC

/* Shadow windows control registers */
#define FIMD_SHD_ADD0_START         0x40A0
#define FIMD_SHD_ADD0_END           0x40C0
#define FIMD_SHD_ADD1_START         0x40D0
#define FIMD_SHD_ADD1_END           0x40F0
#define FIMD_SHD_ADD2_START         0x4100
#define FIMD_SHD_ADD2_END           0x4110

/* Palette memory */
#define FIMD_PAL_MEM_START          0x2400
#define FIMD_PAL_MEM_END            0x37FC
/* Palette memory aliases for windows 0 and 1 */
#define FIMD_PALMEM_AL_START        0x0400
#define FIMD_PALMEM_AL_END          0x0BFC

typedef struct {
    uint8_t r, g, b;
    /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */
    uint32_t a;
} rgba;
#define RGBA_SIZE  7

typedef void pixel_to_rgb_func(uint32_t pixel, rgba *p);
typedef struct Exynos4210fimdWindow Exynos4210fimdWindow;

struct Exynos4210fimdWindow {
    uint32_t wincon;        /* Window control register */
    uint32_t buf_start[3];  /* Start address for video frame buffer */
    uint32_t buf_end[3];    /* End address for video frame buffer */
    uint32_t keycon[2];     /* Window color key registers */
    uint32_t keyalpha;      /* Color key alpha control register */
    uint32_t winmap;        /* Window color map register */
    uint32_t blendeq;       /* Window blending equation control register */
    uint32_t rtqoscon;      /* Window RTQOS Control Registers */
    uint32_t palette[256];  /* Palette RAM */
    uint32_t shadow_buf_start;      /* Start address of shadow frame buffer */
    uint32_t shadow_buf_end;        /* End address of shadow frame buffer */
    uint32_t shadow_buf_size;       /* Virtual shadow screen width */

    pixel_to_rgb_func *pixel_to_rgb;
    void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst,
            bool blend);
    uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a);
    uint16_t lefttop_x, lefttop_y;   /* VIDOSD0 register */
    uint16_t rightbot_x, rightbot_y; /* VIDOSD1 register */
    uint32_t osdsize;                /* VIDOSD2&3 register */
    uint32_t alpha_val[2];           /* VIDOSD2&3, VIDWALPHA registers */
    uint16_t virtpage_width;         /* VIDWADD2 register */
    uint16_t virtpage_offsize;       /* VIDWADD2 register */
    MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */
    uint8_t *host_fb_addr;           /* Host pointer to window's framebuffer */
    hwaddr fb_len;       /* Framebuffer length */
};

typedef struct {
    SysBusDevice busdev;
    MemoryRegion iomem;
    QemuConsole *console;
    qemu_irq irq[3];

    uint32_t vidcon[4];     /* Video main control registers 0-3 */
    uint32_t vidtcon[4];    /* Video time control registers 0-3 */
    uint32_t shadowcon;     /* Window shadow control register */
    uint32_t winchmap;      /* Channel mapping control register */
    uint32_t vidintcon[2];  /* Video interrupt control registers */
    uint32_t dithmode;      /* Dithering control register */
    uint32_t wpalcon[2];    /* Window palette control registers */
    uint32_t trigcon;       /* Trigger control register */
    uint32_t i80ifcon[4];   /* I80 interface control registers */
    uint32_t colorgaincon;  /* Color gain control register */
    uint32_t ldi_cmdcon[2]; /* LCD I80 interface command control */
    uint32_t sifccon[3];    /* I80 System Interface Manual Command Control */
    uint32_t huecoef_cr[4]; /* Hue control registers */
    uint32_t huecoef_cb[4]; /* Hue control registers */
    uint32_t hueoffset;     /* Hue offset control register */
    uint32_t blendcon;      /* Blending control register */
    uint32_t i80ifcmd[12];  /* LCD I80 Interface Command */

    Exynos4210fimdWindow window[5];    /* Window-specific registers */
    uint8_t *ifb;           /* Internal frame buffer */
    bool invalidate;        /* Image needs to be redrawn */
    bool enabled;           /* Display controller is enabled */
} Exynos4210fimdState;

/* Perform byte/halfword/word swap of data according to WINCON */
static inline void fimd_swap_data(unsigned int swap_ctl, uint64_t *data)
{
    int i;
    uint64_t res;
    uint64_t x = *data;

    if (swap_ctl & FIMD_WINCON_SWAP_BITS) {
        res = 0;
        for (i = 0; i < 64; i++) {
            if (x & (1ULL << (64 - i))) {
                res |= (1ULL << i);
            }
        }
        x = res;
    }

    if (swap_ctl & FIMD_WINCON_SWAP_BYTE) {
        x = bswap64(x);
    }

    if (swap_ctl & FIMD_WINCON_SWAP_HWORD) {
        x = ((x & 0x000000000000FFFFULL) << 48) |
            ((x & 0x00000000FFFF0000ULL) << 16) |
            ((x & 0x0000FFFF00000000ULL) >> 16) |
            ((x & 0xFFFF000000000000ULL) >> 48);
    }

    if (swap_ctl & FIMD_WINCON_SWAP_WORD) {
        x = ((x & 0x00000000FFFFFFFFULL) << 32) |
            ((x & 0xFFFFFFFF00000000ULL) >> 32);
    }

    *data = x;
}

/* Conversion routines of Pixel data from frame buffer area to internal RGBA
 * pixel representation.
 * Every color component internally represented as 8-bit value. If original
 * data has less than 8 bit for component, data is extended to 8 bit. For
 * example, if blue component has only two possible values 0 and 1 it will be
 * extended to 0 and 0xFF */

/* One bit for alpha representation */
#define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \
static void N(uint32_t pixel, rgba *p) \
{ \
    p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
           ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
    pixel >>= (B); \
    p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
           ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
    pixel >>= (G); \
    p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
           ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
    pixel >>= (R); \
    p->a = (pixel & 0x1); \
}

DEF_PIXEL_TO_RGB_A1(pixel_a444_to_rgb, 4, 4, 4)
DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb, 5, 5, 5)
DEF_PIXEL_TO_RGB_A1(pixel_a666_to_rgb, 6, 6, 6)
DEF_PIXEL_TO_RGB_A1(pixel_a665_to_rgb, 6, 6, 5)
DEF_PIXEL_TO_RGB_A1(pixel_a888_to_rgb, 8, 8, 8)
DEF_PIXEL_TO_RGB_A1(pixel_a887_to_rgb, 8, 8, 7)

/* Alpha component is always zero */
#define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \
static void N(uint32_t pixel, rgba *p) \
{ \
    p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
           ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
    pixel >>= (B); \
    p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
           ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
    pixel >>= (G); \
    p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
           ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
    p->a = 0x0; \
}

DEF_PIXEL_TO_RGB_A0(pixel_565_to_rgb,  5, 6, 5)
DEF_PIXEL_TO_RGB_A0(pixel_555_to_rgb,  5, 5, 5)
DEF_PIXEL_TO_RGB_A0(pixel_666_to_rgb,  6, 6, 6)
DEF_PIXEL_TO_RGB_A0(pixel_888_to_rgb,  8, 8, 8)

/* Alpha component has some meaningful value */
#define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \
static void N(uint32_t pixel, rgba *p) \
{ \
    p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
           ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
    pixel >>= (B); \
    p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
           ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
    pixel >>= (G); \
    p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
           ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
    pixel >>= (R); \
    p->a = (pixel & ((1 << (A)) - 1)) << (8 - (A)) | \
           ((pixel >> (2 * (A) - 8)) & ((1 << (8 - (A))) - 1)); \
    p->a = p->a | (p->a << 8) | (p->a << 16); \
}

DEF_PIXEL_TO_RGB_A(pixel_4444_to_rgb, 4, 4, 4, 4)
DEF_PIXEL_TO_RGB_A(pixel_8888_to_rgb, 8, 8, 8, 8)

/* Lookup table to extent 2-bit color component to 8 bit */
static const uint8_t pixel_lutable_2b[4] = {
     0x0, 0x55, 0xAA, 0xFF
};
/* Lookup table to extent 3-bit color component to 8 bit */
static const uint8_t pixel_lutable_3b[8] = {
     0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF
};
/* Special case for a232 bpp mode */
static void pixel_a232_to_rgb(uint32_t pixel, rgba *p)
{
    p->b = pixel_lutable_2b[(pixel & 0x3)];
    pixel >>= 2;
    p->g = pixel_lutable_3b[(pixel & 0x7)];
    pixel >>= 3;
    p->r = pixel_lutable_2b[(pixel & 0x3)];
    pixel >>= 2;
    p->a = (pixel & 0x1);
}

/* Special case for (5+1, 5+1, 5+1) mode. Data bit 15 is common LSB
 * for all three color components */
static void pixel_1555_to_rgb(uint32_t pixel, rgba *p)
{
    uint8_t comm = (pixel >> 15) & 1;
    p->b = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
    pixel >>= 5;
    p->g = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
    pixel >>= 5;
    p->r = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
    p->a = 0x0;
}

/* Put/get pixel to/from internal LCD Controller framebuffer */

static int put_pixel_ifb(const rgba p, uint8_t *d)
{
    *(uint8_t *)d++ = p.r;
    *(uint8_t *)d++ = p.g;
    *(uint8_t *)d++ = p.b;
    *(uint32_t *)d = p.a;
    return RGBA_SIZE;
}

static int get_pixel_ifb(const uint8_t *s, rgba *p)
{
    p->r = *(uint8_t *)s++;
    p->g = *(uint8_t *)s++;
    p->b = *(uint8_t *)s++;
    p->a = (*(uint32_t *)s) & 0x00FFFFFF;
    return RGBA_SIZE;
}

static pixel_to_rgb_func *palette_data_format[8] = {
    [0] = pixel_565_to_rgb,
    [1] = pixel_a555_to_rgb,
    [2] = pixel_666_to_rgb,
    [3] = pixel_a665_to_rgb,
    [4] = pixel_a666_to_rgb,
    [5] = pixel_888_to_rgb,
    [6] = pixel_a888_to_rgb,
    [7] = pixel_8888_to_rgb
};

/* Returns Index in palette data formats table for given window number WINDOW */
static uint32_t
exynos4210_fimd_palette_format(Exynos4210fimdState *s, int window)
{
    uint32_t ret;

    switch (window) {
    case 0:
        ret = (s->wpalcon[1] >> FIMD_WPAL_W0PAL_L_SHT) & FIMD_WPAL_W0PAL_L;
        if (ret != 7) {
            ret = 6 - ret;
        }
        break;
    case 1:
        ret = (s->wpalcon[1] >> FIMD_WPAL_W1PAL_L_SHT) & FIMD_WPAL_W1PAL_L;
        if (ret != 7) {
            ret = 6 - ret;
        }
        break;
    case 2:
        ret = ((s->wpalcon[0] >> FIMD_WPAL_W2PAL_H_SHT) & FIMD_WPAL_W2PAL_H) |
            ((s->wpalcon[1] >> FIMD_WPAL_W2PAL_L_SHT) & FIMD_WPAL_W2PAL_L);
        break;
    case 3:
        ret = ((s->wpalcon[0] >> FIMD_WPAL_W3PAL_H_SHT) & FIMD_WPAL_W3PAL_H) |
            ((s->wpalcon[1] >> FIMD_WPAL_W3PAL_L_SHT) & FIMD_WPAL_W3PAL_L);
        break;
    case 4:
        ret = ((s->wpalcon[0] >> FIMD_WPAL_W4PAL_H_SHT) & FIMD_WPAL_W4PAL_H) |
            ((s->wpalcon[1] >> FIMD_WPAL_W4PAL_L_SHT) & FIMD_WPAL_W4PAL_L);
        break;
    default:
        hw_error("exynos4210.fimd: incorrect window number %d\n", window);
        ret = 0;
        break;
    }
    return ret;
}

#define FIMD_1_MINUS_COLOR(x)    \
            ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \
                                  (0xFF0000 - ((x) & 0xFF0000)))
#define EXTEND_LOWER_HALFBYTE(x) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0))
#define EXTEND_UPPER_HALFBYTE(x) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F))

/* Multiply three lower bytes of two 32-bit words with each other.
 * Each byte with values 0-255 is considered as a number with possible values
 * in a range [0 - 1] */
static inline uint32_t fimd_mult_each_byte(uint32_t a, uint32_t b)
{
    uint32_t tmp;
    uint32_t ret;

    ret = ((tmp = (((a & 0xFF) * (b & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp;
    ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF)) / 0xFF)) > 0xFF) ?
            0xFF00 : tmp << 8;
    ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
            0xFF0000 : tmp << 16;
    return ret;
}

/* For each corresponding bytes of two 32-bit words: (a*b + c*d)
 * Byte values 0-255 are mapped to a range [0 .. 1] */
static inline uint32_t
fimd_mult_and_sum_each_byte(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
{
    uint32_t tmp;
    uint32_t ret;

    ret = ((tmp = (((a & 0xFF) * (b & 0xFF) + (c & 0xFF) * (d & 0xFF)) / 0xFF))
            > 0xFF) ? 0xFF : tmp;
    ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF) + ((c >> 8) & 0xFF) *
            ((d >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp << 8;
    ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF) +
            ((c >> 16) & 0xFF) * ((d >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
                    0xFF0000 : tmp << 16;
    return ret;
}

/* These routines cover all possible sources of window's transparent factor
 * used in blending equation. Choice of routine is affected by WPALCON
 * registers, BLENDCON register and window's WINCON register */

static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow *w, uint32_t pix_a)
{
    return pix_a;
}

static uint32_t
fimd_get_alpha_pix_extlow(Exynos4210fimdWindow *w, uint32_t pix_a)
{
    return EXTEND_LOWER_HALFBYTE(pix_a);
}

static uint32_t
fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow *w, uint32_t pix_a)
{
    return EXTEND_UPPER_HALFBYTE(pix_a);
}

static uint32_t fimd_get_alpha_mult(Exynos4210fimdWindow *w, uint32_t pix_a)
{
    return fimd_mult_each_byte(pix_a, w->alpha_val[0]);
}

static uint32_t fimd_get_alpha_mult_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
{
    return fimd_mult_each_byte(EXTEND_LOWER_HALFBYTE(pix_a),
            EXTEND_UPPER_HALFBYTE(w->alpha_val[0]));
}

static uint32_t fimd_get_alpha_aen(Exynos4210fimdWindow *w, uint32_t pix_a)
{
    return w->alpha_val[pix_a];
}

static uint32_t fimd_get_alpha_aen_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
{
    return EXTEND_UPPER_HALFBYTE(w->alpha_val[pix_a]);
}

static uint32_t fimd_get_alpha_sel(Exynos4210fimdWindow *w, uint32_t pix_a)
{
    return w->alpha_val[(w->wincon & FIMD_WINCON_ALPHA_SEL) ? 1 : 0];
}

static uint32_t fimd_get_alpha_sel_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
{
    return EXTEND_UPPER_HALFBYTE(w->alpha_val[(w->wincon &
            FIMD_WINCON_ALPHA_SEL) ? 1 : 0]);
}

/* Updates currently active alpha value get function for specified window */
static void fimd_update_get_alpha(Exynos4210fimdState *s, int win)
{
    Exynos4210fimdWindow *w = &s->window[win];
    const bool alpha_is_8bit = s->blendcon & FIMD_ALPHA_8BIT;

    if (w->wincon & FIMD_WINCON_BLD_PIX) {
        if ((w->wincon & FIMD_WINCON_ALPHA_SEL) && WIN_BPP_MODE_WITH_ALPHA(w)) {
            /* In this case, alpha component contains meaningful value */
            if (w->wincon & FIMD_WINCON_ALPHA_MUL) {
                w->get_alpha = alpha_is_8bit ?
                        fimd_get_alpha_mult : fimd_get_alpha_mult_ext;
            } else {
                w->get_alpha = alpha_is_8bit ?
                        fimd_get_alpha_pix : fimd_get_alpha_pix_extlow;
            }
        } else {
            if (IS_PALETTIZED_MODE(w) &&
                  PAL_MODE_WITH_ALPHA(exynos4210_fimd_palette_format(s, win))) {
                /* Alpha component has 8-bit numeric value */
                w->get_alpha = alpha_is_8bit ?
                        fimd_get_alpha_pix : fimd_get_alpha_pix_exthigh;
            } else {
                /* Alpha has only two possible values (AEN) */
                w->get_alpha = alpha_is_8bit ?
                        fimd_get_alpha_aen : fimd_get_alpha_aen_ext;
            }
        }
    } else {
        w->get_alpha = alpha_is_8bit ? fimd_get_alpha_sel :
                fimd_get_alpha_sel_ext;
    }
}

/* Blends current window's (w) pixel (foreground pixel *ret) with background
 * window (w_blend) pixel p_bg according to formula:
 * NEW_COLOR = a_coef x FG_PIXEL_COLOR + b_coef x BG_PIXEL_COLOR
 * NEW_ALPHA = p_coef x FG_ALPHA + q_coef x BG_ALPHA
 */
static void
exynos4210_fimd_blend_pixel(Exynos4210fimdWindow *w, rgba p_bg, rgba *ret)
{
    rgba p_fg = *ret;
    uint32_t bg_color = ((p_bg.r & 0xFF) << 16) | ((p_bg.g & 0xFF) << 8) |
            (p_bg.b & 0xFF);
    uint32_t fg_color = ((p_fg.r & 0xFF) << 16) | ((p_fg.g & 0xFF) << 8) |
            (p_fg.b & 0xFF);
    uint32_t alpha_fg = p_fg.a;
    int i;
    /* It is possible that blending equation parameters a and b do not
     * depend on window BLENEQ register. Account for this with first_coef */
    enum { A_COEF = 0, B_COEF = 1, P_COEF = 2, Q_COEF = 3, COEF_NUM = 4};
    uint32_t first_coef = A_COEF;
    uint32_t blend_param[COEF_NUM];

    if (w->keycon[0] & FIMD_WKEYCON0_KEYEN) {
        uint32_t colorkey = (w->keycon[1] &
              ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) & FIMD_WKEYCON0_COMPKEY;

        if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) &&
            (bg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) {
            /* Foreground pixel is displayed */
            if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) {
                alpha_fg = w->keyalpha;
                blend_param[A_COEF] = alpha_fg;
                blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg);
            } else {
                alpha_fg = 0;
                blend_param[A_COEF] = 0xFFFFFF;
                blend_param[B_COEF] = 0x0;
            }
            first_coef = P_COEF;
        } else if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) == 0 &&
            (fg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) {
            /* Background pixel is displayed */
            if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) {
                alpha_fg = w->keyalpha;
                blend_param[A_COEF] = alpha_fg;
                blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg);
            } else {
                alpha_fg = 0;
                blend_param[A_COEF] = 0x0;
                blend_param[B_COEF] = 0xFFFFFF;
            }
            first_coef = P_COEF;
        }
    }

    for (i = first_coef; i < COEF_NUM; i++) {
        switch ((w->blendeq >> i * 6) & FIMD_BLENDEQ_COEF_MASK) {
        case 0:
            blend_param[i] = 0;
            break;
        case 1:
            blend_param[i] = 0xFFFFFF;
            break;
        case 2:
            blend_param[i] = alpha_fg;
            break;
        case 3:
            blend_param[i] = FIMD_1_MINUS_COLOR(alpha_fg);
            break;
        case 4:
            blend_param[i] = p_bg.a;
            break;
        case 5:
            blend_param[i] = FIMD_1_MINUS_COLOR(p_bg.a);
            break;
        case 6:
            blend_param[i] = w->alpha_val[0];
            break;
        case 10:
            blend_param[i] = fg_color;
            break;
        case 11:
            blend_param[i] = FIMD_1_MINUS_COLOR(fg_color);
            break;
        case 12:
            blend_param[i] = bg_color;
            break;
        case 13:
            blend_param[i] = FIMD_1_MINUS_COLOR(bg_color);
            break;
        default:
            hw_error("exynos4210.fimd: blend equation coef illegal value\n");
            break;
        }
    }

    fg_color = fimd_mult_and_sum_each_byte(bg_color, blend_param[B_COEF],
            fg_color, blend_param[A_COEF]);
    ret->b = fg_color & 0xFF;
    fg_color >>= 8;
    ret->g = fg_color & 0xFF;
    fg_color >>= 8;
    ret->r = fg_color & 0xFF;
    ret->a = fimd_mult_and_sum_each_byte(alpha_fg, blend_param[P_COEF],
            p_bg.a, blend_param[Q_COEF]);
}

/* These routines read data from video frame buffer in system RAM, convert
 * this data to display controller internal representation, if necessary,
 * perform pixel blending with data, currently presented in internal buffer.
 * Result is stored in display controller internal frame buffer. */

/* Draw line with index in palette table in RAM frame buffer data */
#define DEF_DRAW_LINE_PALETTE(N) \
static void glue(draw_line_palette_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
               uint8_t *dst, bool blend) \
{ \
    int width = w->rightbot_x - w->lefttop_x + 1; \
    uint8_t *ifb = dst; \
    uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
    uint64_t data; \
    rgba p, p_old; \
    int i; \
    do { \
        memcpy(&data, src, sizeof(data)); \
        src += 8; \
        fimd_swap_data(swap, &data); \
        for (i = (64 / (N) - 1); i >= 0; i--) { \
            w->pixel_to_rgb(w->palette[(data >> ((N) * i)) & \
                                   ((1ULL << (N)) - 1)], &p); \
            p.a = w->get_alpha(w, p.a); \
            if (blend) { \
                ifb +=  get_pixel_ifb(ifb, &p_old); \
                exynos4210_fimd_blend_pixel(w, p_old, &p); \
            } \
            dst += put_pixel_ifb(p, dst); \
        } \
        width -= (64 / (N)); \
    } while (width > 0); \
}

/* Draw line with direct color value in RAM frame buffer data */
#define DEF_DRAW_LINE_NOPALETTE(N) \
static void glue(draw_line_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
                    uint8_t *dst, bool blend) \
{ \
    int width = w->rightbot_x - w->lefttop_x + 1; \
    uint8_t *ifb = dst; \
    uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
    uint64_t data; \
    rgba p, p_old; \
    int i; \
    do { \
        memcpy(&data, src, sizeof(data)); \
        src += 8; \
        fimd_swap_data(swap, &data); \
        for (i = (64 / (N) - 1); i >= 0; i--) { \
            w->pixel_to_rgb((data >> ((N) * i)) & ((1ULL << (N)) - 1), &p); \
            p.a = w->get_alpha(w, p.a); \
            if (blend) { \
                ifb += get_pixel_ifb(ifb, &p_old); \
                exynos4210_fimd_blend_pixel(w, p_old, &p); \
            } \
            dst += put_pixel_ifb(p, dst); \
        } \
        width -= (64 / (N)); \
    } while (width > 0); \
}

DEF_DRAW_LINE_PALETTE(1)
DEF_DRAW_LINE_PALETTE(2)
DEF_DRAW_LINE_PALETTE(4)
DEF_DRAW_LINE_PALETTE(8)
DEF_DRAW_LINE_NOPALETTE(8)  /* 8bpp mode has palette and non-palette versions */
DEF_DRAW_LINE_NOPALETTE(16)
DEF_DRAW_LINE_NOPALETTE(32)

/* Special draw line routine for window color map case */
static void draw_line_mapcolor(Exynos4210fimdWindow *w, uint8_t *src,
                       uint8_t *dst, bool blend)
{
    rgba p, p_old;
    uint8_t *ifb = dst;
    int width = w->rightbot_x - w->lefttop_x + 1;
    uint32_t map_color = w->winmap & FIMD_WINMAP_COLOR_MASK;

    do {
        pixel_888_to_rgb(map_color, &p);
        p.a = w->get_alpha(w, p.a);
        if (blend) {
            ifb += get_pixel_ifb(ifb, &p_old);
            exynos4210_fimd_blend_pixel(w, p_old, &p);
        }
        dst += put_pixel_ifb(p, dst);
    } while (--width);
}

/* Write RGB to QEMU's GraphicConsole framebuffer */

static int put_to_qemufb_pixel8(const rgba p, uint8_t *d)
{
    uint32_t pixel = rgb_to_pixel8(p.r, p.g, p.b);
    *(uint8_t *)d = pixel;
    return 1;
}

static int put_to_qemufb_pixel15(const rgba p, uint8_t *d)
{
    uint32_t pixel = rgb_to_pixel15(p.r, p.g, p.b);
    *(uint16_t *)d = pixel;
    return 2;
}

static int put_to_qemufb_pixel16(const rgba p, uint8_t *d)
{
    uint32_t pixel = rgb_to_pixel16(p.r, p.g, p.b);
    *(uint16_t *)d = pixel;
    return 2;
}

static int put_to_qemufb_pixel24(const rgba p, uint8_t *d)
{
    uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
    *(uint8_t *)d++ = (pixel >>  0) & 0xFF;
    *(uint8_t *)d++ = (pixel >>  8) & 0xFF;
    *(uint8_t *)d++ = (pixel >> 16) & 0xFF;
    return 3;
}

static int put_to_qemufb_pixel32(const rgba p, uint8_t *d)
{
    uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
    *(uint32_t *)d = pixel;
    return 4;
}

/* Routine to copy pixel from internal buffer to QEMU buffer */
static int (*put_pixel_toqemu)(const rgba p, uint8_t *pixel);
static inline void fimd_update_putpix_qemu(int bpp)
{
    switch (bpp) {
    case 8:
        put_pixel_toqemu = put_to_qemufb_pixel8;
        break;
    case 15:
        put_pixel_toqemu = put_to_qemufb_pixel15;
        break;
    case 16:
        put_pixel_toqemu = put_to_qemufb_pixel16;
        break;
    case 24:
        put_pixel_toqemu = put_to_qemufb_pixel24;
        break;
    case 32:
        put_pixel_toqemu = put_to_qemufb_pixel32;
        break;
    default:
        hw_error("exynos4210.fimd: unsupported BPP (%d)", bpp);
        break;
    }
}

/* Routine to copy a line from internal frame buffer to QEMU display */
static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst)
{
    rgba p;

    do {
        src += get_pixel_ifb(src, &p);
        dst += put_pixel_toqemu(p, dst);
    } while (--width);
}

/* Parse BPPMODE_F = WINCON1[5:2] bits */
static void exynos4210_fimd_update_win_bppmode(Exynos4210fimdState *s, int win)
{
    Exynos4210fimdWindow *w = &s->window[win];

    if (w->winmap & FIMD_WINMAP_EN) {
        w->draw_line = draw_line_mapcolor;
        return;
    }

    switch (WIN_BPP_MODE(w)) {
    case 0:
        w->draw_line = draw_line_palette_1;
        w->pixel_to_rgb =
                palette_data_format[exynos4210_fimd_palette_format(s, win)];
        break;
    case 1:
        w->draw_line = draw_line_palette_2;
        w->pixel_to_rgb =
                palette_data_format[exynos4210_fimd_palette_format(s, win)];
        break;
    case 2:
        w->draw_line = draw_line_palette_4;
        w->pixel_to_rgb =
                palette_data_format[exynos4210_fimd_palette_format(s, win)];
        break;
    case 3:
        w->draw_line = draw_line_palette_8;
        w->pixel_to_rgb =
                palette_data_format[exynos4210_fimd_palette_format(s, win)];
        break;
    case 4:
        w->draw_line = draw_line_8;
        w->pixel_to_rgb = pixel_a232_to_rgb;
        break;
    case 5:
        w->draw_line = draw_line_16;
        w->pixel_to_rgb = pixel_565_to_rgb;
        break;
    case 6:
        w->draw_line = draw_line_16;
        w->pixel_to_rgb = pixel_a555_to_rgb;
        break;
    case 7:
        w->draw_line = draw_line_16;
        w->pixel_to_rgb = pixel_1555_to_rgb;
        break;
    case 8:
        w->draw_line = draw_line_32;
        w->pixel_to_rgb = pixel_666_to_rgb;
        break;
    case 9:
        w->draw_line = draw_line_32;
        w->pixel_to_rgb = pixel_a665_to_rgb;
        break;
    case 10:
        w->draw_line = draw_line_32;
        w->pixel_to_rgb = pixel_a666_to_rgb;
        break;
    case 11:
        w->draw_line = draw_line_32;
        w->pixel_to_rgb = pixel_888_to_rgb;
        break;
    case 12:
        w->draw_line = draw_line_32;
        w->pixel_to_rgb = pixel_a887_to_rgb;
        break;
    case 13:
        w->draw_line = draw_line_32;
        if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon &
                FIMD_WINCON_ALPHA_SEL)) {
            w->pixel_to_rgb = pixel_8888_to_rgb;
        } else {
            w->pixel_to_rgb = pixel_a888_to_rgb;
        }
        break;
    case 14:
        w->draw_line = draw_line_16;
        if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon &
                FIMD_WINCON_ALPHA_SEL)) {
            w->pixel_to_rgb = pixel_4444_to_rgb;
        } else {
            w->pixel_to_rgb = pixel_a444_to_rgb;
        }
        break;
    case 15:
        w->draw_line = draw_line_16;
        w->pixel_to_rgb = pixel_555_to_rgb;
        break;
    }
}

#if EXYNOS4210_FIMD_MODE_TRACE > 0
static const char *exynos4210_fimd_get_bppmode(int mode_code)
{
    switch (mode_code) {
    case 0:
        return "1 bpp";
    case 1:
        return "2 bpp";
    case 2:
        return "4 bpp";
    case 3:
        return "8 bpp (palettized)";
    case 4:
        return "8 bpp (non-palettized, A: 1-R:2-G:3-B:2)";
    case 5:
        return "16 bpp (non-palettized, R:5-G:6-B:5)";
    case 6:
        return "16 bpp (non-palettized, A:1-R:5-G:5-B:5)";
    case 7:
        return "16 bpp (non-palettized, I :1-R:5-G:5-B:5)";
    case 8:
        return "Unpacked 18 bpp (non-palettized, R:6-G:6-B:6)";
    case 9:
        return "Unpacked 18bpp (non-palettized,A:1-R:6-G:6-B:5)";
    case 10:
        return "Unpacked 19bpp (non-palettized,A:1-R:6-G:6-B:6)";
    case 11:
        return "Unpacked 24 bpp (non-palettized R:8-G:8-B:8)";
    case 12:
        return "Unpacked 24 bpp (non-palettized A:1-R:8-G:8-B:7)";
    case 13:
        return "Unpacked 25 bpp (non-palettized A:1-R:8-G:8-B:8)";
    case 14:
        return "Unpacked 13 bpp (non-palettized A:1-R:4-G:4-B:4)";
    case 15:
        return "Unpacked 15 bpp (non-palettized R:5-G:5-B:5)";
    default:
        return "Non-existing bpp mode";
    }
}

static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
                int win_num, uint32_t val)
{
    Exynos4210fimdWindow *w = &s->window[win_num];

    if (w->winmap & FIMD_WINMAP_EN) {
        printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n",
                win_num, w->winmap & 0xFFFFFF);
        return;
    }

    if ((val != 0xFFFFFFFF) && ((w->wincon >> 2) & 0xF) == ((val >> 2) & 0xF)) {
        return;
    }
    printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num,
        exynos4210_fimd_get_bppmode((val >> 2) & 0xF));
}
#else
static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
        int win_num, uint32_t val)
{

}
#endif

static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
{
    switch (w->wincon & FIMD_WINCON_BUFSTATUS) {
    case FIMD_WINCON_BUF0_STAT:
        return 0;
    case FIMD_WINCON_BUF1_STAT:
        return 1;
    case FIMD_WINCON_BUF2_STAT:
        return 2;
    default:
        DPRINT_ERROR("Non-existent buffer index\n");
        return 0;
    }
}

/* Updates specified window's MemorySection based on values of WINCON,
 * VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */
static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
{
    Exynos4210fimdWindow *w = &s->window[win];
    hwaddr fb_start_addr, fb_mapped_len;

    if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) ||
            FIMD_WINDOW_PROTECTED(s->shadowcon, win)) {
        return;
    }

    if (w->host_fb_addr) {
        cpu_physical_memory_unmap(w->host_fb_addr, w->fb_len, 0, 0);
        w->host_fb_addr = NULL;
        w->fb_len = 0;
    }

    fb_start_addr = w->buf_start[fimd_get_buffer_id(w)];
    /* Total number of bytes of virtual screen used by current window */
    w->fb_len = fb_mapped_len = (w->virtpage_width + w->virtpage_offsize) *
            (w->rightbot_y - w->lefttop_y + 1);
    w->mem_section = memory_region_find(sysbus_address_space(&s->busdev),
            fb_start_addr, w->fb_len);
    assert(w->mem_section.mr);
    assert(w->mem_section.offset_within_address_space == fb_start_addr);
    DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n",
            win, fb_start_addr, w->fb_len);

    if (w->mem_section.size != w->fb_len ||
            !memory_region_is_ram(w->mem_section.mr)) {
        DPRINT_ERROR("Failed to find window %u framebuffer region\n", win);
        goto error_return;
    }

    w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, 0);
    if (!w->host_fb_addr) {
        DPRINT_ERROR("Failed to map window %u framebuffer\n", win);
        goto error_return;
    }

    if (fb_mapped_len != w->fb_len) {
        DPRINT_ERROR("Window %u mapped framebuffer length is less then "
                "expected\n", win);
        cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0);
        goto error_return;
    }
    return;

error_return:
    w->mem_section.mr = NULL;
    w->mem_section.size = 0;
    w->host_fb_addr = NULL;
    w->fb_len = 0;
}

static void exynos4210_fimd_enable(Exynos4210fimdState *s, bool enabled)
{
    if (enabled && !s->enabled) {
        unsigned w;
        s->enabled = true;
        for (w = 0; w < NUM_OF_WINDOWS; w++) {
            fimd_update_memory_section(s, w);
        }
    }
    s->enabled = enabled;
    DPRINT_TRACE("display controller %s\n", enabled ? "enabled" : "disabled");
}

static inline uint32_t unpack_upper_4(uint32_t x)
{
    return ((x & 0xF00) << 12) | ((x & 0xF0) << 8) | ((x & 0xF) << 4);
}

static inline uint32_t pack_upper_4(uint32_t x)
{
    return (((x & 0xF00000) >> 12) | ((x & 0xF000) >> 8) |
            ((x & 0xF0) >> 4)) & 0xFFF;
}

static void exynos4210_fimd_update_irq(Exynos4210fimdState *s)
{
    if (!(s->vidintcon[0] & FIMD_VIDINT_INTEN)) {
        qemu_irq_lower(s->irq[0]);
        qemu_irq_lower(s->irq[1]);
        qemu_irq_lower(s->irq[2]);
        return;
    }
    if ((s->vidintcon[0] & FIMD_VIDINT_INTFIFOEN) &&
            (s->vidintcon[1] & FIMD_VIDINT_INTFIFOPEND)) {
        qemu_irq_raise(s->irq[0]);
    } else {
        qemu_irq_lower(s->irq[0]);
    }
    if ((s->vidintcon[0] & FIMD_VIDINT_INTFRMEN) &&
            (s->vidintcon[1] & FIMD_VIDINT_INTFRMPEND)) {
        qemu_irq_raise(s->irq[1]);
    } else {
        qemu_irq_lower(s->irq[1]);
    }
    if ((s->vidintcon[0] & FIMD_VIDINT_I80IFDONE) &&
            (s->vidintcon[1] & FIMD_VIDINT_INTI80PEND)) {
        qemu_irq_raise(s->irq[2]);
    } else {
        qemu_irq_lower(s->irq[2]);
    }
}

static void exynos4210_fimd_invalidate(void *opaque)
{
    Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
    s->invalidate = true;
}

static void exynos4210_update_resolution(Exynos4210fimdState *s)
{
    DisplaySurface *surface = qemu_console_surface(s->console);

    /* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */
    uint32_t width = ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT) &
            FIMD_VIDTCON2_SIZE_MASK) + 1;
    uint32_t height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) &
            FIMD_VIDTCON2_SIZE_MASK) + 1;

    if (s->ifb == NULL || surface_width(surface) != width ||
            surface_height(surface) != height) {
        DPRINT_L1("Resolution changed from %ux%u to %ux%u\n",
           surface_width(surface), surface_height(surface), width, height);
        qemu_console_resize(s->console, width, height);
        s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE + 1);
        memset(s->ifb, 0, width * height * RGBA_SIZE + 1);
        exynos4210_fimd_invalidate(s);
    }
}

static void exynos4210_fimd_update(void *opaque)
{
    Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
    DisplaySurface *surface;
    Exynos4210fimdWindow *w;
    int i, line;
    hwaddr fb_line_addr, inc_size;
    int scrn_height;
    int first_line = -1, last_line = -1, scrn_width;
    bool blend = false;
    uint8_t *host_fb_addr;
    bool is_dirty = false;
    const int global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
    const int global_height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) &
            FIMD_VIDTCON2_SIZE_MASK) + 1;

    if (!s || !s->console || !s->enabled ||
        surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) {
        return;
    }
    exynos4210_update_resolution(s);
    surface = qemu_console_surface(s->console);

    for (i = 0; i < NUM_OF_WINDOWS; i++) {
        w = &s->window[i];
        if ((w->wincon & FIMD_WINCON_ENWIN) && w->host_fb_addr) {
            scrn_height = w->rightbot_y - w->lefttop_y + 1;
            scrn_width = w->virtpage_width;
            /* Total width of virtual screen page in bytes */
            inc_size = scrn_width + w->virtpage_offsize;
            memory_region_sync_dirty_bitmap(w->mem_section.mr);
            host_fb_addr = w->host_fb_addr;
            fb_line_addr = w->mem_section.offset_within_region;

            for (line = 0; line < scrn_height; line++) {
                is_dirty = memory_region_get_dirty(w->mem_section.mr,
                            fb_line_addr, scrn_width, DIRTY_MEMORY_VGA);

                if (s->invalidate || is_dirty) {
                    if (first_line == -1) {
                        first_line = line;
                    }
                    last_line = line;
                    w->draw_line(w, host_fb_addr, s->ifb +
                        w->lefttop_x * RGBA_SIZE + (w->lefttop_y + line) *
                        global_width * RGBA_SIZE, blend);
                }
                host_fb_addr += inc_size;
                fb_line_addr += inc_size;
                is_dirty = false;
            }
            memory_region_reset_dirty(w->mem_section.mr,
                w->mem_section.offset_within_region,
                w->fb_len, DIRTY_MEMORY_VGA);
            blend = true;
        }
    }

    /* Copy resulting image to QEMU_CONSOLE. */
    if (first_line >= 0) {
        uint8_t *d;
        int bpp;

        bpp = surface_bits_per_pixel(surface);
        fimd_update_putpix_qemu(bpp);
        bpp = (bpp + 1) >> 3;
        d = surface_data(surface);
        for (line = first_line; line <= last_line; line++) {
            fimd_copy_line_toqemu(global_width, s->ifb + global_width * line *
                    RGBA_SIZE, d + global_width * line * bpp);
        }
        dpy_gfx_update(s->console, 0, 0, global_width, global_height);
    }
    s->invalidate = false;
    s->vidintcon[1] |= FIMD_VIDINT_INTFRMPEND;
    if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F) == 0) {
        exynos4210_fimd_enable(s, false);
    }
    exynos4210_fimd_update_irq(s);
}

static void exynos4210_fimd_reset(DeviceState *d)
{
    Exynos4210fimdState *s = DO_UPCAST(Exynos4210fimdState, busdev.qdev, d);
    unsigned w;

    DPRINT_TRACE("Display controller reset\n");
    /* Set all display controller registers to 0 */
    memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon);
    for (w = 0; w < NUM_OF_WINDOWS; w++) {
        memset(&s->window[w], 0, sizeof(Exynos4210fimdWindow));
        s->window[w].blendeq = 0xC2;
        exynos4210_fimd_update_win_bppmode(s, w);
        exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
        fimd_update_get_alpha(s, w);
    }

    if (s->ifb != NULL) {
        g_free(s->ifb);
    }
    s->ifb = NULL;

    exynos4210_fimd_invalidate(s);
    exynos4210_fimd_enable(s, false);
    /* Some registers have non-zero initial values */
    s->winchmap = 0x7D517D51;
    s->colorgaincon = 0x10040100;
    s->huecoef_cr[0] = s->huecoef_cr[3] = 0x01000100;
    s->huecoef_cb[0] = s->huecoef_cb[3] = 0x01000100;
    s->hueoffset = 0x01800080;
}

static void exynos4210_fimd_write(void *opaque, hwaddr offset,
                              uint64_t val, unsigned size)
{
    Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
    unsigned w, i;
    uint32_t old_value;

    DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset,
            (long long unsigned int)val, (long long unsigned int)val);

    switch (offset) {
    case FIMD_VIDCON0:
        if ((val & FIMD_VIDCON0_ENVID_MASK) == FIMD_VIDCON0_ENVID_MASK) {
            exynos4210_fimd_enable(s, true);
        } else {
            if ((val & FIMD_VIDCON0_ENVID) == 0) {
                exynos4210_fimd_enable(s, false);
            }
        }
        s->vidcon[0] = val;
        break;
    case FIMD_VIDCON1:
        /* Leave read-only bits as is */
        val = (val & (~FIMD_VIDCON1_ROMASK)) |
                (s->vidcon[1] & FIMD_VIDCON1_ROMASK);
        s->vidcon[1] = val;
        break;
    case FIMD_VIDCON2 ... FIMD_VIDCON3:
        s->vidcon[(offset) >> 2] = val;
        break;
    case FIMD_VIDTCON_START ... FIMD_VIDTCON_END:
        s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2] = val;
        break;
    case FIMD_WINCON_START ... FIMD_WINCON_END:
        w = (offset - FIMD_WINCON_START) >> 2;
        /* Window's current buffer ID */
        i = fimd_get_buffer_id(&s->window[w]);
        old_value = s->window[w].wincon;
        val = (val & ~FIMD_WINCON_ROMASK) |
                (s->window[w].wincon & FIMD_WINCON_ROMASK);
        if (w == 0) {
            /* Window 0 wincon ALPHA_MUL bit must always be 0 */
            val &= ~FIMD_WINCON_ALPHA_MUL;
        }
        exynos4210_fimd_trace_bppmode(s, w, val);
        switch (val & FIMD_WINCON_BUFSELECT) {
        case FIMD_WINCON_BUF0_SEL:
            val &= ~FIMD_WINCON_BUFSTATUS;
            break;
        case FIMD_WINCON_BUF1_SEL:
            val = (val & ~FIMD_WINCON_BUFSTAT_H) | FIMD_WINCON_BUFSTAT_L;
            break;
        case FIMD_WINCON_BUF2_SEL:
            if (val & FIMD_WINCON_BUFMODE) {
                val = (val & ~FIMD_WINCON_BUFSTAT_L) | FIMD_WINCON_BUFSTAT_H;
            }
            break;
        default:
            break;
        }
        s->window[w].wincon = val;
        exynos4210_fimd_update_win_bppmode(s, w);
        fimd_update_get_alpha(s, w);
        if ((i != fimd_get_buffer_id(&s->window[w])) ||
                (!(old_value & FIMD_WINCON_ENWIN) && (s->window[w].wincon &
                        FIMD_WINCON_ENWIN))) {
            fimd_update_memory_section(s, w);
        }
        break;
    case FIMD_SHADOWCON:
        old_value = s->shadowcon;
        s->shadowcon = val;
        for (w = 0; w < NUM_OF_WINDOWS; w++) {
            if (FIMD_WINDOW_PROTECTED(old_value, w) &&
                    !FIMD_WINDOW_PROTECTED(s->shadowcon, w)) {
                fimd_update_memory_section(s, w);
            }
        }
        break;
    case FIMD_WINCHMAP:
        s->winchmap = val;
        break;
    case FIMD_VIDOSD_START ... FIMD_VIDOSD_END:
        w = (offset - FIMD_VIDOSD_START) >> 4;
        i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2;
        switch (i) {
        case 0:
            old_value = s->window[w].lefttop_y;
            s->window[w].lefttop_x = (val >> FIMD_VIDOSD_HOR_SHIFT) &
                                      FIMD_VIDOSD_COORD_MASK;
            s->window[w].lefttop_y = (val >> FIMD_VIDOSD_VER_SHIFT) &
                                      FIMD_VIDOSD_COORD_MASK;
            if (s->window[w].lefttop_y != old_value) {
                fimd_update_memory_section(s, w);
            }
            break;
        case 1:
            old_value = s->window[w].rightbot_y;
            s->window[w].rightbot_x = (val >> FIMD_VIDOSD_HOR_SHIFT) &
                                       FIMD_VIDOSD_COORD_MASK;
            s->window[w].rightbot_y = (val >> FIMD_VIDOSD_VER_SHIFT) &
                                       FIMD_VIDOSD_COORD_MASK;
            if (s->window[w].rightbot_y != old_value) {
                fimd_update_memory_section(s, w);
            }
            break;
        case 2:
            if (w == 0) {
                s->window[w].osdsize = val;
            } else {
                s->window[w].alpha_val[0] =
                    unpack_upper_4((val & FIMD_VIDOSD_ALPHA_AEN0) >>
                    FIMD_VIDOSD_AEN0_SHIFT) |
                    (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER);
                s->window[w].alpha_val[1] =
                    unpack_upper_4(val & FIMD_VIDOSD_ALPHA_AEN1) |
                    (s->window[w].alpha_val[1] & FIMD_VIDALPHA_ALPHA_LOWER);
            }
            break;
        case 3:
            if (w != 1 && w != 2) {
                DPRINT_ERROR("Bad write offset 0x%08x\n", offset);
                return;
            }
            s->window[w].osdsize = val;
            break;
        }
        break;
    case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END:
        w = (offset - FIMD_VIDWADD0_START) >> 3;
        i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1;
        if (i == fimd_get_buffer_id(&s->window[w]) &&
                s->window[w].buf_start[i] != val) {
            s->window[w].buf_start[i] = val;
            fimd_update_memory_section(s, w);
            break;
        }
        s->window[w].buf_start[i] = val;
        break;
    case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END:
        w = (offset - FIMD_VIDWADD1_START) >> 3;
        i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1;
        s->window[w].buf_end[i] = val;
        break;
    case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END:
        w = (offset - FIMD_VIDWADD2_START) >> 2;
        if (((val & FIMD_VIDWADD2_PAGEWIDTH) != s->window[w].virtpage_width) ||
            (((val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE) !=
                        s->window[w].virtpage_offsize)) {
            s->window[w].virtpage_width = val & FIMD_VIDWADD2_PAGEWIDTH;
            s->window[w].virtpage_offsize =
                (val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE;
            fimd_update_memory_section(s, w);
        }
        break;
    case FIMD_VIDINTCON0:
        s->vidintcon[0] = val;
        break;
    case FIMD_VIDINTCON1:
        s->vidintcon[1] &= ~(val & 7);
        exynos4210_fimd_update_irq(s);
        break;
    case FIMD_WKEYCON_START ... FIMD_WKEYCON_END:
        w = ((offset - FIMD_WKEYCON_START) >> 3) + 1;
        i = ((offset - FIMD_WKEYCON_START) >> 2) & 1;
        s->window[w].keycon[i] = val;
        break;
    case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END:
        w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1;
        s->window[w].keyalpha = val;
        break;
    case FIMD_DITHMODE:
        s->dithmode = val;
        break;
    case FIMD_WINMAP_START ... FIMD_WINMAP_END:
        w = (offset - FIMD_WINMAP_START) >> 2;
        old_value = s->window[w].winmap;
        s->window[w].winmap = val;
        if ((val & FIMD_WINMAP_EN) ^ (old_value & FIMD_WINMAP_EN)) {
            exynos4210_fimd_invalidate(s);
            exynos4210_fimd_update_win_bppmode(s, w);
            exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
            exynos4210_fimd_update(s);
        }
        break;
    case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW:
        i = (offset - FIMD_WPALCON_HIGH) >> 2;
        s->wpalcon[i] = val;
        if (s->wpalcon[1] & FIMD_WPALCON_UPDATEEN) {
            for (w = 0; w < NUM_OF_WINDOWS; w++) {
                exynos4210_fimd_update_win_bppmode(s, w);
                fimd_update_get_alpha(s, w);
            }
        }
        break;
    case FIMD_TRIGCON:
        val = (val & ~FIMD_TRIGCON_ROMASK) | (s->trigcon & FIMD_TRIGCON_ROMASK);
        s->trigcon = val;
        break;
    case FIMD_I80IFCON_START ... FIMD_I80IFCON_END:
        s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2] = val;
        break;
    case FIMD_COLORGAINCON:
        s->colorgaincon = val;
        break;
    case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1:
        s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2] = val;
        break;
    case FIMD_SIFCCON0 ... FIMD_SIFCCON2:
        i = (offset - FIMD_SIFCCON0) >> 2;
        if (i != 2) {
            s->sifccon[i] = val;
        }
        break;
    case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END:
        i = (offset - FIMD_HUECOEFCR_START) >> 2;
        s->huecoef_cr[i] = val;
        break;
    case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END:
        i = (offset - FIMD_HUECOEFCB_START) >> 2;
        s->huecoef_cb[i] = val;
        break;
    case FIMD_HUEOFFSET:
        s->hueoffset = val;
        break;
    case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END:
        w = ((offset - FIMD_VIDWALPHA_START) >> 3);
        i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1;
        if (w == 0) {
            s->window[w].alpha_val[i] = val;
        } else {
            s->window[w].alpha_val[i] = (val & FIMD_VIDALPHA_ALPHA_LOWER) |
                (s->window[w].alpha_val[i] & FIMD_VIDALPHA_ALPHA_UPPER);
        }
        break;
    case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END:
        s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq = val;
        break;
    case FIMD_BLENDCON:
        old_value = s->blendcon;
        s->blendcon = val;
        if ((s->blendcon & FIMD_ALPHA_8BIT) != (old_value & FIMD_ALPHA_8BIT)) {
            for (w = 0; w < NUM_OF_WINDOWS; w++) {
                fimd_update_get_alpha(s, w);
            }
        }
        break;
    case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END:
        s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon = val;
        break;
    case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END:
        s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2] = val;
        break;
    case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
        if (offset & 0x0004) {
            DPRINT_ERROR("bad write offset 0x%08x\n", offset);
            break;
        }
        w = (offset - FIMD_VIDW0ADD0_B2) >> 3;
        if (fimd_get_buffer_id(&s->window[w]) == 2 &&
                s->window[w].buf_start[2] != val) {
            s->window[w].buf_start[2] = val;
            fimd_update_memory_section(s, w);
            break;
        }
        s->window[w].buf_start[2] = val;
        break;
    case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
        if (offset & 0x0004) {
            DPRINT_ERROR("bad write offset 0x%08x\n", offset);
            break;
        }
        s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start = val;
        break;
    case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
        if (offset & 0x0004) {
            DPRINT_ERROR("bad write offset 0x%08x\n", offset);
            break;
        }
        s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end = val;
        break;
    case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END:
        s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size = val;
        break;
    case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END:
        w = (offset - FIMD_PAL_MEM_START) >> 10;
        i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF;
        s->window[w].palette[i] = val;
        break;
    case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END:
        /* Palette memory aliases for windows 0 and 1 */
        w = (offset - FIMD_PALMEM_AL_START) >> 10;
        i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF;
        s->window[w].palette[i] = val;
        break;
    default:
        DPRINT_ERROR("bad write offset 0x%08x\n", offset);
        break;
    }
}

static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
                                  unsigned size)
{
    Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
    int w, i;
    uint32_t ret = 0;

    DPRINT_L2("read offset 0x%08x\n", offset);

    switch (offset) {
    case FIMD_VIDCON0 ... FIMD_VIDCON3:
        return s->vidcon[(offset - FIMD_VIDCON0) >> 2];
    case FIMD_VIDTCON_START ... FIMD_VIDTCON_END:
        return s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2];
    case FIMD_WINCON_START ... FIMD_WINCON_END:
        return s->window[(offset - FIMD_WINCON_START) >> 2].wincon;
    case FIMD_SHADOWCON:
        return s->shadowcon;
    case FIMD_WINCHMAP:
        return s->winchmap;
    case FIMD_VIDOSD_START ... FIMD_VIDOSD_END:
        w = (offset - FIMD_VIDOSD_START) >> 4;
        i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2;
        switch (i) {
        case 0:
            ret = ((s->window[w].lefttop_x & FIMD_VIDOSD_COORD_MASK) <<
            FIMD_VIDOSD_HOR_SHIFT) |
            (s->window[w].lefttop_y & FIMD_VIDOSD_COORD_MASK);
            break;
        case 1:
            ret = ((s->window[w].rightbot_x & FIMD_VIDOSD_COORD_MASK) <<
                FIMD_VIDOSD_HOR_SHIFT) |
                (s->window[w].rightbot_y & FIMD_VIDOSD_COORD_MASK);
            break;
        case 2:
            if (w == 0) {
                ret = s->window[w].osdsize;
            } else {
                ret = (pack_upper_4(s->window[w].alpha_val[0]) <<
                    FIMD_VIDOSD_AEN0_SHIFT) |
                    pack_upper_4(s->window[w].alpha_val[1]);
            }
            break;
        case 3:
            if (w != 1 && w != 2) {
                DPRINT_ERROR("bad read offset 0x%08x\n", offset);
                return 0xBAADBAAD;
            }
            ret = s->window[w].osdsize;
            break;
        }
        return ret;
    case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END:
        w = (offset - FIMD_VIDWADD0_START) >> 3;
        i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1;
        return s->window[w].buf_start[i];
    case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END:
        w = (offset - FIMD_VIDWADD1_START) >> 3;
        i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1;
        return s->window[w].buf_end[i];
    case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END:
        w = (offset - FIMD_VIDWADD2_START) >> 2;
        return s->window[w].virtpage_width | (s->window[w].virtpage_offsize <<
            FIMD_VIDWADD2_OFFSIZE_SHIFT);
    case FIMD_VIDINTCON0 ... FIMD_VIDINTCON1:
        return s->vidintcon[(offset - FIMD_VIDINTCON0) >> 2];
    case FIMD_WKEYCON_START ... FIMD_WKEYCON_END:
        w = ((offset - FIMD_WKEYCON_START) >> 3) + 1;
        i = ((offset - FIMD_WKEYCON_START) >> 2) & 1;
        return s->window[w].keycon[i];
    case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END:
        w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1;
        return s->window[w].keyalpha;
    case FIMD_DITHMODE:
        return s->dithmode;
    case FIMD_WINMAP_START ... FIMD_WINMAP_END:
        return s->window[(offset - FIMD_WINMAP_START) >> 2].winmap;
    case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW:
        return s->wpalcon[(offset - FIMD_WPALCON_HIGH) >> 2];
    case FIMD_TRIGCON:
        return s->trigcon;
    case FIMD_I80IFCON_START ... FIMD_I80IFCON_END:
        return s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2];
    case FIMD_COLORGAINCON:
        return s->colorgaincon;
    case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1:
        return s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2];
    case FIMD_SIFCCON0 ... FIMD_SIFCCON2:
        i = (offset - FIMD_SIFCCON0) >> 2;
        return s->sifccon[i];
    case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END:
        i = (offset - FIMD_HUECOEFCR_START) >> 2;
        return s->huecoef_cr[i];
    case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END:
        i = (offset - FIMD_HUECOEFCB_START) >> 2;
        return s->huecoef_cb[i];
    case FIMD_HUEOFFSET:
        return s->hueoffset;
    case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END:
        w = ((offset - FIMD_VIDWALPHA_START) >> 3);
        i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1;
        return s->window[w].alpha_val[i] &
                (w == 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER);
    case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END:
        return s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq;
    case FIMD_BLENDCON:
        return s->blendcon;
    case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END:
        return s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon;
    case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END:
        return s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2];
    case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
        if (offset & 0x0004) {
            break;
        }
        return s->window[(offset - FIMD_VIDW0ADD0_B2) >> 3].buf_start[2];
    case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
        if (offset & 0x0004) {
            break;
        }
        return s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start;
    case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
        if (offset & 0x0004) {
            break;
        }
        return s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end;
    case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END:
        return s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size;
    case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END:
        w = (offset - FIMD_PAL_MEM_START) >> 10;
        i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF;
        return s->window[w].palette[i];
    case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END:
        /* Palette aliases for win 0,1 */
        w = (offset - FIMD_PALMEM_AL_START) >> 10;
        i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF;
        return s->window[w].palette[i];
    }

    DPRINT_ERROR("bad read offset 0x%08x\n", offset);
    return 0xBAADBAAD;
}

static const MemoryRegionOps exynos4210_fimd_mmio_ops = {
    .read = exynos4210_fimd_read,
    .write = exynos4210_fimd_write,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
        .unaligned = false
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int exynos4210_fimd_load(void *opaque, int version_id)
{
    Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
    int w;

    if (version_id != 1) {
        return -EINVAL;
    }

    for (w = 0; w < NUM_OF_WINDOWS; w++) {
        exynos4210_fimd_update_win_bppmode(s, w);
        fimd_update_get_alpha(s, w);
        fimd_update_memory_section(s, w);
    }

    /* Redraw the whole screen */
    exynos4210_update_resolution(s);
    exynos4210_fimd_invalidate(s);
    exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK) ==
            FIMD_VIDCON0_ENVID_MASK);
    return 0;
}

static const VMStateDescription exynos4210_fimd_window_vmstate = {
    .name = "exynos4210.fimd_window",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(wincon, Exynos4210fimdWindow),
        VMSTATE_UINT32_ARRAY(buf_start, Exynos4210fimdWindow, 3),
        VMSTATE_UINT32_ARRAY(buf_end, Exynos4210fimdWindow, 3),
        VMSTATE_UINT32_ARRAY(keycon, Exynos4210fimdWindow, 2),
        VMSTATE_UINT32(keyalpha, Exynos4210fimdWindow),
        VMSTATE_UINT32(winmap, Exynos4210fimdWindow),
        VMSTATE_UINT32(blendeq, Exynos4210fimdWindow),
        VMSTATE_UINT32(rtqoscon, Exynos4210fimdWindow),
        VMSTATE_UINT32_ARRAY(palette, Exynos4210fimdWindow, 256),
        VMSTATE_UINT32(shadow_buf_start, Exynos4210fimdWindow),
        VMSTATE_UINT32(shadow_buf_end, Exynos4210fimdWindow),
        VMSTATE_UINT32(shadow_buf_size, Exynos4210fimdWindow),
        VMSTATE_UINT16(lefttop_x, Exynos4210fimdWindow),
        VMSTATE_UINT16(lefttop_y, Exynos4210fimdWindow),
        VMSTATE_UINT16(rightbot_x, Exynos4210fimdWindow),
        VMSTATE_UINT16(rightbot_y, Exynos4210fimdWindow),
        VMSTATE_UINT32(osdsize, Exynos4210fimdWindow),
        VMSTATE_UINT32_ARRAY(alpha_val, Exynos4210fimdWindow, 2),
        VMSTATE_UINT16(virtpage_width, Exynos4210fimdWindow),
        VMSTATE_UINT16(virtpage_offsize, Exynos4210fimdWindow),
        VMSTATE_END_OF_LIST()
    }
};

static const VMStateDescription exynos4210_fimd_vmstate = {
    .name = "exynos4210.fimd",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = exynos4210_fimd_load,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(vidcon, Exynos4210fimdState, 4),
        VMSTATE_UINT32_ARRAY(vidtcon, Exynos4210fimdState, 4),
        VMSTATE_UINT32(shadowcon, Exynos4210fimdState),
        VMSTATE_UINT32(winchmap, Exynos4210fimdState),
        VMSTATE_UINT32_ARRAY(vidintcon, Exynos4210fimdState, 2),
        VMSTATE_UINT32(dithmode, Exynos4210fimdState),
        VMSTATE_UINT32_ARRAY(wpalcon, Exynos4210fimdState, 2),
        VMSTATE_UINT32(trigcon, Exynos4210fimdState),
        VMSTATE_UINT32_ARRAY(i80ifcon, Exynos4210fimdState, 4),
        VMSTATE_UINT32(colorgaincon, Exynos4210fimdState),
        VMSTATE_UINT32_ARRAY(ldi_cmdcon, Exynos4210fimdState, 2),
        VMSTATE_UINT32_ARRAY(sifccon, Exynos4210fimdState, 3),
        VMSTATE_UINT32_ARRAY(huecoef_cr, Exynos4210fimdState, 4),
        VMSTATE_UINT32_ARRAY(huecoef_cb, Exynos4210fimdState, 4),
        VMSTATE_UINT32(hueoffset, Exynos4210fimdState),
        VMSTATE_UINT32_ARRAY(i80ifcmd, Exynos4210fimdState, 12),
        VMSTATE_UINT32(blendcon, Exynos4210fimdState),
        VMSTATE_STRUCT_ARRAY(window, Exynos4210fimdState, 5, 1,
                exynos4210_fimd_window_vmstate, Exynos4210fimdWindow),
        VMSTATE_END_OF_LIST()
    }
};

static int exynos4210_fimd_init(SysBusDevice *dev)
{
    Exynos4210fimdState *s = FROM_SYSBUS(Exynos4210fimdState, dev);

    s->ifb = NULL;

    sysbus_init_irq(dev, &s->irq[0]);
    sysbus_init_irq(dev, &s->irq[1]);
    sysbus_init_irq(dev, &s->irq[2]);

    memory_region_init_io(&s->iomem, &exynos4210_fimd_mmio_ops, s,
            "exynos4210.fimd", FIMD_REGS_SIZE);
    sysbus_init_mmio(dev, &s->iomem);
    s->console = graphic_console_init(exynos4210_fimd_update,
                                  exynos4210_fimd_invalidate, NULL, NULL, s);

    return 0;
}

static void exynos4210_fimd_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    dc->vmsd = &exynos4210_fimd_vmstate;
    dc->reset = exynos4210_fimd_reset;
    k->init = exynos4210_fimd_init;
}

static const TypeInfo exynos4210_fimd_info = {
    .name = "exynos4210.fimd",
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(Exynos4210fimdState),
    .class_init = exynos4210_fimd_class_init,
};

static void exynos4210_fimd_register_types(void)
{
    type_register_static(&exynos4210_fimd_info);
}

type_init(exynos4210_fimd_register_types)