tag name | pull-target-arm-20220930 (a71d43369e8b9d3cdd20052fc3d11d436bd0bac1) |
tag date | 2022-09-30 14:33:47 +0100 |
tagged by | Peter Maydell <peter.maydell@linaro.org> |
tagged object | commit beeec926d2... |
target-arm queue:
* Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
PMCNTENSET_EL0 or PMCNTENCLR_EL0
* Make writes to MDCR_EL3 use PMU start/finish calls
* Let AArch32 write to SDCR.SCCD
* Rearrange cpu64.c so all the CPU initfns are together
* hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
* hw/arm/virt: fix some minor issues with generated device tree
* Fix regression where EL3 could not write to SP_EL1 if there is no EL2
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