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tag namepull-target-arm-20181102 (3c9a110e1513b4eeeaa23b3c7684d3c65b8f4a08)
tag date2018-11-02 17:13:20 +0000
tagged byPeter Maydell <peter.maydell@linaro.org>
tagged objectcommit 6f16da53ff...
target-arm queue:
* microbit: Add the UART to our nRF51 SoC model * Add a virtual Xilinx Versal board "xlnx-versal-virt" * hw/arm/virt: Set VIRT_COMPAT_3_0 compat * MAINTAINERS: Remove bouncing email in ARM ACPI * strongarm: mask off high[31:28] bits from dir and state registers * target/arm: Conditionalize some asserts on aarch32 support * hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJb3IYDAAoJEDwlJe0UNgzegKkP/iJVu5o7hEVEqh4GRrNwLaJO dUL5+xk1XU9VEpgkfqgw/N/EvPCl5QYtT0fm86srRu7AFjgsqeMq2pDR9VrUEzOM UyIuD28ra46kLi6kDzu0vkSf89YySv1AcfJe32jLQrEEIRgwUkGEmcbebokmgPy+ pkV28zVbk5VVQzbx8uLvDOhVEhlH/vnkbyDWWUk/XFR13AaFfpZNJFVqQEzM5RNz ih8zazVRK0bdmd5oBG427SUbzR7vkkiQ6Kov/KqENarXcHPa9gdwPmrJMg03TbLn +vkzIvLHPLaeiVYlM2rqSaOYBPJ/l6wn4kh4PtHDvIyWrffqL2NiMtAeDIPauK50 PCLk343C7j6Hy6EFbDa5C0w1er89fGsHBtxQb+IcfeCXvzrKkzUrp+Yg/NEipn20 4moHLM1/SdKsllUaCaA8UB0fMt/kGiIwE6IhAsZ0d+i9DklHKQk3XQwefhWJ2rPn 5YkJjXUybNWQRqbpPkPqIWtZ9VrbGZWayfHt+lrL920BB8gwMGK0SDJpqmaVWHJ4 tmY0hMnfptZ9s8+vr/cXoIvsRdW9cuZRDuc3mCaknVAZ1q73F/HiSXNDUhlGo0tt 1G9PYDBul3jC7w/fNVRw5vpgv2aVjfoIWqWLb5TTdWYlTxtAwwC90aIQDOt/cAGx IOyIIYpcO1HrcRhuhwnl =aLCP -----END PGP SIGNATURE-----