target-arm queue:

 * ssi-sd: Make devices picking up backends unavailable with -device
 * Add support for VCPU event states
 * Move towards making ID registers the source of truth for
   whether a guest CPU implements a feature, rather than having
   parallel ID registers and feature bit flags
 * Implement various HCR hypervisor trap/config bits
 * Get IL bit correct for v7 syndrome values
 * Report correct syndrome for FP/SIMD traps to Hyp mode
 * hw/arm/boot: Increase compliance with kernel arm64 boot protocol
 * Refactor A32 Neon to use generic vector infrastructure
 * Fix a bug in A32 VLD2 "(multiple 2-element structures)" insn
 * net: cadence_gem: Report features correctly in ID register
 * Avoid some unnecessary TLB flushes on TTBR register writes
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1

iQIcBAABCAAGBQJb0D9ZAAoJEDwlJe0UNgzevOgP/A/36uB7UJq0fhZIP0Ltm+Mg
Nr1QZY7yz7ggNnrX1GSFRGloSE2U4QDdySS6YG7HolSQqb/kYd0mUgQJ/kOyRThb
1VWlSQeVQ499W+yBscbEaKNjPnpFCv1mUVcyZgTkEy90AOpNFacxw5IBpZEbROQ2
KJ85Ca7yzzboI084HGqvx5NxJ+Vwt4rsu9pjvGGcoybwQzdc1CsjEJSAD5Om8XEg
RogIL3EbRPQn9oMWssbm993YeQ31DmcKuGReEHHUvKp1PzxY+7mTikzIeVGzFwa6
6HWQ9+w7KfdgUpD1mEDlpzs5yB+bDuIZzDgKsfDbyvF6YhH/ErJz4Rr6eOYG1GAS
wUUQa+vQxdK9RRpo4GJLqxS6COcK6nFoj1klBo2959AYqcnl24Kxy0ZegBbh70Lr
zsNBd5f1hwEDt7tXzco9IiPsGI9B/+g40Hp9LpiTi8gRKbHyAiEIWRiwV+0tXd/O
7mlL5k5T4zgyJ1cfKvF0KtmsWcM8VOu6fB5593HlcRud8bw1CfE2E2rCzI5wqoB+
S/k73LbAU97RW4/JQrEapFM7vKnQ+Cf1Ntfs3iJrQvkVd9f3EvaPGkHtrLD85b+5
ove0lZxiA7/9+Iu9XkljQpYA8xP7FH0xpVz+1E7SDa/bVp7QPAUYTCeaj1DTSlxn
RsBCYl7jYzdiQLX4vEND
=Fa5X
-----END PGP SIGNATURE-----