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tag namepull-target-arm-20181019 (6eb94292dea1a96f7b5045e7e8966c357bdcd2ae)
tag date2018-10-19 17:56:23 +0100
tagged byPeter Maydell <peter.maydell@linaro.org>
tagged objectcommit 88c9add25e...
target-arm queue:
* ssi-sd: Make devices picking up backends unavailable with -device * Add support for VCPU event states * Move towards making ID registers the source of truth for whether a guest CPU implements a feature, rather than having parallel ID registers and feature bit flags * Implement various HCR hypervisor trap/config bits * Get IL bit correct for v7 syndrome values * Report correct syndrome for FP/SIMD traps to Hyp mode * hw/arm/boot: Increase compliance with kernel arm64 boot protocol * Refactor A32 Neon to use generic vector infrastructure * Fix a bug in A32 VLD2 "(multiple 2-element structures)" insn * net: cadence_gem: Report features correctly in ID register * Avoid some unnecessary TLB flushes on TTBR register writes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJbygy/AAoJEDwlJe0UNgzey50P/3rUuEMRjEP8wP4zgRuPDz2l PiubMQyDjkPRodhq+hB25XF9twvQVO11sWKORYf73gTw193a3j3mPN6GPa0dcP37 sVZqGGe0w9kwCTNj6viJJrPwvcbMC4W+2zkbIkGETIgz25MlpxsppZU1hsRKlaAa EXf2u3HYmbVQQyR2SxvlVlQxNBYuAOiAbmyTX/BBmiFQ3TKoi0z+DtKdSSRbsx7E IReZab/KIAN3Rj73DWXnSMhLLOBSCpXcoZ6YBq/HMhDGa+1N2CYpD0/p3Lu+drAR qwnByD/O6UnkCit/SlXTHMwyXjmZ8vpkckcZTBdbfc5kh+UoVZ/68Ku8cdtimAnJ HmmLdpeEWub/grnKueKiImLaI1C5bOBefc42wxgfqy/TweBZon6LcGIaep53A+vi wA4crRDRZKtpOYbolxMalzwgo5AZmeeRa3owAu/7zdKEQHwiztHKSvXchsbQbmU2 0MOGaEn2Kz691mdGsHQcELPoNpG3tG368VmcD/aF2PKUDQGcrulbN+CMFM6EWpGO dxZvU2GguG6Xq9285+FhRs1OvGWBX0+ckXMdhYcNPuzLmTkykd72poVCozLbfV6Y 35li09sCQmq50H9ZcJWDp90guEnQO4/HqcUMEUoEP91HbvAjDhrUOYnDBzl3Mv3v 1FcSK/F1ZK7OwZm5KdtV =7KvY -----END PGP SIGNATURE-----