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tag namepull-target-arm-20181016-1 (f351b1b0d077add7fc868b04fa52360c28c972ee)
tag date2018-10-16 17:41:50 +0100
tagged byPeter Maydell <peter.maydell@linaro.org>
tagged objectcommit 2ef297af07...
target-arm queue:
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART * target/arm: Fix aarch64_sve_change_el wrt EL0 * target/arm: Define fields of ISAR registers * target/arm: Align cortex-r5 id_isar0 * target/arm: Fix cortex-a7 id_isar0 * net/cadence_gem: Fix various bugs, add support for new features that will be used by the Xilinx Versal board * target-arm: powerctl: Enable HVC when starting CPUs to EL2 * target/arm: Add the Cortex-A72 * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO * target/arm: Mask PMOVSR writes based on supported counters * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJbxhTZAAoJEDwlJe0UNgzeksAP/iHi7Oo9FMWIrGcAC2BTkwNZ GVGKNg2tIf4BBfuGyYpNt5s9frzQl/hRPXp323Bc6ryLwqnVsAVPhRfyLcoEoAeU qMA2oeCiKWacE2KbK/E2i17Mr0zynlIURVoondBzR1W2/Vdt5mRcY5+qsGhcwqUA Ib9SO5viWHNR/VPJjT28/kPRtBOcLkyi+/sS5q8uXBy53xxcz8iaEKMtlhMuunv8 ar9PVuVDZ25dBkgOX5NRrxxfpV0L49sweJVWjyv7G84s/xFvbz1ZaoNrq5w5oYY/ FmiT+kAPSEUzRHEBJwew6+QKsHWALs/0Z9ZgF6TvwJ5KFBvowMEraHbLiWcS9eCb h89fpftPso3TiqIZyUliDRZxIKBzRBPfRYwfuy4WxMH9O6aoJhO4UpfYwI9I2AKj YxuXUCtf9B6C5HRlXTdQXQSMxS04AvKs0OxM4NIO4pgazopnAaaUQuzhaZLo9VJO HLRZmgitOyJspxl7QeDreMK5Tb1lzLuXVSU80Tgedkx03Z2vhoIM5DcOIk5VBW8k KPzN0jgHHS1R2NfJ1GwaHYWtskMm3AuWQ8YDxv0bUs9f2uQQBwfiYckp5LnGd0Sz oAXJgb3keQBiXsCpolx665DA9NFEOF581ufup6wp4J1tBwtH0UYkFkqxPqjpWQyX hCUmXQQkuskpLUvRbWT9 =T/np -----END PGP SIGNATURE-----