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tag namepull-target-arm-20181016 (535b45803f577b4f1456b5f927bd72356b77ffab)
tag date2018-10-16 16:16:59 +0100
tagged byPeter Maydell <peter.maydell@linaro.org>
tagged objectcommit bdaffef4bb...
downloadqemu-arm-pull-target-arm-20181016.tar.gz
target-arm queue:
* hw/arm/virt: add DT property /secure-chosen/stdout-path indicating secure UART * target/arm: Fix aarch64_sve_change_el wrt EL0 * target/arm: Define fields of ISAR registers * target/arm: Align cortex-r5 id_isar0 * target/arm: Fix cortex-a7 id_isar0 * net/cadence_gem: Fix various bugs, add support for new features that will be used by the Xilinx Versal board * target-arm: powerctl: Enable HVC when starting CPUs to EL2 * target/arm: Add the Cortex-A72 * target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO * target/arm: Mask PMOVSR writes based on supported counters * target/arm: Initialize ARMMMUFaultInfo in v7m_stack_read/write * coccinelle: new inplace-byteswaps.cocci to remove inplace-byteswapping calls -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJbxgGTAAoJEDwlJe0UNgzeg0IQAKJHHumDxrvJZ0bWEG/6Atyt qhLyP8VPKoXrmYg89259JODxPcdl4M8jVeieNbTU7mozmq6Z5Y57OJub5eVRJo3b kmlK+X2b+BW6G5fgM0gLozQgFtFbhKJ/c1LZhN6F6SLDemiTJjJBF+9ECo8W2jKU lxKNZKLYn99kl7LqnL4A/aDijgt+AebcjPTIGl6CPtNVGPdWcY/JNY1lNoazVAoq OyivEwlifL0SytHthBJUgZGvGsSuYnBuU3xEqh1yNXPKhfVGRus0FZhqn2Nl5gsv DeCPJLWLDNpqs+RYIPSKsNFjhhc7SA6qFwNNWB03n3tdVMsKXf4J+hE6pDvrsNwK t7Ga3Ogn/VlR4hrc/xUHG/08fSvS+GMiiJDn+2rBFqoL1HxYmgNM8r4U4+LRE5G+ vOmn4OJghwpJiRvfPlvz4AdZgwsz1rs1hP0Cx6hckTdrNYdT2PuhQ3H9UeSHlzQD FPxhhqbq7yCPXCWEbQJAs8OrXrGW4pDZnjJi3u4PphA/XnIcSUcGQmcmM6juAcpS ZUlDiVh5u9ykqRYu+rpk7kCivR0eWCq3Sgu8+EI+PAX4tIkl/LTdt0xVpeps5nGq FRvrjvEpi3ZmRLN5K520j6M2PgZh8w6TDvVKdHaGlS9dUnyR0Rmc8nu4Y5m7ZOAJ rc2QPPZapiNQuLyF7XOj =Slsb -----END PGP SIGNATURE-----