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tag namepull-target-arm-20150205 (5f1d91fcd8dea18fdf98fbb7749309c9c035d2d1)
tag date2015-02-05 13:56:19 +0000
tagged byPeter Maydell <peter.maydell@linaro.org>
tagged objectcommit fc1792e9aa...
target-arm queue:
* refactor/clean up armv7m_init() * some initial cleanup in the direction of supporting 64-bit EL3 * fix broken synchronization of registers between QEMU and KVM for 32-bit ARM hosts (which among other things broke memory access via gdbstub) * fix flush-to-zero handling in FMULX, FRECPS, FRSQRTS and FRECPE * don't crash QEMU for UNPREDICTABLE BFI insns in A32 encoding * explain why virt board's device-to-transport mapping code is the way it is * implement mmu_idx values which match the architectural distinctions, and introduce the concept of a translation regime to get_phys_addr() rather than incorrectly looking at the current CPU state * update to upstream VIXL 1.7 (gives us correct code addresses when dissassembling pc-relative references) * sync system register state between KVM and QEMU for 64-bit ARM * support virtio on big-endian guests by implementing the "which endian is the guest now?" CPU method -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABCAAGBQJU03foAAoJEDwlJe0UNgze6xsP/jJHiEE4EieGfzkd0rKBAWlP 0iW0oI8VRdYgbwmgRfZJwdbcR/7qYATS6ffS1QINfb6zQRyNHF1J3Qv9sOnU/NC5 k7hQedqLoG68RUe3QwA0LxrF3r6NVYIddDKMPkjWgbByDbcAtUdElB2UTpd6yLFF hrRfkQWUbWqUoe1yqSPUaffo8s88MXFHqArhCHOhN5LQ/KAr70iggAEity6irJIX z+dhXaIoi7V6R1rSX+uAt6YAfja3/7GYzG3zK+xy/wdLv3Ka7ametCkwZZP+cvcp Zfbo1cpkbKSoPcxmaPoT/FDVH5AGKyO00QKQI/1Nsjb4CcR49dKczqIvlFfK82XL M0lNmfDFIf5K4D6KYsXkCbSCETEPuTeDQFI14z/gFNevAUMmRp02HGK+6/Z/mn0W n17nWiLiKhpvKo7xoPrIhCaYuaFP7OzL4g0ZktGlKYEGBrNATzpAH2v8pAYn4S41 aF9Yzo5PF4lVlNpCZQSmilX6VmXLAuC4WSEB8nUkRjjk+wsBxzYO7SqXB+gxvagW leahFyHExRMTbOFXsrRAoCGcdOCpNjAam3QYKQaIAhgYy89XmqSl8wKnV6PESOxt QSBB/frbmn1Uj4aPMM2xSG/5vVpM/TtaBWDIi6+nlokCE4PO37kSjOprNUT/INeJ QATeeqh5iPio7BQwgjH8 =gmUH -----END PGP SIGNATURE-----