tag name | pull-target-arm-20141024 (3f06344928bbc6b692fd62e5a38a37420455ce30) |
tag date | 2014-10-24 12:30:30 +0100 |
tagged by | Peter Maydell <peter.maydell@linaro.org> |
tagged object | commit dbe9d16367... |
target-arm queue:
* remove pointless 'info pcmcia' and a lot of now-dead code
* register ARM cpu reset handlers even if not using -kernel
* update to libvixl 1.6
* various minor code cleanups
* support PSCI under TCG ('virt' machine can now be shut down,
SMP configurations work)
* correct the sense of the AArch64 DCZID DZP bit
* report a valid L1Ip field in CTR_EL0 for CPU type "any"
* correctly UNDEF writes to FPINST/FPINST2 from EL0
* more preparatory code refactoring for EL2/EL3 support
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