From db77d8523909b32d798cd2c80de422b68f9e5c42 Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Wed, 9 Sep 2015 14:45:36 +0100 Subject: target-mips: add missing restriction in DAUI instruction rs cannot be the zero register, Reserved Instruction exception must be signalled for this case. Signed-off-by: Leon Alrae Reviewed-by: Aurelien Jarno --- target-mips/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'target-mips') diff --git a/target-mips/translate.c b/target-mips/translate.c index cd0cf8b655..0883782b8c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19525,7 +19525,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) #if defined(TARGET_MIPS64) /* OPC_DAUI */ check_mips_64(ctx); - if (rt != 0) { + if (rs == 0) { + generate_exception(ctx, EXCP_RI); + } else if (rt != 0) { TCGv t0 = tcg_temp_new(); gen_load_gpr(t0, rs); tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16); -- cgit v1.2.3