From 42a268c241183877192c376d03bd9b6d527407c7 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 13 Feb 2015 12:51:55 -0800 Subject: tcg: Change translator-side labels to a pointer This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Cc: Peter Maydell Cc: Edgar E. Iglesias Cc: Michael Walle Cc: Leon Alrae Cc: Anthony Green Cc: Jia Liu Cc: Alexander Graf Cc: Aurelien Jarno Cc: Blue Swirl Cc: Guan Xuetao Cc: Paolo Bonzini Cc: Max Filippov Reviewed-by: Bastian Koppelmann Signed-off-by: Richard Henderson --- target-arm/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'target-arm/translate.c') diff --git a/target-arm/translate.c b/target-arm/translate.c index 36868ed05f..381d89624f 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -736,10 +736,10 @@ static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b) * generate a conditional branch based on ARM condition code cc. * This is common between ARM and Aarch64 targets. */ -void arm_gen_test_cc(int cc, int label) +void arm_gen_test_cc(int cc, TCGLabel *label) { TCGv_i32 tmp; - int inv; + TCGLabel *inv; switch (cc) { case 0: /* eq: Z */ @@ -7440,8 +7440,8 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, { TCGv_i32 tmp; TCGv_i64 val64, extaddr; - int done_label; - int fail_label; + TCGLabel *done_label; + TCGLabel *fail_label; /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) { [addr] = {Rt}; -- cgit v1.2.3