From 3a181bd2b8a0f90e1f0bb6fd2d3bf2e81be01535 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 20 Mar 2012 17:25:52 +0000 Subject: target-arm: Convert debug registers to cp_reginfo Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the cp_reginfo scheme. --- target-arm/helper.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'target-arm/helper.c') diff --git a/target-arm/helper.c b/target-arm/helper.c index b241cb7a24..a5fbf35020 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -209,6 +209,27 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) return 0; } +static const ARMCPRegInfo cp_reginfo[] = { + /* DBGDIDR: just RAZ. In particular this means the "debug architecture + * version" bits will read as a reserved value, which should cause + * Linux to not try to use the debug hardware. + */ + { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo v7_cp_reginfo[] = { + /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped + * debug components + */ + { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -218,6 +239,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) return; } + define_arm_cp_regs(env, cp_reginfo); + if (arm_feature(env, ARM_FEATURE_V7)) { + define_arm_cp_regs(env, v7_cp_reginfo); + } } CPUARMState *cpu_arm_init(const char *cpu_model) -- cgit v1.2.3