From c700dead3d8cf2751f41dce699965442972298aa Mon Sep 17 00:00:00 2001 From: Jeff Kubascik Date: Fri, 17 Jan 2020 14:09:31 +0000 Subject: arm/gicv3: update virtual irq state after IAR register read MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the register activates the highest priority pending interrupt and provides its interrupt ID. Activating an interrupt can change the CPU's virtual interrupt state - this change makes sure the virtual irq state is updated. Signed-off-by: Jeff Kubascik Reviewed-by: Philippe Mathieu-Daudé Message-id: 20200113154607.97032-1-jeff.kubascik@dornerworks.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index a254b0ce87..08e000e33c 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -664,6 +664,9 @@ static uint64_t icv_iar_read(CPUARMState *env, const ARMCPRegInfo *ri) trace_gicv3_icv_iar_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), intid); + + gicv3_cpuif_virt_update(cs); + return intid; } -- cgit v1.2.3