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2014-12-17target-xtensa: test cross-page opcodeMax Filippov
Alter cross-page TB test to also test cross-page opcode. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-11-10target-xtensa: add entry overflow testMax Filippov
Check that entry instruction raises window overflow exception when PS.CALLINC points to live registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-11-03target-xtensa: tests: pre-process tests linker scriptMax Filippov
Xtensa cores have configurable interrupt vectors and endiannes. This information is needed to link executable images correctly for a specific core configuration. Instead of hard-coding dc232 defaults pull endianness, number of high-priority interrupts and location of vectors from the core configuration and pass it through the C preprocessor. While at it clean up tabs and align the initial stack on 16 bytes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-05-28Merge remote-tracking branch 'remotes/xtensa/tags/20140526-xtensa' into stagingPeter Maydell
Xtensa fixes queue 2014-05-26: - fix cross-page jumps/calls at the end of TB; - add tests for TBs and instructions crossing page boundary. # gpg: Signature made Mon 26 May 2014 09:37:39 BST using RSA key ID F83FA044 # gpg: Can't check signature: public key not found * remotes/xtensa/tags/20140526-xtensa: target-xtensa: add tests for cross-page TB target-xtensa: completely clean TLB between MMU tests target-xtensa: fix cross-page jumps/calls at the end of TB Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-26target-xtensa: add tests for cross-page TBMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-05-26target-xtensa: completely clean TLB between MMU testsMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-05-24test: lm32: use semihosting for testingMichael Walle
Instead of the lm32-sys device, use semihosting to print to the host console and exit the test. Signed-off-by: Michael Walle <michael@walle.cc>
2014-05-24test: lm32: make test cases independentMichael Walle
Make test cases independent from from each other. Eg. if a test case needs a specific value in register A, don't rely on the fact that it is already set by the preceding test case. Signed-off-by: Michael Walle <michael@walle.cc>
2014-05-07tests/tcg: Fix compilation of test_pathPeter Maydell
The test_path binary is (unlike the other test binaries in tests/tcg) actually intended to be compiled with the same compiler used to build the main QEMU executables. It actually #includes a number of the QEMU source files in an attempt to unit-test the util/path.c functions, and so if it is not compiled with the same compiler used by configure to set CONFIG_ settings then it is liable to fail to build. Fix the makefile to build it with the default C compiler rules, not CC_I386, and fix the test itself not to include a lot of unnecessary trace related source files which cause the build to fail if the trace backend is anything other than 'simple'. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-03-15tests: Fix 'make test' for i686 hosts (build regression)Stefan Weil
'make test' is broken at least since commit baacf04799ace72a9c735dd9306a1ceaf305e7cf. Several source files were moved to util/, and some of them there split, so add the missing prefix and new files to fix the compiler and linker errors. There remain more issues, but these changes allow running the test on a Linux i686 host. Cc: qemu-stable@nongnu.org Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-02-24target-xtensa: add basic tests for cache opcodesMax Filippov
Test that non-locking prefetch operations don't cause exceptions on missing TLB and that other 'hit' cache operations do. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24target-xtensa: allow using core configuration in testsMax Filippov
Add path to the core configuration directory to test build command and replace .include asm directive with #include to enable preprocessing. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-24target-xtensa: add overridable test_init macroMax Filippov
Some test suites, like MMU, need per-test initialization. Don't make them redefine test macro, add test_init for that purpose. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2014-02-04tests: lm32: new rule for single test casesMichael Walle
Introduce new target "check_%" to run individual test caes, eg. make check_mmu Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2013-11-20target-openrisc: Correct carry flag check of l.addc and l.addic test casesSebastian Macke
The test cases did not correctly test for the carry flag. Signed-off-by: Sebastian Macke <sebastian@macke.de> Reviewed-by: Jia Liu <proljc@gmail.com> Signed-off-by: Jia Liu <proljc@gmail.com>
2013-08-05Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into stagingAnthony Liguori
xtensa queue 2013-07-29 * filippov/tags/20130729-xtensa: target-xtensa: check register window inline target-xtensa: don't generate dead code to access invalid SRs tests/tcg/xtensa: Fix out-of-tree build target-xtensa: avoid double-stopping at breakpoints target-xtensa: add fallthrough markers target-xtensa: add extui unit test Conflicts: configure Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-30target-mips: correct the values in the DSP testsPetar Jovanovic
Five tests files for DSP instructions had wrong expected values in the tests. This change fixes this, and this has been cross-checked by running the same test binaries on Malta 74K board. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-29tests/tcg/xtensa: Fix out-of-tree buildAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-29target-xtensa: add extui unit testMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2013-07-29target-mips: fix mipsdsp_mul_q31_q31Petar Jovanovic
Multiplication of two fractional word elements is not correct when sign extension/promotion is needed. This change fixes it by adding correct casts from unsigned to signed values. In addition, the tests (dpaq_sa_l_w.c and dpsq_sa_l_w.c) have been extended to trigger the current issue. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-29target-mips: fix mipsdsp_trunc16_sat16_roundPetar Jovanovic
This change corrects rounding and saturation of Q31 fractional value in mipsdsp_trunc16_sat16_round(). Overflow detection was incorrect for the corner case for PRECRQ_RS.PH, and this test case is also part of the change. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-07-28target-mips: fix multiplication in mipsdsp_rndq15_mul_q15_q15Petar Jovanovic
Multiplication of Q15 fractional halfword vectors was incorrect in the previous implementation of mipsdsp_rndq15_mul_q15_q15. It failed to take element signs into account. This change fixes it, and it adds a test case for it. The change also removes unnecessary cast in the function mipsdsp_mul_q15_q15_overflowflag21(). Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-22Merge remote-tracking branch 'mjt/trivial-patches' into stagingAnthony Liguori
# By Christophe Lyon (1) and others # Via Michael Tokarev * mjt/trivial-patches: target-moxie: replace target_phys_addr_t with hwaddr Rename hexdump to avoid FreeBSD libutil conflict remove some double-includes translate: remove redundantly included qemu/timer.h Remove twice include of qemu-common.h fix /proc/self/maps output Message-id: 51977B44.1000302@msgid.tls.msk.ru Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-05-19target-mips: fix EXTPDP and setting up pos field in the DSPControl regPetar Jovanovic
This change makes sure that modifications of pos field in the DSPControl register do not trash other bits in the register. This bug can be triggered with the additional test case in mips32-dsp/extpdp.c in this commit. In addition to this, this change corrects incorrect calculation of the mask for EXTPDP. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-18remove some double-includesMichael Tokarev
Some source files #include the same header more than once for no good reason. Remove second #includes in such cases. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2013-05-17target-mips: fix incorrect behaviour for EXTPPetar Jovanovic
The mask for EXTP instruction when size=31 has not been correctly calculated. The test (mips32-dsp/extp.c) has been extended to include the case that triggers the issue. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-08target-mips: fix incorrect behaviour for INSVPetar Jovanovic
Corner case for INSV instruction when size=32 has not been correctly implemented. The mask for size should be one bit wider, and preparing the filter variable should be aware of this case too. The test for INSV has been extended to include the case that triggers the bug. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-05-03target-mips: fix calculation of overflow for SHLL.PH and SHLL.QBPetar Jovanovic
This change corrects and simplifies how discard is calculated for shift left logical vector instructions. It is used to detect overflow and set bit 22 in the DSPControl register. The existing tests (shll_ph.c, shll_qb.c) are extended with the corner cases that expose incorrectness in the previous implementation. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-04-15target-mips: fix mipsdsp_mul_q15_q15 and tests for MAQ_SA_W_PHL/PHRPetar Jovanovic
The operands for MAQ_SA_W.PHL/MAQ_SA_W.PHR must in specified format. Otherwise, the results are unpredictable. Once the operands were corrected in the tests (part of this change), a bug in mipsdsp_mul_q15_q15 became visible. This change corrects the tests for MAQ_SA_W.PHL/MAQ_SA_W.PHR and fixes sign-related issue in mipsdsp_mul_q15_q15. It also removes unnecessary comment. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
2013-03-18tests: tcg: lm32: add more test casesMichael Walle
Esp. for testing zero/sign extend in compare operations. Signed-off-by: Michael Walle <michael@walle.cc>
2013-03-17target-mips: fix rndrashift_short_acc and code for EXTR_ instructionsPetar Jovanovic
Fix for rndrashift_short_acc to set correct value to higher 64 bits. This change also corrects conditions when bit 23 of the DSPControl register is set. The existing test files have been extended with several examples that trigger the issues. One bug/example in the test file for EXTR_RS_W has been found and reported by Klaus Peichl. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-03-04target-mips: fix DSP overflow macro and affected routinesPetar Jovanovic
The previous implementation incorrectly used same macro to detect overflow for addition and subtraction. This patch makes distinction between these two, and creates separate macros. The affected routines are changed accordingly. This change also includes additions to the existing tests for SUBQ_S_PH and SUBQ_S_W that would trigger the fixed issue, and it removes dead code from the test file. The last test case in subq_s_w.c is a bug found/reported/ isolated by Klaus Peichl from Dolby. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-02-23target-mips: fix for sign-issue in MULQ_W helperPetar Jovanovic
Correct sign-propagation before multiplication in MULQ_W helper. The change also fixes previously incorrect expected values in the tests for MULQ_RS.W and MULQ_S.W. Signed-off-by: Petar Jovanovic <petarj@mips.com> Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-02-23target-mips: fix for incorrect multiplication with MULQ_S.PHPetar Jovanovic
The change corrects sign-related issue with MULQ_S.PH. It also includes extension to the already existing test which will trigger the issue. Signed-off-by: Petar Jovanovic <petarj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-02-18test-i386: make it compile with a recent gccPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-02-18test-i386: QEMU_PACKED is not defined herePaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-31target-mips: fix incorrect test for MTHLIPPetar Jovanovic
The pos field in the DSPControl register is not correctly initialized. Per documentation, the result of MTHLIP is unpredictable if the value of the pos field before the execution is greater than 32. Signed-off-by: Petar Jovanovic <petarj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-08target-mips: Fix helper and tests for dot/cross-dot product instructionsPetar Jovanovic
Helper function for dpa_w_ph, dpax_w_ph, dps_w_ph and dpsx_w_ph incorrectly defines halfword vector elements as unsigned values. This results in wrong output which is not triggered in the tests as they also follow this logic. Signed-off-by: Petar Jovanovic <petarj@mips.com> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-01target-mips: Fix for helpers for EXTR_* instructionsPetar Jovanovic
The change removes some unnecessary and incorrect code for EXTR_S.H. Further, it corrects the mask for shift value in the EXTR_ instructions. It also extends the existing tests so they trigger the issues corrected with the change. Signed-off-by: Petar Jovanovic <petarj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2013-01-01target-mips: Fix incorrect reads and writes to DSPControl registerPetar Jovanovic
Upper 4 bits of ccond (bits 31..28 ) of DSPControl register are not used in the MIPS32 architecture. They are used in the MIPS64 architecture. For MIPS32 these bits must be written as zero, and return zero on read. The change fixes writes (WRDSP) and reads (RDDSP) to the register. It also fixes the tests that use these instructions, and makes them smaller and simpler. Signed-off-by: Petar Jovanovic <petarj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-12-19misc: move include files to include/qemu/Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-19janitor: add guards to headersPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-12-08target-xtensa: add s32c1i unit testsMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08target-xtensa: add SR accessibility unit testsMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-06target-mips: Fix incorrect shift for SHILO and SHILOVPetar Jovanovic
helper_shilo has not been shifting an accumulator value correctly for negative values in 'shift' field. Minor optimization for shift=0 case. This change also adds tests that will trigger issue and check for regressions. Signed-off-by: Petar Jovanovic <petarj@mips.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-12-06target-mips: Fix incorrect code and test for INSVPetar Jovanovic
Content of register rs should be shifted for pos before applying a mask. This change contains both fix for the instruction and to the existing test. Signed-off-by: Petar Jovanovic <petarj@mips.com> Reviewed-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-11-10tests/tcg: new test for i386 FPREM and FPREM1Catalin Patulea
This is setting the stage for a cleanup of FPREM and FPREM1 helpers while being sure that they behave same as bare metal. The test constructs operands using combinations of corner cases for the floating-point bitfields and prints operands, result and FPU status word for FPREM and FPREM1. The outputs can then be compared between bare metal and QEMU. The 'run-test-i386-fprem' make target does just that. Signed-off-by: Catalin Patulea <catalinp@google.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-31target-mips: Add ASE DSP testcasesJia Liu
Add MIPS ASE DSP testcases. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-30tests/tcg: fix unused result warningsCatalin Patulea
With i386-linux-user target on x86_64 host, this does not introduce any new test failures. Signed-off-by: Catalin Patulea <catalinp@google.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-27tests/tcg: fix a few warningsCatalin Patulea
Signed-off-by: Catalin Patulea <catalinp@google.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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