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2011-06-26TCG/Sparc64: use stack for TCG tempsBlue Swirl
Use stack instead of temp_buf array in CPUState for TCG temps. On Sparc64, stack pointer is not aligned but there is a fixed bias of 2047, so don't try to enforce alignment. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26Delegate setup of TCG temporaries to targetsBlue Swirl
Delegate TCG temp_buf setup to targets, so that they can use a stack frame later instead. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26cpu-exec.c: avoid AREG0 useBlue Swirl
Make functions take a parameter for CPUState instead of relying on global env. Pass CPUState pointer to TCG prologue, which moves it to AREG0. Thanks to Peter Maydell and Laurent Desnogues for the ARM prologue change. Revert the hacks to avoid AREG0 use on Sparc hosts. Move cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. Compile the file without HELPER_CFLAGS. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-16tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson
Some hosts (amd64, ia64) have an ABI that ignores the high bits of the 64-bit register when passing 32-bit arguments. Others require the value to be properly sign-extended for the type. I.e. "int32_t" must be sign-extended and "uint32_t" must be zero-extended to 64-bits. To effect this, extend the "sizemask" parameter to tcg_gen_callN to include the signedness of the type of each parameter. If the tcg target requires it, extend each 32-bit argument into a 64-bit temp and pass that to the function call. This ABI feature is required by sparc64, ppc64 and s390x. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09tcg: Make some tcg-target.c routines static.Richard Henderson
Both tcg_target_init and tcg_target_qemu_prologue are unused outside of tcg.c. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09tcg: Add TYPE parameter to tcg_out_mov.Richard Henderson
Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64 to perform the move at the proper width, which may elide a REX prefix. Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data" as represented by the existing TCG_TYPE_PTR. Update all targets to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-05Split TLB addend and target_phys_addr_tPaul Brook
Historically the qemu tlb "addend" field was used for both RAM and IO accesses, so needed to be able to hold both host addresses (unsigned long) and guest physical addresses (target_phys_addr_t). However since the introduction of the iotlb field it has only been used for RAM accesses. This means we can change the type of addend to unsigned long, and remove associated hacks in the big-endian TCG backends. We can also remove the host dependence from target_phys_addr_t. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson
Use the TCGCond enumeration type in the brcond and setcond related prototypes in tcg-op.h and each code generator. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Name the opcode enumeration.Richard Henderson
Give the enumeration formed from tcg-opc.h a name: TCGOpcode. Use that enumeration type instead of "int" whereever appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13Fix Sparc host build breakageBlue Swirl
Fix error: CC sparc-bsd-user/op_helper.o In file included from /src/qemu/tcg/tcg.c:158: /src/qemu/tcg/sparc/tcg-target.c:728:5: "TARGET_PHYS_ADDR_BITS" is not defined Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-22tcg: fix build on 32-bit hppa, ppc and sparc hostsJay Foad
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: malc <av1474@comtv.ru>
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement ORC.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement ANDC.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement not.Richard Henderson
The fallback implementation of "ret = arg1 ^ -1" isn't ideal because of the extra tcg op to load the minus one. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement neg.Richard Henderson
The fallback implementation of "ret = 0 - arg1" isn't ideal, first because of the extra tcg op to load the zero, and second because we fail to handle zero as %g0 for arg1 of the sub. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16tcg-sparc: Implement setcond, setcond2.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Implement ext32[su]_i64Richard Henderson
The 32-bit right-shift instructions is defined to extend the shifted output to 64-bits. A shift count of zero therefore is a simple extension without actually shifting. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Implement division properly.Richard Henderson
The {div,divu}2 opcodes are intended for systems for which the division instruction produces both quotient and remainder. Sparc is not such a system. Indeed, the remainder must be computed as quot = a / b rem = a - (quot * b) Split out a tcg_out_div32 function that properly initializes Y with the extension of the input to 64-bits. Discard the code that used the 64-bit DIVX on sparc9/sparcv8plus without extending the inputs to 64-bits. Implement remainders in terms of division followed by multiplication. Signed-off-by: Richard Henderson <rth@twiddle.net> [blauwirbel@gmail.com: applied rth's typo fix in tcg_out_div32] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Do not remove %o[012] from 'r' constraint.Richard Henderson
Only 'L' constraint needs that. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Implement add2, sub2, mulu2.Richard Henderson
Add missing 32-bit double-word support opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Add tcg_out_arithc.Richard Henderson
Add a function to handle the register-vs-immediate test for arithmetic. Also, adjust the OP_32_64 macro so that it auto-indents properly. Rename the gen_arith32 label to gen_arith, since it handles 64-bit arithmetic as well. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Implement brcond2.Richard Henderson
Split out tcg_out_cmp and properly handle immediate arguments. Fix constraints on brcond to match what SUBCC accepts. Add tcg_out_brcond2_i32 for 32-bit host. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.Richard Henderson
The test TCG_TARGET_REG_BITS==64 is exactly the feature that we are checking for, whereas something involving __sparc_v9__ or __sparc_v8plus__ should be reserved for something ISA related, as with SMULX. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Improve tcg_out_movi for sparc64.Richard Henderson
Generate sign-extended 32-bit constants with SETHI+XOR. Otherwise tidy the routine to avoid the need for conditional compilation and code duplication with movi_imm32. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Fix imm13 check in movi.Richard Henderson
We were unnecessarily restricting imm13 constants to 12 bits. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-27change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}Juan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-04-04Fix branches and TLB matches for 64 bit targetsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6974 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-04Allocate space for static call args, increase stack frame size on Sparc64blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6973 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg: rename bswap_i32/i64 functionsaurel32
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-08Prune unused TCG_AREGsblueswir1
Remove definitions for TCG_AREGs corresponding to AREG definitions removed in r6778. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-05Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-13Use 64 bit loads for tlb addend only if addend size is 64 bitsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5203 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-13Fix stack alignment on Sparc32 hostblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5202 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-17Fix 64 bit constant generationblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5020 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-17Fix 32 bit address overflowblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5019 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-17Restore AREG0 after callsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5018 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-16Sparc code generator update (fix qemu_ld & qemu_st)blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5014 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-15Sparc code generator updateblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5009 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-26Try to avoid glibc global register mangling, againblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4953 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-07Fix 64 bit constant generationblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4854 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-25Implement byte swapping accessesblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4574 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-24Implement 64-bit constant loadsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4561 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-24Use sethi and arith functions, fix commentblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4560 c046a42c-6fe2-441c-8c8c-71466251a162
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