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2010-02-20tcg-sparc: Implement not.Richard Henderson
The fallback implementation of "ret = arg1 ^ -1" isn't ideal because of the extra tcg op to load the minus one. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg-sparc: Implement neg.Richard Henderson
The fallback implementation of "ret = 0 - arg1" isn't ideal, first because of the extra tcg op to load the zero, and second because we fail to handle zero as %g0 for arg1 of the sub. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-16tcg-sparc: Implement setcond, setcond2.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Implement ext32[su]_i64Richard Henderson
The 32-bit right-shift instructions is defined to extend the shifted output to 64-bits. A shift count of zero therefore is a simple extension without actually shifting. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Implement division properly.Richard Henderson
The {div,divu}2 opcodes are intended for systems for which the division instruction produces both quotient and remainder. Sparc is not such a system. Indeed, the remainder must be computed as quot = a / b rem = a - (quot * b) Split out a tcg_out_div32 function that properly initializes Y with the extension of the input to 64-bits. Discard the code that used the 64-bit DIVX on sparc9/sparcv8plus without extending the inputs to 64-bits. Implement remainders in terms of division followed by multiplication. Signed-off-by: Richard Henderson <rth@twiddle.net> [blauwirbel@gmail.com: applied rth's typo fix in tcg_out_div32] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Do not remove %o[012] from 'r' constraint.Richard Henderson
Only 'L' constraint needs that. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Implement add2, sub2, mulu2.Richard Henderson
Add missing 32-bit double-word support opcodes. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12tcg-sparc: Add tcg_out_arithc.Richard Henderson
Add a function to handle the register-vs-immediate test for arithmetic. Also, adjust the OP_32_64 macro so that it auto-indents properly. Rename the gen_arith32 label to gen_arith, since it handles 64-bit arithmetic as well. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Implement brcond2.Richard Henderson
Split out tcg_out_cmp and properly handle immediate arguments. Fix constraints on brcond to match what SUBCC accepts. Add tcg_out_brcond2_i32 for 32-bit host. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.Richard Henderson
The test TCG_TARGET_REG_BITS==64 is exactly the feature that we are checking for, whereas something involving __sparc_v9__ or __sparc_v8plus__ should be reserved for something ISA related, as with SMULX. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Improve tcg_out_movi for sparc64.Richard Henderson
Generate sign-extended 32-bit constants with SETHI+XOR. Otherwise tidy the routine to avoid the need for conditional compilation and code duplication with movi_imm32. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21tcg-sparc: Fix imm13 check in movi.Richard Henderson
We were unnecessarily restricting imm13 constants to 12 bits. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-27change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}Juan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-04-04Fix branches and TLB matches for 64 bit targetsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6974 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-04Allocate space for static call args, increase stack frame size on Sparc64blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6973 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg: rename bswap_i32/i64 functionsaurel32
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-08Prune unused TCG_AREGsblueswir1
Remove definitions for TCG_AREGs corresponding to AREG definitions removed in r6778. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-05Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-13Use 64 bit loads for tlb addend only if addend size is 64 bitsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5203 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-13Fix stack alignment on Sparc32 hostblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5202 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-17Fix 64 bit constant generationblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5020 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-17Fix 32 bit address overflowblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5019 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-17Restore AREG0 after callsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5018 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-16Sparc code generator update (fix qemu_ld & qemu_st)blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5014 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-15Sparc code generator updateblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5009 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-26Try to avoid glibc global register mangling, againblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4953 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-07Fix 64 bit constant generationblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4854 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-25Implement byte swapping accessesblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4574 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-24Implement 64-bit constant loadsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4561 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-24Use sethi and arith functions, fix commentblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4560 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-24Fix stack offsets and alignmentblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4559 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-24Define stack offsetsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4554 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-18Fix constant checks on Sparc64 hostblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4486 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-17Fix qemu_ld/st branches, constification, use orcc for tst synthetic opblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4466 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-16Implement qemu_ld/st, fix brcond, handle more corner casesblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4463 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-15Implement brcond, ldst with large offset; fix direct jump, prologueblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4461 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-15Fix bit fitting checksblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4460 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-14Fix compilation on Sparc host, implement ld and stblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4457 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-12HPPA (PA-RISC) host supportaurel32
(Stuart Brady) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4199 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-13 Fix i32 memory backed variables on 64-bit hostblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4044 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-11 Remove blank elements in tcg_target_reg_alloc_order[] (Stuart Brady)blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4039 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-08 Add function prologue, fix pointer load on Sparc64 hostblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4027 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-07 Update based on Stuart Brady's commentsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4026 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-29 Fix register references (Igor Kovalenko)blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4002 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-27 Preliminary Sparc TCG targetblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3995 c046a42c-6fe2-441c-8c8c-71466251a162
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