peter.maydell/qemu-arm.git - This qemu repo is mostly a place to put together pull requests for upstream

Age	Commit message (Expand)	Author
2021-04-30	target/arm: Enforce alignment for sve LD1R	Richard Henderson
2021-04-30	target/arm: Enforce alignment for aa64 vector LDn/STn (single)	Richard Henderson
2021-04-30	target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)	Richard Henderson
2021-04-30	target/arm: Use MemOp for size + endian in aa64 vector ld/st	Richard Henderson
2021-04-30	target/arm: Enforce alignment for aa64 load-acq/store-rel	Richard Henderson
2021-04-30	target/arm: Use finalize_memop for aa64 fpr load/store	Richard Henderson
2021-04-30	target/arm: Use finalize_memop for aa64 gpr load/store	Richard Henderson
2021-04-30	target/arm: Enforce alignment for VLDn/VSTn (single)	Richard Henderson
2021-04-30	target/arm: Enforce alignment for VLDn/VSTn (multiple)	Richard Henderson
2021-04-30	target/arm: Enforce alignment for VLDn (all lanes)	Richard Henderson
2021-04-30	target/arm: Enforce alignment for VLDR/VSTR	Richard Henderson
2021-04-30	target/arm: Enforce alignment for VLDM/VSTM	Richard Henderson
2021-04-30	target/arm: Enforce alignment for SRS	Richard Henderson
2021-04-30	target/arm: Enforce alignment for RFE	Richard Henderson
2021-04-30	target/arm: Enforce alignment for LDM/STM	Richard Henderson
2021-04-30	target/arm: Enforce alignment for LDA/LDAH/STL/STLH	Richard Henderson
2021-04-30	target/arm: Enforce word alignment for LDRD/STRD	Richard Henderson
2021-04-30	target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness	Richard Henderson
2021-04-30	target/arm: Fix SCTLR_B test for TCGv_i64 load/store	Richard Henderson
2021-04-30	target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64	Richard Henderson
2021-04-30	target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness	Richard Henderson
2021-04-30	target/arm: Add ALIGN_MEM to TBFLAG_ANY	Richard Henderson
2021-04-30	target/arm: Move TBFLAG_ANY bits to the bottom	Richard Henderson
2021-04-30	target/arm: Move TBFLAG_AM32 bits to the top	Richard Henderson
2021-04-30	target/arm: Move mode specific TB flags to tb->cs_base	Richard Henderson
2021-04-30	target/arm: Introduce CPUARMTBFlags	Richard Henderson
2021-04-30	target/arm: Add wrapper macros for accessing tbflags	Richard Henderson
2021-04-30	target/arm: Rename TBFLAG_ANY, PSTATE_SS	Richard Henderson
2021-04-30	target/arm: Rename TBFLAG_A32, SCTLR_B	Richard Henderson
2021-04-30	target/arm: Fix decode of align in VLDST_single	Richard Henderson
2021-04-30	target/arm: Remove log2_esize parameter to gen_mte_checkN	Richard Henderson
2021-04-30	target/arm: Simplify sve mte checking	Richard Henderson
2021-04-30	target/arm: Rename mte_probe1 to mte_probe	Richard Henderson
2021-04-30	target/arm: Merge mte_check1, mte_checkN	Richard Henderson
2021-04-30	target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1	Richard Henderson
2021-04-30	target/arm: Fix unaligned checks for mte_check1, mte_probe1	Richard Henderson
2021-04-30	target/arm: Split out mte_probe_int	Richard Henderson
2021-04-30	target/arm: Fix mte_checkN	Richard Henderson
2021-04-30	target/arm: Make Thumb store insns UNDEF for Rn==1111	Peter Maydell
2021-04-23	target/s390x: fix s390_probe_access to check PAGE_WRITE_ORG for writeability	Alex Bennée
2021-04-20	target/mips/rel6_translate: Change license to GNU LGPL v2.1 (or later)	Philippe Mathieu-Daudé
2021-04-17	target/arm: drop CF_LAST_IO/dc->condjump check	Alex Bennée
2021-04-13	target/mips: Fix TCG temporary leak in gen_cache_operation()	Philippe Mathieu-Daudé
2021-04-12	target/arm: Check PAGE_WRITE_ORG for MTE writeability	Richard Henderson
2021-04-09	i386: Add missing cpu feature bits in EPYC-Rome model	Babu Moger
2021-04-06	Revert "target/arm: Make number of counters in PMCR follow the CPU"	Peter Maydell
2021-04-05	target/alpha: fix icount handling for timer instructions	Pavel Dovgalyuk
2021-04-04	Merge remote-tracking branch 'remotes/xtensa/tags/20210403-xtensa' into staging	Peter Maydell
2021-04-03	target/xtensa: make xtensa_modules static on import	Max Filippov
2021-04-03	target/xtensa: fix meson.build rule for xtensa cores	Max Filippov