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AgeCommit message (Expand)Author
2023-02-16target/arm: Move cpregs code out of cpu.hFabiano Rosas
2023-02-16target/arm: Move PC alignment checkFabiano Rosas
2023-02-16target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()Claudio Fontana
2023-02-16target/arm: wrap psci call with tcg_enabledClaudio Fontana
2023-02-16target/arm: rename handle_semihosting to tcg_handle_semihostingClaudio Fontana
2023-02-16target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'Philippe Mathieu-Daudé
2023-02-16target/arm: Store CPUARMState::nvic as NVICState*Philippe Mathieu-Daudé
2023-02-16target/arm: Restrict CPUARMState::nvic to sysemuPhilippe Mathieu-Daudé
2023-02-16target/arm: Restrict CPUARMState::arm_boot_info to sysemuPhilippe Mathieu-Daudé
2023-02-16target/arm: Restrict CPUARMState::gicv3state to sysemuPhilippe Mathieu-Daudé
2023-02-16target/arm: Avoid resetting CPUARMState::eabi fieldPhilippe Mathieu-Daudé
2023-02-16target/arm: Convert CPUARMState::eabi to booleanPhilippe Mathieu-Daudé
2023-02-16target/arm: Constify ID_PFR1 on user emulationPhilippe Mathieu-Daudé
2023-02-16target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scopePhilippe Mathieu-Daudé
2023-02-16target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulationPhilippe Mathieu-Daudé
2023-02-11target/i386: fix ADOX followed by ADCXPaolo Bonzini
2023-02-11target/i386: Fix C flag for BLSI, BLSMSK, BLSRRichard Henderson
2023-02-11target/i386: Fix BEXTR instructionRichard Henderson
2023-02-08Merge tag 'pull-tricore-20230208' of https://github.com/bkoppelmann/qemu into...Peter Maydell
2023-02-08target/tricore: Fix OPC1_16_SRO_LD_H translationAnton Kochkov
2023-02-08target/tricore: Fix OPC2_32_BO_LD_BU_PREINCBastian Koppelmann
2023-02-08target/tricore: Fix OPC2_32_RRRR_DEXTRBastian Koppelmann
2023-02-08target/tricore: Fix RRPW_DEXTRBastian Koppelmann
2023-02-08target/tricore: Fix OPC2_32_RCRW_INSERT translationBastian Koppelmann
2023-02-08target/tricore: Fix OPC2_32_RCRW_IMASK translationBastian Koppelmann
2023-02-08Drop duplicate #includeMarkus Armbruster
2023-02-08riscv: Clean up includesMarkus Armbruster
2023-02-08target/hexagon: Clean up includesMarkus Armbruster
2023-02-07target/riscv: fix SBI getchar handler for KVMVladimir Isaev
2023-02-07target/riscv: fix ctzw behaviorVladimir Isaev
2023-02-07target/riscv: fix for virtual instr exceptionDeepak Gupta
2023-02-07RISC-V: Adding XTheadFmv ISA extensionChristoph Müllner
2023-02-07RISC-V: Add initial support for T-Head C906Christoph Müllner
2023-02-07RISC-V: Set minimum priv version for Zfh to 1.11Christoph Müllner
2023-02-07RISC-V: Adding T-Head FMemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemIdx extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head MemPair extensionChristoph Müllner
2023-02-07RISC-V: Adding T-Head multiply-accumulate instructionsChristoph Müllner
2023-02-07RISC-V: Adding XTheadCondMov ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBs ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBb ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadBa ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadSync ISA extensionChristoph Müllner
2023-02-07RISC-V: Adding XTheadCmo ISA extensionChristoph Müllner
2023-02-07target/riscv: set tval for triggered watchpointsSergey Matyukevich
2023-02-07target/riscv: Ensure opcode is saved for all relevant instructionsAnup Patel
2023-02-07target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAXAnup Patel
2023-02-07target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIPAnup Patel
2023-02-07target/riscv: Update VS timer whenever htimedelta changesAnup Patel
2023-02-04Merge tag 'pull-tcg-20230204' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell