| Age | Commit message (Expand) | Author |
|---|
| 2021-09-13 | target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn | Richard Henderson |
| 2021-09-13 | target/arm: Take an exception if PSTATE.IL is set | Peter Maydell |
| 2021-09-13 | hw/arm/virt: add ITS support in virt GIC | Shashi Mallela |
| 2021-09-13 | hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM | Marc Zyngier |
| 2021-09-08 | target/sparc: Drop use of gen_io_end() | Peter Maydell |
| 2021-09-07 | s390x/cpumodel: Add more feature to gen16 default model | Christian Borntraeger |
| 2021-09-06 | hw/s390x/s390-skeys: lazy storage key enablement under TCG | David Hildenbrand |
| 2021-09-06 | s390x/mmu_helper: avoid setting the storage key if nothing changed | David Hildenbrand |
| 2021-09-06 | s390x/mmu_helper: move address validation into mmu_translate*() | David Hildenbrand |
| 2021-09-06 | s390x/mmu_helper: fixup mmu_translate() documentation | David Hildenbrand |
| 2021-09-06 | s390x/mmu_helper: no need to pass access type to mmu_translate_asce() | David Hildenbrand |
| 2021-09-06 | s390x/tcg: check for addressing exceptions for RRBE, SSKE and ISKE | David Hildenbrand |
| 2021-09-06 | s390x/tcg: convert real to absolute address for RRBE, SSKE and ISKE | David Hildenbrand |
| 2021-09-06 | s390x/tcg: fix ignoring bit 63 when setting the storage key in SSKE | David Hildenbrand |
| 2021-09-06 | s390x/tcg: wrap address for RRBE | David Hildenbrand |
| 2021-09-06 | s390x/ioinst: Fix wrong MSCH alignment check on little endian | David Hildenbrand |
| 2021-09-06 | s390x/tcg: fix and optimize SPX (SET PREFIX) | David Hildenbrand |
| 2021-09-01 | target-arm: Add support for Fujitsu A64FX | Shuuichirou Ishii |
| 2021-09-01 | target/arm: Enable MVE in Cortex-M55 | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VRINT insns | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VCVT between single and half precision | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VCVT with specified rounding mode | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VCVT between fp and integer | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VCVT between floating and fixed point | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE fp scalar comparisons | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE fp vector comparisons | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE FP max/min across vector | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE fp-with-scalar VFMA, VFMAS | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE scalar fp insns | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VMAXNMA and VMINNMA | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VCMUL and VCMLA | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VFMA and VFMS | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VCADD | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM | Peter Maydell |
| 2021-09-01 | target/arm: Implement MVE VADD (floating-point) | Peter Maydell |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVV | Richard Henderson |
| 2021-09-01 | target/riscv: Tidy trans_rvh.c.inc | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVD | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVF | Richard Henderson |
| 2021-09-01 | target/riscv: Use gen_shift_imm_fn for slli_uw | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get,dest}_gpr for RVA | Richard Henderson |
| 2021-09-01 | target/riscv: Reorg csr instructions | Richard Henderson |
| 2021-09-01 | target/riscv: Fix hgeie, hgeip | Richard Henderson |
| 2021-09-01 | target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation | Richard Henderson |
| 2021-09-01 | target/riscv: Use {get, dest}_gpr for integer load/store | Richard Henderson |
| 2021-09-01 | target/riscv: Use get_gpr in branches | Richard Henderson |
| 2021-09-01 | target/riscv: Use extracts for sraiw and srliw | Richard Henderson |
| 2021-09-01 | target/riscv: Use DisasExtend in shift operations | Richard Henderson |
| 2021-09-01 | target/riscv: Add DisasExtend to gen_unary | Richard Henderson |
| 2021-09-01 | target/riscv: Move gen_* helpers for RVB | Richard Henderson |
