peter.maydell/qemu-arm.git - This qemu repo is mostly a place to put together pull requests for upstream

Age	Commit message (Expand)	Author
2019-06-12	Supply missing header guards	Markus Armbruster
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster
2019-06-11	qemu-common: Move qemu_isalnum() etc. to qemu/ctype.h	Markus Armbruster
2019-06-10	cpu: Remove CPU_COMMON	Richard Henderson
2019-06-10	cpu: Introduce CPUNegativeOffsetState	Richard Henderson
2019-06-10	cpu: Introduce cpu_set_cpustate_pointers	Richard Henderson
2019-06-10	cpu: Move ENV_OFFSET to exec/gen-icount.h	Richard Henderson
2019-06-10	target/riscv: Use env_cpu, env_archcpu	Richard Henderson
2019-06-10	cpu: Replace ENV_GET_CPU with env_cpu	Richard Henderson
2019-06-10	cpu: Define ArchCPU	Richard Henderson
2019-06-10	cpu: Define CPUArchState with typedef	Richard Henderson
2019-06-10	tcg: Split out target/arch/cpu-param.h	Richard Henderson
2019-05-24	target/riscv: Only flush TLB if SATP.ASID changes	Jonathan Behrens
2019-05-24	target/riscv: More accurate handling of `sip` CSR	Jonathan Behrens
2019-05-24	target/riscv: Add checks for several RVC reserved operands	Richard Henderson
2019-05-24	target/riscv: Add the HGATP register masks	Alistair Francis
2019-05-24	target/riscv: Add the HSTATUS register masks	Alistair Francis
2019-05-24	target/riscv: Add Hypervisor CSR macros	Alistair Francis
2019-05-24	target/riscv: Allow setting mstatus virtulisation bits	Alistair Francis
2019-05-24	target/riscv: Add the MPV and MTL mstatus bits	Alistair Francis
2019-05-24	target/riscv: Improve the scause logic	Alistair Francis
2019-05-24	target/riscv: Trigger interrupt on MIP update asynchronously	Alistair Francis
2019-05-24	target/riscv: Mark privilege level 2 as reserved	Alistair Francis
2019-05-24	target/riscv: Add a base 32 and 64 bit CPU	Alistair Francis
2019-05-24	target/riscv: Create settable CPU properties	Alistair Francis
2019-05-24	target/riscv: Remove spaces from register names	Richard Henderson
2019-05-24	target/riscv: Split gen_arith_imm into functional and temp	Richard Henderson
2019-05-24	target/riscv: Split RVC32 and RVC64 insns into separate files	Richard Henderson
2019-05-24	target/riscv: Use pattern groups in insn16.decode	Richard Henderson
2019-05-24	target/riscv: Merge argument decode for RVC shifti	Richard Henderson
2019-05-24	target/riscv: Merge argument sets for insn32 and insn16	Richard Henderson
2019-05-24	target/riscv: Use --static-decode for decodetree	Richard Henderson
2019-05-24	target/riscv: Name the argument sets for all of insn32 formats	Richard Henderson
2019-05-24	RISC-V: fix single stepping over ret and other branching instructions	Fabien Chouteau
2019-05-24	target/riscv: Do not allow sfence.vma from user mode	Jonathan Behrens
2019-05-16	Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into staging	Peter Maydell
2019-05-13	Clean up ill-advised or unusual header guards	Markus Armbruster
2019-05-10	tcg: Use CPUClass::tlb_fill in cputlb.c	Richard Henderson
2019-05-10	target/riscv: Convert to CPUClass::tlb_fill	Richard Henderson
2019-05-06	decodetree: Add DisasContext argument to !function expanders	Richard Henderson
2019-04-24	tcg: Hoist max_insns computation to tb_gen_code	Richard Henderson
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster
2019-03-26	target/riscv: Fix wrong expanding for c.fswsp	Kito Cheng
2019-03-22	target/riscv: Zero extend the inputs of divuw and remuw	Palmer Dabbelt
2019-03-19	target/riscv: Remove unused struct	Alistair Francis
2019-03-19	RISC-V: Update load reservation comment in do_interrupt	Michael Clark
2019-03-19	RISC-V: Convert trap debugging to trace events	Michael Clark
2019-03-19	RISC-V: Add support for vectored interrupts	Michael Clark
2019-03-19	RISC-V: Change local interrupts from edge to level	Michael Clark