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path: root/target/arm/t32.decode
AgeCommit message (Expand)Author
2021-07-02target/arm: Implement MVE shifts by registerpull-target-arm-20210702Peter Maydell
2021-07-02target/arm: Implement MVE shifts by immediatePeter Maydell
2021-07-02target/arm: Implement MVE long shifts by registerPeter Maydell
2021-07-02target/arm: Implement MVE long shifts by immediatePeter Maydell
2021-06-16target/arm: Implement MVE LETP insnPeter Maydell
2021-06-16target/arm: Implement MVE DLSTPPeter Maydell
2021-06-16target/arm: Implement MVE WLSTP insnPeter Maydell
2021-06-16target/arm: Implement MVE LCTPPeter Maydell
2020-12-10target/arm: Implement M-profile "minimal RAS implementation"Peter Maydell
2020-12-10target/arm: Implement CLRM instructionPeter Maydell
2020-11-15arm tcg cpus: Fix Lesser GPL version numberChetan Pant
2020-10-20target/arm: Implement v8.1M low-overhead-loop instructionsPeter Maydell
2020-10-20target/arm: Implement v8.1M branch-future insns (as NOPs)Peter Maydell
2020-10-20target/arm: Make the t32 insn[25:23]=111 group non-overlappingPeter Maydell
2020-10-20target/arm: Implement v8.1M conditional-select insnsPeter Maydell
2020-08-24target/arm: Convert T32 coprocessor insns to decodetreePeter Maydell
2020-06-09target/arm: Use a non-overlapping group for misc controlRichard Henderson
2019-09-05target/arm: Convert TTRichard Henderson
2019-09-05target/arm: Convert SGRichard Henderson
2019-09-05target/arm: Convert Table BranchRichard Henderson
2019-09-05target/arm: Convert CPS (privileged)Richard Henderson
2019-09-05target/arm: Convert Clear-Exclusive, BarriersRichard Henderson
2019-09-05target/arm: Convert RFE and SRSRichard Henderson
2019-09-05target/arm: Convert B, BL, BLX (immediate)Richard Henderson
2019-09-05target/arm: Convert LDM, STMRichard Henderson
2019-09-05target/arm: Convert MOVW, MOVTRichard Henderson
2019-09-05target/arm: Convert Signed multiply, signed and unsigned divideRichard Henderson
2019-09-05target/arm: Convert packing, unpacking, saturation, and reversalRichard Henderson
2019-09-05target/arm: Convert Parallel addition and subtractionRichard Henderson
2019-09-05target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDFRichard Henderson
2019-09-05target/arm: Convert Synchronization primitivesRichard Henderson
2019-09-05target/arm: Convert load/store (register, immediate, literal)Richard Henderson
2019-09-05target/arm: Convert T32 ADDW/SUBWRichard Henderson
2019-09-05target/arm: Convert the rest of A32 Miscelaneous instructionsRichard Henderson
2019-09-05target/arm: Convert ERETRichard Henderson
2019-09-05target/arm: Convert CLZRichard Henderson
2019-09-05target/arm: Convert BX, BXJ, BLX (register)Richard Henderson
2019-09-05target/arm: Convert Cyclic Redundancy CheckRichard Henderson
2019-09-05target/arm: Convert MRS/MSR (banked, register)Richard Henderson
2019-09-05target/arm: Convert MSR (immediate) and hintsRichard Henderson
2019-09-05target/arm: Convert Halfword multiply and multiply accumulateRichard Henderson
2019-09-05target/arm: Convert Saturating addition and subtractionRichard Henderson
2019-09-05target/arm: Convert multiply and multiply accumulateRichard Henderson
2019-09-05target/arm: Convert Data Processing (immediate)Richard Henderson
2019-09-05target/arm: Convert Data Processing (reg-shifted-reg)Richard Henderson
2019-09-05target/arm: Convert Data Processing (register)Richard Henderson
2019-09-05target/arm: Add stubs for aa32 decodetreeRichard Henderson