path: root/target-ppc/cpu-qom.h
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2016-12-20Move target-* CPU file into a target/ folderThomas Huth
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-10-24exec: call cpu_exec_exit() from a CPU unrealize common functionLaurent Vivier
As cpu_exec_exit() mirrors the cpu_exec_realizefn(), rename it as cpu_exec_unrealizefn(). Create and register a cpu_common_unrealizefn() function for the CPU device class and call cpu_exec_unrealizefn() from this function. Remove cpu_exec_exit() from cpu_common_finalize() (which mirrors init, not realize), and as x86_cpu_unrealizefn() and ppc_cpu_unrealizefn() overwrite the device class unrealize function, add a call to a parent_unrealize pointer. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2016-09-07target-ppc: Introduce Power9 familyAneesh Kumar K.V
The patch adds CPU PVR definition for POWER9 and enables QEMU to launch guests/linux-user in TCG mode. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [ Added POWER9 alias, POWER9 SPAPR core and dropped MMU defines ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Dropped sPAPR core type again for now] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-01ppc: Fix 64K pages support in full emulationBenjamin Herrenschmidt
We were always advertising only 4K & 16M. Additionally the code wasn't properly matching the page size with the PTE content, which meant we could potentially hit an incorrect PTE if the guest used multiple sizes. Finally, honor the CPU capabilities when decoding the size from the SLB so we don't try to use 64K pages on 970. This still doesn't add support for MPSS (Multiple Page Sizes per Segment) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors commits 61a36c9b5a12 and 1114e712c998 reworked the hpte code doing insertion/removal in hw/ppc/spapr_hcall.c. The hunks modifying these areas were removed. ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-23ppc: Add P7/P8 Power Management instructionsBenjamin Herrenschmidt
This adds the ISA 2.06 and later power management instructions (doze, nap, sleep and rvwinkle) and associated wakeup cause testing in LPCR Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: fixed checkpatch.pl errors ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-06-14ppc: Split pcr_mask settings into supported bits and the register maskThomas Huth
The current pcr_mask values are ambiguous: Should these be the mask that defines valid bits in the PCR register? Or should these rather indicate which compatibility levels are possible? Anyway, POWER6 and POWER7 should certainly not use the same values here. So let's introduce an additional variable "pcr_supported" here which is used to indicate the valid compatibility levels, and use pcr_mask to signal the valid bits in the PCR register. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-05-19target-ppc: make cpu-qom.h not target specificPaolo Bonzini
Make PowerPCCPU an opaque type within cpu-qom.h, and move all definitions of private methods, as well as all type definitions that require knowledge of the layout to cpu.h. Conversely, move all definitions needed to define a class to cpu-qom.h. This helps making files independent of NEED_CPU_H if they only need to pass around CPU pointers. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-19target-ppc: do not make PowerPCCPUClass depend on target-specific symbolsPaolo Bonzini
Just leave some members in even if they are unused on e.g. 32-bit PPC or user-mode emulation. This avoids complications when using PowerPCCPUClass in code that is compiled just once (because it applies to both 32-bit and 64-bit PPC for example) but still needs to peek at PPC-specific members. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-19target-ppc: do not use target_ulong in cpu-qom.hPaolo Bonzini
Bring the PowerPCCPUClass handle_mmu_fault method type into line with the one in CPUClass. Using vaddr also makes the cpu-qom.h file target independent. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-19cpu: make cpu-qom.h only include-able from cpu.hPaolo Bonzini
Make cpu-qom.h so that it is only included from cpu.h. Then there is no need for it to include cpu.h again. Later we will make cpu-qom.h target independent and we will _want_ to include it from elsewhere, but for now reduce the number of cases to handle. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-01-15dump: qemunotes aren't commonly neededAndrew Jones
Only one of three architectures implementing qmp-dump-guest-memory write qemu notes. And, another architecture (arm/aarch64) is coming, which won't use them either. Make the common implementation truly common. (No functional change.) Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1452542185-10914-3-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-11-12monitor/target-ppc: Define target_get_monitor_defAlexey Kardashevskiy
At the moment get_monitor_def() returns only registers from statically defined monitor_defs array. However there is a lot of BOOK3S SPRs which are not in the list and cannot be printed from the monitor. This adds a new target platform hook - target_get_monitor_def(). The hook is called if a register was not found in the static array returned by the target_monitor_defs() hook. The hook is only defined for POWERPC, it returns registered SPRs and fails on unregistered ones providing the user with information on what is actually supported on the running CPU. The register value is saved as uint64_t as it is the biggest supported register size; target_ulong cannot be used because of the stub - it is in a "common" code and cannot include "cpu.h", etc; this is also why the hook prototype is redefined in the stub instead of being included from some header. This replaces static descriptors for GPRs, FPRs, SRs with a helper which looks for a value in a corresponding array in the CPUPPCState. The immediate effect is that all 32 SRs can be printed now (instead of 16); later this can be reused for VSX or TM registers. This replaces callbacks for MSR and XER with static descriptors in monitor_defs as they are stored in CPUPPCState. While we are here, this adds "cr" as a synonym of "ccr". Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2014-09-25target-ppc: Use cpu_exec_interrupt qom hookRichard Henderson
Cc: qemu-ppc@nongnu.org Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-22-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-25spapr: Add support for new NMI interfaceAlexey Kardashevskiy
This implements an NMI interface POWERPC SPAPR machine. This enables an "nmi" HMP/QMP command supported on SPAPR. This calls POWERPC_EXCP_RESET (vector 0x100) in the guest to deliver NMI to every CPU. The expected result is XMON (in-kernel debugger) invocation. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-07-08target-ppc: Add pvr_match() callbackAlexey Kardashevskiy
So far it was enough to have a base PVR value and mask per CPU family such as POWER7 or POWER8. However there CPUs which are completely architecturally compatible but have different PVRs such as POWER7/POWER7+ and POWER8/POWER8E. For these CPUs, top 16 bits are CPU family and low 16 bits are the version. The families have PVR base values different enough so defining a mask which would cover both (or potentially more) CPUs within the family is not possible. This adds a pvr_match() callback to PowerPCCPUClass. The default handler simply compares PVR defined in the class. This implements ppc_pvr_match_power7/ppc_pvr_match_power8 callbacks for POWER7/8 families. These check for POWER7/POWER7+ and POWER8/POWER8E. This changes ppc_cpu_compare_class_pvr_mask() not to check masks but use the pvr_match() callback. Since all server CPUs use the same mask, this defines one mask value - CPU_POWERPC_POWER_SERVER_MASK - which is used everywhere now. This removes other mask definitions. This removes pvr_mask from PowerPCCPUClass as it is not used anymore. This removes pvr initialization for POWER7/8 families as it is not used to find the class, the pvr_match() callback is used instead. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-27PPC: Add support for Apple gdb in gdbstubAlexander Graf
The Apple gdbstub protocol is different from the normal gdbstub protocol used on PowerPC. Add support for the different variant, so that we can use Apple's gdb to debug guest code. Keep in mind that the switch is a compile time option. We can't detect during runtime whether a gdb connecting to us is an upstream gdb or an Apple gdb. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Define Processor Compatibility MasksAlexey Kardashevskiy
This introduces PCR mask for supported compatibility modes. This will be used later by the ibm,client-architecture-support call. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Implement "compat" CPU optionAlexey Kardashevskiy
This adds basic support for the "compat" CPU option. By specifying the compat property, the user can manually switch guest CPU mode from "raw" to "architected". This defines feature disable bits which are not used yet as, for example, PowerISA 2.07 says if 2.06 mode is selected, the TM bit does not matter - transactional memory (TM) will be disabled because 2.06 does not define it at all. The same is true for VSX and 2.05 mode. So just setting a mode must be ok. This does not change the existing behavior as the actual compatibility mode support is coming in next patches. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: fix compilation on 32bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add "compat" CPU optionAlexey Kardashevskiy
PowerISA defines a compatibility mode for server POWERPC CPUs which is supported by the PCR special register which is hypervisor privileged. To support this mode for guests, SPAPR defines a set of virtual PVRs, one per PowerISA spec version. When a hypervisor needs a guest to work in a compatibility mode, it puts a virtual PVR value into @cpu-version property of a CPU node. This introduces a "compat" CPU option which defines maximal compatibility mode enabled. The supported modes are power6/power7/power8. This does not change the existing behaviour, new property will be used by next patches. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce callback for interrupt endiannessGreg Kurz
POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR special purpose register to decide the endianness to use when entering interrupt handlers. When running a Linux guest, this provides a hint on the endianness used by the kernel. And when it comes to dumping a guest, the information is needed to write ELF headers using the kernel endianness. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> [agraf: change subject line] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Add support for time base offset migrationAlexey Kardashevskiy
This allows guests to have a different timebase origin from the host. This is needed for migration, where a guest can migrate from one host to another and the two hosts might have a different timebase origin. However, the timebase seen by the guest must not go backwards, and should go forwards only by a small amount corresponding to the time taken for the migration. This is only supported for recent POWER hardware which has the TBU40 (timebase upper 40 bits) register. That includes POWER6, 7, 8 but not 970. This adds kvm_access_one_reg() to access a special register which is not in env->spr. This requires kvm_set_one_reg/kvm_get_one_reg patch. The feature must be present in the host kernel. This bumps vmstate_spapr::version_id and enables new vmstate_ppc_timebase only for it. Since the vmstate_spapr::minimum_version_id remains unchanged, migration from older QEMU is supported but without vmstate_ppc_timebase. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-03-13target-ppc: Use PowerPCCPU in PowerPCCPUClass::handle_mmu_fault hookAndreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-03-05target-ppc: add PowerPCCPU::cpu_dt_idAlexey Kardashevskiy
Normally CPUState::cpu_index is used to pick the right CPU for various operations. However default consecutive numbering does not always work for POWERPC. These indexes are reflected in /proc/device-tree/cpus/PowerPC,POWER7@XX and used to call KVM VCPU's ioctls. In order to achieve this, kvmppc_fixup_cpu() was introduced. Roughly speaking, it multiplies cpu_index by the number of threads per core. This approach has disadvantages such as: 1. NUMA configuration stays broken after the fixup; 2. CPU-targeted commands from the QEMU Monitor do not work properly as CPU indexes have been fixed and there is no clear way for the user to know what the new CPU indexes are. This introduces a @cpu_dt_id field in the CPUPPCState struct which is initialized from @cpu_index by default and can be fixed later to meet the device tree requirements. This adds an API to handle @cpu_dt_id. This removes kvmppc_fixup_cpu() as it is not more needed, @cpu_dt_id is calculated in ppc_cpu_realize(). This will be used later in machine code. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Mike Day <ncmike@ncultra.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-12-20powerpc: add PVR mask supportAlexey Kardashevskiy
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and a CPU version in lower 16 bits. Since there is no significant change in behavior between versions, there is no point to add every single CPU version in QEMU's CPU list. Also, new CPU versions of already supported CPU won't break the existing code. This adds PVR value/mask support for KVM, i.e. for -cpu host option. As CPU family class name for POWER7 is "POWER7-family", there is no need to touch aliases. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-10-25target-ppc: dump-guest-memory supportAneesh Kumar K.V
This patch add support for dumping guest memory using dump-guest-memory monitor command. Before patch: (qemu) dump-guest-memory testcrash this feature or command is not currently supported (qemu) After patch: (qemu) dump-guest-memory testcrash (qemu) crash was able to read the file crash> bt PID: 0 TASK: c000000000c0d0d0 CPU: 0 COMMAND: "swapper/0" R0: 0000000028000084 R1: c000000000cafa50 R2: c000000000cb05b0 R3: 0000000000000000 R4: c000000000bc4cb0 R5: 0000000000000000 R6: 001efe93b8000000 R7: 0000000000000000 R8: 0000000000000000 R9: b000000000001032 R10: 0000000000000001 R11: 0001eb2117e00d55 .... ... NOTE: Currently crash tools doesn't look at ELF notes in the dump on ppc64. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-07-29target-ppc: Convert ppc cpu savevm to VMStateDescriptionAlexey Kardashevskiy
The savevm code for the powerpc cpu emulation is currently based around the old register_savevm() rather than register_vmstate() method. It's also rather broken, missing some important state on some CPU models. This patch completely rewrites the savevm for target-ppc, using the new VMStateDescription approach. Exactly what needs to be saved in what configurations has been more carefully examined, too. This introduces a new version (5) of the cpu save format. The old load function is retained to support version 4 images. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Message-id: 1374175984-8930-2-git-send-email-aliguori@us.ibm.com [aik: ppc cpu savevm convertion fixed to use PowerPCCPU instead of CPUPPCState] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2013-07-27cpu: Introduce CPUClass::gdb_{read,write}_register()Andreas Färber
Completes migration of target-specific code to new target-*/gdbstub.c. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-23cpu: Turn cpu_get_phys_page_debug() into a CPUClass hookAndreas Färber
Change breakpoint_invalidate() argument to CPUState alongside. Since all targets now assign a softmmu-only field, we can drop helpers cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd(). Prepares for changing cpu_memory_rw_debug() argument to CPUState. Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-09cpu: Drop unnecessary dynamic casts in *_env_get_cpu()Andreas Färber
A transition from CPUFooState to FooCPU can be considered safe, just like FooCPU::env access in the opposite direction. The only benefit of the FOO_CPU() casts would be protection against bogus CPUFooState pointers, but then surrounding code would likely break, too. This should slightly improve interrupt etc. performance when going from CPUFooState to FooCPU. For any additional CPU() casts see 3556c233d931ad5ffa46a35cb25cfc057732ebb8 (qom: allow turning cast debugging off). Reported-by: Anthony Liguori <aliguori@us.ibm.com> Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber
Make cpustats monitor command available unconditionally. Prepares for changing kvm_handle_internal_error() and kvm_cpu_exec() arguments to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-04-26pseries: Fixes and enhancements to L1 cache propertiesDavid Gibson
PAPR requires that the device tree's CPU nodes have several properties with information about the L1 cache. We already create two of these properties, but with incorrect names - "[id]cache-block-size" instead of "[id]-cache-block-size" (note the extra hyphen). We were also missing some of the required cache properties. This patch adds the [id]-cache-line-size properties (which have the same values as the block size properties in all current cases). We also add the [id]-cache-size properties. Adding the cache sizes requires some extra infrastructure in the general target-ppc code to (optionally) set the cache sizes for various CPUs. The CPU family descriptions in translate_init.c can set these sizes - this patch adds correct information for POWER7, I'm leaving other CPU types to people who have a physical example to verify against. In addition, for -cpu host we take the values advertised by the host (if available) and use those to override the information based on PVR. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-22target-ppc: Use QOM method dispatch for MMU fault handlingDavid Gibson
After previous cleanups, the many scattered checks of env->mmu_model in the ppc MMU implementation have, at least for "classic" hash MMUs been reduced (almost) to a single switch at the top of cpu_ppc_handle_mmu_fault(). An explicit switch is still a pretty ugly way of handling this though. Now that Andreas Färber's CPU QOM cleanups for ppc have gone in, it's quite straightforward to instead make the handle_mmu_fault function a QOM method on the CPU object. This patch implements such a scheme, initializing the method pointer at the same time as the mmu_model variable. We need to keep the latter around for now, because of the MMU types (BookE, 4xx, et al) which haven't been converted to the new scheme yet, and also for a few other uses. It would be good to clean those up eventually. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber
This removes a global per-target function and thus takes us one step closer to compiling multiple targets into one executable. It will also allow to override the interrupt handling for certain CPU families. Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-03-08target-ppc: Convert CPU definitionsAndreas Färber
Turn the array of model definitions into a set of self-registering QOM types with their own class_init. Unique identifiers are obtained from the combination of PVR, SVR and family identifiers; this requires all alias #defines to be removed from the list. Possibly there are some more left after this commit that are not currently being compiled. Prepares for introducing abstract intermediate CPU types for families. Keep the right-aligned macro line breaks within 78 chars to aid three-way merges. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-03-03cpu: Introduce ENV_OFFSET macrosAndreas Färber
Introduce ENV_OFFSET macros which can be used in non-target-specific code that needs to generate TCG instructions which reference CPUState fields given the cpu_env register that TCG targets set up with a pointer to the CPUArchState struct. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2013-02-16target-ppc: Update PowerPCCPU to QOM realizefnAndreas Färber
Adapt ppc_cpu_realize() signature, hook it up to DeviceClass and set realized = true in cpu_ppc_init(). Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-01-07target-ppc: Slim conversion of model definitions to QOM subclassesAndreas Färber
Since the model list is highly macrofied, keep ppc_def_t for now and save a pointer to it in PowerPCCPUClass. This results in a flat list of subclasses including aliases, to be refined later. Move cpu_ppc_init() to translate_init.c and drop helper.c. Long-term the idea is to turn translate_init.c into a standalone cpu.c. Inline cpu_ppc_usable() into type registration. Split cpu_ppc_register() in two by code movement into the initfn and by turning the remaining part into a realizefn. Move qemu_init_vcpu() call into the new realizefn and adapt create_ppc_opcodes() to return an Error. Change ppc_find_by_pvr() -> ppc_cpu_class_by_pvr(). Change ppc_find_by_name() -> ppc_cpu_class_by_name(). Turn -cpu host into its own subclass. This requires to move the kvm_enabled() check in ppc_cpu_class_by_name() to avoid the class being found via the normal name lookup in the !kvm_enabled() case. Turn kvmppc_host_cpu_def() into the class_init and add an initfn that asserts KVM is in fact enabled. Implement -cpu ? and the QMP equivalent in terms of subclasses. This newly exposes -cpu host to the user, ordered last for -cpu ?. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-19qom: move include files to include/qom/Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2012-04-15target-ppc: QOM'ify CPUAndreas Färber
Embed CPUPPCState as first member of PowerPCCPU. Distinguish between "powerpc-cpu", "powerpc64-cpu" and "embedded-powerpc-cpu". Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>