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2014-09-29target-arm: Implement setting guest breakpointsPeter Maydell
This patch adds support for setting guest breakpoints based on values the guest writes to the DBGBVR and DBGBCR registers. (It doesn't include the code to handle when these breakpoints fire, so has no guest-visible effect.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1410523465-13400-2-git-send-email-peter.maydell@linaro.org
2014-09-25target-arm: Use cpu_exec_interrupt qom hookRichard Henderson
Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-15-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12target-arm: Make *IS TLB maintenance ops affect all CPUsPeter Maydell
The ARM architecture defines that the "IS" variants of TLB maintenance operations must affect all TLBs in the Inner Shareable domain, which for us means all CPUs. We were incorrectly implementing these to only affect the current CPU, which meant that SMP TCG operation was unstable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1410274883-9578-3-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org
2014-09-12target-arm: Push legacy wildcard TLB ops back into v6Peter Maydell
When we implemented ARMv8 in QEMU we retained our legacy loose wildcarded decoding of the TLB maintenance operations for v7 and earlier CPUs and provided the correct stricter decode for v8. However the loose decode is in fact wrong for v7MP, because it doesn't correctly implement the operations which must apply to every CPU in the Inner Shareable domain. Move the legacy wildcarding from the not_v8 reginfo array into the not_v7 array, and move the strictly decoded operations from the v8 reginfo to v7 or v7mp arrays as appropriate. Cache and TLB lockdown legacy wildcarding remains in the not_v8 array for the moment. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1410274883-9578-2-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org
2014-09-12target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0Peter Maydell
Implement debug registers DBGVCR, OSDLR_EL1 and MDCCSR_EL0 (as dummy or limited-functionality). 32 bit Linux kernels will access these at startup so they are required for breakpoints and watchpoints to be supported. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12target-arm: Remove comment about MDSCR_EL1 being dummy implementationPeter Maydell
MDSCR_EL1 has actual functionality now; remove the out of date comment that claims it is a dummy implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12target-arm: Set DBGDSCR.MOE for debug exceptions taken to AArch32Peter Maydell
For debug exceptions taken to AArch32 we have to set the DBGDSCR.MOE (Method Of Entry) bits; we can identify the kind of debug exception from the information in exception.syndrome. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12target-arm: Implement handling of fired watchpointsPeter Maydell
Implement the ARM debug exception handler for dealing with fired watchpoints. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12target-arm: Move extended_addresses_enabled() to internals.hPeter Maydell
Move the utility function extended_addresses_enabled() into internals.h; we're going to need to call it from op_helper.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12target-arm: Implement setting of watchpointsPeter Maydell
Implement support for setting QEMU watchpoints based on the values the guest writes to the ARM architected watchpoint registers. (We do not yet report the firing of the watchpoints to the guest, so they will just be ignored.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12target-arm: Fix broken indentation in arm_cpu_reest()Martin Galvan
Fix a single misindented line in arm_cpu_reset(). Signed-off-by: Martin Galvan <martin.galvan@tallertechnologies.com> [PMM: split this out from the previous commit] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12target-arm: Fix resetting issues on ARMv7-M CPUsMartin Galvan
When calling qemu_system_reset after startup on a Cortex-M CPU, the initial values of PC, MSP and the Thumb bit weren't being set correctly if the vector table was in ROM. In particular, since Thumb was 0, a Usage Fault would arise immediately after trying to execute any instruction on a Cortex-M. Signed-off-by: Martin Galvan <martin.galvan@tallertechnologies.com> Message-id: CAOKbPbaLt-LJsAKkQdOE0cs9Xx4OWrUfpDhATXPSdtuNw2xu_A@mail.gmail.com [PMM: removed an incorrect comment] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Implement pmccfiltr_write functionpull-target-arm-20140829Alistair Francis
This is the function that is called when writing to the PMCCFILTR_EL0 register Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 73da3da6404855b17d5ae82975a32ff3a4dcae3d.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Remove old code and replace with new functionsAlistair Francis
Remove the old PMCCNTR code and replace it with calls to the new pmccntr_sync() and arm_ccnt_enabled() functions. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 693a6e437d915c2195fd3dc7303f384ca538b7bf.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Implement pmccntr_sync functionAlistair Francis
This is used to synchronise the PMCCNTR counter and swap its state between enabled and disabled if required. It must always be called twice, both before and after any logic that could change the state of the PMCCNTR counter. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 62811d4c0f7b1384f7aab62ea2fcfda3dcb0db50.1409025949.git.peter.crosthwaite@xilinx.com [PMM: fixed minor typos in pmccntr_sync doc comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Add arm_ccnt_enabled functionAlistair Francis
Include a helper function to determine if the CCNT counter is enabled. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e1a64f17a756e06c8bda8238ad4826d705049f7a.1409025949.git.peter.crosthwaite@xilinx.com [ PC changes * Remove EL based checks ] Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Implement PMCCNTR_EL0 and related registersAlistair Francis
This patch adds support for the ARMv8 version of the PMCCNTR and related registers. It also starts to implement the PMCCFILTR_EL0 register. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b5d1094764a5416363ee95216799b394ecd011e8.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29arm: Implement PMCCNTR 32b read-modify-writePeter Crosthwaite
The register is now 64bit, however a 32 bit write to the register should leave the higher bits unchanged. The open coded write handler does not implement this, so we need to read-modify-write accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Alistair Francis <alistair23@gmail.com> Message-id: ec350573424bb2adc1701c3b9278d26598e2f2d1.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Make the ARM PMCCNTR register 64-bitAlistair Francis
This makes the PMCCNTR register 64-bit to allow for the 64-bit ARMv8 version. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 6c5bac5fd0ea54963b1fc0e7f9464909f2e19a73.1409025949.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register valuesPeter Maydell
We implement the crypto extensions but were incorrectly reporting ID register values for the Cortex-A57 which did not advertise crypto. Use the correct values as described in the TRM. With this fix Linux correctly detects presence of the crypto features and advertises them in /proc/cpuinfo. Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1408718660-7295-1-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-29target-arm: Fix regression that disabled VFP for ARMv5 CPUsPeter Maydell
Commit 2c7ffc414 added support for honouring the CPACR coprocessor access control register bits which may disable access to VFP and Neon instructions. However it failed to account for the fact that the CPACR is only present starting from the ARMv6 architecture version, so it accidentally disabled VFP completely for ARMv5 CPUs like the ARM926. Linux would detect this as "no VFP present" and probably fall back to its own emulation, but other guest OSes might crash or misbehave. This fixes bug LP:1359930. Reported-by: Jakub Jermar <jakub@jermar.eu> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1408714940-7192-1-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19arm: cortex-a9: Fix cache-line size and associativityPeter Crosthwaite
For A9, The cache associativity is 4 and the lines size is 32B. Self identify in CCSIDR accordingly. Cache size remains at 16k. QEMU doesn't emulate caches, but we should still report the correct cache-line size to the guest. Some guests (like u-boot) complain if the cache-line size mismatches a requested flush or invalidate operation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1de6bd40155a1d2f2e93e24b1b1d1d677a432641.1408346233.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2Christoffer Dall
The current code supplies the PSCI v0.1 function IDs in the DT even when KVM uses PSCI v0.2. This will break guest kernels that only support PSCI v0.1 as they will use the IDs provided in the DT. Guest kernels with PSCI v0.2 support are not affected by this patch, because they ignore the function IDs in the device tree and rely on the architecture definition. Define QEMU versions of the constants and check that they correspond to the Linux defines on Linux build hosts. After this patch, both guest kernels with PSCI v0.1 support and guest kernels with PSCI v0.2 should work. Tested on TC2 for 32-bit and APM Mustang for 64-bit (aarch64 guest only). Both cases tested with 3.14 and linus/master and verified I could bring up 2 cpus with both guest kernels. Also tested 32-bit with a 3.14 host kernel with only PSCI v0.1 and both guests booted here as well. Cc: qemu-stable@nongnu.org Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19target-arm: Rename QEMU PSCI v0.1 definitionsChristoffer Dall
The function IDs for PSCI v0.1 are exported by KVM and defined as KVM_PSCI_FN_<something>. To build using these defines in non-KVM code, QEMU defines these IDs locally and check their correctness against the KVM headers when those are available. However, the naming scheme used for QEMU (almost) clashes with the PSCI v0.2 definitions from Linux so to avoid unfortunate naming when we introduce local PSCI v0.2 defines, rename the current local defines with QEMU_ prependend and clearly identify the PSCI version as v0.1 in the defines. Cc: qemu-stable@nongnu.org Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19target-arm: Implement MDSCR_EL1 as having statePeter Maydell
Now that all the new code to support single-stepping is in place, wire up the guest-visible MDSCR_EL1, so the guest can enable single-stepping. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: Implement ARMv8 single-stepping for AArch32 codePeter Maydell
ARMv8 single-stepping requires the exception level that controls the single-stepping to be in AArch64 execution state, but the code being stepped may be in AArch64 or AArch32. Implement the necessary support code for single-stepping AArch32 code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: Implement ARMv8 single-step handling for A64 codePeter Maydell
Implement ARMv8 software single-step handling for A64 code: correctly update the single-step state machine and generate debug exceptions when stepping A64 code. This patch has no behavioural change since MDSCR_EL1.SS can't be set by the guest yet. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: A64: Avoid duplicate exit_tb(0) in non-linked goto_tbPeter Maydell
If gen_goto_tb() decides not to link the two TBs, then the fallback path generates unnecessary code: * if singlestep is enabled then we generate unreachable code after the gen_exception_internal(EXCP_DEBUG) * if singlestep is disabled then we will generate exit_tb(0) twice, once in gen_goto_tb() and once coming out of the main loop with is_jmp set to DISAS_JUMP Correct these deficiencies by only emitting exit_tb() in the non-singlestep case, in which case we can use DISAS_TB_JUMP to suppress the main-loop exit_tb(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: Set PSTATE.SS correctly on exception return from AArch64Peter Maydell
Set the PSTATE.SS bit correctly on exception returns from AArch64, as required by the debug single-step functionality. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: Correctly handle PSTATE.SS when taking exception to AArch32Peter Maydell
When an exception is taken to AArch32, we must clear the PSTATE.SS bit for the exception handler, and must also ensure that the SS bit is not set in the value saved to SPSR_<mode>. Achieve both of these aims by clearing the bit in uncached_cpsr before saving it to the SPSR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: Don't allow AArch32 to access RES0 CPSR bitsPeter Maydell
The CPSR has a new-in-v8 execution state bit (IL), and also some state which has effects in AArch32 but appears only in the SPSR format (SS) but is RES0 in the CPSR. Add the IL bit to CPSR_EXEC, and enforce that guest direct reads and writes to CPSR can't read or write the RES0 bits, so the guest can't get at the SS bit which we store in uncached_cpsr. This includes not permitting exception returns to copy reserved bits from an SPSR into CPSR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: Adjust debug ID registers per-CPUPeter Maydell
Allow each CPU type to specify the value for the debug ID registers, by putting them in the ARMCPU struct, and use the resulting information to only expose the correct number of watchpoint and breakpoint registers for the CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: Provide both 32 and 64 bit versions of debug registersPeter Maydell
Bring the 32 bit and 64 bit views of the debug registers into line by providing the same set of registers in both cases. (This still isn't a complete set, but it is consistent.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: Allow STATE_BOTH reginfo descriptions for more than cp14Peter Maydell
Currently the STATE_BOTH shorthand for allowing a single reginfo struct to define handling for both AArch32 and AArch64 views of a register only permits this where the AArch32 view is in cp15. It turns out that the debug registers in cp14 also have neatly lined up encodings; allow these also to share reginfo structs by permitting a STATE_BOTH reginfo to specify the .cp field (and continue to default to 15 if it is not specified). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: Collect up the debug cp register definitionsPeter Maydell
At the moment we have a mixed set of mostly dummy register definitions for various debug related registers which have been added piecemeal in order to get Linux kernels to boot. In preparation for actually implementing debug support, bring them all together into one place. This commit doesn't change behaviour: we still expose exactly the same registers and behaviour to the guest in all configurations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2014-08-19target-arm: Fix return address for A64 BRK instructionsPeter Maydell
When we take an exception resulting from a BRK instruction, the architecture requires that the "preferred return address" reported to the exception handler is the address of the BRK itself, not the following instruction (like undefined insns, and in contrast with SVC, HVC and SMC). Follow this, rather than incorrectly reporting the address of the following insn. (We do get this correct for the A32/T32 BKPT insns.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Cc: qemu-stable@nongnu.org
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-08-04target-arm: A64: fix TLB flush instructionspull-target-arm-20140804Alex Bennée
According to the ARM ARM we weren't correctly flushing the TLB entries where bits 63:56 didn't match bit 55 of the virtual address. This exposed a problem when we switched QEMU's internal TARGET_PAGE_BITS to 12 for aarch64. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1406733627-24255-3-git-send-email-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: don't hardcode mask values in arm_cpu_handle_mmu_faultAlex Bennée
Otherwise we break quickly when we change TARGET_PAGE_SIZE. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1406733627-24255-2-git-send-email-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: Fix bit test in sp_el0_accessStefan Weil
Static code analyzers complain about a dubious & operation used for a boolean value. The code does not test the PSTATE_SP bit as it should. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1406359601-25583-1-git-send-email-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: Add FAR_EL2 and 3Edgar E. Iglesias
Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1402994746-8328-7-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: Add ESR_EL2 and 3Edgar E. Iglesias
Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1402994746-8328-6-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: Make far_el1 an arrayEdgar E. Iglesias
No functional change. Prepares for future additions of the EL2 and 3 versions of this reg. Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1402994746-8328-5-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: A64: Respect SPSEL when taking exceptionsEdgar E. Iglesias
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1402994746-8328-4-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: A64: Respect SPSEL in ERET SP restoreEdgar E. Iglesias
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1402994746-8328-3-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04target-arm: A64: Break out aarch64_save/restore_spEdgar E. Iglesias
Break out code to save/restore AArch64 SP into functions. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1402994746-8328-2-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-07-08target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUspull-target-arm-20140708Peter Maydell
Implement kvm_arm_vcpu_init() as a simple call to arm_arm_vcpu_init() (which uses the KVM_ARM_VCPU_INIT vcpu ioctl to tell the kernel to re-initialize the vCPU), rather than via the complicated code which saves a copy of the register state on first init and then writes it back to the kernel. This is much simpler and brings the 32-bit KVM code into line with the 64-bit code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1403802973-20841-1-git-send-email-peter.maydell@linaro.org
2014-06-24Fix new typos (found by codespell)Stefan Weil
* accomodate -> accommodate * aquiring -> acquiring * beacuse -> because * loosing -> losing * prefering -> preferring * threshhold -> threshold Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2014-06-19target-arm: Introduce per-CPU field for PSCI versionPranavkumar Sawargaonkar
We require to know the PSCI version available to given CPU at potentially many places. Currently, we need to know PSCI version when generating DTB for virt machine. This patch introduce per-CPU 32bit field representing the PSCI version available to the CPU. The encoding of this 32bit field is same as described in PSCI v0.2 spec. Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> Signed-off-by: Anup Patel <anup.patel@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1402901605-24551-8-git-send-email-pranavkumar@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-19target-arm: Implement kvm_arch_reset_vcpu() for KVM ARM64Pranavkumar Sawargaonkar
To implement kvm_arch_reset_vcpu(), we simply re-init the VCPU using kvm_arm_vcpu_init() so that all registers of VCPU are set to their reset values by in-kernel KVM code. Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> Signed-off-by: Anup Patel <anup.patel@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1402901605-24551-7-git-send-email-pranavkumar@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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