aboutsummaryrefslogtreecommitdiff
path: root/target-arm/helper.c
AgeCommit message (Expand)Author
2016-01-14target-arm: Support multiple address spaces in page table walksPeter Maydell
2016-01-14target-arm: Implement cpu_get_phys_page_attrs_debugPeter Maydell
2015-12-17target-arm: raise exception on misaligned LDREX operandsAndrew Baumann
2015-11-24target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8Peter Maydell
2015-11-03target-arm: Add and use symbolic names for register banksSoren Brinkmann
2015-10-27target-arm: Add support for S1 + S2 MMU translationspull-target-arm-20151027-1Edgar E. Iglesias
2015-10-27target-arm: Add S2 translation to 32bit S1 PTWsEdgar E. Iglesias
2015-10-27target-arm: Add S2 translation to 64bit S1 PTWsEdgar E. Iglesias
2015-10-27target-arm: Add ARMMMUFaultInfoEdgar E. Iglesias
2015-10-27target-arm: Avoid inline for get_phys_addrEdgar E. Iglesias
2015-10-27target-arm: Add support for S2 page-table protection bitsEdgar E. Iglesias
2015-10-27target-arm: Add computation of starting level for S2 PTWEdgar E. Iglesias
2015-10-27target-arm: lpae: Rename granule_sz to strideEdgar E. Iglesias
2015-10-27target-arm: lpae: Replace tsz with computed inputsizeEdgar E. Iglesias
2015-10-27target-arm: Add support for AArch32 S2 negative t0szEdgar E. Iglesias
2015-10-27target-arm: lpae: Move declaration of t0sz and t1szEdgar E. Iglesias
2015-10-27target-arm: lpae: Make t0sz and t1sz signed integersEdgar E. Iglesias
2015-10-27target-arm: Add HPFAR_EL2Edgar E. Iglesias
2015-10-27target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)Soren Brinkmann
2015-10-16target-arm: Add MDCR_EL2Sergey Fedorov
2015-10-16target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregsDavorin Mista
2015-10-16target-arm: Avoid calling arm_el_is_aa64() function for unimplemented ELSergey Sorokin
2015-10-16target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin
2015-10-16target-arm: Add missing 'static' attributeStefan Weil
2015-09-25arm: clarify the use of muldiv64()Laurent Vivier
2015-09-15target-arm: Use new revbit functionsRichard Henderson
2015-09-14target-arm: Add VMPIDR_EL2pull-target-arm-20150914Edgar E. Iglesias
2015-09-14target-arm: Break out mpidr_read_val()Edgar E. Iglesias
2015-09-14target-arm: Add VPIDR_EL2Edgar E. Iglesias
2015-09-14target-arm: Suppress EPD for S2, EL2 and EL3 translationsEdgar E. Iglesias
2015-09-14target-arm: Suppress TBI for S2 translationsEdgar E. Iglesias
2015-09-14target-arm: Add VTTBR_EL2Edgar E. Iglesias
2015-09-14target-arm: Add VTCR_EL2Edgar E. Iglesias
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt
2015-09-11maint: remove / fix many doubled wordsDaniel P. Berrange
2015-09-08target-arm: Add AArch64 access to PAR_EL1Edgar E. Iglesias
2015-09-08target-arm: Correct opc1 for AT_S12ExxEdgar E. Iglesias
2015-09-07target-arm: Fix AArch32:AArch64 general-purpose register mappingSergey Sorokin
2015-09-07arm: Remove hw_error() usages.Peter Crosthwaite
2015-09-07target-arm: Improve semihosting debug printsChristopher Covington
2015-08-25target-arm: Implement AArch64 TLBI operations on IPAspull-target-arm-20150825-1Peter Maydell
2015-08-25target-arm: Implement missing EL3 TLB invalidate operationsPeter Maydell
2015-08-25target-arm: Implement missing EL2 TLBI operationsPeter Maydell
2015-08-25target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touchPeter Maydell
2015-08-25target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric orderPeter Maydell
2015-08-25target-arm: Implement AArch32 ATS1H* operationsPeter Maydell
2015-08-25target-arm: Enable the AArch32 ATS12NSO opsPeter Maydell
2015-08-25target-arm: Wire up AArch64 EL2 and EL3 address translation opsPeter Maydell
2015-08-25target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translationsPeter Maydell
2015-08-25target-arm: Implement missing ACTLR registersPeter Maydell