aboutsummaryrefslogtreecommitdiff
path: root/target-arm/helper.c
AgeCommit message (Expand)Author
2016-02-19target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEFmissing-idregsPeter Maydell
2016-02-18target-arm: Add PMUSERENR_EL0 registerAlistair Francis
2016-02-18target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis
2016-02-18target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis
2016-02-18target-arm: Move bank_number() into internals.hPeter Maydell
2016-02-18target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell
2016-02-18target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell
2016-02-18target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA trapsPeter Maydell
2016-02-18target-arm: Implement MDCR_EL2.TDRA trapsPeter Maydell
2016-02-18target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA trapsPeter Maydell
2016-02-18target-arm: correct CNTFRQ access rightsPeter Maydell
2016-02-11target-arm: Implement NSACR trapping behaviourPeter Maydell
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell
2016-02-11target-arm: Use access_trap_aa32s_el1() for SCR and MVBARPeter Maydell
2016-02-11target-arm: Implement MDCR_EL3 and SDCRPeter Maydell
2016-02-03target-arm: Implement the S2 MMU inputsize > pamax checkEdgar E. Iglesias
2016-02-03target-arm: Rename check_s2_startlevel to check_s2_mmu_setupEdgar E. Iglesias
2016-02-03target-arm: Apply S2 MMU startlevel table size check to AArch64Edgar E. Iglesias
2016-02-03target-arm: Make various system registers visible to EL3Peter Maydell
2016-01-21target-arm: Implement FPEXC32_EL2 system registerpull-target-arm-20160121Peter Maydell
2016-01-21target-arm: Fix wrong AArch64 entry offset for EL2/EL3 targetPeter Maydell
2016-01-21target-arm: Pull semihosting handling out to arm_cpu_do_interrupt()Peter Maydell
2016-01-21target-arm: Use a single entry point for AArch64 and AArch32 exceptionsPeter Maydell
2016-01-21target-arm: Move aarch64_cpu_do_interrupt() to helper.cPeter Maydell
2016-01-21target-arm: Support multiple address spaces in page table walksPeter Maydell
2016-01-21target-arm: Implement cpu_get_phys_page_attrs_debugPeter Maydell
2016-01-18target-arm: Clean up includesPeter Maydell
2016-01-15target-arm: Use the right MMU index in arm_regime_using_lpae_formatAlvise Rigo
2015-12-17target-arm: raise exception on misaligned LDREX operandsAndrew Baumann
2015-11-24target-arm: Don't mask out bits [47:40] in LPAE descriptors for v8Peter Maydell
2015-11-03target-arm: Add and use symbolic names for register banksSoren Brinkmann
2015-10-27target-arm: Add support for S1 + S2 MMU translationspull-target-arm-20151027-1Edgar E. Iglesias
2015-10-27target-arm: Add S2 translation to 32bit S1 PTWsEdgar E. Iglesias
2015-10-27target-arm: Add S2 translation to 64bit S1 PTWsEdgar E. Iglesias
2015-10-27target-arm: Add ARMMMUFaultInfoEdgar E. Iglesias
2015-10-27target-arm: Avoid inline for get_phys_addrEdgar E. Iglesias
2015-10-27target-arm: Add support for S2 page-table protection bitsEdgar E. Iglesias
2015-10-27target-arm: Add computation of starting level for S2 PTWEdgar E. Iglesias
2015-10-27target-arm: lpae: Rename granule_sz to strideEdgar E. Iglesias
2015-10-27target-arm: lpae: Replace tsz with computed inputsizeEdgar E. Iglesias
2015-10-27target-arm: Add support for AArch32 S2 negative t0szEdgar E. Iglesias
2015-10-27target-arm: lpae: Move declaration of t0sz and t1szEdgar E. Iglesias
2015-10-27target-arm: lpae: Make t0sz and t1sz signed integersEdgar E. Iglesias
2015-10-27target-arm: Add HPFAR_EL2Edgar E. Iglesias
2015-10-27target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)Soren Brinkmann
2015-10-16target-arm: Add MDCR_EL2Sergey Fedorov
2015-10-16target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregsDavorin Mista
2015-10-16target-arm: Avoid calling arm_el_is_aa64() function for unimplemented ELSergey Sorokin
2015-10-16target-arm: Break the TB after ISB to execute self-modified code correctlySergey Sorokin
2015-10-16target-arm: Add missing 'static' attributeStefan Weil